JP2015023774A - Gate drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate drive circuit capable of preventing erroneous ignition and increasing a speed of a switching operation.SOLUTION: A gate drive circuit 1 includes a voltage supply unit 3 that selectively applies a positive voltage V1 and a negative voltage V2 to a gate terminal G of a low-side switch LS, a gate resistor Rg connected to between an output terminal 4B of the voltage supply unit 3 and the gate terminal G of the low-side switch LS, a connection switch SW1 that forms a conduction path bypassing the gate resistor Rg when a connection control signal becomes a high level, and a monitoring circuit 5 that changes the connection control signal to an operation level for closing the connection switch SW1 when a gate voltage VG in a case where the negative voltage V2 is applied to the gate terminal G of the low-side switch LS, exceeds a setting voltage VS lower than a threshold voltage Vth of the low-side switch LS.

Description

  The present invention relates to a gate drive circuit for driving a voltage-driven semiconductor element.

  A high-side switch and a low-side switch (both voltage-driven semiconductor elements) connected in series in a half-bridge circuit used in an inverter or a converter are driven and controlled by a gate drive circuit. Examples of voltage-driven semiconductor elements include MOSFETs (MOS field effect transistors) and IGBTs (insulated gate bipolar transistors).

For example, when the high-side switch of a half bridge circuit composed of IGBTs is turned on, high dV / dt is generated in the low-side switch. Current due to such a high dV / dt is the flow in the gate resistance via the parasitic Miller capacitance C _CG between the low-side switch collector gate voltage due to the gate resistance occurs. When this voltage exceeds the gate threshold voltage of the IGBT, the low-side switch is falsely fired (self-turned on), causing a power supply short circuit. This false firing is also seen in the high side switch when the low side switch is turned on. In the case of N-type MOSFETs other than IGBTs, P-type MOSFETs, and the like, false firing may occur in the same manner.

  In view of this, the gate drive circuit disclosed in Patent Document 1 includes another switching element for extracting charge from the gate terminal of the MOSFET constituting the low-side switch. When the high-side switch is turned on, the switching element is turned on to extract charges from the gate terminal of the MOSFET of the low-side switch, thereby suppressing erroneous firing of the MOSFET.

  The gate drive circuit of Patent Document 2 includes a negative power supply circuit that applies a negative voltage between the gate and the emitter of the IGBT, for example, and the IGBT gate power supply supplies two power sources (positive and negative power sources). By supplying a negative power source to the gate terminal when the IGBT is turned off, erroneous firing due to a rise in the gate voltage caused by a rapid rise in the collector voltage of the IGBT in the off state is suppressed.

JP 2012-44836 A Japanese Patent No. 5130310

  However, in the gate drive circuit disclosed in Patent Document 1, the rising speed of the drain-source voltage of the MOSFET is suppressed by reducing the charge extraction capability of the switching element, and the switching operation cannot be accelerated.

  In addition, power switching elements using wide gap semiconductors (SiC (silicon carbide), GaN (gallium nitride), etc.) have a low gate threshold voltage in order to reduce switching loss. is there. When such an element having a low gate threshold voltage is gate-driven by the gate driving circuit disclosed in Patent Document 1, false firing may occur.

  In the gate drive circuit disclosed in Patent Document 2, a margin up to the gate threshold voltage can be obtained by supplying a negative power source to the gate terminal when the IGBT is turned off and lowering the off voltage. However, in a power switching element capable of high-speed switching operation using a wide gap semiconductor, dV / dt increases as the switching operation speeds up, and the voltage drop due to gate resistance increases. As a result, this voltage exceeds the margin and exceeds the gate threshold voltage, causing false firing.

  Thus, there is a trade-off relationship between speeding up the switching operation and false firing. That is, the switching operation needs to be speeded up for high-frequency operation of the switching element. However, when the switching operation is speeded up, high dV / dt is generated, and erroneous firing occurs.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a gate drive circuit that can prevent false ignition and realize high-speed switching operation.

In order to achieve the above object, a gate driving circuit according to the present invention includes:
A gate driving circuit for driving a voltage-driven semiconductor element,
A voltage supply unit that selectively applies a positive voltage and a negative voltage to the gate terminal of the voltage-driven semiconductor element;
A gate resistor connected between an output terminal of the voltage supply unit and a gate terminal of the voltage-driven semiconductor element;
When the connection control signal is at an operation level for closing the switch, a connection switch that turns on the conduction path that bypasses the gate resistance;
When a negative voltage is applied to the gate terminal of the voltage-driven semiconductor element, the gate voltage is monitored, and when the gate voltage exceeds a set voltage lower than the gate threshold voltage of the voltage-driven semiconductor element Monitoring means for changing the connection control signal to the operation level;
Is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the gate drive circuit which can prevent false ignition and can implement | achieve high-speed switching operation can be provided.

It is a circuit block diagram of the gate drive circuit which concerns on Embodiment 1 of this invention. (A)-(f) is a timing chart which shows each part voltage etc. of the gate drive circuit. (A), (b) is a figure which shows waveforms, such as each part voltage, when the switch for connection is not turned ON in the gate drive circuit. (A), (b) is a figure which shows waveforms, such as each part voltage at the time of turning on the switch for a connection in the gate drive circuit. It is a figure which shows the solar energy power generation system at the time of applying the gate drive circuit which concerns on Embodiment 1 of this invention for inverter drive. It is a circuit block diagram of the principal part of the gate drive circuit concerning Embodiment 2 of this invention. It is a circuit block diagram of the gate drive circuit which concerns on Embodiment 3 of this invention. (A)-(f) is a timing chart which shows each part voltage etc. of the gate drive circuit. It is a circuit block diagram of the gate drive circuit which concerns on a modification.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
As shown in FIG. 1, the gate drive circuit 1 according to the first embodiment of the present invention drives the high-side switch HS and the low-side switch LS connected in series in the half bridge circuit 2. Since the high-side gate drive circuit 1 and the low-side gate drive circuit 1 have the same circuit configuration, the circuit configuration of the gate drive circuit 1 of the low-side switch LS will be described below.

  The high-side switch HS and the low-side switch LS are N-type MOSFETs (N-channel MOSFETs). The MOSFET has a built-in (circular) diode FWD connected in parallel. Hereinafter, the N-type MOSFET constituting the high-side switch HS is referred to as a high-side switch HS, and the N-type MOSFET constituting the low-side switch LS is referred to as a low-side switch LS.

  The gate drive circuit 1 is connected to the gate terminal G of the high-side switch HS, and a DC positive voltage (DC (+)) is applied to the drain terminal D. Further, the gate drive circuit 1 is connected to the gate terminal G of the low-side switch LS, and a DC negative voltage (DC (−)) is applied to the source terminal S. The source terminal S of the high side switch HS and the drain terminal D of the low side switch LS are connected and output from the connection point P2.

  The low-side gate drive circuit 1 includes a voltage supply unit 3 that selectively applies positive and negative driving voltages to turn on and off the gate terminal G of the low-side switch LS, and a gate resistor connected to the gate terminal G of the low-side switch LS. A monitoring circuit 5 for monitoring Rg, the gate voltage VG, and a connection switch SW1 connected in parallel to the gate resistor Rg.

The voltage supply unit 3 includes a positive power source V _A and a negative power source V _B connected in series, and a push-pull circuit 4, and a positive voltage V 1 (for example, +18 V) is applied to the gate terminal G of the low-side switch LS via the gate resistor Rg. And a negative voltage V2 (for example, -6V) are selectively applied.

  The push-pull circuit 4 is configured by connecting an NPN transistor Tr1 and a PNP transistor Tr2 in positive and negative symmetry, and an input unit 4A in which base terminals B of both transistors Tr1 and Tr2 are connected to each other, and both transistors Tr1, An output terminal 4B connecting the emitter terminals of Tr2.

The positive power source V _A applies a positive voltage V 1 to the collector terminal C of the NPN transistor Tr 1 of the push-pull circuit 4. Negative supply _{V B} applies the negative voltage V2 to the PNP type transistor Tr2 of the push-pull circuit 4. The connection point P1 connecting the negative side terminal of the positive power source V _{A and} the positive side terminal of the negative power source V _B is set to the zero potential V0.

  The gate resistor Rg is connected between the output terminal 4B of the voltage supply unit 3 and the gate terminal G of the low side switch LS.

  When the switching control signal to the input section 4A of the push-pull circuit 4 becomes high level, the NPN transistor Tr1 is turned on and the PNP transistor Tr2 is turned off, and is connected to the gate terminal G of the low-side switch LS via the gate resistor Rg. A positive voltage V1 is applied, and the low-side switch LS is turned on. When the switching control signal becomes low level, the NPN transistor Tr1 is turned off and the PNP transistor Tr2 is turned on, and the negative voltage V2 is applied to the gate terminal G of the low side switch LS via the gate resistance Rg. The switch LS is turned off.

  The connection switch SW1 is an N-type MOSFET. The drain terminal D of the connection switch SW1 is connected to the low-side switch LS side of the gate resistance Rg, the source terminal S is connected to the anode terminal of the backflow prevention diode BPD, and the gate terminal G is connected to the monitoring circuit 5. Note that the MOSFET as the connection switch SW1 has a freewheeling diode FWD connected in parallel.

  The backflow prevention diode BPD has a cathode terminal connected to the push-pull circuit 4 side of the gate resistance Rg and an anode terminal connected to the source terminal S side of the connection switch SW1. A connection switch SW1 and a backflow prevention diode BPD connected in series are connected in parallel to the gate resistor Rg.

  The connection switch SW1 receives a connection control signal (gate voltage signal VSW1 for opening and closing the switch) from the monitoring circuit 5 at its gate terminal G. When the connection control signal to the connection switch SW1 becomes high level, the connection switch SW1 is turned on (the drain and the source become conductive), and the push-pull is connected to the gate terminal G of the low-side switch LS via the backflow prevention diode BPD. The emitter terminal E of the transistor Tr2 of the circuit 4 becomes conductive. When the connection control signal to the connection switch SW1 becomes a low level, the connection switch SW1 is turned off (the drain and the source are not conductive).

  The monitoring circuit 5 compares the gate voltage VG of the low-side switch LS with the set voltage VS as a reference voltage, and inputs a negative gate voltage VG to the non-inverting input terminal of the comparator 6. A resistor R1 for setting and a resistor R2 for setting the set voltage VS.

  The monitoring circuit 5 monitors the gate voltage VG when the low-side switch LS is off (for example, when a negative voltage is applied to the gate terminal G of the MOSFET constituting the low-side switch LS). In the monitoring circuit 5, the negative level gate voltage VG (here, −6V) applied from the voltage supply unit 3 is lower than the threshold voltage Vth (for example, + 2V) of the low-side switch LS. When the voltage exceeds (for example, −4 V), the circuit configuration is such that the connection control signal (gate voltage signal) to the connection switch SW1 is set to the high level.

  If the gate voltage VG <the set voltage VS, the monitoring circuit 5 sets the connection control signal to the gate terminal G of the connection switch SW1 to the low level, the connection switch SW1 is off, and is indicated by a broken line arrow in FIG. Thus, the current Ig1 flows through the gate resistance Rg. If the gate voltage VG ≧ the set voltage VS, the connection control signal is set to the high level, the connection switch SW1 is turned on, and the current Ig2 flows through the connection switch SW1 as indicated by the solid line arrow in FIG.

  The monitoring circuit 5 controls connection to the connection switch SW1 until a predetermined time (for example, several nanoseconds to several tens of nanoseconds) elapses after the gate voltage VG reaches the set voltage VS. The signal is set to the high level, and the connection switch SW1 is turned on during the period. By providing, for example, a one-shot circuit at the output terminal of the comparator 6, it is possible to obtain a connection control signal that remains high for the predetermined time.

  Here, the operation of the gate drive circuit 1 of the low-side switch LS will be described with reference to FIG.

  It is assumed that the low side switch LS is in the on state and the high side switch HS is in the off state immediately before time t1 shown in FIG. Specifically, immediately before time t1, the switching control signal to the input unit 4A (see FIG. 1) of the push-pull circuit 4 is at a high level, and the NPN type of the push-pull circuit 4 in the gate drive circuit 1 of the low-side switch LS. The transistor Tr1 is on (see FIG. 2A), the PNP transistor Tr2 of the push-pull circuit 4 is off (see FIG. 2B), the positive voltage V1 is applied to the gate resistance Rg, and the low-side switch LS The gate voltage VG becomes high level (see FIG. 2D). Conversely, the gate voltage VG of the high side switch HS is at a low level (see FIG. 2C).

  At time t1, the switching control signal to the input unit 4A (see FIG. 1) of the push-pull circuit 4 becomes low level, so that the NPN type of the push-pull circuit 4 is shown in FIGS. The transistor Tr1 is turned off, the PNP transistor Tr2 of the push-pull circuit 4 is turned on, and the gate voltage VG of the low-side switch LS starts to decrease as shown in FIG. At time t2, the gate voltage VG of the low-side switch LS becomes low level, and the passing current (current flowing between the drain and source) of the low-side switch LS becomes zero as shown in FIG. The low side switch LS is turned off.

  At time t3, the switching control signal to the input part 4A of the push-pull circuit 4 in the gate drive circuit 1 of the high side switch HS is changed from low level to high level. As a result, the dead time DT from time t2 to t3 is secured until the high-side switch HS is turned on (see FIG. 2D). The dead time DT is a standby period (a standby period for preventing DC short-circuit) for preventing both the high-side switch HS and the low-side switch LS from being DC short-circuited.

Subsequently, the gate drive circuit 1 of the high side switch HS changes the switching control signal to the input unit 4A of the push-pull circuit 4 to a high level at time t3. Thereby, the gate voltage VG of the high side switch HS exceeds the threshold voltage Vth at time t4, and the high side switch HS is turned on (see FIG. 2C). At this time, when the voltage (V _DS ) across the low-side switch LS in the off state rapidly rises, the current Ig1 indicated by the broken line arrow in FIG. 1 flows via the gate-drain mirror capacitance C _DG and the gate resistance Rg. The voltage drop VRg due to the gate resistance Rg increases, and the gate voltage VG of the low-side switch LS rises as shown by the broken line in FIG.

The monitoring circuit 5 monitors the gate voltage VG, and when it exceeds a preset voltage VS, a connection control signal (gate voltage signal VSW1) to the connection switch SW1 is set to a high level as shown in FIG. The connection switch SW1 is turned on, and the current Ig2 indicated by the solid line arrow in FIG. 1 flows through the connection switch SW1. Since the on-resistance R _SW (for example, several milliohms) of the connection switch SW1 is sufficiently small relative to Rg (for example, several ohms), the voltage generation due to the gate resistance Rg can be suppressed, and the rise of the gate voltage VG can be suppressed.

  As a result, it is possible to prevent erroneous firing of the low side switch LS without exceeding the threshold voltage Vth, and it is possible to prevent a DC short circuit due to conduction of the high side and low side switch LS. In the period from time t4 to t6, as shown in FIG. 2 (f), the passing current of the low-side switch LS remains zero as shown by the solid line, and a DC short circuit is prevented.

  If the connection switch SW1 is not provided, the gate voltage VG of the low-side switch LS exceeds the threshold voltage Vth as shown by the broken line in FIG. 2D, and the low-side switch LS is erroneously fired. An overcurrent Ish (DC short-circuit current) indicated by a broken line in FIG. 2F flows through the low-side switch LS.

  Then, when the switching control signal to the input part 4A of the push-pull circuit 4 in the gate drive circuit 1 of the high side switch HS becomes low level, the high side switch HS is turned off. Then, after the elapse of the dead time DT, the switching control signal to the input part 4A of the push-pull circuit 4 in the gate drive circuit 1 of the low side switch LS becomes high level, whereby the low side switch LS is turned on. Then, a series of cycles in which the low-side switch LS is turned off at time t1 described above are repeated.

  Here, in the gate drive circuit 1 of the first embodiment, the gate resistance Rg shown in FIG. 1 is set to 3.3Ω (ohms), and the inactive mode in which the connection switch SW1 is not turned on is set in FIG. As shown in a), experimental results indicating the risk of self-turn-on have been obtained.

  In FIG. 3A, the gate resistance Rg is 3.3Ω (ohms), and the gate voltage of the low-side switch LS (turn-off state) when the high-side switch HS is turned on in the high-voltage operation of the half bridge circuit 2. VG is lifted. That is, a voltage increase ΔVg (= 6.5 V) is generated in the gate voltage VG applied to a negative voltage (for example, −6 V (volt)), and 1.1 with respect to the threshold voltage Vth (for example, +2 V). There is a risk of self-turn-on, with no more than 5V.

  Therefore, a case where the gate resistance Rg is increased to suppress the increase in the gate voltage VG due to high dV / dt will be described with reference to FIG. Specifically, the gate resistance Rg is changed to 9Ω, which is larger than 3.3Ω. In this case, as shown in FIG. 3B, the voltage increase ΔVg (= 5 V) of the gate voltage VG of the low-side switch LS (turn-off state) is suppressed. In other words, the gate voltage VG applied to a negative voltage (for example, −6 V (volt)) is stopped from causing a voltage increase ΔVg (= 5 V), which is 3 V with respect to the threshold voltage Vth (for example, +2 V). As a difference, the risk of self-turn-on is reduced compared to the case of 3.3Ω. However, it can be seen that the falling slope of the drain-source voltage of the high-side switch HS becomes gentle, the switching loss increases, and high-speed switching cannot be performed.

  Thus, there is a trade-off relationship between speeding up the switching operation and false firing. That is, the switching operation needs to be speeded up for high-frequency operation of the switching element. However, when the switching operation is speeded up, high dV / dt is generated, and erroneous firing occurs.

  On the other hand, when the gate drive circuit 1 according to the first embodiment is released from the non-operation mode to the original operation mode (that is, the monitor circuit 5 monitors the gate voltage VG, the gate voltage VG When the voltage exceeds the set voltage VS, when the connection switch SW1 is turned on), even when the gate resistance Rg is small as shown in FIG. 4, the self-turn-on can be prevented and high-speed switching can be realized. was gotten. This will be described below.

  Even when the gate resistance Rg shown in FIG. 1 is set to a low value (for example, 3.3Ω), as shown in FIG. 4A, the gate voltage VG of the low-side switch LS (turn-off state) is equal to the set voltage VS (= −4V). When the monitoring circuit 5 detects that the voltage exceeds the limit, the connection switch SW1 is turned on and a current flows through the connection switch SW1, so that the voltage increase ΔVg (= 2V) is suppressed. In other words, the gate voltage VG applied to a negative voltage (for example, −6V (volt)) is stopped from causing a voltage increase ΔVg (= 2V), which is 6V with respect to the threshold voltage Vth (for example, + 2V). As a difference, self-turn-on of the low-side switch LS can be prevented. In addition, the slope of the drain-source voltage of the high-side switch HS is steep, the switching loss can be reduced by 15% (for example, reduced from 0.6 mJ to 0.51 mJ), and the off time is 130 nsec (nanoseconds). , High-speed switching is possible in which the ON time is 100 nsec (nanoseconds). It should be noted that the drain-source voltage of the high-side switch HS in FIG. 4 has a waveform illustrated with the upper side being zero potential and the lower side being positive potential.

  Next, the case where the gate resistance Rg is set to a lower value (for example, 2.5Ω) will be described below. As shown in FIG. 4B, the gate voltage VG of the low-side switch LS (turn-off state) may exceed the set voltage VS (= −4 V) even when the gate resistance Rg is set to a lower value (for example, 2.5Ω). When detected by the monitoring circuit 5, the connection switch SW1 is turned on and a current flows through the connection switch SW1, so that the voltage increase ΔVg (= 2V) can be suppressed, and the low-side switch LS can be prevented from self-turning on. Moreover, the slope of the drain-source voltage of the high-side switch HS is further steep, so that the switching loss can be reduced by 60% (for example, reduced from 0.6 mJ to 0.24 mJ), and the off time is 120 nsec (nanoseconds). In addition, high-speed switching is possible in which the ON time is 90 nsec (nanoseconds).

  Even when the gate resistance Rg is set to a lower value, self-turn-on of the low-side switch LS can be prevented, and further high-speed switching can be performed, leading to high efficiency (low loss).

  Moreover, the gate drive circuit 1 of this Embodiment 1 is applicable, for example as an inverter drive of the solar power generation system 10, as shown in FIG.

  As shown in FIG. 5, the solar power generation system 10 includes a solar cell PV that converts solar energy into electric power, and a power conditioner 20 that converts DC power output from the solar cell PV into AC power and outputs the load. AC power is supplied to the AC system 50 on the side.

  The power conditioner 20 includes a converter 30 that converts a voltage from the solar battery PV into a predetermined voltage, a converter gate drive circuit 31 that controls a switching element in the converter 30, and a converter gate that performs MPPT control on the converter 30, for example. And a converter control circuit 32 that controls the drive circuit 31. This MPPT control is a control that automatically follows the maximum output point so as to always maximize the output of the solar cell PV. The input current from the solar cell PV to the power conditioner 20 is detected by the input current detection circuit 33 and input to the converter control circuit 32. Further, the input voltage from the solar cell PV to the power conditioner 20 is detected by the input voltage detection circuit 34 and input to the converter control circuit 32.

  The power conditioner 20 also controls the inverter 40 that converts the DC power from the converter 30 into AC power, the inverter gate drive circuit 41 that controls the switching elements in the inverter 40, and the inverter 40 (for example, Vdc (DC And an inverter control circuit 42 that controls the inverter gate drive circuit 41 so as to perform (voltage) control and output power control).

  The input voltage from the converter 30 to the inverter 40 is detected by the input voltage detection circuit 43 and input to the inverter control circuit 42. The output current and output voltage of the inverter 40 are detected by the output current detection circuit 44 and the output voltage detection circuit 45, respectively, and input to the inverter control circuit 42, respectively.

  By applying the gate drive circuit 1 of the first embodiment to the inverter gate drive circuit 41, the switching element in the inverter 40 can be switched at high speed, and the inverter 40 with high efficiency (low loss) can be realized. .

  As described above, according to the gate drive circuit 1 according to the first embodiment of the present invention, the monitoring circuit 5 uses the gate voltage VG when the negative voltage V2 is applied to the gate terminal G of the low-side switch LS. When this gate voltage VG exceeds a set voltage VS lower than the threshold voltage Vth of the low-side switch LS, the connection control signal to the gate terminal G of the connection switch SW1 connected in parallel to the gate resistor Rg is increased. To level. The connection switch SW1 forms a conduction path that bypasses the gate resistor Rg when the connection control signal becomes high level. As a result, the gate voltage VG of the low-side switch LS does not exceed the threshold voltage Vth, and erroneous firing can be prevented.

For example, in the case of a power switching element capable of high-speed switching using a wide gap semiconductor and having a low loss, the gate voltage VG generated by a rapid dV / dt in order to increase the switching operation speed When the voltage supply unit 3 capable of supplying two power supplies supplies negative power when it is off, a margin up to the threshold voltage Vth can be obtained, and connection is detected when it is detected that the gate voltage VG exceeds the set voltage VS. by the switch SW1, because it can form a circuit connecting a low impedance gate terminal G to the negative power supply V _B, it can be reliably prevented from increasing gate voltage VG. Therefore, it is possible to provide a gate drive circuit that can prevent false ignition and realize high-speed switching operation.

  Further, since the backflow prevention diode BPD for preventing the current from the voltage supply unit 3 from flowing into the connection switch SW1 is provided between the connection switch SW1 and the voltage supply unit 3, the on-current of the low-side switch LS is provided. Can be prevented from flowing to the gate terminal G side through the freewheeling diode FWD of the connection switch SW1.

  The monitoring circuit 5 controls connection to the connection switch SW1 until a predetermined time (for example, several nanoseconds to several tens of nanoseconds) elapses after the gate voltage VG reaches the set voltage VS. The signal (gate voltage signal VSW1 shown in FIG. 2E) is set to the high level, and the connection switch SW1 is turned on during this period. Thereby, it is possible to prevent the connection switch SW1 from chattering due to a surge voltage ripple or the like of the gate terminal G, and it is possible to prevent the connection switch SW1 from malfunctioning.

(Embodiment 2)
Next, the gate drive circuit 1 according to Embodiment 2 of the present invention will be described. In the following description, the same reference numerals are given to components and the like that are common to the first embodiment.

  In the first embodiment described above, a single gate resistance Rg is used as shown in FIG. 1, but the present invention is not limited to this. In the second embodiment, as shown in FIG. 6, a turn-on gate resistance Rgon and a turn-off gate resistance Rgoff are provided.

The gate drive circuit 1 shown in FIG. 6, to the ON operation and the OFF operation of the low-side switch LS a different gate resistance R _g, a and a gate resistor Rgoff for gate resistor Rgon and turn-off for turning on . For example, the turn-on period can be accelerated and the turn-off period can be delayed, or vice versa, and the turn-on period and the turn-off period can be made different.

  Specifically, between the output terminal 4B of the voltage supply unit 3 and the gate terminal G of the low-side switch LS, an off-line L1 that is a negative power supply line when the low-side switch LS is off and an on-time of the low-side switch LS The on-line L2 which is a positive power supply line is formed in parallel.

  The off-line L1 includes a turn-off gate resistor Rgoff as a gate resistor, and a first diode D1 connected in series to the turn-off gate resistor Rgoff with the cathode facing the output terminal 4B of the voltage supply unit 3. .

  The turn-on line L2 includes a turn-on gate resistor Rgon and a second diode D2 connected in series to the turn-on gate resistor Rgon with the anode directed to the output terminal 4B of the voltage supply unit 3.

  The connection switch SW1 is connected in parallel to the turn-off gate resistor Rgoff.

  When the low-side switch LS is on, the positive power supply from the voltage supply unit 3 is supplied to the gate terminal G of the low-side switch LS via the turn-on gate resistor Rgon. Further, when the low-side switch LS is turned off, the negative power supply from the voltage supply unit 3 is supplied to the gate terminal G of the low-side switch LS via the turn-off gate resistor Rgoff.

  Also in the gate drive circuit 1 of the second embodiment, the monitoring circuit 5 detects the gate voltage VG ≧ the set voltage VS when the negative power supply from the voltage supply unit 3 is supplied to the gate terminal G of the low-side switch LS. Then, the connection control signal to the connection switch SW1 is set to the high level, the connection switch SW1 is turned on, and a conduction path that bypasses the gate resistance Rgoff is formed (configures a low impedance circuit).

  That is, the current flow through the turn-off gate resistor Rgoff (the current flow indicated by the dashed arrow) can be changed to the current flow through the connection switch SW1 (the current flow indicated by the solid line), and the turn-off gate resistance The amount of voltage generated by Rgoff can be suppressed, the rise of the gate voltage VG can be suppressed, and erroneous firing of the low side switch LS can be prevented.

  As described above, according to the gate drive circuit 1 according to the second embodiment of the present invention, when the low-side switch LS is on, the positive power supply from the voltage supply unit 3 is connected to the low-side switch via the turn-on gate resistor Rgon. LS is supplied to the gate terminal G of LS. Further, when the low side switch LS is turned off, the negative power source from the voltage supply unit 3 is supplied to the gate terminal G of the low side switch LS via the turn-off gate resistance Rgoff, and the gate voltage VG at this time exceeds the set value. The connection switch SW1 connected in parallel to the turn-off gate resistor Rgoff is turned on to constitute a low impedance circuit.

  Accordingly, it is possible to provide a gate drive circuit capable of realizing a high-speed switching operation without erroneous firing of the low-side switch LS in the off state even in a gate drive circuit having different switching speeds depending on whether the low-side switch LS is turned on or off. Can do.

(Embodiment 3)
Next, the gate drive circuit 1 according to Embodiment 3 of the present invention will be described. In the following description, the same reference numerals are given to components and the like that are common to the first embodiment.

  In the first embodiment, as shown in FIG. 1, when the low-side switch LS is in the OFF state, the gate voltage VG of the low-side switch LS is monitored, and if the gate voltage VG exceeds the set voltage VS, the connection is established. However, the present invention is not limited to this.

  In the third embodiment, as shown in FIG. 7, the monitoring circuit 5 of the low-side switch LS monitors the gate voltage VG of the high-side switch HS, and the gate voltage VG of the high-side switch HS is a threshold value as a determination voltage. When the voltage Vth is exceeded, the connection switch SW1 in the low-side switch LS in the off state is turned on.

  That is, as shown in FIG. 8, at the timing when the high-side switch HS is turned on (time t4), a high dV / dt is generated in the low-side switch LS in the off state, so that the gate voltage VG of the high-side switch HS is reduced. When the threshold value is exceeded (time t4), the connection switch SW1 on the low-side switch LS side is turned on.

As described above, according to the gate drive circuit 1 according to the third embodiment of the present invention, the monitoring circuit 5 of the low side switch LS monitors the gate voltage VG of the high side switch HS, and the gate of the high side switch HS. When the voltage VG exceeds the threshold voltage Vth (determination voltage) (that is, the high side switch HS is turned on), the connection control signal to the connection switch SW1 of the low side switch LS is set to the high level. of the negative power supply V _B side by the connection switch SW1 and the gate terminal G can be connected with a low impedance, the increase of the gate voltage VG of the low-side switch LS can be made smaller than in the first embodiment described above. Therefore, it is possible to provide a gate drive circuit that can realize high-speed switching operation without erroneous firing.

  Note that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  In each of the embodiments described above, as shown in FIG. 1, the current Ig2 flows through the PNP transistor Tr2 of the push-pull circuit 4 through the connection switch SW1, but as shown in FIG. One end (drain terminal D) of the switch SW1 is connected to a terminal on the gate terminal G side of the low-side switch LS of the gate resistor Rg, and the other end (source terminal S) of the connection switch SW1 is a terminal at the reference potential point (zero potential) Terminal V0) and may flow to zero potential V0 via the connection switch SW1. The terminal of the reference potential point may be a negative voltage terminal (negative voltage V2 or other negative voltage terminal).

  Further, when the low-side switch LS is in an off state, the gate terminal G of the low-side switch LS may be fixed to a negative voltage.

  In each of the above-described embodiments, the gate drive circuit 1 of the low-side switch LS is described as an example. However, the present invention is not limited to this, and the gate drive circuit 1 of the high-side switch HS may be used. . When applied to the high-side switch HS, erroneous firing of the high-side switch HS can be prevented and the switching operation can be speeded up.

Here, the false ignition of the high side switch will be described. When the low side switch is turned on, the high side switch is erroneously ignited. Specifically, when the low-side switch is turned on, high dV / dt is generated through the free-wheeling diode of the off-side high-side switch. Current due to such a high dV / dt is the flow in the gate resistance via the parasitic Miller capacitance C _CG of the high-side switch, the voltage due to the gate resistance occurs. If this voltage exceeds the threshold voltage, the high-side switch will also falsely fire (self-turn on), causing a power supply short circuit.

Specifically, the monitoring circuit 5 monitors the gate voltage VG when the negative voltage V2 is applied to the gate terminal G of the high side switch HS, and the gate voltage VG is higher than the threshold voltage Vth of the high side switch HS. If the set voltage VS is too low, the connection control signal to the connection switch SW1 connected in parallel to the gate resistor Rg is set to the high level. Connection switch SW1, the connection control signal for connecting the negative power supply V _B side of the gate terminal G and the voltage supply unit 3 becomes a high level at a low impedance. In this case, it is possible to prevent the high side switch HS from being erroneously fired due to the low side switch LS being turned on when the high side switch HS is in the off state.

  In each of the above-described embodiments, the voltage supply unit 3 selectively switches the drive positive / negative voltage for turning it on / off to the gate terminal G of the low-side switch LS. It may be switched alternately or after the dead time.

  In each of the embodiments described above, the connection switch SW1 is a MOSFET, but is not limited thereto, and may be an analog switch, IGBT, junction FET, bipolar transistor, or the like. For example, when a mechanical analog switch is employed as the connection switch SW1, the backflow prevention diode BPD is not necessary.

  In each of the embodiments described above, the high-side switch HS and the low-side switch LS are n-type MOSFETs. However, the present invention is not limited to this, and p-type MOSFETs and IGBTs (both n-type and p-type are used). Possible), junction FET (both n-type and p-type are possible), bipolar transistor (both n-type and p-type are possible), and the like.

  In addition, although it has been described that the gate drive circuit 1 of each embodiment described above can be applied to, for example, the inverter gate drive circuit 41 of the power conditioner 20 in the photovoltaic power generation system 10, it is not limited thereto. Instead, the present invention can be applied to various gate drive circuits such as a gate drive circuit for driving the converter 30 and a gate drive circuit for driving a three-phase bridge inverter.

  In each of the above-described embodiments, the monitoring circuit 5 waits until a predetermined time (for example, several nanoseconds to several tens of nanoseconds) elapses from when the gate voltage VG reaches the set voltage VS. During this period, the connection control signal to the connection switch SW1 is set to the high level and the connection switch SW1 is turned on during this period, but this is not restrictive. For example, the monitoring circuit 5 may maintain the high level of the connection control signal to the connection switch SW1 until the monitoring circuit 5 decreases to the first lower limit voltage lower than the set voltage VS of the gate voltage VG. As the first lower limit voltage, for example, a lower limit voltage lower than the set voltage VS is set by setting a hysteresis (voltage range for preventing malfunction).

  Further, the connection control signal to the connection switch SW1 of the low side switch LS may be set to the high level until the voltage falls to the second lower limit voltage lower than the determination voltage that is the threshold voltage Vth of the high side switch HS. . As the second lower limit voltage, for example, a lower limit voltage lower than the set voltage VS is set by setting a hysteresis (voltage region for preventing malfunction).

  Also in these cases, the connection switch SW1 can be prevented from chattering due to the surge voltage ripple of the gate terminal G, and the connection switch SW1 can be prevented from malfunctioning.

DESCRIPTION OF SYMBOLS 1 Gate drive circuit 2 Half bridge circuit 3 Voltage supply part 4B Output terminal 5 Monitoring circuit (monitoring means)
BPD Backflow prevention diode (Backflow prevention element)
D1 1st diode D2 2nd diode FWD Freewheeling diode HS High side switch (voltage drive type semiconductor element, 2nd element)
LS Low-side switch (voltage-driven semiconductor element, first element)
L1 OFF line L2 ON line Rg Gate resistance Rgoff Turn-off gate resistance (gate-off resistance)
Rgon Turn-on gate resistance (gate-on resistance)
SW1 connection switch (switching element)

Claims (7)

A gate driving circuit for driving a voltage-driven semiconductor element,
A voltage supply unit that selectively applies a positive voltage and a negative voltage to the gate terminal of the voltage-driven semiconductor element;
A gate resistor connected between an output terminal of the voltage supply unit and a gate terminal of the voltage-driven semiconductor element;
When the connection control signal is at an operation level for closing the switch, a connection switch that turns on the conduction path that bypasses the gate resistance;
When a negative voltage is applied to the gate terminal of the voltage-driven semiconductor element, the gate voltage is monitored, and when the gate voltage exceeds a set voltage lower than the gate threshold voltage of the voltage-driven semiconductor element Monitoring means for changing the connection control signal to the operation level;
A gate drive circuit comprising: The connection switch is connected in parallel to the gate resistor, and when the connection control signal reaches the operation level, a conduction path that bypasses the gate resistor is turned on.
The gate drive circuit according to claim 1, wherein: One end of the connection switch is connected to the terminal of the gate resistor on the gate terminal side of the voltage-driven semiconductor element, the other end is connected to a terminal of a reference potential point, and the connection control signal is at the operation level. A conduction path different from the gate resistance is made conductive;
The gate drive circuit according to claim 1, wherein: Between the output terminal of the voltage supply unit and the gate terminal of the voltage-driven semiconductor element, an off line and an on line are formed in parallel,
The off-line has a gate-off resistance as the gate resistance, and a first diode connected in series with the gate-off resistance with the cathode facing the output terminal of the voltage supply unit,
The on-line has a gate-on resistance and a second diode having an anode connected in series to the gate-on resistance toward the voltage supply unit,
The connection switch is connected in parallel to the gate-off resistor;
The gate drive circuit according to claim 1, wherein the gate drive circuit is a gate drive circuit. A second element as another voltage-driven semiconductor element connected in series with the first element as the voltage-driven semiconductor element;
Instead of monitoring whether the gate voltage of the first element exceeds the set voltage, the monitoring means monitors the gate voltage of the second element, and the gate voltage of the second element is a threshold. When a determination voltage that is a value voltage is exceeded, the connection control signal to the connection switch of the first element is changed to the operation level.
The gate drive circuit according to claim 1, wherein the gate drive circuit is provided. The connection switch is a switching element,
Between the switching element and the output terminal of the voltage supply unit, a backflow prevention element that prevents a current from the voltage supply unit from flowing to the switching element is provided.
The gate drive circuit according to claim 1, wherein the gate drive circuit is provided. The monitoring means operates the operation of the connection control signal to the connection switch until a predetermined time set in advance elapses or until the first lower limit voltage lower than the set voltage is lowered. Keep the level,
The gate drive circuit according to claim 1, wherein the gate drive circuit is provided.

Images