JP2015015319A - 集積回路装置 - Google Patents
集積回路装置 Download PDFInfo
- Publication number
- JP2015015319A JP2015015319A JP2013140194A JP2013140194A JP2015015319A JP 2015015319 A JP2015015319 A JP 2015015319A JP 2013140194 A JP2013140194 A JP 2013140194A JP 2013140194 A JP2013140194 A JP 2013140194A JP 2015015319 A JP2015015319 A JP 2015015319A
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- JP
- Japan
- Prior art keywords
- integrated circuit
- chip
- circuit chip
- cooling
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims (8)
- 複数の集積回路チップと冷却用チップとを積層した集積回路装置であって、
第1の集積回路チップの第1の面に接する同一平面上に、前記冷却用チップと第2の集積回路チップを配置したことを特徴とする集積回路装置。 - 前記第2の集積回路チップを、前記第1の集積回路チップの第1の面上において前記冷却用チップに隣接するように配置し、
前記冷却用チップにおける前記第1の集積回路チップとは反対側の面上に第3の集積回路チップを配置したことを特徴とする請求項1に記載の集積回路装置。 - 前記第1の集積回路チップ、前記第3の集積回路チップ、前記第2の集積回路チップの順で発熱量が小さいことを特徴とする請求項1または2に記載の集積回路装置。
- 前記第1の集積回路チップにおける発熱量が相対的に大きい領域に前記冷却用チップを配置し、発熱量が相対的に小さい領域に前記第2の集積回路チップを配置したことを特徴とする請求項1ないし3のいずれか1項に記載の集積回路装置。
- 前記第1の集積回路チップにおける前記第2の集積回路チップの回路モジュールが配置されている領域と、前記第2の集積回路チップとを平面視でオーバーラップするように配置したことを特徴とする請求項1ないし3のいずれか1項に記載の集積回路装置。
- 前記冷却用チップと前記第3の集積回路チップとを面接触するように配置し、
前記第1の集積回路チップと前記第3の集積回路チップとを、前記冷却用チップの内部に形成された貫通電極を介して電気的に接続したことを特徴とする請求項2に記載の集積回路装置。 - 前記第1の集積回路チップと前記第3の集積回路チップとを接続する端子位置を夫々のチップの外周側に配置し、
前記第2の集積回路チップを、平面視でほぼ中央に配置し、
前記冷却用チップを前記第2の集積回路チップに隣接するように配置したことを特徴とする請求項2に記載の集積回路装置。 - 前記第1の集積回路チップと前記第3の集積回路チップとを接続する接続チップを、夫々のチップの外周側に配置したことを特徴とする請求項7に記載の集積回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2013140194A JP2015015319A (ja) | 2013-07-03 | 2013-07-03 | 集積回路装置 |
Applications Claiming Priority (1)
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JP2013140194A JP2015015319A (ja) | 2013-07-03 | 2013-07-03 | 集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015015319A true JP2015015319A (ja) | 2015-01-22 |
JP2015015319A5 JP2015015319A5 (ja) | 2016-08-18 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2013140194A Pending JP2015015319A (ja) | 2013-07-03 | 2013-07-03 | 集積回路装置 |
Country Status (1)
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JP (1) | JP2015015319A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2024024794A1 (ja) * | 2022-07-26 | 2024-02-01 | ソニーセミコンダクタソリューションズ株式会社 | 電子デバイス |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120025388A1 (en) * | 2010-07-29 | 2012-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional integrated circuit structure having improved power and thermal management |
WO2013078536A1 (en) * | 2011-12-01 | 2013-06-06 | Mosaid Technologies Incorporated | Cpu with stacked memory |
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2013
- 2013-07-03 JP JP2013140194A patent/JP2015015319A/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120025388A1 (en) * | 2010-07-29 | 2012-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional integrated circuit structure having improved power and thermal management |
WO2013078536A1 (en) * | 2011-12-01 | 2013-06-06 | Mosaid Technologies Incorporated | Cpu with stacked memory |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2024024794A1 (ja) * | 2022-07-26 | 2024-02-01 | ソニーセミコンダクタソリューションズ株式会社 | 電子デバイス |
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