JP2014508402A - Soi基板の活性層内に形成されるデバイス構造体、製造する方法、及び、集積回路の設計構造体 - Google Patents
Soi基板の活性層内に形成されるデバイス構造体、製造する方法、及び、集積回路の設計構造体 Download PDFInfo
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- 238000013461 design Methods 0.000 title claims abstract description 82
- 239000000758 substrate Substances 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title description 26
- 238000000034 method Methods 0.000 claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims description 79
- 239000002019 doping agent Substances 0.000 claims description 18
- 238000002513 implantation Methods 0.000 claims description 16
- 239000012212 insulator Substances 0.000 claims description 14
- 238000003860 storage Methods 0.000 claims description 6
- 238000013500 data storage Methods 0.000 claims description 4
- 238000011960 computer-aided design Methods 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 22
- 238000002955 isolation Methods 0.000 abstract description 16
- 230000002829 reductive effect Effects 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 27
- 150000002500 ions Chemical class 0.000 description 25
- 238000012938 design process Methods 0.000 description 14
- 238000005468 ion implantation Methods 0.000 description 14
- 238000012545 processing Methods 0.000 description 14
- 239000003989 dielectric material Substances 0.000 description 9
- 238000004088 simulation Methods 0.000 description 9
- 238000003672 processing method Methods 0.000 description 8
- 238000012360 testing method Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000470 constituent Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000012804 iterative process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000000547 structure data Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002076 thermal analysis method Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
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- G—PHYSICS
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Abstract
【解決手段】 デバイス構造体は、デバイス領域(18)内に配置された、アノード(40、42)とカソード(28、30、48a、48b、49a、49b、50a、50b)との間のp−n接合部(52、54)に交差する、STI領域のような1つ又は複数の誘電体領域(20a、20b、20c)を含む。この誘電体領域は、浅いトレンチ分離技術を用いて形成することができ、p−n接合部から横方向に離間した位置におけるカソード及びアノードの幅の面積に対して、p−n接合部の幅を縮小するように機能する。幅の違い及び誘電体領域の存在が、非対称ダイオード構造を作り出す。誘電体領域が占めるデバイス領域の体積は、カソード及びアノードの体積を確保するように最小にされる。
【選択図】 図5
Description
12:ハンドル・ウェハ
14:デバイス又はSOI層
16:埋込み誘電体層
17:横方向分離構造体
18:デバイス領域
20a、20b、20c、72a、72b、72c、74a、74b、74c:誘電体領域
22、36、46:イオン
24、26、62a、62b、64a、64b:マスク構造体
28、30、48a、48b、49a、49b、50a、50b:ドープ領域(カソード)
40、42、76a、76b、76c:ドープ領域(アノード)
32、44:イオン注入マスク
52、52a、52b、54:p−n接合部
56:横型ダイオード
58、60、80、82、84、86:誘電体領域の側端部
66、67、68、69:マスク構造体の側端部
100:設計フロー
102:入力設計構造体
104:設計プロセス
106:ネットリスト
120:設計構造体
Claims (25)
- 半導体オン・インシュレータ(SOI)基板の半導体層内にデバイス構造体を作成する方法であって、
前記半導体層内に、第1の導電型及び第1の幅の第1の領域を含むカソードを形成することと、
前記半導体層内に、第2の導電型の第1の領域を含むアノードを形成することと
を含み、
前記アノードは、前記アノードの前記第1の領域がp−n接合部に沿って前記カソードの前記第1の領域と同一の広がりをもつように前記カソードに対して配置され、前記p−n接合部は、前記p−n接合部から横方向に離間した位置で計測された前記第1の領域の前記第1の幅より小さい、前記第1の幅に平行な方向に計測された第2の幅を有する、
方法。 - 前記SOI基板は、埋込み誘電体層と、前記半導体層から前記埋込み誘電体層によって隔てられたハンドル・ウェハとを含み、前記方法は、
前記半導体層内に、前記半導体層の上面から前記埋込み誘電体層まで延びる少なくとも1つの誘電体領域を形成することをさらに含み、
前記少なくとも1つの誘電体領域は、前記p−n接合部を、総計で前記第2の幅を定める個々の幅の複数の区域に分割する、
請求項1に記載の方法。 - 前記半導体層の前記上面の上に、前記第1及び第2の幅にそれぞれ位置合せされた第1の側端部及び第2の側端部を有する第1のマスク構造体を形成することをさらに含み、
前記少なくとも1つの誘電体領域は、前記第1及び第2の幅に位置合せされた第1の側端部を有し、前記少なくとも1つの誘電体領域の前記第1の側端部は、前記第1のマスク構造体の前記第1の側端部と第2の側端部との間に配置される、
請求項2に記載の方法。 - 前記半導体層内に、前記第2の導電型の前記第1の領域を含む前記アノードを形成することは、
前記半導体層内に第1のドーパントを注入して前記アノードの前記第1の領域を形成することを含み、
前記第1のドーパントの前記注入の間、前記第1のマスク構造体が前記カソードの前記第1の領域を覆い、前記第1のマスク構造体の前記第1の側端部が前記p−n接合部に垂直方向に位置合せされる、
請求項3に記載の方法。 - 前記半導体層の前記上面の上に、前記第1のマスク構造体と平行に配向する、前記第1のマスク構造体の前記第1の側端部から離間した第2のマスク構造体を形成することをさらに含む、請求項4に記載の方法。
- 前記少なくとも1つの誘電体領域は、前記少なくとも1つの誘電体領域の前記第1の側端部に平行な第2の側端部を有し、前記第2のマスク構造体は前記少なくとも1つの誘電体領域の前記第2の側端部に完全に重なり、その結果、前記少なくとも1つの誘電体領域が前記第1のマスク構造体から前記第2のマスク構造体まで橋を架ける、請求項5に記載の方法。
- 前記少なくとも1つの誘電体領域は、前記少なくとも1つの誘電体領域の前記第1の側端部に平行な第2の側端部を有し、前記少なくとも1つの誘電体領域の前記第2の側端部は、前記第1のマスク構造体の前記第1の側端部と前記第2のマスク構造体との横方向の間にあり、その結果、前記第1の領域の一部分が前記少なくとも1つの誘電体領域の前記第2の側端部と前記第2のマスク構造体との間に配置される、請求項5に記載の方法。
- 前記半導体層に第2のドーパントを注入して、前記カソードの前記第1の領域と同じ導電型で前記カソードの前記第1の領域より高い導電率を有する前記カソードの第2の領域を形成することをさらに含み、
前記第1のマスク構造体の前記第2の側端部が前記カソードの前記第1の領域と前記カソードの前記第2の領域との間の境界を定める、
請求項3に記載の方法。 - 前記第1のマスク構造体が前記少なくとも1つの誘電体領域の前記第1の側端部と部分的に重なり、その結果、前記カソードの前記第2の領域の一部分が前記少なくとも1つの誘電体領域の前記第1の側端部と同一の広がりをもつ、請求項8に記載の方法。
- 前記第1のマスク構造体が前記少なくとも1つの誘電体領域の前記第1の側端部と完全に重なり、その結果、前記カソードの前記第2の領域が前記少なくとも1つの誘電体領域の前記第1の側端部から前記カソードの前記第1の領域によって隔てられる、請求項8に記載の方法。
- 前記SOI基板は、埋込み誘電体層と、前記半導体層から前記埋込み誘電体層によって隔てられたハンドル・ウェハとを含み、前記方法は、
前記半導体層内に、前記半導体層の上面から前記埋込み誘電体層まで延びる複数の誘電体領域を形成することをさらに含み、
前記誘電体領域は、前記p−n接合部を、総計で第2の幅を与える複数の区域に分割する、
請求項1に記載の方法。 - 半導体オン・インシュレータ(SOI)基板の半導体層内に作成されるデバイス構造体であって、
前記半導体層内の、第1の導電型及び第1の幅でドープされた前記半導体層の第1の領域を含むカソードと、
前記半導体層内の、第2の導電型の第1の領域を含むアノードと
を備え、
前記アノードは、前記アノードの前記第1の領域がp−n接合部に沿って前記カソードの前記第1の領域と同一の広がりをもつように前記カソードに対して配置され、前記p−n接合部は、前記p−n接合部から横方向に離間した位置で計測された前記第1の領域の前記第1の幅より小さい、前記第1の幅に平行な方向に計測された第2の幅を有する、
デバイス構造体。 - 前記SOI基板は、埋込み誘電体層と、前記半導体層から前記埋込み誘電体層によって隔てられたハンドル・ウェハとを含み、前記デバイス構造体は、
前記半導体層の上面から前記埋込み誘電体層まで延びる少なくとも1つの第1の誘電体領域を前記半導体層内にさらに備え、
前記少なくとも1つの誘電体領域は、前記p−n接合部を、総計で第2の幅を定める個々の幅の複数の区域に分割する、
請求項12に記載のデバイス構造体。 - 前記少なくとも1つの第1の誘電体領域は、前記第1及び第2の幅に位置合せされた側端部を有し、前記デバイス構造体は、
前記半導体層の上面から前記埋込み誘電体層まで延びる少なくとも1つの第2の誘電体領域を前記半導体層内にさらに備え、
前記少なくとも1つの第2の誘電体領域は、前記第1の幅及び第2の幅に位置合せされた側端部を有し、前記少なくとも1つの第2の誘電体領域の前記側端部は、前記第1の誘電体領域の前記側端部から、前記アノードの一部分が前記側端部の間に配置されるように離間する、
請求項13に記載のデバイス構造体。 - 前記カソードは、前記第1の導電型にドープされた前記半導体層の第2の領域を含み、前記カソードの前記第2の領域は、前記カソードの前記第1の領域によって前記アノードから隔てられる、請求項13に記載のデバイス構造体。
- 前記少なくとも1つの第1の誘電体領域は、前記第1及び第2の幅に位置合せされた第1の側端部、並びに、前記第1の側端部に平行な第2の側端部を有し、前記カソードの前記第2の領域は、前記少なくとも1つの誘電体領域の前記第1の側端部と同一の広がりをもつ、請求項15に記載のデバイス構造体。
- 前記少なくとも1つの第1の誘電体領域は、前記第1及び第2の幅に位置合せされた第1の側端部、並びに、前記第1の側端部に平行な第2の側端部を有し、前記カソードの前記第2の領域は、前記少なくとも1つの誘電体領域の前記第1の側端部から前記カソードの前記第1の領域によって隔てられる、請求項15に記載のデバイス構造体、
- 前記SOI基板は、埋込み誘電体層と、前記半導体層から前記埋込み誘電体層によって隔てられたハンドル・ウェハとを含み、前記デバイス構造体は、
前記半導体層の上面から前記埋込み誘電体層まで延びる複数の誘電体領域を前記半導体層内にさらに備え、
前記誘電体領域は、前記p−n接合部を、総計で第2の幅を与える複数の区域に分割する、
請求項12に記載のデバイス構造体。 - 前記アノード及びカソードが横型ダイオードを構成する、請求項12に記載のデバイス構造体。
- 前記カソードは、前記第1の導電型にドープされた前記半導体層の第2の領域を含み、前記カソードの前記第2の領域は、前記カソードの前記第1の領域によって前記アノードから隔てられる、請求項12に記載のデバイス構造体。
- 前記カソードの前記第1の導電型はn型であり、前記アノードの前記第2の導電型はp型である、請求項12に記載のデバイス構造体。
- 機械可読データ記憶媒体上にエンコードされたハードウェア記述言語(HDL)設計構造体であって、前記HDL設計構造体は、コンピュータ支援設計システムにおいて処理されたとき、半導体オン・インシュレータ(SOI)基板の半導体層内に形成されるデバイス構造体の機械実行可能表現を生成する要素を含み、前記HDL設計構造体は、
前記半導体層内の、第1の導電型及び第1の幅でドープされた前記半導体層の第1の領域を含むカソードと、
前記半導体層内の、第2の導電型の第1の領域を含むアノードと
を備え、
前記アノードは、前記アノードの前記第1の領域がp−n接合部に沿って前記カソードの前記第1の領域と同一の広がりをもつように前記カソードに対して配置され、前記p−n接合部は、前記p−n接合部から横方向に離間した位置で計測された前記第1の領域の前記第1の幅より小さい、前記第1の幅に平行な方向に計測された第2の幅を有する、
HDL設計構造体。 - 前記設計構造体はネットリストを含む、請求項22に記載のHDL設計構造体。
- 前記設計構造体は、集積回路のレイアウト・データの交換に用いられるデータ形式で記憶媒体上に存在する、請求項22に記載のHDL設計構造体。
- 前記設計構造体は、プログラム可能ゲート・アレイ内に存在する、請求項22に記載のHDL設計構造体。
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TW335503B (en) | 1996-02-23 | 1998-07-01 | Semiconductor Energy Lab Kk | Semiconductor thin film and manufacturing method and semiconductor device and its manufacturing method |
US5773326A (en) | 1996-09-19 | 1998-06-30 | Motorola, Inc. | Method of making an SOI integrated circuit with ESD protection |
US6121661A (en) | 1996-12-11 | 2000-09-19 | International Business Machines Corporation | Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation |
US5952695A (en) | 1997-03-05 | 1999-09-14 | International Business Machines Corporation | Silicon-on-insulator and CMOS-on-SOI double film structures |
US6180487B1 (en) | 1999-10-25 | 2001-01-30 | Advanced Micro Devices, Inc. | Selective thinning of barrier oxide through masked SIMOX implant |
US6483147B1 (en) | 1999-10-25 | 2002-11-19 | Advanced Micro Devices, Inc. | Through wafer backside contact to improve SOI heat dissipation |
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US6452234B1 (en) | 2000-11-27 | 2002-09-17 | Advanced Micro Devices, Inc. | How to improve the ESD on SOI devices |
US6589823B1 (en) | 2001-02-22 | 2003-07-08 | Advanced Micro Devices, Inc. | Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug |
US6462381B1 (en) | 2001-02-22 | 2002-10-08 | Advanced Micro Devices, Inc. | Silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device with backside contact opening |
US6573566B2 (en) * | 2001-07-09 | 2003-06-03 | United Microelectronics Corp. | Low-voltage-triggered SOI-SCR device and associated ESD protection circuit |
SG107645A1 (en) * | 2002-09-10 | 2004-12-29 | Sarnoff Corp | Electrostatic discharge protection silicon controlled rectifier (esd-scr) for silicon germanium technologies |
US20050212051A1 (en) * | 2003-04-16 | 2005-09-29 | Sarnoff Corporation | Low voltage silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection of silicon-on-insulator technologies |
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US7825473B2 (en) * | 2005-07-21 | 2010-11-02 | Industrial Technology Research Institute | Initial-on SCR device for on-chip ESD protection |
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US7884599B2 (en) * | 2006-07-24 | 2011-02-08 | International Business Machines Corporation | HDL design structure for integrating test structures into an integrated circuit design |
US8015538B2 (en) | 2006-10-11 | 2011-09-06 | International Business Machines Corporation | Design structure with a deep sub-collector, a reach-through structure and trench isolation |
US7804119B2 (en) | 2008-04-08 | 2010-09-28 | International Business Machines Corporation | Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit |
US8389372B2 (en) * | 2010-11-22 | 2013-03-05 | International Business Machines Corporation | Heterojunction bipolar transistors with reduced base resistance |
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