JP2014204378A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a level shift circuit from malfunctioning owing to a drop in a potential difference (VB-COM voltage) between a positive side potential (VB potential) of an operating power supply for a P side drive circuit 100 and a common potential (COM potential).SOLUTION: A level shift circuit 101 includes a level shift section 110, a VB-COM voltage drop detection section 120, and a D latch circuit 130. The level shift section 110 has a resistive element 112 and a high voltage MOS transistor 111 controlled by an input signal DC, both connected in series between the VB potential and the COM potential, and outputs a level shift signal LS corresponding to a voltage drop across the resistive element 112. The VB-COM voltage drop detection section 120 outputs a lock signal LCK that inverts earlier than the level shift signal LS when the VB-COM voltage drops. The level shift signal LS is input into an input terminal of the D latch circuit 130, and the lock signal LCK is input into a strobe terminal of the D latch circuit 130.

Description

  The present invention relates to a level shift circuit provided in a drive circuit of a power semiconductor device (power device), for example.

  An inverter as a power device has a high-potential side (P-side) switching device connected to a totem pole between a high potential of about 600 to 1200 V (hereinafter “VP potential”) and a common potential (hereinafter “COM potential”) and a low potential. It is composed of a potential side (N side) switching device. Therefore, the inverter drive circuit includes a P-side drive circuit that drives the P-side switching device and an N-side drive circuit that drives the N-side switching device.

  The N-side switching device operates with the COM potential as the reference potential, but the P-side switching device operates with the potential at the connection point with the N-side switching device (hereinafter referred to as “VS potential”) as the reference potential. Is provided with a level shift circuit for converting an input signal into a signal having the VS potential as a reference potential.

  The operating power supply for the P-side drive circuit is a floating power supply that floats with respect to the COM potential because the VS potential is the reference potential. Therefore, the positive side potential (hereinafter, “VB potential”) of the operating power supply of the P-side drive circuit floats as the P-side and N-side switching devices are turned on (conductive) and turned off (non-conductive).

  A general level shift circuit includes a configuration in which a resistance element and a MOS transistor are connected in series between a VB potential and a COM potential. Then, the MOS transistor is driven by the input signal to control the current flowing through the resistance element, and a signal corresponding to the voltage drop generated in the resistance element is output as a signal after level conversion (level shift signal).

  The fluctuation of the VB potential causes a current (dv / dt displacement current) to flow through the parasitic capacitor of the MOS transistor constituting the level shift circuit, and causes an error signal to be output from the level shift circuit. For example, Patent Document 1 below proposes a technique for masking an erroneous signal generated due to a dv / dt displacement current using a D latch circuit.

JP 2009-117179 A

  In the level shift circuit of Patent Document 1, a DC signal is used as an input signal. Therefore, the input signal is fixed at the H (High) level during the period in which the P-side switching device is turned on. In the meantime, the MOS transistor of the level shift circuit is maintained in the ON state, a current flows through the resistance element, a voltage drop occurs, and the level shift signal is set to a desired logic level.

  However, if the VB potential fluctuates during the period when the P-side switching device is turned on and the potential difference between the VB potential and the COM potential (VB-COM voltage) is insufficient, sufficient current does not flow through the resistance element. In this case, the voltage drop of the resistance element is reduced, the level shift signal is inverted from the desired logic level, and an erroneous signal is generated.

  Since this erroneous signal is essentially different from that caused by the dv / dt displacement current, it cannot be masked by the technique of Patent Document 1. In addition, since the decrease in the VB-COM voltage occurs at the time of switching of the power device due to the configuration of the power device, it is difficult to take a countermeasure by improving the power supply environment.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a level shift circuit capable of preventing malfunction caused by a decrease in the VB-COM voltage.

  A level shift circuit according to the present invention includes a first load element connected in series between a power supply potential and a common potential, and a first switching element controlled by an input signal, and a voltage drop of the first load element. A level shift unit that outputs a corresponding level shift signal, and a voltage that outputs a lock signal whose logic level is inverted prior to the level shift signal when the voltage between the power supply potential and the common potential drops A drop detection unit, and a D latch circuit having an input terminal to which the level shift signal is supplied and a strobe terminal to which the lock signal is supplied.

  According to the present invention, the D latch circuit holds the output signal in accordance with the inversion of the lock signal before the error signal of the level shift signal is generated due to the decrease in the VB-COM voltage. As a result, the erroneous signal of the level shift signal is masked, and the malfunction of the level shift circuit is prevented.

1 is a diagram illustrating a configuration of a drive circuit according to a first embodiment. It is a circuit diagram of D latch circuit (mask circuit). It is a timing diagram for demonstrating operation | movement of a VB-COM voltage fall detection part. FIG. 4 is a diagram illustrating a configuration of a drive circuit according to a second embodiment. FIG. 6 is a diagram illustrating a configuration of a drive circuit according to a third embodiment. It is a figure which shows the structural example of a delay circuit. FIG. 6 is a diagram illustrating a configuration of a drive circuit according to a fourth embodiment. FIG. 10 is a diagram illustrating a configuration of a drive circuit according to a fifth embodiment.

<Embodiment 1>
FIG. 1 is a diagram illustrating a configuration of a drive circuit according to the first embodiment. The drive circuit drives a half-bridge type power device (inverter) composed of P-side and N-side switching devices 10 and 20 that are totem-pole connected between a VP potential and a COM potential.

  The P-side switching device 10 operates using the potential (VS potential) at the connection point with the N-side switching device 20 as a reference potential. On the other hand, the N-side switching device 20 operates using the COM potential as a reference potential. The drive circuit according to the first embodiment includes a P-side drive circuit 100 that drives the P-side switching device 10 and an N-side drive circuit 200 that drives the N-side switching device 20. Is not related to the invention of the present application and will not be described.

  A DC signal having a COM potential as a reference potential is input to the P-side drive circuit 100 as an input signal DC for controlling the P-side switching device 10. The P-side drive circuit 100 outputs a drive signal for the P-side switching device 10 based on the level shift circuit 101 that converts the input signal DC into a signal (level shift signal) having the VS potential as a reference potential. Output circuit 102. The P-side drive circuit 100 is supplied with the positive potential (VB potential) of the operating power supply from the power supply 150 (P-side power supply) with reference to the VS potential.

  The level shift circuit 101 includes a level shift unit 110, a VB-COM voltage drop detection unit 120, and a D latch circuit 130.

  The level shift unit 110 includes a high breakdown voltage field effect transistor (high voltage MOS transistor) 111 that is a switching element having a gate to which an input signal DC is supplied, and a load element connected between the drain of the high voltage MOS transistor 111 and the VB potential. And an inverter 113 that receives the voltage of the drain of the high voltage MOS transistor 111 (a connection node between the high voltage MOS transistor 111 and the resistance element 112) and outputs a level shift signal LS. The source of the high voltage MOS transistor 111 is connected to the COM potential (that is, the resistance element 112 and the high voltage MOS transistor 111 are connected in series between the VB potential and the COM potential).

  The VB-COM voltage drop detection unit 120 has a function of detecting a drop in the potential difference (VB-COM voltage) between the VB potential and the COM potential. When the VB-COM voltage is lowered, the VB-COM voltage drop detection unit 120 The detection signal whose logic level is inverted first is output. Hereinafter, this detection signal is referred to as “lock signal LCK”.

  As can be seen from FIG. 1, the VB-COM voltage drop detection unit 120 of the first embodiment has the same configuration as the level shift unit 110. Specifically, the VB-COM voltage drop detection unit 120 is a high voltage MOS transistor 121 having a gate to which an input signal DC is supplied, and a load element connected between the drain of the high voltage MOS transistor 121 and the VB potential. A resistance element 122 and an inverter 123 to which the voltage of the drain of the high voltage MOS transistor 121 is input are provided. That is, the resistance element 122 and the high voltage MOS transistor 121 are connected in series between the VB potential and the COM potential, and the inverter 123 is connected to a connection node between the high voltage MOS transistor 121 and the resistance element 122. The output of the inverter 123 becomes the lock signal LCK.

Here, as the high voltage MOS transistor 121 of the VB-COM voltage drop detection unit 120, a transistor having the same electrical characteristics (on resistance value and response speed) as the high voltage MOS transistor 111 of the level shift unit 110 is used. Further, as the resistance element 112 of the VB-COM voltage drop detection unit 120, an element having a resistance value equivalent to that of the resistance element 112 of the level shift unit 110 is used. However, as the inverter 123 of the VB-COM voltage drop detection unit 120, the inverter 123 having a lower threshold voltage than the inverter 113 of the level shift unit 110 is used. That is, if the threshold voltage of the inverter 113 is TH ₁₁₃ and the threshold voltage of the inverter 123 is TH ₁₂₃ , TH ₁₁₃ > TH ₁₂₃ .

  When the strobe terminal (STB terminal) is at the H (High) level, the D latch circuit 130 transmits the level of the input terminal (D terminal) to the output terminal (Q terminal), and the STB terminal is at the L (Low) level. When the signal is transmitted from the D terminal to the Q terminal, the operation is performed so as to maintain the previous output level.

  FIG. 2 is an example of a circuit diagram of the D latch circuit 130. The D latch circuit 130 can be composed of switch elements SW1 and SW2 and inverters IV1 to IV4. When the STB terminal is at the H level, the output (point a) of the inverter IV1 is at the L level and the output (point b) of the inverter IV2 is at the H level, so that the switch element SW1 is turned on and the switch element SW2 is turned off. In this state, the switch element SW1 transmits the signal at the D terminal to the Q terminal through the inverters IV3 and IV4.

  When the STB terminal is at L level, the output (point a) of the inverter IV1 is at H level and the output of the inverter IV2 (point b) is at L level, so that the switch element SW1 is off and the switch element SW2 is on. Become. In this state, the switch element SW1 cuts off the signal at the D terminal, and the switch element SW2 and the inverters IV3 and IV4 hold the output (point c) of the switch element SW1 and the level of the Q terminal so far.

  As shown in FIG. 1, the level shift signal LS output from the level shift unit 110 is input to the D terminal of the D latch circuit 130. The lock signal LCK output from the VB-COM voltage drop detection unit 120 is input to the STB terminal of the D latch circuit 130.

  An output signal (Q terminal signal) of the D latch circuit 130 is input to the output circuit 102. The output circuit 102 has a function as a buffer circuit that increases the drive capability of the output signal of the D latch circuit 130 and outputs the drive signal of the P-side switching device 10.

  Next, the operation of the P-side switching device 10 will be described.

  When the P-side switching device 10 is turned on, the input signal DC is set to H level. Then, in the level shift unit 110, the high voltage MOS transistor 111 is turned on, a voltage drop occurs in the resistance element 112, and the input of the inverter 113 becomes L level. Therefore, the level shift signal LS input to the D terminal of the D latch circuit 130 becomes H level. Similarly, in the VB-COM voltage drop detection unit 120, the high voltage MOS transistor 121 is turned on, a voltage drop occurs in the resistance element 122, and the input of the inverter 123 becomes L level. Therefore, the lock signal LCK input to the STB terminal of the D latch circuit 130 is also at the H level.

  Therefore, the level of the Q terminal of the D latch circuit 130 becomes the same H level as the D terminal. As a result, an H level signal is input to the output circuit 102, and the output circuit 102 turns on the P-side switching device 10.

  When the P-side switching device 10 is turned off, the input signal DC is set to L level. Then, in the level shift unit 110, the high voltage MOS transistor 111 is turned off, no voltage drop occurs in the resistance element 112, and the input of the inverter 113 becomes H level. Therefore, the level shift input to the D terminal of the D latch circuit 130 The signal LS becomes L level. Similarly, in the VB-COM voltage drop detection unit 120, the high voltage MOS transistor 121 is turned off, no voltage drop occurs in the resistance element 122, and the input of the inverter 123 becomes H level. The input lock signal LCK also becomes L level.

  Here, the threshold voltage of the inverter 123 is lower than the threshold voltage of the inverter 113, but the falling speed of the input signal DC is fast, so the falling timing of the level shift signal LS and the falling timing of the lock signal LCK. Are almost simultaneous. In this case, after the operating time of the inverter IV1 and the switch element SW1 of the D latch circuit 130 (FIG. 2) acts and the level of the Q terminal changes to the same L level as the D terminal, the switch element SW1 is turned off. Become. Therefore, an L level signal is input to the output circuit 102, and the output circuit 102 turns off the P-side switching device 10.

  FIG. 3 is a timing diagram for explaining the operation of the VB-COM voltage drop detection unit 120. Here, it is assumed that the VS potential fluctuates and the VB-COM voltage decreases during a period in which the input signal DC is set to the H level.

  As described above, when the input signal DC is at the H level, the high voltage MOS transistors 111 and 121 are both turned on, and the inputs of the inverters 113 and 123 are both at the L level. Therefore, the outputs of inverters 113 and 123 both become H level.

However, when the VB-COM voltage decreases as shown in FIG. 3, the current (level shift resistance current) flowing through each of the resistance elements 112 and 122 decreases, and the voltage drop across the resistance elements 112 and 122 decreases. Both of the input voltages (inverter input voltages) of the inverters 113 and 123 with reference to the voltage rise. At this time, if the input voltage of the inverter 113 reaches the threshold voltage (TH ₁₁₃ ) and the output of the inverter 113 is inverted to the L level, an error signal of the level shift signal LS occurs.

  In the present embodiment, since the threshold voltage of inverter 123 is set smaller than the threshold voltage of inverter 113, lock signal LCK is set to L level before level shift signal LS is inverted to L level. Invert. Therefore, in the D latch circuit 130, the STB terminal becomes L level before the error signal (L level level shift signal LS) is input to the D terminal. Even after the input, it remains at the H level. That is, an error signal of the level shift signal LS is prevented from being masked by the D latch circuit 130 and transmitted to the output circuit 102. Thereby, malfunction of the P-side drive circuit 100 is prevented.

  When the VB-COM voltage is lowered and returns to the normal value, the level shift signal LS output from the inverter 113 first becomes H level, and then the lock signal LCK output from the inverter 123 thereafter becomes H level. become. Therefore, also in this case, the Q terminal of the D latch circuit 130 is maintained at the H level, and the error signal of the level shift signal LS is not transmitted to the output circuit 102.

<Embodiment 2>
FIG. 4 is a diagram illustrating a configuration of a drive circuit according to the second embodiment. The drive circuit omits the high voltage MOS transistor 121 and the resistance element 122 of the VB-COM voltage drop detection unit 120, and the voltage obtained by dividing the voltage drop of the resistance element 112 of the level shift unit 110 into the inverter 123, as compared to FIG. Is entered. Specifically, the resistance element 112 of the level shift unit 110 is replaced with resistance elements 112a and 112b connected in series, and the input terminal of the inverter 123 is connected to the connection node between the resistance elements 112a and 112b.

In the second embodiment, the input voltage of the inverter 123 is always higher than the input voltage of the inverter 113. Therefore, even if the threshold voltage of the inverter ₁₂₃ is set to be the same as the threshold voltage of the inverter 113 (TH ₁₁₃ = TH ₁₂₃ ), the level shift signal LS is inverted to the L level when the VB-COM voltage decreases. Before this, the lock signal LCK is inverted to the L level, and the same effect as in the first embodiment can be obtained. Further, there is an advantage that the circuit formation area can be reduced as compared with the first embodiment.

<Embodiment 3>
FIG. 5 is a diagram illustrating a configuration of a drive circuit according to the third embodiment. In the drive circuit, a delay circuit 124 is provided in the VB-COM voltage drop detection unit 120 in the configuration shown in FIG. The delay circuit 124 delays the input signal DC and supplies it to the gate of the high voltage MOS transistor 121.

  The delay circuit 124 can be realized by, for example, the circuit shown in FIG. 6 includes an inverter IV11 that receives an input signal DC, an inverter IV12 that receives an output of the inverter IV11, and a capacitor C10 that is connected to a connection point (point e) between the inverter IV11 and the inverter IV12. . In the delay circuit 124, the input signal DC is delayed according to the time required for charging or discharging the capacitor C10.

  In the first embodiment, when the input signal DC is changed to L level in order to turn off the P-side switching device 10, the falling timing of the level shift signal LS and the falling timing of the lock signal LCK are almost the same. The operating time of the inverter IV1 and the switch element SW1 of the D latch circuit 130 (FIG. 2) acts to change the level of the Q terminal to the same L level as the D terminal, and then the switch element SW1 is turned off. However, if the falling timing of the lock signal LCK is earlier than the falling timing of the level shift signal LS due to, for example, manufacturing variations of the resistance element 112 and the high voltage MOS transistor 121, the operation of the D latch circuit 130 becomes unstable. Become.

  In the third embodiment, since the input signal DC delayed by the delay circuit 124 is input to the high voltage MOS transistor 121 of the VB-COM voltage drop detection unit 120, when the input signal DC is changed to L level, the lock is applied. The falling timing of the signal LCK becomes later than the falling timing of the level shift signal LS, and the operation of the D latch circuit 130 is stabilized.

  When the input signal DC is changed to the H level, the rising timing of the lock signal LCK is later than the rising timing of the level shift signal LS, so that the rising of the signal level at the D terminal of the D latch circuit 130 is slightly delayed. There is no problem in operation as the side drive circuit 100.

<Embodiment 4>
FIG. 7 is a diagram illustrating a configuration of a drive circuit according to the fourth embodiment. 1, the drive circuit omits the high voltage MOS transistor 121 and the resistance element 122 of the VB-COM voltage drop detection unit 120, and the input terminal of the inverter 123 is connected to the drain of the high voltage MOS transistor 111 of the level shift unit 110 ( A connection node between the resistance element 112 and the high-voltage MOS transistor 111). That is, the same signal as the inverter 113 is input to the inverter 123. The threshold voltage of inverter 123 is set to a value smaller than the threshold voltage of inverter 113 (TH ₁₁₃ > TH ₁₂₃ ), as in the first embodiment.

  Since high voltage MOS transistor 111 and resistance element 112 in FIG. 7 function in the same manner as high voltage MOS transistor 121 and resistance element 122 in the first embodiment (FIG. 1), operation of inverter 123 is the same as in the first embodiment. Become. Therefore, when the VB-COM voltage decreases, the lock signal LCK is inverted to the L level before the level shift signal LS is inverted to the L level, and the same effect as in the first embodiment can be obtained. Further, there is an advantage that the circuit formation area can be reduced as compared with the first embodiment.

<Embodiment 5>
FIG. 8 is a diagram illustrating a configuration of a drive circuit according to the fifth embodiment. The driving circuit is obtained by providing a speed-up circuit 140 in the P-side driving circuit 100 with respect to the configuration of FIG.

  The speed-up circuit 140 includes an inverter 141 that inverts the input signal DC, a pulse generation circuit 142 that outputs a one-shot pulse signal when the output of the inverter 141 rises, a level shift circuit that receives the pulse signal, and the level shift It comprises a P-channel type high voltage MOS transistor 147 driven by the output of the circuit.

  The level shift circuit in the high speed circuit 140 includes a high voltage MOS transistor 143 having a gate to which a pulse signal from the pulse generation circuit 142 is supplied, and a resistance element 144 connected between the drain of the high voltage MOS transistor 143 and the VB potential. And an inverter 145 to which the voltage of the drain of the high-voltage MOS transistor 143 is input, and an inverter 146 that receives the output of the inverter 145. The source of the high voltage MOS transistor 143 is connected to the COM potential.

  The high voltage MOS transistor 147 has a gate to which the output of the inverter 146 is supplied, and is connected in parallel to the resistance element 112 of the level shift unit 110.

  The high speed circuit 140 operates during the off period of the high voltage MOS transistor 111 of the level shift unit 110, at least when the high voltage MOS transistor 111 is turned off. That is, when the input signal DC changes from the H level to the L level, the output of the inverter 141 changes from the L level to the H level, and the pulse generation circuit 142 outputs a one-shot pulse signal in response to the rise. This pulse signal turns on the high voltage MOS transistor 143, a voltage drop occurs in the resistance element 144, and the input of the inverter 145 becomes L level. In response, the output of inverter 145 becomes H level, the output of inverter 146 becomes L level, and high voltage MOS transistor 147 is turned on.

  On the other hand, in the level shifter 110, when the input signal DC becomes L level, the high voltage MOS transistor 111 is turned off and the drain level rises. At this time, the high voltage MOS transistor 147 connected in parallel to the resistance element 112 is By turning on, the time constant of the circuit is reduced, and the rising speed of the drain level of the high-voltage MOS transistor 111 is increased. That is, since the rising speed of the input signal of the inverter 113 is increased, the falling timing of the level shift signal LS is advanced.

  As described above, in the fifth embodiment, the falling timing of the level shift signal LS when the input signal DC is set to the L level is advanced, so that the falling timing of the level shift signal LS is delayed from the rising timing of the lock signal LCK. Is prevented, and the operation of the D latch circuit 130 is stabilized. This effect is the same as the effect of the third embodiment using the delay circuit 124. However, in the fifth embodiment, the response speed of the level shift unit 110 is increased, so that the operation of the entire level shift circuit 101 is accelerated. The further effect that it becomes possible is also acquired.

  The high-voltage MOS transistor 143 of the high-speed circuit 140 is driven by a DC signal having a phase opposite to that of the input signal DC (that is, the pulse generation circuit 142 is omitted), and the high-voltage MOS transistor 111 is turned off while it is off. The MOS transistor 147 may be configured to be continuously turned on, but in that case, the time during which the high voltage MOS transistor 143 is turned on becomes longer, so that power consumption increases. As in this embodiment, driving the pulse generation circuit 142 with a pulse signal and turning on the high-voltage MOS transistor 143 only when the high-voltage MOS transistor 111 is turned off can suppress an increase in power consumption.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  10 P side switching device, 20 N side switching device, 100 P side drive circuit, 101 level shift circuit, 102 output circuit, 110 level shift unit, 111, 121, 143, 147 high voltage MOS transistor, 112, 122, 144 resistance element 113, 123, 141, 145, 146 inverter, 120 VB-COM voltage drop detection unit, 121 high voltage MOS transistor, 124 delay circuit, 130 D latch circuit, 140 high speed circuit, 142 pulse generation circuit, 150 P side power supply, 200 N side drive circuit.

Claims (7)

A level having a first load element connected in series between a power supply potential and a common potential and a first switching element controlled by an input signal, and outputting a level shift signal corresponding to a voltage drop of the first load element A shift section;
When the voltage between the power supply potential and the common potential drops, a voltage drop detection unit that outputs a lock signal whose logic level is inverted before the level shift signal;
A level shift circuit comprising: a D latch circuit having an input terminal to which the level shift signal is supplied and a strobe terminal to which the lock signal is supplied. The level shift unit includes:
A first inverter that receives a voltage at a connection node between the first load element and the first switching element and outputs the level shift signal;
The voltage drop detector is
A second load element connected in series between the power supply potential and the common potential and a second switching element controlled by the input signal;
A voltage at a connection node between the second load element and the second switching element is input, and the second inverter outputs the lock signal.
The level shift circuit according to claim 1, wherein a threshold voltage of the second inverter is set lower than a threshold voltage of the first inverter. The voltage drop detector is
The level shift circuit according to claim 2, further comprising a delay circuit that delays the input signal and supplies the input signal to the second switching element. The level shift unit includes:
A first inverter that receives a voltage at a connection node between the first load element and the first switching element and outputs the level shift signal;
The voltage drop detector is
The level shift circuit according to claim 1, further comprising a second inverter that receives a voltage obtained by dividing a voltage drop of the first load element and outputs the lock signal. The level shift unit includes:
A first inverter that receives a voltage at a connection node between the first load element and the first switching element and outputs the level shift signal;
The voltage drop detector is
A voltage at a connection node between the first load element and the first switching element is input, and a second inverter that outputs the lock signal is provided.
The level shift circuit according to claim 1, wherein a threshold voltage of the second inverter is set lower than a threshold voltage of the first inverter. A third switching element connected in parallel to the first load element;
The level shift circuit according to claim 1, wherein the third switching element is controlled to be turned on during an off period of the first switching element. The level shift circuit according to claim 6, wherein the third switching element is controlled to be turned on only when the first switching element is turned off.

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