JP2014197212A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a current storage circuit whose area can be reduced, whose configuration is made simple, since the number of elements is reduced, which can be operated under low power consumption, and in manufacturing of which high yield can be expected, and to achieve improvement of pixel aperture ratio, high reliability, high performance, and the like, in a display device by applying the current storage circuit to a current drive type display device such as an OLED display device.SOLUTION: A new semiconductor element in a shape such as a transistor having a plurality of drains or sources, is used. When the semiconductor elements are used for a writing element and a driving element, reading and storing of current value and current output can be performed by two semiconductor elements, thereby reduction of area can be markedly facilitated.

Description

The present invention relates to a structure of a semiconductor element and an electric circuit using the element. The present invention also relates to a light-emitting device provided with a light-emitting element and the semiconductor element that controls the light-emitting element. Or it relates to a display device. Further, the present invention relates to an electronic device equipped with the light emitting device and the display device.

In recent years, the importance of display devices that display images has increased. As a display device, a liquid crystal display device that displays an image using a liquid crystal element, taking advantage of high image quality, thinness, light weight, etc.,
It is widely used as a display device for various applications including mobile phones and personal computers.

On the other hand, development of a light-emitting device and a light-emitting display device using a light-emitting element which is a self-light-emitting element is also underway. This self-luminous element includes organic materials, inorganic materials, thin film materials, bulk materials, dispersed materials,
There are a wide variety of devices.

Among them, a typical self-luminous element is an organic light emitting diode (OLED) element. OLE
OLED display devices that use D elements as light-emitting elements have features such as high response speed, high viewing angle, and low-voltage drive suitable for video display, in addition to features that are thinner and lighter than existing liquid crystal display devices. Mobile phones and personal digital assistants (PDAs)
A wide range of applications such as TVs and monitors are expected, and it is attracting attention as a next-generation display.

In particular, an active matrix (AM) type OLED display device has a passive matrix (P
High resolution and large-screen display, which is difficult with the M) type, is possible, and it has high reliability with low power consumption operation that exceeds that of the PM type.

One of various elements necessary for putting a light-emitting device such as an OLED display device into practical use is to maintain the light emission luminance substantially constant. In particular, the OLED element has a problem that the light emission luminance is considerably dependent on the environmental temperature. Many OLED elements have a large amount of current under a high temperature under a constant voltage condition. The greater the amount of current flowing through the OLED element, the higher the luminance of the OLED element.

Then, the OLED light emitting device becomes unstable and very inconvenient, in which the display on the entire screen changes in brightness as the temperature changes.

In addition, current OLED elements generally have a problem in that light emission luminance tends to decrease over time due to light emission. The degree of the decrease in light emission luminance is a serious problem, although it varies depending on the configuration of the OLED element.

If the light emission luminance decreases with time due to the amount of light emission, and the light emission luminance of the light emitting element cannot be maintained substantially constant, the display of the light emitting device not only becomes unstable in overall brightness but also in each pixel. The gradation display will be hindered. For example, if a still image with a significant difference in light emission luminance is displayed for a long time at each pixel in the screen, the image will be burned and become very unsightly.

In particular, in the case of an OLED display device that displays a color image using three types of light emitting elements corresponding to R (red), G (green), and B (blue), it is possible to increase the efficiency of light emission and reduce the power consumption. From the viewpoint, normally, a “three-color coating method” is used in which different OLED elements are used for each color. Then
The color shift is caused by the temperature dependency of the light emission luminance for each color. Alternatively, the light emission luminance of each OLED element decreases with time at a different speed for each color, causing the display color of the light emitting device to cause a color shift.

In view of these points, the present invention has a simple configuration of a light-emitting device in which a light-emitting element maintains a substantially constant luminance without being influenced by changes in environmental temperature and without greatly decreasing the luminance of light emitted over time. It is an issue to provide. Another object is to provide a light-emitting device capable of performing a desired color display without color misregistration with a simple configuration. It is another object of the present invention to provide a structure of a semiconductor element that can be used for realizing such a light-emitting device and an electric circuit using the element.

The decrease in light emission luminance of the OLED element over time is compared with the case where the current applied to the OLED element is constant (constant current driving) when the voltage applied to the OLED element is constant (constant voltage driving). And get bigger. This is due to the following reason.

In general, the light emission luminance L of an OLED element is the amount of current I (V) that flows through the OLED element.
Is proportional to If this proportionality constant is c (V), L = c (V) I (V)
The relationship is established. Here, V is a voltage applied to the OLED element that is required to emit light with luminance L.

However, as the OLED element continues to emit light, both c (V) and I (V) gradually decrease. Here, in the case of constant voltage driving of the OLED element, c (V) and I (V)
Both of these decreases are reflected in the decrease in L. On the other hand, in the case of constant current driving of the OLED element, c (
A decrease in only V) is reflected in a decrease in L. Therefore, if the magnitude of the decrease in L is compared, the constant voltage drive is larger than the constant current drive.

The background of the decrease in c (V) is that the OLED element is originally vulnerable to moisture, oxygen, light, heat, etc., and these tend to tend to initiate or accelerate the modification or deterioration of the element itself. However, the progress rate of element deterioration is significantly affected by the type of light emitting material, the material of the electrode, the structure of the device that drives the light emitting device, the manufacturing environment, the manufacturing conditions, and the like. Therefore, it is possible to suppress the decrease in c (V) over time to some extent by these improvements.

Further, regarding the temperature dependence of the light emission luminance of the OLED element, the temperature dependence is remarkable in the case of constant voltage driving, but the temperature dependence is often insignificant in the case of constant current driving. this is,
In L = c (V) I (V), it can be understood that I (V) has a large temperature dependence, but c (V) has almost no temperature dependence.

Then, if gradation display is performed by driving the light emitting element of the OLED light emitting device by current driving instead of voltage driving, the emission luminance is not greatly reduced over time, and it is not affected by changes in environmental temperature, It should be possible for the light emitting element to maintain a substantially constant brightness.

Note that light-emitting elements other than OLED elements also have a small temperature dependency, although depending on the type, generally, constant-current driving is used rather than constant-voltage driving. In that respect, constant current driving is still preferable.

In a light emitting device such as an AM type OLED display device, a current storage circuit can be incorporated in a pixel to drive a current of the light emitting element. A current storage circuit incorporated in a pixel can be manufactured using an active element such as a thin film transistor (TFT).

However, not only the current storage circuit but also a pixel circuit is generally desired to be as simple as possible from the viewpoint of reducing manufacturing costs and suppressing the occurrence rate of defects.

In addition, in order to save power and stabilize light emission, improvement in the light emission area ratio (aperture ratio) is also strongly required,
The smaller the circuit area, the better. When the light emitting area ratio (aperture ratio) is small, it is necessary to cause the light emitting element to emit light at a high current density in order to obtain a predetermined luminance, and the modification and deterioration of the light emitting element are likely to be promoted.

Here, the most direct and effective method for increasing the light emission area ratio (aperture ratio) is to build a pixel circuit on the side opposite to the light emission direction. However, at present, this is not an effective solution. This is because an OLED element can be stably formed by forming a pixel circuit on the light emitting direction side.

Furthermore, another reason why it is preferable that the circuit area is small is that the pixel circuit can be highly integrated to achieve high functionality.

Therefore, in the present invention, first, a pixel is provided with a light emitting element, a driving element for controlling the light emitting element, and a writing element. Normally, except for the light emitting element, TFTs are used. However, in this case, the number of TFTs is increased, and the circuit area including wiring is increased. Therefore, in the present invention, the circuit is simplified and the area is reduced by using the following new element.

The novel element is shaped like a transistor having a plurality of drains, and in this specification, this is referred to as a multi-drain transistor. In other words, the multi-drain transistor is a semiconductor element having a gate electrode and at least three impurity regions.

More specifically, the multi-drain transistor includes a semiconductor layer, a gate insulating film formed so as to cover the semiconductor layer, and a gate electrode in contact with the gate insulating film, the semiconductor layer including a channel formation region, And at least three impurity-doped source or drain regions, the channel formation region and the gate electrode overlap with the gate insulating film interposed therebetween, and the at least three impurity regions are the channel formation region It can be expressed that it is a semiconductor element characterized by being in contact with. One of the impurity regions is a source and the other is a drain.

Here, it should be noted that the multi-drain transistor may be more appropriately referred to as a multi-source transistor or a multi-source multi-drain transistor depending on the method of use. In general, the source and drain of a transistor (especially a TFT) are often the same in structure and are not always clearly distinguishable. In the present specification, the multi-source transistor and the multi-source multi-drain transistor are collectively referred to as a multi-drain transistor.

The shape of the multi-drain transistor is not particularly limited including the size and the presence or absence of symmetry. The semiconductor that forms the multi-drain transistor may be of any composition material, bulk, amorphous (amorphous) thin film, polycrystalline (poly) thin film, or the like. However, it is most practical to use a polycrystalline silicon (polysilicon) thin film semiconductor as the driving element for controlling the light emitting element. The channel type of each drain or source of the multi-drain transistor is not particularly limited including the presence or absence of symmetry.

A multi-drain transistor having two drains in particular is referred to as a double drain transistor. Hereinafter, the present invention will be described focusing on an example of a pixel circuit with a current storage function using a double drain transistor using a polysilicon thin film double drain transistor.

By utilizing the multi-drain transistor which is a semiconductor element of the present invention, a circuit that is difficult to configure with only a conventional single drain transistor can be realized. Alternatively, a configuration with only a conventional single drain transistor is possible, but a circuit that becomes complicated or requires a large area can be provided without such inconvenience by using a multi-drain transistor.

The current memory circuit of the present invention is configured using a writing element and a driving element, and a multi-drain transistor is used for one or both of the two elements. Therefore, it is useful for simplification, area reduction, and high integration of various circuits that require a current storage function such as a current signal buffer. Further, since the number of elements is small, a high manufacturing yield can be expected.

In the light emitting device of the present invention, the current flowing through the light emitting element in the light emitting display device can be favorably maintained even in the following cases by driving the light emitting element with current. When the electrical resistance of the light-emitting element greatly depends on the environmental temperature, when the light-emitting element decreases in luminance over time when driven by voltage. By maintaining a good current flowing through the light emitting element, the light emission luminance can be kept good. As a result, color misregistration can be avoided in a color display device in which RGB sub-pixels are formed independently.

In addition, by driving the light emitting element with current, even when the characteristics of the driving element that controls the current flowing through the light emitting element are different between pixels, the magnitude of the current flowing through the light emitting element varies greatly between pixels. Occurrence can be prevented, and the occurrence of uneven brightness on the display screen can also be suppressed.

Furthermore, since the current flowing through the light emitting element can be maintained at a desired value, it is possible to prevent the gradation from being changed due to a potential drop due to the wiring resistance. This is also a feature compared to the case where the light emitting element is driven by voltage.

In addition, the light emitting device of the present invention can reduce the area of the pixel circuit by using the semiconductor element multi-drain transistor of the present invention for the pixel circuit. As a result, since the aperture ratio increases, the density of current flowing through the light emitting element decreases, and as a result, power saving and deterioration suppression of the light emitting element itself can be achieved.

The display device of the present invention can also reduce the area of the pixel circuit, increase the integration, and improve the performance by using the semiconductor element multi-drain transistor of the present invention for the pixel circuit.

The electronic device of the present invention has the features of high performance and high reliability by mounting the light emitting device or the display device of the present invention having the above features.

The figure which shows the example of a structure schematic of the light-emitting device of this invention. FIG. 6 illustrates a pixel circuit example of a light-emitting device of the present invention. The figure which shows the timing chart of the signal input into a gate signal line FIG. 4 is a schematic diagram of a pixel in a writing period and a display period. FIG. 6 is a block diagram of an example of a source signal line driver circuit. FIG. 6 is a block diagram of an example of a source signal line driver circuit. 4 is a block diagram of an example of a writing gate signal line driving circuit and an example of an initialization gate signal line driving circuit. FIG. FIG. 11 shows a structural example of a semiconductor element of the present invention. FIG. 11 shows a structural example of a semiconductor element of the present invention. FIG. 11 shows a structural example of a semiconductor element of the present invention. 4A and 4B illustrate a manufacturing process of a light-emitting device of the present invention. 4A and 4B illustrate a manufacturing process of a light-emitting device of the present invention. The figure which shows the external appearance of the light-emitting device of this invention. FIG. 14 illustrates an electronic device of the invention. FIG. 6 illustrates a pixel circuit example of a light-emitting device of the present invention. FIG. 11 shows a structural example of a semiconductor element of the present invention. The figure which shows the structural example of the electric circuit of this invention. The figure which shows the example which connects 3 nodes with the conventional TFT.

(Embodiment 1)
An example of a pixel circuit with a current storage function in the light emitting device of the present invention is shown in FIG.

2 includes a source signal line Si (one of S1 to Sx), a write gate signal line Pj (one of P1 to Py), and an initialization gate signal line Ej (E1 to E1). Ey) and a power supply line Vi (one of V1 to Vx). The pixel 201
Includes a writing element 101, a driving element 102, an initialization element 103, a capacitor element 104, and a light emitting element 105.

The initialization element 103 is not an essential element of the present invention, but is added in FIG. 2 because it is useful. In some cases, the capacitor 104 may not be provided explicitly but may be provided by a parasitic capacitance or the like.

Further, if necessary, other elements or circuits may be attached in addition to the driving element, the writing element, the initialization element, the capacitor element, and the light emitting element.

In the present invention, at least one of the driving element and the writing element is a multi-drain transistor, but both of them are not necessarily multi-drain transistors, and one of them is a normal transistor (especially when distinction is necessary, (Hereinafter referred to as a single drain transistor). FIG. 15 shows an example in which only the driving element is a multi-drain transistor.

In the pixel circuit of FIG. 2, double drain transistors are used for both the driving element and the writing element. Any one drain of the double drain transistor is distinguished as a first drain and the other drain as a second drain. There is no limitation as to which drain is the first drain and the second drain, and each drain is arbitrarily designated. Depending on the method of use, it may be difficult to distinguish between the source, the first drain, and the second drain. In that case, the source and the drain are arbitrarily specified.

Channel portions connected to the source, the first drain, and the second drain in one double drain transistor (hereinafter referred to as a source channel, a first drain channel, and a second drain channel, respectively. The channel length and the channel width are all arbitrary as long as they are collectively referred to as all channels of the double drain transistor), and need not be uniform or symmetrical. Each channel length and channel width can be freely determined according to the application.

In the present embodiment, all channels of the double drain transistor (hereinafter simply referred to as write element) of the write element 101 are n-type, and all channels of the double drain transistor (hereinafter simply referred to as drive element) of the drive element 102 are p-type. The channel of the type and initialization element 103 is n-type. However, the writing element 101 and the initialization element 103 may be p-channel type. In addition, all the channels of the driving element 102 can be n-type. Furthermore, the double drain transistor itself does not necessarily have to be of the same type for all channels.

In the double drain transistor, the connection of the three nodes can be controlled by a voltage applied to the gate electrode. The gate electrode of the writing element 101 is connected to the writing gate signal line Pj. The source, the first drain, and the second drain of the writing element 101 are
The source signal line Si, the drain of the initialization element 103, and the first drain of the driving element 102 are connected to each other (see also FIG. 4A). The switching element 101 includes a pixel 20
1 has a function of controlling the writing of signals to 1.

The gate electrode of the driving element 102 is connected to the drain region of the initialization element 103. The source region, the first drain region, and the second drain region of the driving element 102 are connected to the power supply line Vi, the second drain of the writing element 101, and the pixel electrode of the light emitting element 105, respectively. The driving element 102 has a function of controlling a current flowing through the light emitting element.

Various light-emitting elements 105 can be used. For example, OLED elements, inorganic light emitting diode elements, other light emitting diode elements, inorganic EL elements, other solid light emitting elements, FED elements, and other vacuum light emitting elements. Here, the light emitting element 105 has an OL.
An ED element is used. The OLED element has an anode, a cathode, and an organic light emitting layer sandwiched between the anode and cathode.

In this embodiment, the OLED element 105 uses an anode as a pixel electrode and a cathode as a counter electrode. In general, when all the channels of the driving element 102 are p-type, it is preferable to use the anode as a pixel electrode and the cathode as a counter electrode. Conversely, the driving element 102
When all the channels are n-type, it is preferable to use the cathode as the pixel electrode and the anode as the counter electrode. However, the present invention is not limited to this. Other uses are not impossible.

Note that the OLED element 105 can be manufactured using a known light emitting material for the organic light emitting layer. Further, the organic light emitting layer has various structures such as a single layer structure, a laminated structure, or an intermediate structure, but any known structure may be used in the present invention.
Luminescence in the organic light-emitting layer includes light emission when returning from the singlet excited state to the ground state (
Fluorescence) and light emission (phosphorescence) when returning from the triplet excited state to the ground state, both of which can be applied to the present invention.

The gate electrode of the initialization element 103 is connected to the initialization gate signal line Ej. The source of the initialization element 103 is connected to the gate electrode of the driving element 102 and the drain power supply line Vi.

One of the two electrodes included in the capacitor 104 is the power supply line Vi and the other is the driving element 102.
Connected to the gate. More specifically, the two electrodes of the capacitor 104 are connected to the gate of the driving element 102 and the source of the driving element 102.

In the present embodiment, the voltage of the power supply line Vi (power supply voltage) and the voltage of the counter electrode are kept constant. Keeping the voltage of the power supply line Vi (power supply voltage) and the voltage of the counter electrode at a constant value
Although it is not essential from the beginning, this is done to simplify the explanation. The reliability of the light-emitting element may be improved by changing the power supply voltage or the like and applying a reverse bias to the light-emitting element 105 for a certain period.

In this embodiment, since the pixel electrode is the anode of the OLED element, the voltage of the counter electrode is set to a predetermined value lower than the power supply voltage. When the pixel electrode is a cathode of an OLED element, the voltage of the counter electrode is a predetermined value higher than the power supply voltage.

Next, FIG. 1 shows a schematic diagram of the overall configuration of the light emitting device of the present invention on which the pixel 201 of FIG. 2 is mounted. Reference numeral 200 denotes a pixel portion, and pixels having the circuit of FIG. 2 are formed in a matrix.
Reference numeral 202 denotes a source signal line drive circuit, 203 denotes a write gate signal line drive circuit, and 204 denotes an initialization gate signal line drive circuit.

In FIG. 1, one source signal line driver circuit 202, one write gate signal line driver circuit 203, and one initialization gate signal line driver circuit 204 are provided, but the present invention is not limited to this configuration. The number of source signal line drive circuits 202, write gate signal line drive circuits 203, and initialization gate signal line drive circuits 204 can be arbitrarily set in accordance with the configuration of the pixel 201. For example, when the pixel does not include the initialization element 103 (FIG. 1), the second write gate signal line drive circuit 2 is replaced with the initialization gate signal line drive circuit 204.
03 may be installed.

The source signal line drive circuit 202, the write gate signal line drive circuit 203, and the initialization gate signal line drive circuit 204 can be formed on a single glass substrate by using polysilicon TFTs. However, part or all of the source signal line driver circuit 202, the write gate signal line driver circuit 203, and the initialization gate signal line driver circuit 204 are formed on a different substrate (chip or the like) from the pixel portion 200. The pixel unit 2 is connected via a connector such as an FPC.
00 may be connected.

Although not shown in FIG. 1, the pixel portion 200 is provided with source signal lines S1 to Sx, power supply lines V1 to Vx, write gate signal lines P1 to Py, and initialization gate signal lines E1 to Ey. ing. Note that the numbers of the source signal lines S1 to Sx and the power supply lines V1 to Vx are not necessarily the same. The write gate signal lines P1 to Py and the initialization gate signal lines E1 to E1
The number of Ey is not necessarily the same. Further, it is not always necessary to have all of these wirings, and other different wirings may be provided in addition to these wirings.

The power supply lines V1 to Vx are kept at a predetermined voltage. Note that in this embodiment mode, a structure of a light-emitting device that displays a monochrome image is shown; however, the present invention may be a light-emitting device that displays a color image. In that case, the voltage levels of the power supply lines V1 to Vx may not be kept the same, but may be changed for each corresponding color.

Next, a driving method of the above-described light emitting device of the present invention will be described with reference to FIGS. The operation of the light-emitting device of the present invention can be described separately for each pixel of each line by an address period Ta, a display period Td, an initialization period Te, and a non-display period Tu. FIG. 4 is a timing chart of a gate signal line and an initialization gate signal line. Note that in this specification, the writing gate signal line and the initialization gate signal line are collectively referred to as a gate signal line. A period in which the gate signal line is selected, in other words, a period in which all the semiconductor elements whose gate electrodes are connected to the gate signal line is in an ON state is indicated by ON. On the contrary, a period in which the gate signal line is not selected, in other words, a period in which all the semiconductor elements connected to the gate signal line in the gate electrode are in the OFF state is indicated by OFF.

FIG. 3 is a diagram simply illustrating a timing chart of the writing period Ta, the display period Td, the initialization period Te, and the non-display period Tu in the pixel 201. In the present embodiment, the writing period Ta and the display period Td, and the initialization period Te and the non-display period Tu are separately provided.
It is not necessary to be limited to this. The initialization period Te is included in the display period Td, or the writing period T
a may be included in the non-display period Tu.
4A shows how the current flows in the pixel 201 during the writing period Ta, and FIG. 4B shows how the current flows in the pixel 201 during the display period Td. FIG. An arrow shown in the pixel 201 is a direction in which a current flows.

First, when the write period Ta starts in the pixels on the first line, the write gate signal line P1 is selected, and the write element 101 is turned on. Since the initialization gate signal line E1 is not selected, the initialization element 103 is turned off.
Then, based on the video signal input to the pixel 201 from the source signal line driver circuit 202,
The source signal lines S1 to Sx and the power supply line V1 are connected via the writing element 101 and the driving element 102.
Current flows between ~ Vx.

The state of current flowing in the pixel 201 during the writing period Ta is shown in FIG.
A little more in detail using. When the write gate signal line P1 is selected, the gate of the write element 101 is opened and the write element 101 is turned on. Then, the driving element 102
In this case, the gate and the first drain are short-circuited, and as a result, the combined portion of the source channel and the first drain channel operates as a diode.

Hereinafter, for convenience, the source, the nth drain, the channel portion (source channel, nth drain channel) and the gate between the source and the nth drain of the double drain transistor are referred to as the nth element transistor of the double drain transistor. The source, the first drain, the channel portion and the gate between the source and the first drain of the driving element 102 become the first element transistor of the driving element 102.

Since the first element transistor of the driving element 102 operates as a diode, the video signal current input from the source signal line Si to the pixel 201 is directly used as the writing element 101.
The current flows to the power supply lines V1 to Vx through the first element transistor of the driving element 102. At the same time, the gate voltage of the first element transistor of the driving element corresponding to the video signal current input from the source signal line Si to the pixel 201 is accumulated in the capacitor 104 via the writing element 101. The voltage accumulated in the capacitor 104 is the driving element 102.
First because it is the gate-source voltage V _GS of the element transistor, in accordance with the voltage of the capacitor 104, the first element transistor of the driving element 102 is turned on.

Note that in the writing period Ta, the first element transistor of the driving element 102 operates in the saturation region because the gate and the drain are connected. Therefore, the gate-source voltage V _GS, mobility mu, the gate capacitance per unit area C _0, the ratio of the channel width W and channel length L of the W / L channel formation region, when the threshold V _TH , the drain current I _dn of the first element transistor of the driving element 102 is represented by the following _{I dn = μC 0 W / L} (V GS -V TH) 2/2.

Μ in _{I dn = μC 0 W / L} (V GS -V TH) 2/2, C 0, W / L, V TH are all a fixed value determined by the individual elements. Therefore, if μ and V _TH vary among the individual elements, even if I _dn for the same V _GS is not necessarily the same value in all the elements. However, if the drain current I _dn of the first element transistor of the driving element 102 is kept the same as the video signal current I _vd , the first element transistors of all the driving elements 102 are not affected by variations in μ and V _TH. At I
All _dn are the same.

When the writing period Ta ends in the pixels on the first line, the selection of the writing gate signal line P1 ends. Then, the display period Td is started next. In the display period Td, the write gate signal line P1 is not selected, so the write element 101 is off.
Also during the display period Td, the initialization gate signal line E1 is not selected, so the initialization element 103 is off.

A current flow of the pixel 201 in the display period Td is described with reference to FIG. V _GS determined in the writing period Ta is applied to the gate electrode of the driving element 102 as the capacitive element 10.
4 is held. However, in the display period Td, since the writing element 101 is off, no current flows to the first element transistor of the driving element 102, and the current flows to the light emitting element through the second element transistor. Will flow.

Here, the second element transistor of the driving element 102 operates in the saturation region.
In order to do so, the video signal current I _vd and the counter electrode voltage to be written to the pixel must be set appropriately in advance.

Since the operation of the saturation region, the drain current I _dn of the second element transistor of the driving element 102 is represented by _{I dn = μC 0 W / L} (V GS -V TH) 2/2. I _dn = μC ₀ W / L (V _GS −
V _TH) is the drain current I _dn according to the ^2/2, mu, but should depend on the value of such V _TH, the V _GS when writing on the other hand, the drain current I _dn of the first element transistor I _vd . Therefore, in the driving element 102 of each pixel, the first element transistor and the second element transistor
If the values of μ, V _TH, etc. of the element transistors are equal, variations in μ, V _TH, etc. between the second element transistors of the driving element 102 in each pixel are reflected in the drain current I _dn of the second element transistor. Not.

That is, it is necessary to suppress variations such as μ and V _TH from the driving elements 102 of the pixels in the entire screen in the light emitting device to the first and second element transistors of the driving elements 102 in each pixel. In the meantime, it was able to compress significantly. Moreover, within a single double drain transistor, the μ, V _TH, etc. of the first element transistor and the second element transistor are originally less varied.

Thus, in the display period Td, the drain current I _dn of the second element transistor of the driving element 102 accurately corresponds to the video signal current I _vd . That is, a desired appropriate current flows from the power supply line Vi to the counter power supply of the light emitting element 105 through the second element transistor of the driving element 102. As a result of the current flowing through the light emitting element 105 being accurate, the light emitting element 105 emits light with accurate luminance. Of course, if the drain current I _dn is zero, the light emitting element 105 does not emit light.

The video signal current I _vd needs to be an accurate current value in principle.
An exception is when the content of the video signal is the darkest gradation “non-lighting”. In this case, the video signal may be voltage value data because the element transistor of the driving element 102 may be turned off.

Further, if the channel length and channel width of the first drain channel and the second drain channel of the driving element are made equal, the video signal current I _vd read during the writing period and the driving current I supplied to the light emitting element during the display period. _el is equal. However, the ratio between the video signal current I _vd to be read and the drive current I _el supplied to the light emitting element in the display period can be adjusted by not intentionally adjusting the channel length and channel width of the first drain and the second drain. Yes (see FIG. 16).

This ratio adjustment is very useful in practice. For example, when a low-luminance display is performed on a small and high-definition light-emitting display device, the drive current I _el supplied to the light-emitting element during the display period is a very small value. Therefore, when considering a load such as parasitic capacitance, the video signal current I is more than I _el.
This is because the pixel cannot be written within the display period unless _vd is increased.

When the writing period Ta ends in the pixels on the first line, P2 is selected as the writing gate signal line, and the writing period Ta starts on the pixels on the second line. Therefore, 2
The writing element 101 is turned on at the pixel on the line. Since the initialization gate signal line E2 is not selected, the initialization element 103 is off. Then, based on the video signal input from the source signal line driver circuit 202 to the pixel 201, the signal lines S1 to Sx and the power line V
1 to Vx, a video signal current flows through the writing element 101 and the driving element 102 in the pixels on the second line.

After that, the writing period Ta ends in the pixels on the second line, and the display period Td starts. In the display period Td, the video signal current I _vd is stored in the pixels in the second line as well as in the pixels in the first line described above, and the light emitting element 105 emits light with a predetermined luminance. When the writing period Ta ends in the pixels on the second line, the writing period Ta starts on the pixels on the third line.

Thereafter, similarly, the display period Td for the pixel on the third line and the writing period Ta for the pixel on the fourth line start, the writing period Ta for the pixel on the fourth line ends, and the display periods Td and 5 for the pixel on the fourth line. The operation of starting the writing period Ta of the pixels on the line is repeated. When the writing period Ta ends in order up to the pixel on the y-th line which is the last line, all the writing periods for one frame are ended.

Visually, images in the display period Td for one frame are temporally overlapped and regarded as an integral image, so that one frame of image can be displayed in the entire display period Td for one frame. In a typical moving image display, 60 Hz drive is performed, that is, 60 frames are displayed in one second.

The above is the entire operation when the initialization element 103 is not provided. When the initialization element 103 is present, the following initialization operation can be further added. If there is no initialization operation, the images of each frame will be displayed continuously, and there is a problem that the motion of the image does not have sufficient smoothness, and the moving image display is somewhat low quality. . If a non-display interval is provided between frames in the initialization operation, this deterioration in moving image quality can be suppressed easily and effectively.

The initialization operation is controlled by a gate signal output from the initialization gate signal line drive circuit 204. First, when the first gate initialization gate signal line E1 is selected by the gate signal output from the initialization gate signal line driving circuit 204, the initialization period Te starts in the first line pixels. . When the initialization gate signal line E1 is selected, the initialization element 103 is turned on. Then, the voltages of the power supply lines V1 to Vx are applied to the gate electrode of the driving element 102 via the initialization element 103. Then, the driving element 102 is forcibly turned off, and no current is supplied to the light emitting element 105. As a result, the light emitting element 105 does not emit light.

Next, the initialization gate signal line to be selected is changed from the first line E1 to the second line E1.
Move to 2. Thereby, in the first line, the initialization period Te ends, and the non-display period Tu starts. At the same time, the initialization period Te is started in the pixels on the second line.

When the initialization gate signal line E2 is selected, the initialization element 10 in the pixels on the second line is selected.
3 turns on. Since the write gate signal line P2 is not selected, the write element 10
1 is off. At this time, the voltages of the constant power supply lines V1 to Vx are applied to the gate electrode of the drive element 102 via the initialization element 103.
Then, the driving element 102 is turned off, and no current is supplied to the light emitting element 105.
As a result, the light emitting element 105 does not emit light.

Next, the initialization period Te is started in order from the second line E2 to the third line E3 so that the selected initialization gate signal line moves from the second line E2 to the third line E3. When the conversion period Te ends, the operation of starting the non-display period Tu is repeated. Thus, the initialization operation is performed in all pixels.

When the initialization element 103 is provided and the initialization operation is performed, the writing period Ta and the display period T
d, the initialization period Te, and the non-display period Tu constitute one frame period, and one frame image is displayed. When one frame period ends, the next frame period starts and the above-described operation is repeated. If a non-display interval is provided between the frames by the initialization operation, the quality of the moving image can be improved easily and effectively. Note that the initialization period Te and the non-display period Tu are not necessarily provided in one frame period. For example, the initialization period Te and the non-display period Tu may be omitted for a still image, and the initialization period Te and the non-display period Tu may be set only for a moving image.

The gradation of each pixel is determined by the magnitude of current flowing through the light emitting element 105 in the writing period Ta and the display period Td. This current value is controlled by a video signal current I _vd input from the source signal line driver circuit 202 to the pixel 201. Therefore, if the video signal current I _vd for n gradations is prepared, an image display of n gradations can be performed. In general, the light emission luminance L of the OLED element is expressed by the amount of current I () flowing through the OLED element as indicated by L = c (V) I (V).
V). Therefore, the video signal current I _{vd for} n gradations becomes n values that are roughly proportionally distributed.

As described above, by adopting the pixel circuit configuration as shown in FIG. 2, the current flowing through the light emitting elements such as the OLED elements in the light emitting display device can be maintained well even in the following cases. it can. The case where the electrical resistance of the light emitting element depends on the environmental temperature, the case where the light emitting luminance decreases with time when the light emitting element is driven with voltage, and the like. By maintaining a good current flowing through the light emitting element, the light emission luminance can be kept good. As a result, color misregistration can be avoided in a color display device in which RGB sub-pixels are formed independently.

Further, even when the characteristics of the driving element 102 that controls the current flowing in the light emitting element are different between pixels by adopting the pixel circuit configuration as shown in FIG. 2 and current driving the light emitting element,
It is possible to prevent a significant variation in the magnitude of the current flowing through the light-emitting element between the pixels, and to suppress the occurrence of luminance unevenness on the display screen.

Furthermore, since the current flowing through the light emitting element can be maintained at a desired value, it is possible to prevent the gradation from being changed due to a potential drop due to the wiring resistance. This is also a feature compared to the case where the light emitting element is driven by voltage.

The multi-drain transistor is a novel element that can be effectively used for a circuit that is difficult to configure with only a single drain transistor or a circuit that can be configured but is complicated or requires a large area. An example of a pixel circuit of a light-emitting device that includes a writing element and a driving element as shown in FIG. 2 or 15 and uses a multi-drain transistor for one or both of the two elements is an example. is there.

Note that a current storage circuit that includes a writing element and a driving element and uses a multi-drain transistor for one or both of the two elements (an example shown in FIG. 17) is not limited to the pixel circuit of the light-emitting device. Can be used for a wide range of applications such as current signal buffers. For example, a current signal buffer using a current storage circuit using a multi-drain transistor can be provided in the source signal line driver circuit 202 (FIG. 1) of the light emitting device.

In some cases, the present invention can be applied to a display device using non-light emitting elements instead of the light emitting elements as shown in FIG.

(Embodiment 2)
In Embodiment 1, an example has been described for each of the semiconductor element multi-drain transistor of the present invention, a current storage circuit using the multi-drain transistor, and a light-emitting device using the current storage circuit for a pixel. However, in the light-emitting device described in Embodiment 1, the video signal has an analog current value (hereinafter referred to as analog drive).
Met. However, it is also possible to drive the video signal using it in digital form (hereinafter referred to as digital drive).

In the case of using a digital video signal, the gradation is encoded and input in binary number. Therefore, as a gradation display method, it is simple and useful to write a video signal of a binary code to a pixel as it is and to control the light emission time or the light emission area according to the binary code while keeping the luminance at the time of light emission constant. is there. In the second embodiment, an example of a method (digital time gradation method) for controlling the light emission time according to the binary code will be briefly described. For more detailed contents, reference can be made to Japanese Patent Application No. 2000-359032.

In the second embodiment, the pixel circuit of FIG. 2 is used. In the case of the digital time gray scale method, it is possible to display one image by repeatedly appearing the writing period Ta and the display period Td in one frame period.

For example, when an image is displayed by an n-bit video signal, at least n writing periods and n display periods are provided in one frame period. n writing periods (Ta1 to Ta
n) and n display periods (Td1 to Tdn) correspond to each bit of the video signal.

Furthermore, although not essential, n initialization periods or less and n non-display periods can be provided in one frame period. Rather, when a practical display device or light-emitting device in which a signal line driver circuit is formed on a glass substrate is to be manufactured, at least the lower bits must be provided with an initialization period and a non-display period. Given TFT manufacturing technology, there are significant difficulties. For details, Japanese Patent Application No. 2001-257163 can be referred to.

Next to the writing period Tam (m is an arbitrary number from 1 to n), the display period T corresponding to the bit is displayed.
dm appears. When the initialization period Tem and the non-display period Tum are set in the bit, the initialization period Tem and the non-display period Tum appear subsequently. Writing period Ta,
A series of periods including a display period Td, an initialization period Te, and a non-display period Tu (only when there is an initialization period Te and a non-display period Tu) is referred to as a subframe period SF. The subframe period including the writing period Tam and the display period Tdm corresponding to the m-th bit is SFm.

The ratio of the lengths of the subframe periods SF1 to SFn is as follows: SF1: SF2:...: SFn = 2 ⁰ :
2 ¹ : ...: 2 ^n-1 is satisfied.

In each subframe period, whether or not the light emitting element emits light is selected by each bit of the digital video signal. Then, the number of gradations can be controlled by controlling the sum of the lengths of the display periods during which light is emitted during one frame period.

Note that a subframe period having a long display period may be divided into several parts in order to improve image quality on display.

The operation of the pixel circuit and the drive circuit are almost the same as in the first embodiment. However, the source signal line driver circuit only needs to be able to accurately output even a predetermined value when the light emitting element emits light as the current value. As a result, there is an advantage that the configuration can be greatly simplified as compared with the case of Embodiment 1 that requires analog current values corresponding to the number of gradations. When a signal that does not cause the light-emitting element to emit light is output from the source signal line driver circuit, voltage value data may be used, as in the case of outputting a signal with zero gradation in the first embodiment.

In this embodiment, an example of the source signal line driver circuit 202 shown in FIG. 1 will be described. The source signal line driver circuit 202 can supply a current (signal current I _vd ) having a magnitude corresponding to the voltage of the video signal input to the pixel 201 to each of the source signal lines S1 to Sx. In this embodiment, an example 302 of a source signal line driver circuit in the case of digital driving will be described with reference to FIG. Next, an example of a source signal line driving circuit 40 in the case of analog driving 40
2 will be described with reference to FIG.
After that, an example of the gate signal line driver circuit will be described with reference to FIG.

An example 302 of the source signal line driver circuit in the case of first digital driving will be described with reference to FIG. The source signal line driver circuit 302 includes a shift register 302a, a latch (A) 302b that can store a digital video signal, a latch (B) 302c, and a voltage-current conversion circuit (V / C conversion circuit) 302d. Yes.

The shift register 302a includes a clock signal (CLK) and a start pulse signal (SP).
Is entered. Clock signal (CLK) and start pulse signal (SP)
Based on the above, the shift register 402a sequentially generates a timing signal for sampling the video signal. Based on each timing signal, the latch (A) 302b reads the video signal from the video signal line and stores it.

The video signal stored in the latch (A) 302b is read and stored in the latch (B) 302c according to the timing of the latch pulse. When data is read into the latch (B) 302c, the V / C conversion circuit 302d outputs predetermined current data when the data is ON. When the data is off, another predetermined current data may be output, but it is more efficient and preferable to output voltage data.

In the digital drive, the light emitting element is turned on (brightness is 100%) and off (
This is a system driven by two states (brightness is 0%). With the above-described structure of the source signal line driver circuit, the digitally driven light-emitting device expresses gray scales when the light-emitting element is turned on or off.

Next, an example 402 of the source signal line driver circuit in the case of analog driving is described with reference to FIGS. A source signal line driver circuit 402 of this embodiment shown in FIG. 6A includes a shift register 402a, a buffer 402b, a sampling circuit 402c, and a current conversion circuit 402d.

The shift register 402a includes a clock signal (CLK) and a start pulse signal (SP).
Is entered. Clock signal (CLK) and start pulse signal (SP)
Based on the above, the shift register 402a sequentially generates a timing signal for sampling the video signal.

This timing signal is amplified in a buffer manner in the buffer 402b and input to the sampling circuit 402c. However, if necessary, a level shifter may be provided instead of the buffer to amplify the voltage of the timing signal. Further, both a buffer and a level shifter may be provided. On the contrary, the timing signal does not have to be particularly amplified without providing a buffer or a level shifter.

Based on the timing signals amplified as necessary, the sampling circuit 402c
Takes the video signal and transmits it to the V / C conversion circuit.

FIG. 6B illustrates specific structures of the sampling circuit 402c and the current conversion circuit 402d. The sampling circuit 402c is connected to the output unit of the buffer 402b at a terminal 410.

The sampling circuit 402c is provided with a plurality of switches 411. Each switch 411 samples the analog video signal from the video signal line 406 in synchronization with the timing signal, and transmits the sampled video signal to the subsequent current conversion circuit 402d.
Note that in FIG. 6B, only the current conversion circuit connected to one of the switches 411 included in the sampling circuit 402c is shown as the current conversion circuit 402d; however, in FIG. A current conversion circuit 402d as shown in FIG.

In this embodiment, only one transistor is used for the switch 411. However, the switch 411 may be any switch that can sample an analog video signal in synchronization with the timing signal, and is not limited to the configuration of this embodiment.

The sampled analog video signal is input to a current output circuit 412 included in the current conversion circuit 402d. The current output circuit 412 outputs a current (signal current I _vd ) corresponding to the input video signal voltage. In FIG. 6, a current output circuit is formed by using an amplifier and a transistor. However, the present invention is not limited to this configuration, and any circuit that can output a current corresponding to an input video signal can be used. It ’s fine.

The signal current I _vd is also input to the reset circuit 417 included in the current conversion circuit 402d. The reset circuit 417 includes two analog switches 413 and 414 and an inverter 4
16 and a power source 415.

The analog switch 414 is controlled by a reset signal (Res). The analog switch 413 is controlled by a reset signal (Res) inverted by the inverter 416.
Therefore, the analog switch 413 and the analog switch 414 operate in synchronization with the inverted reset signal and the reset signal, respectively, so that when one is on, the other is off.

When the analog switch 413 is on, a signal current is input to the source signal line. Conversely, when the analog switch 414 is on, the voltage of the power source 415 is applied to the source signal line, and the source signal line is reset. Note that the voltage of the power supply 415 is preferably substantially the same as the voltage of the power supply line provided in the pixel, and is close if the current flowing to the source signal line is close to 0 when the source signal line is reset. Good enough.

Note that the source signal line is desirably reset during the return period. However, if it is outside the period during which the image is displayed, it can be reset to a period other than the blanking period as necessary.

Note that the source signal line may be selected using another circuit such as a decoder circuit instead of the shift register.

Next, the write gate signal line drive circuit 203 and the initialization gate signal line drive circuit 204
The configuration will be described with reference to FIG.

FIG. 7A is a block diagram illustrating a configuration of the write gate signal line driver circuit 203. The write gate signal line drive circuit 203 includes a shift register 203a and a buffer 20 respectively.
3b. In some cases, a level shifter may be further provided, or the buffer 203b may not be provided.

In the write gate signal line driving circuit 203, the clock C is supplied to the shift register 203a.
By inputting the LK and the start pulse signal SP, timing signals are sequentially generated. Each of the generated timing signals is buffered and amplified in the buffer 203b and supplied to the corresponding write gate signal line.

The gate electrode of the writing element 101 of pixels for one line is connected to the writing gate signal line. Since the writing elements 101 of pixels for one line must be turned on all at once, the buffer 203b is used to flow a large current.

Next, FIG. 7B is a block diagram showing a configuration of the initialization gate signal line driver circuit 204. Each of the write gate signal line driver circuits 204 includes a shift register 204a and a buffer 204b. In some cases, a level shifter may be further provided, or the buffer 203b may not be provided.

In the initialization gate signal line driving circuit 204, the clock C is supplied to the shift register 204a.
By inputting the LK and the start pulse signal SP, timing signals are sequentially generated. Each generated timing signal is buffered and amplified in the buffer 204b and supplied to the corresponding initialization gate signal line.

The initialization gate signal line is connected to the gate electrode of the initialization element 103 for one line of pixels. Since the initialization elements 103 for the pixels for one line must be turned on all at once, a buffer 204b that can flow a large current is used.

Note that another circuit such as a decoder circuit may be used instead of the shift register so that the gate signal line (scanning line) can be selected.

In this embodiment, the write gate signal line drive circuit 203 and the initialization gate signal line drive circuit 204 have the same configuration, but they may have different configurations.
The source signal line driving circuit, the writing gate signal line driving circuit, and the initialization gate signal line driving circuit for driving the light emitting device of the present invention are not limited to the configurations shown in this embodiment.

The structure of this example can be implemented by freely combining with the structure shown in Embodiment Modes 1 and 2.

In this example, an example of a semiconductor element used for the light-emitting device of the present invention will be described with reference to FIGS. 8A is a top view of the semiconductor element of the present invention, and FIG. 8B is a plan view of FIG.
8C corresponds to a cross-sectional view taken along the broken line BB ′ in FIG. 8A.

The semiconductor element of the present invention includes a semiconductor layer 501, a gate insulating film 502 in contact with the semiconductor layer, and a gate electrode 503 in contact with the gate insulating film 502. The semiconductor layer 501 includes a channel formation region 504 and impurity regions 505 and 50 to which an impurity imparting a conductivity type is added.
6, 507. Typical examples of impurities include boron for the p-channel type and phosphorus for the n-channel type. The gate electrode 503 and the channel formation region 504 overlap with the gate insulating film interposed therebetween.

The impurity regions 505, 506, and 507 are in contact with the channel formation region 504, respectively.
In this embodiment, all the impurity regions are in contact with the channel formation region 504 respectively, but the present invention is not limited to this structure. A low-concentration impurity region (LDD region) having an impurity concentration lower than that of the impurity region may be provided between the impurity region and the channel formation region, or a region not added with an impurity that does not overlap with the gate electrode (offset region) ) May be provided.

The gate insulating film 50 is formed so as to cover the impurity regions 505, 506, and 507 of the semiconductor layer 501.
An insulating film 508 is formed on 2. Connection wirings 509, 510, and 511 connected to the impurity regions 505, 506, and 507 are formed through contact holes formed in the insulating film 508 and the gate insulating film 502. Note that although the gate insulating film 502 covers the impurity regions 505, 506, and 507 in FIG. 8, the present invention is not limited to this structure. The impurity regions 505, 506, and 507 are not necessarily covered by the gate insulating film 502, and may be exposed.

In the semiconductor element illustrated in FIG. 8, the resistance between the connection wirings 509, 510, and 511 is simultaneously controlled by the voltage applied to the gate electrode 503.

The simplest method of using the semiconductor device of FIG. 8 is to use three nodes, specifically the node 509,
510 and 511 are simultaneously connected or opened. In the present specification, the connection means an electrical connection unless otherwise specified.

However, the method of using the multi-drain transistor is not limited thereto. For example,
The node 509 is set to a high potential, the node 510 is set to a low potential, the node 511 is set to a medium potential, and the gate electrode 503 is connected to the node 511, so that either the node 509 or the node 510 is selectively connected to the node 511. It is also possible to pass a current between the two.

In general, when the connection of three nodes is controlled using a single drain transistor, 2
It is necessary to use more than one transistor. An example is shown in FIG.
However, by using one multi-drain transistor in the present invention, the total area occupied by semiconductor elements such as transistors can be kept small. As a result, when applied to a pixel circuit of a display device, high definition or high functionality can be achieved without reducing the aperture ratio of the pixel.

The configuration of this example can be implemented by freely combining with the configurations shown in Embodiment Modes 1 and 2 and Example 1.

In this embodiment, a semiconductor element of the present invention having a so-called multi-gate structure in which two or more channel formation regions are provided between impurity regions connected to a connection wiring will be described. Note that in this embodiment, a semiconductor element having a double gate structure in which two channel formation regions are provided between the connection wirings will be described. However, the present invention is not limited to the double gate structure, and the channel formation region is provided between the connection wirings. May have a multi-gate structure in which three or more are provided.

The structure of the semiconductor element of this embodiment will be described with reference to FIG. 9A is a top view of a semiconductor element used in the light-emitting device of the present invention, and FIG. 9B is a broken line A in FIG. 9A.
9C corresponds to a cross-sectional view taken along a broken line BB ′ in FIG. 9A.

The semiconductor element of the present invention includes a semiconductor layer 601, a gate insulating film 602 in contact with the semiconductor layer, and gate electrodes 603a, 603b, and 603c in contact with the gate insulating film 602. The gate electrodes 603a, 603b, and 603c are electrically connected. In this embodiment, all the gate electrodes are part of the gate wiring 613. The semiconductor layer 601 includes channel formation regions 604a, 604b, and 604c and an impurity region 60 to which an impurity imparting a conductivity type is added.
5, 606, 607, 612. Typical examples of impurities include boron for the p-channel type and phosphorus for the n-channel type.

The gate electrode 603a and the channel formation region 604a overlap with the gate insulating film 602 interposed therebetween. The gate electrode 603b and the channel formation region 604b are formed of the gate insulating film 602.
It overlaps with a gap in between. The gate electrode 603c and the channel formation region 604c overlap with the gate insulating film 602 interposed therebetween.

The impurity regions 605, 606, and 607 are channel formation regions 604a, 604b,
It is in contact with 604c. The impurity region 612 is in contact with all the channel formation region formation regions 604a, 604b, and 604c. Therefore, two channel formation regions 604a and 604b are provided between the impurity regions 605 and 606, and the impurity regions 606 and 6 are provided.
Two channel formation regions 604b and 604c are provided between the two regions 07, and two channel formation regions 604c and 604a are provided between the impurity regions 607 and 605.

In this embodiment, all the impurity regions are in contact with the channel formation regions, respectively, but the present invention is not limited to this configuration. A low-concentration impurity region (LDD region) having an impurity concentration lower than that of the impurity region may be provided between the impurity region and the channel formation region, or a region not added with an impurity that does not overlap with the gate electrode (offset region) ) May be provided.

The gate insulating film 60 is formed so as to cover the impurity regions 605, 606, and 607 of the semiconductor layer 601.
An insulating film 608 is formed on 2. Connection wirings 609, 610, and 611 connected to the impurity regions 605, 606, and 607 are formed through contact holes formed in the insulating film 608 and the gate insulating film 602. Note that although the gate insulating film 602 covers the impurity regions 605, 606, and 607 in FIG. 9, the present invention is not limited to this structure. The impurity regions 605, 606, and 607 are not necessarily covered with the gate insulating film 602, and may be exposed.

In the semiconductor element shown in FIG. 9, the resistance between the connection wirings 609, 610, and 611 is controlled by the voltage applied to the gate electrodes 603a, 603b, and 603c.

The semiconductor element in FIG. 9 can simultaneously connect three nodes, specifically, connection wirings 609, 610, and 611.

With the above structure, the area of the semiconductor element can be suppressed. As a result, when applied to a pixel circuit of a display device, the area occupied by a pixel of a semiconductor element can be suppressed, and high definition or high functionality can be achieved without reducing the aperture ratio of the pixel. On the other hand, when the connection of the three nodes is controlled using a double-gate three-terminal transistor, for example, it is performed as shown in FIG. 18B. Also occupies a large area.

In addition, the multi-gate structure can further reduce the off current compared to the single gate structure. Therefore, it is more suitable when a transistor is used as a switch element.

The configuration of this example can be implemented by freely combining with the configurations shown in Embodiment Modes 1 and 2 and Examples 1 and 2.

In this embodiment, a bottom gate type semiconductor element of the present invention in which a gate electrode is formed between a substrate and a semiconductor layer will be described.

The structure of the semiconductor element of the present invention will be described with reference to FIG. FIG. 10 (A)
FIG. 10B is a top view of the semiconductor element of the present invention, and FIG. 10B is a broken line AA ′ in FIG.
10C corresponds to the cross-sectional view taken along the broken line BB ′ in FIG. 10A.

The semiconductor element of this embodiment includes a gate electrode 701, a gate insulating film 702 in contact with the gate electrode 701, and an active layer 703 in contact with the gate insulating film 702. Semiconductor layer 7
03 is a channel formation region 704 and an impurity region 7 to which an impurity imparting a conductivity type is added.
05, 706, and 707. The gate electrode 701 and the channel formation region 704 overlap with the gate insulating film 702 interposed therebetween. Note that reference numeral 708 denotes a mask used for forming a channel formation region, and is formed of an insulating film.

The impurity regions 705, 706, and 707 are in contact with the channel formation region 704, respectively.
In this embodiment, all the impurity regions are in contact with the channel formation region 704, but the present invention is not limited to this structure. A low-concentration impurity region (LDD region) having an impurity concentration lower than that of the impurity region may be provided between the impurity region and the channel formation region, or a region not added with an impurity that does not overlap with the gate electrode (offset region) ) May be provided.

An insulating film 708 is formed so as to cover the impurity regions 705, 706, and 707 of the semiconductor layer 703. Connection wirings 709, 710, and 711 connected to the impurity regions 705, 706, and 707 are formed through contact holes formed in the insulating film 708.

In the semiconductor element illustrated in FIG. 10, the resistance between the connection wirings 709, 710, and 711 is controlled by the voltage applied to the gate electrode 701.

The semiconductor element in FIG. 10 can connect three nodes, specifically, connection wirings 709, 710, and 711 simultaneously.

With the above structure, the area of the semiconductor element can be suppressed. As a result, when applied to a pixel circuit of a display device, high definition or high functionality can be achieved without reducing the aperture ratio of the pixel.

Note that a multi-gate structure may be provided by providing two or more channel formation regions between the connection wirings.

The configuration of this example can be implemented by freely combining with the configurations shown in Embodiment Modes 1 and 2 and Examples 1 to 3.

An example of a method for manufacturing the light-emitting device of the present invention will be described with reference to FIGS. In this example, a method for manufacturing a light-emitting device having the pixel shown in FIGS. Note that the initialization element 103 is typically shown here. The writing element 101 and the driving element 102
Although not shown in particular, it can be manufactured according to the manufacturing method of this embodiment.

In this embodiment, an example of a light-emitting device using an OLED element as a light-emitting element is shown; however, a light-emitting device in which only the light-emitting element is replaced can be manufactured.

First, as shown in FIG. 11A, a silicon oxide film is formed on a substrate 5001 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass. A base film 5002 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. For example, Si by plasma CVD method
A silicon oxynitride film 5002a made of H ₄ , NH ₃ , and N ₂ O is formed by 10 to 200 [nm] (
Preferably, the silicon oxynitride silicon film 5002b formed from SiH ₄ and N ₂ O is formed to a thickness of 50 to 200 [nm] (preferably 100 to 150 [nm]). Then, it is laminated.
Although the base film 5002 is shown as a two-layer structure in this embodiment, it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.

The island-shaped semiconductor layers 5005 and 5006 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a known thermal crystallization method. This island-shaped semiconductor layer 50
The thicknesses of 05 and 5006 are 25 to 80 [nm] (preferably 30 to 60 [nm]). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In the case of manufacturing a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser is used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 [Hz] and the laser energy density is 100 to 400 [mJ / cm ² ] (typically 200 to 300 [mJ / cm ² ]). Also,
When using a YAG laser, the second harmonic is used and the pulse oscillation frequency is 30 to 300 [k.
Hz], and the laser energy density is 300 to 600 [mJ / cm ² ] (typically 350 to 500).
[mJ / cm ² ]). Then, a laser beam focused in a linear shape with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the overlay rate of the linear laser beam at this time is 50. Perform as ~ 90 [%].

As the laser, a continuous wave or pulsed gas laser or solid-state laser can be used. Examples of gas lasers include excimer laser, Ar laser, and Kr laser. Examples of solid-state lasers include YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandride laser, and Ti: sapphire laser. Can be mentioned. Solid lasers include Cr, Nd, Er, Ho, Ce, Co, Ti
Alternatively, a laser using a crystal such as YAG, YVO ₄ , YLF, and YAlO ₃ doped with Tm can be used. The fundamental wave of the laser differs depending on the material to be doped, and a laser beam having a fundamental wave of about 1 μm can be obtained. The harmonic with respect to the fundamental wave can be obtained by using a nonlinear optical element.

In crystallization of the amorphous semiconductor film, in order to obtain a crystal with a large grain size, it is preferable to apply a second to fourth harmonic of the fundamental wave using a solid-state laser capable of continuous oscillation. Typically, the second harmonic (532 nm) or third harmonic (Nd: YVO ₄ laser (fundamental wave 1064 nm))
355 nm) is desirable. Specifically, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method of emitting harmonics by putting a YVO ₄ crystal and a nonlinear optical element in a resonator. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the object to be processed. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.

Next, a gate insulating film 5007 is formed to cover the island-shaped semiconductor layers 5005 and 5006. The gate insulating film 5007 is formed by plasma CVD or sputtering, and has a thickness of 40 to 150 [n].
m] is formed of an insulating film containing silicon. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 [nm]. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Ort) is formed by plasma CVD.
hosilicate) and O ₂ are mixed, the reaction pressure is 40 [Pa], the substrate temperature is 300 to 400 [° C.],
It can be formed by discharging at a high frequency (13.56 [MHz]) and a power density of 0.5 to 0.8 [W / cm ² ]. The silicon oxide film thus produced can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].

Then, a first conductive film 5008 for forming a gate electrode over the gate insulating film 5007.
And a second conductive film 5009 are formed. In this embodiment, the first conductive film 5008 is made of 5 with Ta.
A second conductive film 5009 is formed to a thickness of 100 to 300 [nm] with W.

The Ta film is formed by sputtering, and a Ta target is sputtered with Ar.
In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 [μΩcm] and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 [μΩcm] and is used as the gate electrode. It is unsuitable. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to Ta's α-phase is formed on a Ta base with a thickness of about 10 to 50 nm. It can be easily obtained.

When forming a W film, it is formed by sputtering using W as a target. In addition, it can also be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is 20 [
[μΩcm] or less is desirable. Although the resistivity of the W film can be reduced by increasing the crystal grains, if the impurity element such as oxygen is large in W, the crystallization is hindered and the resistance is increased. From this, when the sputtering method is used, the purity is 99.9999 or 99.99 [%].
A resistivity of 9 to 20 [[mu] [Omega] cm] can be realized by using a W target and forming a W film with sufficient consideration so that impurities are not mixed in the gas phase during film formation.

Note that in this embodiment, the first conductive film 5008 is Ta and the second conductive film 5009 is W, but there is no particular limitation, and any of them is selected from Ta, W, Ti, Mo, Al, Cu, and the like. Or an alloy material or a compound material containing the element as a main component. Also,
A semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As an example of other combinations other than the present embodiment, the first conductive film 50 is desirable.
A combination in which 08 is formed of tantalum nitride (TaN) and the second conductive film 5009 is W,
The first conductive film 5008 is formed of tantalum nitride (TaN), and the second conductive film 5009 is formed of Al.
And a combination in which the first conductive film 5008 is formed of tantalum nitride (TaN) and the second conductive film 5009 is Cu.

Next, a resist mask 5010 is formed, and a first etching process is performed to form electrodes and wirings. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, CF ₄ and Cl ₂ are mixed in an etching gas, and a coil type electrode of 500 [W] is applied at a pressure of 1 [Pa]. RF (13.56 [MHz]) power is applied to generate plasma. 100 [W] RF (13.56 [MHz]) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film are etched to the same extent.

Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °.
In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. The selectivity of the silicon oxynitride film to the W film is 2
Since it is ˜4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 [nm] by the over-etching process. Thus, the first shape conductive layers 5013, 5 made of the first conductive layer and the second conductive layer are formed by the first etching process.
014 (first conductive layers 5013a and 5014a and second conductive layers 5013b and 5014b)
Form. At this time, in the gate insulating film 5007, the first shape conductive layer 5013 is formed.
, 5014 is etched by about 20 to 50 [nm] to form a thinned region.

Then, an impurity element imparting n-type is added by performing a first doping process.
As a doping method, an ion doping method or an ion implantation method may be used. The conditions for the ion doping method are a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ [atoms / cm ² ] and an acceleration voltage of 60 to 100 [
keV]. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 5013 and 5014 serve as a mask for the impurity element imparting n-type, and the first impurity regions 5017 and 5018 are formed in a self-aligning manner. First impurity regions 5017 and 5018
Is added with an impurity element imparting n-type in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ [atoms / cm ³ ]. (Fig. 11 (B))

Next, as shown in FIG. 11C, a second etching process is performed without removing the resist mask. The W film is selectively etched using CF ₄ , Cl ₂ and O _{2 as an} etching gas. At this time, the second shape conductive layers 5028 and 5029 (
First conductive layers 5028a and 5029a and second conductive layers 5028b and 5029b) are formed. At this time, in the gate insulating film 5007, the second shape conductive layers 5028 and 502 are formed.
The region not covered with 9 is further etched by about 20 to 50 [nm] to form a thinned region.

The etching reaction of the W film or Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radicals or ion species and the vapor pressure of the reaction product. When the vapor pressures of W and Ta fluorides and chlorides are compared, WF _6, which is a fluoride of W, is extremely high, and other WCl ₅
, TaF ₅ and TaCl ₅ are comparable. Therefore, in the mixed gas of CF ₄ and Cl ₂ , the W film and T
Both a films are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂
Reacts to CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Also, Ta is more easily oxidized than W, so
The surface of Ta is oxidized by adding O ₂ . Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, an impurity element imparting n-type conductivity is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 [keV] and 1 × 10 ¹³ [atoms / cm
² ], and a new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. 11B. Doping is performed on the second shape conductive layers 5028, 5029.
Is used as a mask against the impurity element, and doping is performed so that the impurity element is also added to the lower regions of the first conductive layers 5028a and 5029a. Thus, the third impurity region 5
034, 5035 are formed. The concentration of phosphorus (P) added to the third impurity regions 5034 and 5035 has a gradual concentration gradient according to the film thickness of the tapered portions of the first conductive layers 5028a and 5029a. Note that, in the semiconductor layer overlapping the tapered portions of the first conductive layers 5028a and 5029a, although the impurity concentration slightly decreases inward from the end portions of the tapered portions of the first conductive layers 5028a and 5029a, the impurity concentration is almost reduced. The concentration is similar.

Next, a third etching process is performed as shown in FIG. CH as etching gas
Using F ₆ , a reactive ion etching method (RIE method) is used. By the third etching treatment, the tapered portions of the first conductive layers 5028a and 5029a are partially etched, so that a region where the first conductive layer overlaps with the semiconductor layer is reduced. By the third etching process,
Third shape conductive layers 5039 and 5040 (first conductive layers 5039a and 5040a and second conductive layers 5039b and 5040b) are formed. At this time, in the gate insulating film 5007, regions that are not covered with the third shape conductive layers 5039 and 5040 are further etched and thinned by about 20 to 50 [nm].

By the third etching process, in the third impurity regions 5034 and 5035, the third impurity regions 5034a and 5035a overlapping with the first conductive layers 5039a and 5040a, the first impurity region, the third impurity region, Second impurity regions 5034b and 5035 in between
b.

Then, as shown in FIG. 12B, an island-shaped semiconductor layer 50 forming a p-channel TFT is formed.
In step 05, fourth impurity regions 5049 to 5054 having a conductivity type opposite to the first conductivity type are formed.
Using the third shape conductive layer 5040b as a mask for the impurity element, an impurity region is formed in a self-aligning manner. At this time, the entire surface of the island-like semiconductor layer 5006 for forming the n-channel TFT is covered with a resist mask 5200. Although phosphorus is added to the impurity regions 5049 to 5054 at different concentrations, the impurity regions 5049 to 5054 are formed by ion doping using diborane (B ₂ H ₆ ), and the impurity concentration is 2 × 10 ²⁰ to 2 × 10 ²¹ [atoms / cm ³
] To be.

Through the above steps, impurity regions are formed in each island-like semiconductor layer. The third shape conductive layers 5039 and 5040 overlapping with the island-shaped semiconductor layers function as gate electrodes.

After removing the resist mask 5200, a process of activating the impurity element added to each island-like semiconductor layer is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
In the thermal annealing method, oxygen concentration is 1 [ppm] or less, preferably 0.1 [ppm] or less in a nitrogen atmosphere at 400 to 700 [° C.], typically 500 to 600 [° C.], In this embodiment, 5
Heat treatment is performed at 00 [° C.] for 4 hours. However, if the wiring material used for the third shape conductive layers 5039 and 5040 is weak against heat, activation is performed after an interlayer insulating film (mainly composed of silicon) is formed to protect the wiring and the like. Preferably it is done.

When activation is performed using a laser annealing method, the laser used for crystallization can be used. In the case of activation, the moving speed is the same as that of crystallization, and 0.01 to
100 MW / cm ² about (preferably 0.01~10MW / cm ²⁾ is required energy density.

Further, a heat treatment is performed at 300 to 450 [° C.] for 1 to 12 hours in an atmosphere containing 3 to 100 [%] hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, as shown in FIG. 13C, a first interlayer insulating film 5055 is formed from a silicon oxynitride film to a thickness of 100 to 200 [nm]. After a second interlayer insulating film 5056 made of an organic insulating material is formed thereon, a first interlayer insulating film 5055, a second interlayer insulating film 5056,
In addition, contact holes are formed in the gate insulating film 5007 and wirings 5059 to 50 are formed.
After patterning 62, the pixel electrode 5064 in contact with the connection wiring 5062 is formed by patterning.

As the second interlayer insulating film 5056, a film made of an organic resin is used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 5056 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. Preferably 1-5 [μm] (more preferably 2-2
4 [μm]).

The contact holes are formed by dry etching or wet etching, and contact holes reaching n-type impurity regions 5017 or p-type impurity regions 5049 and 5054 are formed.

Further, as wiring (including connection wiring and signal lines) 5059 to 5062, a Ti film is formed to 100 [n.
m], an aluminum film containing Ti having a thickness of 300 [nm] and a Ti film 150 [nm] continuously formed by sputtering is used to pattern a laminated film having a desired shape. Of course, other conductive films may be used.

In this embodiment, an ITO film is formed as the pixel electrode 5064 with a thickness of 110 [nm]
Patterning was performed. A contact is made by arranging the pixel electrode 5064 so as to be in contact with and overlapping with the connection wiring 5062. In addition, 2-20 [%] zinc oxide (
A transparent conductive film mixed with ZnO) may be used. This pixel electrode 5064 becomes the anode of the light emitting element. (Fig. 12 (A))

Next, as shown in FIG. 12D, an insulating film containing silicon (in this embodiment, a silicon oxide film) is formed by 5
A third interlayer insulating film 5065 functioning as a bank is formed by forming an opening at a position corresponding to the pixel electrode 5064, with a thickness of 00 [nm]. When the opening is formed, a tapered sidewall can be easily formed by using a wet etching method. If the side wall of the opening is not sufficiently gentle, the deterioration of the organic light emitting layer due to the step becomes a significant problem, so care must be taken.

Next, the organic light emitting layer 5066 and the cathode (MgAg electrode) 5067 are continuously formed by using a vacuum evaporation method without releasing to the atmosphere. The film thickness of the organic light emitting layer 5066 is 80 to 200 [nm].
(Typically 100 to 120 [nm]), and the thickness of the cathode 5067 may be 180 to 300 [nm] (typically 200 to 250 [nm]).

In this step, the organic light emitting layer is sequentially formed on the pixel corresponding to red, the pixel corresponding to green, and the pixel corresponding to blue. However, since the organic light emitting layer has poor resistance to a solution, it must be formed for each color individually without using a photolithography technique. Therefore, it is preferable to use a metal mask to hide other than the desired pixels and to selectively form the organic light emitting layer only at necessary portions.

That is, first, a mask that hides all pixels other than those corresponding to red is set, and an organic light emitting layer that emits red light is selectively formed using the mask. Next, a mask that hides all but the pixels corresponding to green is set, and an organic light emitting layer that emits green light is selectively formed using the mask. Next, similarly, a mask for hiding all but the pixels corresponding to blue is set, and a blue light emitting organic light emitting layer is selectively formed using the mask. Note that although all the different masks are described here, the same mask may be used.

Here, a method of forming three types of light emitting elements corresponding to RGB was used, but a method of combining a white light emitting element and a color filter, a blue or blue green light emitting element, and a phosphor (
A method in which a fluorescent color conversion layer (CCM) is combined, a method in which light emitting elements corresponding to RGB are stacked on a cathode (counter electrode) using a transparent electrode, and the like may be used.

A known material can be used for the organic light emitting layer 5066. As the known material, it is preferable to use an organic material in consideration of the driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the organic light emitting layer.

Next, a cathode 5067 is formed using a metal mask. In this embodiment, the cathode 5067 is used.
Although MgAg was used as the present invention, the present invention is not limited to this. Other known materials may be used for the cathode 5067.

Finally, a passivation film 5068 made of a silicon nitride film is formed to a thickness of 300 [nm]. By forming the passivation film 5068, the organic light emitting layer 5066 can be protected from moisture and the like, and the reliability of the light emitting element can be further improved.

  Thus, a light emitting device having a structure as shown in FIG. 12D is completed.

By the way, the light emitting device of this embodiment has a TF structure that is optimal not only for the pixel portion but also for the drive circuit portion.
By disposing T, very high reliability can be shown and the operating characteristics can be improved. In addition, it is possible to increase the crystallinity by adding a metal catalyst such as Ni in the crystallization step. Thereby, the driving frequency of the signal line driving circuit can be increased to 10 [MHz] or more.

First, a TFT having a structure that reduces hot carrier injection so as not to reduce the operating speed as much as possible is used as an n-channel TFT of a CMOS circuit that forms a drive circuit portion. Note that the driving circuit here includes a shift register, a buffer, a level shifter, a latch in line sequential driving, a transmission gate in dot sequential driving, and the like.

In this embodiment, the active layer of the n-channel TFT has an overlap LDD region ( _LOV region) that overlaps the gate electrode with the source region, drain region, and gate insulating film in between, and a gate insulating film in between. And an offset LDD region (L _OFF region) that does not overlap with the gate electrode and a channel formation region.

In addition, since the p-channel TFT of the CMOS circuit is hardly concerned with deterioration due to hot carrier injection, it is not particularly necessary to provide an LDD region. Needless to say, it is possible to provide an LDD region as in the case of the n-channel TFT and take measures against hot carriers.

In addition, in the drive circuit, CMOS in which current flows bidirectionally in the channel formation region
When a circuit, that is, a CMOS circuit in which the roles of the source region and the drain region are switched is used, the n-channel TFT forming the CMOS circuit has an LDD region with a channel forming region sandwiched between both sides of the channel forming region. It is preferable to form. An example of this is a transmission gate used for dot sequential driving. When a CMOS circuit that needs to keep off current as low as possible is used in the drive circuit, CM
The n-channel TFT forming the OS circuit preferably has a _LOV region. As such an example, there is a transmission gate used for dot sequential driving.

In fact, once completed to the state of FIG. 12 (D), in order not to be exposed to the outside air,
It is preferable to package (enclose) with a protective film (laminated film, ultraviolet curable resin film, etc.) or a light-transmitting sealing material with high air tightness and low outgassing. At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the light emitting element is improved.

If the airtightness is improved by processing such as packaging, a connector or FPC (flexible printed circuit) for connecting the terminal drawn from the element or circuit formed on the substrate and the external signal terminal is attached. Completed as a product. In this specification, such a state that can be shipped is referred to as a light emitting device.

Further, according to the steps shown in this embodiment, the number of photomasks necessary for manufacturing a light-emitting device can be suppressed. As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.

The manufacturing method of the light-emitting device of the present invention is not limited to the manufacturing method described in this embodiment.
The light emitting device of the present invention can be manufactured using a known method.

The configuration of this example can be implemented by freely combining with the configurations shown in Embodiment Modes 1 and 2 and Examples 1 to 4.

In this embodiment, the appearance of an embodiment of a light emitting device of the present invention will be described with reference to FIG.
In this embodiment, the light emitting element is an OLED element. However, a light emitting element other than the OLED element may be used.

FIG. 13 is a top view of a light-emitting device formed by sealing an element substrate over which a transistor is formed with a sealing material, and FIG. 13B is a cross-sectional view taken along a line AA ′ in FIG. FIG. 13C is a cross-sectional view taken along line BB ′ of FIG.

A sealant 4009 is provided so as to surround the pixel portion 4002, the source signal line driver circuit 4003, and the writing and initialization gate signal line driver circuits 4004a and 4004b provided on the substrate 4001. In addition, the pixel portion 4002, the source signal line driver circuit 4003,
Sealing material 400 on gate signal line drive circuits 4004a, 400b for writing and initialization
8 is provided. Therefore, the pixel portion 4002, the source signal line driver circuit 4003, and the writing and initialization gate signal line driver circuits 4004 a and 400 b include the substrate 4001 and the sealant 4.
009 and a sealing material 4008 are sealed. The portion 4210 is a hollow portion, but a filler may be inserted.

The pixel portion 4002, the source signal line driver circuit 4003, and the writing and initialization gate signal line driver circuits 4004a and 4004b provided over the substrate 4001 each include a plurality of TFTs. In FIG. 13B, a TFT included in the source signal line driver circuit 4003 (hereinafter referred to as a driver circuit TFT. Here, each of an n-channel TFT and a p-channel TFT is typically formed over the base film 4010. Only one is shown.)
4201 and a driving element 4202 included in the pixel portion 4002 are shown.

In this embodiment, the drive circuit TFT 4201 is a p-channel type TF manufactured by a known method.
A T or n-channel TFT is used, and an n-channel TFT manufactured by a known method is used for the initialization element 103 (not shown in FIG. 13).

On the driving circuit TFT 4201 and the driving element 4202, an interlayer insulating film (planarization film) 430 is formed.
1 is formed, and a pixel electrode (anode) 4203 electrically connected to the drain of the driving element 4202 is formed thereon. As the pixel electrode 4203, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.

An insulating film 4302 is formed over the pixel electrode 4203 layer, and the insulating film 4302 is formed.
Has an opening formed on the pixel electrode 4203. In this opening, the pixel electrode 420
On 3, an organic light emitting layer 4204 is formed. A known organic light emitting material or inorganic light emitting material can be used for the organic light emitting layer 4204. The organic light emitting material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.

As a method for forming the organic light emitting layer 4204, a known vapor deposition technique or coating technique may be used.
The structure of the organic light emitting layer can be a laminated structure in which a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer are freely combined. However, it may be a single layer structure.

On the organic light emitting layer 4204, a cathode 420 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper or silver as a main component or a laminated film of these and another conductive film).
5 is formed. In addition, it is desirable to remove moisture and oxygen present at the interface between the cathode 4205 and the organic light emitting layer 4204 as much as possible. Therefore, it is necessary to devise a method in which the organic light emitting layer 4204 is formed in a nitrogen or rare gas atmosphere and the cathode 4205 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.

As described above, the pixel electrode (anode) 4203, the organic light emitting layer 4204, and the cathode 4205 are used.
A light emitting element 4303 made of is formed. A protective film 4303 is formed over the insulating film 4302 so as to cover the light emitting element 4303. The protective film 4303 is effective in preventing oxygen, moisture, and the like from entering the light emitting element 4303.

Reference numeral 4005 a denotes a lead wiring connected to the power supply line, and is electrically connected to the source region of the driving element 4202. The lead wiring 4005a includes a sealant 4009 and a substrate 4001.
Are electrically connected to the FPC wiring 4301 of the FPC 4006 through the anisotropic conductive film 4300.

As the sealing material 4008, a glass material, a metal material (typically a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. As a plastic material, FRP (Fiberglass-Reinforced Pla
sticks), PVF (polyvinyl fluoride)
A film, mylar film, polyester film or acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

However, when the light emission direction from the light emitting element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

Further, as the filler 4103, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (Polyvinyl butyral) or E
VA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.

Further, in order to expose the filler 4103 to a hygroscopic substance (preferably barium oxide) or a substance that can adsorb oxygen, a recess 400 is formed on the surface of the sealing material 4008 on the substrate 4001 side.
7, a hygroscopic substance or a substance 4207 capable of adsorbing oxygen is disposed. Then, the concave cover material 4208 is prevented so that the hygroscopic substance or the substance 4207 capable of adsorbing oxygen does not scatter.
Thus, the hygroscopic substance or the substance 4207 capable of adsorbing oxygen is held in the recess 4007. Note that the concave cover material 4208 has a fine mesh shape, and is configured to allow air and moisture to pass therethrough but not a hygroscopic substance or a substance 4207 capable of adsorbing oxygen. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the light-emitting element 4303 can be suppressed.

As shown in FIG. 13C, the lead wiring 40 is formed at the same time as the pixel electrode 4203 is formed.
A conductive film 4203a is formed in contact with 05a.

The anisotropic conductive film 4300 has a conductive filler 4300a. Substrate 4
By thermally pressing 001 and FPC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.

The configuration of this example can be implemented by freely combining with the configurations shown in Embodiment Modes 1 and 2 and Examples 1 to 5.

Luminescent materials used for light-emitting elements are roughly classified into low molecular weight and high molecular weight materials. The light emitting device of the present invention can use either a low molecular weight light emitting material or a high molecular weight light emitting material.
In some cases, materials that are difficult to classify as either low molecular or high molecular (for example, Japanese Patent Application No. 20
01-167508, etc.) may be used.

A low molecular weight light emitting material is formed by a vapor deposition method. Therefore, it is easy to take a laminated structure,
High efficiency can be easily achieved by laminating films having different functions such as a hole transport layer and an electron transport layer. However, the hole transport layer, the electron transport layer, etc. do not necessarily exist clearly, and there are a single layer or a plurality of layers in a mixed state (see, for example, Japanese Patent Application No. 2001-020817), and the life of the device is increased. In addition, high luminous efficiency may be achieved.

As a low molecular weight light emitting material, an aluminum complex Alq ₃ having quinolinol as a ligand is used.
And triphenylamine derivative (TPD).

On the other hand, a high-molecular light-emitting material has higher physical strength and higher element durability than a low-molecular material. In addition, since the film can be formed by coating, the device can be manufactured relatively easily.

The structure of a light-emitting element using a high-molecular light-emitting material is basically the same as that when a low-molecular light-emitting material is used, and is a cathode / organic light-emitting layer / anode. However, when forming an organic light emitting layer using a high molecular weight light emitting material, it is difficult to form a laminated structure as in the case of using a low molecular weight light emitting material. The laminated structure of the layers is famous. Specifically, the structure is cathode / light-emitting layer / hole transport layer / anode. In the case of a light emitting element using a high molecular light emitting material, Ca can also be used as a cathode material.

Note that since the color of light emitted from the element is determined by the material for forming the light-emitting layer, a light-emitting element exhibiting desired light emission can be formed by selecting them. Typical examples of the polymer light-emitting material that can be used for forming the light-emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

The polyparaphenylene vinylene system includes derivatives of poly (paraphenylene vinylene) [PPV], poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV],
Poly (2- (2'-ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh- PPV] and the like.

The polyparaphenylene group includes a derivative of polyparaphenylene [PPP], poly (2,5-
Dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1)
, 4-phenylene).

The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [
PCMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3
-(4-Octylphenyl) -thiophene]
[POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOP
T] and the like.

Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

Note that when a hole-transporting polymer light-emitting material is formed between an anode and a light-emitting polymer light-emitting material, hole injectability from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting material.

Examples of the hole-transporting polymer light-emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

The configuration of this example can be implemented by freely combining with the configurations shown in Embodiment Modes 1 and 2 and Examples 1 to 6.

The light-emitting device can be used for display portions of various devices by taking advantage of the light-emitting elements used.
For example, a light-emitting device using an OLED as a light-emitting element is advantageous for monitoring because the contrast between light and dark is higher than that of a liquid crystal display, and the visibility is excellent and the viewing angle is wide. Furthermore, the high-speed response is quite advantageous for a moving image display device. The thin and lightweight point is advantageous for portable devices.

As an electronic device using the light emitting device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device, Play back a recording medium such as a portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.) or recording medium (specifically, Digital Versatile Disc (DVD)) A device having a display capable of displaying). In particular, it is desirable to use a light-emitting device for a portable information terminal that often has an opportunity to see a screen from an oblique direction because the wide viewing angle is important. Specific examples of these electronic devices are shown in FIGS.

FIG. 14A illustrates a light-emitting element display device, which includes a housing 2001, a support base 2002, and a display portion 20.
03, a speaker portion 2004, a video input terminal 2005, and the like. The light emitting device of the present invention can be used for the display portion 2003. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. The light emitting element display device includes all information display devices such as a personal computer, a TV broadcast receiver, and an advertisement display.

FIG. 14B shows a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like.
The light emitting device of the present invention can be used for the display portion 2102.

FIG. 14C illustrates a laptop personal computer, which includes a main body 2201 and a housing 2202.
A display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The light-emitting device of the present invention can be used for the display portion 2203.

FIG. 14D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The light emitting device of the present invention can be used for the display portion 2302.

FIG. 14E shows a portable image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
A main body 2401, a housing 2402, a display portion A 2403, a display portion B 2404, a recording medium (DVD or the like) reading portion 2405, operation keys 2406, a speaker portion 2407, and the like.
Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the light-emitting device of the present invention can be used for the display portions A, B 2403, and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

FIG. 14F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The light emitting device of the present invention includes the display unit 250.
2 can be used.

FIG. 14G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603,
External connection port 2604, remote control receiving unit 2605, image receiving unit 2606, battery 260
7, voice input unit 2608, operation key 2609, and the like. The light emitting device of the present invention includes the display unit 260.
2 can be used.

FIG. 14H illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The light emitting device of the present invention can be used for the display portion 2703. Note that the display portion 2703 can suppress current consumption of the mobile phone by displaying white characters on a black background.

If the emission luminance of the luminescent material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like to be used for a front type or rear type projector.

In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Therefore, a light-emitting device using a light-emitting element with a high response speed is very valuable.

In addition, since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background It is desirable to do.

As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic device of this embodiment may use the light emitting device having any structure shown in Embodiments 1 to 8.

Claims (5)

Having a thin film transistor,
The thin film transistor has an island-shaped semiconductor layer and a conductive layer,
The island-shaped semiconductor layer has a first region and a second region,
The first region is a region provided extending in one direction,
The second region is a region provided extending from a central portion of the first region in a direction perpendicular to the one direction,
The first region has a first impurity region and a second impurity region;
The second region has a third impurity region;
The first to third impurity regions are of the same conductivity type,
A light emitting element is electrically connected to the third impurity region,
The conductive layer has a region disposed so as to overlap a central portion of the first region and a part of the second region;
The display device, wherein the conductive layer has a region functioning as a gate electrode. Having a thin film transistor,
The thin film transistor has a conductive layer and an island-shaped semiconductor layer,
The island-like semiconductor layer extends in a direction perpendicular to the one direction from a first shape provided extending in one direction and a central portion of the first shape extending in the one direction. A second shape provided,
The island-shaped semiconductor layer has first to third end portions and first to third impurity regions,
The first impurity region is provided in a region including the first end;
The second impurity region is provided in a region including the second end,
The third impurity region is provided in a region including the third end;
The first to third impurity regions are of the same conductivity type,
A light emitting element is electrically connected to the third impurity region,
The conductive layer has a central portion of the first shape and a region disposed so as to overlap a part of the second shape;
The display device, wherein the conductive layer has a region functioning as a gate electrode. Having a thin film transistor,
The thin film transistor has a T-shaped island-shaped semiconductor layer and a conductive layer,
The T-type island-like semiconductor layer has first to third end portions and first to third impurity regions,
The first impurity region is provided in a region including the first end;
The second impurity region is provided in a region including the second end,
The third impurity region is provided in a region including the third end;
The first to third impurity regions are of the same conductivity type,
A light emitting element is electrically connected to the third impurity region,
The conductive layer is disposed so as to overlap a region including a T-shaped intersection of the island-shaped semiconductor layers,
The display device, wherein the conductive layer has a region functioning as a gate electrode. An island-shaped semiconductor layer, a first conductive layer, and a second conductive layer;
The island-shaped semiconductor layer has a first region and a second region,
The first region has a first impurity region and a second impurity region;
The second region has a third impurity region,
The first region is a region provided extending in one direction,
The second region is a region provided to extend in a direction perpendicular to the one direction from a region between the first impurity region and the second impurity region,
The first to third impurity regions are of the same conductivity type,
The first conductive layer has a region overlapping with a region between the first impurity region and the second impurity region,
The first conductive layer has a region overlapping with a part of the second region,
The first conductive layer has a region functioning as a gate electrode;
The second conductive layer is electrically connected to the third impurity region;
The second conductive layer has a region functioning as a wiring,
The display device, wherein the first conductive layer does not overlap with the second conductive layer. In any one of Claims 1 thru | or 4,
The thin film transistor is provided on a plastic plate.

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