JP3813555B2 - LIGHT EMITTING DEVICE AND ELECTRONIC DEVICE - Google Patents

Description

【０３７２】
(M.A.Baldo, D.F.O'Brien, Y.You, A.Shoustikov, S.Sibley, M.E.Thompson, S.R.Forrest, Nature 395 (1998) p.151.)
【０３７３】
上記の論文により報告された有機発光材料（Ｐｔ錯体）の分子式を以下に示す。
【０３７４】
【化２】

【０３７５】
(M.A.Baldo, S.Lamansky, P.E.Burrrows, M.E.Thompson, S.R.Forrest, Appl.Phys.Lett.,75 (1999) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)
【０３７６】
上記の論文により報告された有機発光材料（Ｉｒ錯体）の分子式を以下に示す。
【０３７７】
【化３】

【０３７８】
以上のように三重項励起子からの燐光発光を利用できれば原理的には一重項励起子からの蛍光発光を用いる場合より３〜４倍の高い外部発光量子効率の実現が可能となる。
【０３７９】
なお、本実施例の構成は、実施例１〜実施例６のいずれの構成とも自由に組み合わせて実施することが可能である。
【０３８０】
（実施例８）
本実施例では、本発明を用いて発光装置を作製した例について、図２３を用いて説明する。
【０３８１】
図２３は、トランジスタが形成された素子基板をシーリング材によって封止することによって形成された発光装置の上面図であり、図２３（Ｂ）は、図２３（Ａ）のＡ−Ａ’における断面図、図２３（Ｃ）は図２３（Ａ）のＢ−Ｂ’における断面図である。
【０３８２】
基板４００１上に設けられた画素部４００２と、信号線駆動回路４００３と、第１及び第２の走査線駆動回路４００４ａ、ｂとを囲むようにして、シール材４００９が設けられている。また画素部４００２と、信号線駆動回路４００３と、第１及び第２の走査線駆動回路４００４ａ、ｂとの上にシーリング材４００８が設けられている。よって画素部４００２と、信号線駆動回路４００３と、第１及び第２の走査線駆動回路４００４ａ、ｂとは、基板４００１とシール材４００９とシーリング材４００８とによって、充填材４２１０で密封されている。
【０３８３】
また基板４００１上に設けられた画素部４００２と、信号線駆動回路４００３と、第１及び第２の走査線駆動回路４００４ａ、ｂとは、複数のＴＦＴを有している。図２３（Ｂ）では代表的に、下地膜４０１０上に形成された、信号線駆動回路４００３に含まれる駆動ＴＦＴ（但し、ここではｎチャネル型ＴＦＴとｐチャネル型ＴＦＴを図示する）４２０１及び画素部４００２に含まれるトランジスタＴｒ５ ４２０２を図示した。
【０３８４】
本実施例では、駆動ＴＦＴ４２０１には公知の方法で作製されたｐチャネル型ＴＦＴまたはｎチャネル型ＴＦＴが用いられ、トランジスタＴｒ５ ４２０２には公知の方法で作製されたｐチャネル型ＴＦＴが用いられる。
【０３８５】
駆動ＴＦＴ４２０１及びトランジスタＴｒ５ ４２０２上には層間絶縁膜（平坦化膜）４３０１が形成され、その上にトランジスタＴｒ５ ４２０２のドレインと電気的に接続する画素電極（陽極）４２０３が形成される。画素電極４２０３としては仕事関数の大きい透明導電膜が用いられる。透明導電膜としては、酸化インジウムと酸化スズとの化合物、酸化インジウムと酸化亜鉛との化合物、酸化亜鉛、酸化スズまたは酸化インジウムを用いることができる。また、前記透明導電膜にガリウムを添加したものを用いても良い。
【０３８６】
そして、画素電極４２０３の上には絶縁膜４３０２が形成され、絶縁膜４３０２は画素電極４２０３の上に開口部が形成されている。この開口部において、画素電極４２０３の上には有機発光層４２０４が形成される。有機発光層４２０４は公知の有機発光材料または無機発光材料を用いることができる。また、有機発光材料には低分子系（モノマー系）材料と高分子系（ポリマー系）材料があるがどちらを用いても良い。
【０３８７】
有機発光層４２０４の形成方法は公知の蒸着技術もしくは塗布法技術を用いれば良い。また、有機発光層の構造は正孔注入層、正孔輸送層、発光層、電子輸送層または電子注入層を自由に組み合わせて積層構造または単層構造とすれば良い。
【０３８８】
有機発光層４２０４の上には遮光性を有する導電膜（代表的にはアルミニウム、銅もしくは銀を主成分とする導電膜またはそれらと他の導電膜との積層膜）からなる陰極４２０５が形成される。また、陰極４２０５と有機発光層４２０４の界面に存在する水分や酸素は極力排除しておくことが望ましい。従って、有機発光層４２０４を窒素または希ガス雰囲気で形成し、酸素や水分に触れさせないまま陰極４２０５を形成するといった工夫が必要である。本実施例ではマルチチャンバー方式（クラスターツール方式）の成膜装置を用いることで上述のような成膜を可能とする。そして陰極４２０５は所定の電圧が与えられている。
【０３８９】
以上のようにして、画素電極（陽極）４２０３、有機発光層４２０４及び陰極４２０５からなる発光素子４３０３が形成される。そして発光素子４３０３を覆うように、絶縁膜４３０２上に保護膜４２０９が形成されている。保護膜４２０９は、発光素子４３０３に酸素や水分等が入り込むのを防ぐのに効果的である。
【０３９０】
４００５ａは電源線に接続された引き回し配線であり、トランジスタＴｒ５ ４２０２のソースに電気的に接続されている。引き回し配線４００５ａはシール材４００９と基板４００１との間を通り、異方導電性フィルム４３００を介してＦＰＣ４００６が有するＦＰＣ用配線４３０１に電気的に接続される。
【０３９１】
シーリング材４００８としては、ガラス材、金属材（代表的にはステンレス材）、セラミックス材、プラスチック材（プラスチックフィルムも含む）を用いることができる。プラスチック材としては、ＦＲＰ（Ｆｉｂｅｒｇｌａｓｓ−Ｒｅｉｎｆｏｒｃｅｄ Ｐｌａｓｔｉｃｓ）板、ＰＶＦ（ポリビニルフルオライド）フィルム、マイラーフィルム、ポリエステルフィルムまたはアクリル樹脂フィルムを用いることができる。また、アルミニウムホイルをＰＶＦフィルムやマイラーフィルムで挟んだ構造のシートを用いることもできる。
【０３９２】
但し、発光素子からの光の放射方向がカバー材側に向かう場合にはカバー材は透明でなければならない。その場合には、ガラス板、プラスチック板、ポリエステルフィルムまたはアクリルフィルムのような透明物質を用いる。
【０３９３】
また、充填材４２１０としては窒素やアルゴンなどの不活性な気体の他に、紫外線硬化樹脂または熱硬化樹脂を用いることができ、ＰＶＣ（ポリビニルクロライド）、アクリル、ポリイミド、エポキシ樹脂、シリコーン樹脂、ＰＶＢ（ポリビニルブチラル）またはＥＶＡ（エチレンビニルアセテート）を用いることができる。本実施例では充填材として窒素を用いた。
【０３９４】
また充填材４２１０を吸湿性物質（好ましくは酸化バリウム）もしくは酸素を吸着しうる物質にさらしておくために、シーリング材４００８の基板４００１側の面に凹部４００７を設けて吸湿性物質または酸素を吸着しうる物質４２０７を配置する。そして、吸湿性物質または酸素を吸着しうる物質４２０７が飛び散らないように、凹部カバー材４２０８によって吸湿性物質または酸素を吸着しうる物質４２０７は凹部４００７に保持されている。なお凹部カバー材４２０８は目の細かいメッシュ状になっており、空気や水分は通し、吸湿性物質または酸素を吸着しうる物質４２０７は通さない構成になっている。吸湿性物質または酸素を吸着しうる物質４２０７を設けることで、発光素子４３０３の劣化を抑制できる。
【０３９５】
図２３（Ｃ）に示すように、画素電極４２０３が形成されると同時に、引き回し配線４００５ａ上に接するように導電性膜４２０３ａが形成される。
【０３９６】
また、異方導電性フィルム４３００は導電性フィラー４３００ａを有している。基板４００１とＦＰＣ４００６とを熱圧着することで、基板４００１上の導電性膜４２０３ａとＦＰＣ４００６上のＦＰＣ用配線４３０１とが、導電性フィラー４３００ａによって電気的に接続される。
【０３９７】
本実施例の構成は、実施例１〜実施例７に示した構成と自由に組み合わせて実施することが可能である。
【０３９８】
（実施例９）
発光素子に用いられる有機発光材料は低分子系と高分子系に大別される。本発明の発光装置は、低分子系の有機発光材料でも高分子系の有機発光材料でも、どちらでも用いることができる。
【０３９９】
低分子系の有機発光材料は、蒸着法により成膜される。したがって積層構造をとりやすく、ホール輸送層、電子輸送層などの機能が異なる膜を積層することで高効率化しやすい。
【０４００】
低分子系の有機発光材料としては、キノリノールを配位子としたアルミニウム錯体Ａｌｑ₃、トリフェニルアミン誘導体（ＴＰＤ）等が代表的に挙げられる。
【０４０１】
一方、高分子系の有機発光材料は低分子系に比べて物理的強度が高く、素子の耐久性が高い。また塗布により成膜することが可能であるので、素子の作製が比較的容易である。
【０４０２】
高分子系の有機発光材料を用いた発光素子の構造は、低分子系の有機発光材料を用いたときと基本的には同じであり、陰極／有機発光層／陽極となる。しかし、高分子系の有機発光材料を用いた有機発光層を形成する際には、低分子系の有機発光材料を用いたときのような積層構造を形成させることは難しく、知られている中では２層の積層構造が有名である。具体的には、陰極／発光層／正孔輸送層／陽極という構造である。なお、高分子系の有機発光材料を用いた発光素子の場合には、陰極材料としてＣａを用いることも可能である。
【０４０３】
なお、素子の発光色は、発光層を形成する材料で決まるため、これらを選択することで所望の発光を示す発光素子を形成することができる。発光層の形成に用いることができる高分子系の有機発光材料は、ポリパラフェニレンビニレン系、ポリパラフェニレン系、ポリチオフェン系、ポリフルオレン系が代表的に挙げられる。
【０４０４】
ポリパラフェニレンビニレン系には、ポリ（パラフェニレンビニレン） [ＰＰＶ] の誘導体、ポリ（２，５−ジアルコキシ−１，４−フェニレンビニレン） [ＲＯ−ＰＰＶ]、ポリ（２−（２'−エチル−ヘキソキシ）−５−メトキシ−１，４−フェニレンビニレン）[ＭＥＨ−ＰＰＶ]、ポリ（２−（ジアルコキシフェニル）−１,４−フェニレンビニレン）[ＲＯＰｈ−ＰＰＶ]等が挙げられる。
【０４０５】
ポリパラフェニレン系には、ポリパラフェニレン［ＰＰＰ］の誘導体、ポリ（２，５−ジアルコキシ−１，４−フェニレン）[ＲＯ−ＰＰＰ]、ポリ（２，５−ジヘキソキシ−１，４−フェニレン）等が挙げられる。
【０４０６】
ポリチオフェン系には、ポリチオフェン［ＰＴ］の誘導体、ポリ（３−アルキルチオフェン）［ＰＡＴ］、ポリ（３−ヘキシルチオフェン）［ＰＨＴ］、ポリ（３−シクロヘキシルチオフェン）［ＰＣＨＴ］、ポリ（３−シクロヘキシル−４−メチルチオフェン）［ＰＣＨＭＴ］、ポリ（３，４−ジシクロヘキシルチオフェン）［ＰＤＣＨＴ］、ポリ［３−（４−オクチルフェニル）−チオフェン］［ＰＯＰＴ］、ポリ［３−（４−オクチルフェニル）−２，２ビチオフェン］［ＰＴＯＰＴ］等が挙げられる。
【０４０７】
ポリフルオレン系には、ポリフルオレン［ＰＦ］の誘導体、ポリ（９，９−ジアルキルフルオレン）［ＰＤＡＦ］、ポリ（９，９−ジオクチルフルオレン）［ＰＤＯＦ］等が挙げられる。
【０４０８】
なお、正孔輸送性の高分子系の有機発光材料を、陽極と発光性の高分子系有機発光材料の間に挟んで形成すると、陽極からの正孔注入性を向上させることができる。一般にアクセプター材料と共に水に溶解させたものをスピンコート法などで塗布する。また、有機溶媒には不溶であるため、上述した発光性の有機発光材料との積層が可能である。
【０４０９】
正孔輸送性の高分子系の有機発光材料としては、ＰＥＤＯＴとアクセプター材料としてのショウノウスルホン酸（ＣＳＡ）の混合物、ポリアニリン［ＰＡＮＩ］とアクセプター材料としてのポリスチレンスルホン酸［ＰＳＳ］の混合物等が挙げられる。
【０４１０】
なお、本実施例の構成は、実施例１〜実施例８のいずれの構成とも自由に組み合わせて実施することが可能である。
【０４１１】
（実施例１０）
発光素子を用いた発光装置は自発光型であるため、液晶ディスプレイに比べ、明るい場所での視認性に優れ、視野角が広い。従って、様々な電子機器の表示部に用いることができる。
【０４１２】
本発明の発光装置を用いた電子機器として、ビデオカメラ、デジタルカメラ、ゴーグル型ディスプレイ（ヘッドマウントディスプレイ）、ナビゲーションシステム、音響再生装置（カーオーディオ、オーディオコンポ等）、ノート型パーソナルコンピュータ、ゲーム機器、携帯情報端末（モバイルコンピュータ、携帯電話、携帯型ゲーム機または電子書籍等）、記録媒体を備えた画像再生装置（具体的にはDigital Versatile Disc（ＤＶＤ）等の記録媒体を再生し、その画像を表示しうるディスプレイを備えた装置）などが挙げられる。特に、斜め方向から画面を見る機会が多い携帯情報端末は、視野角の広さが重要視されるため、発光装置を用いることが望ましい。それら電子機器の具体例を図２４に示す。
【０４１３】
図２４（Ａ）は発光素子表示装置であり、筐体２００１、支持台２００２、表示部２００３、スピーカー部２００４、ビデオ入力端子２００５等を含む。本発明の発光装置は表示部２００３に用いることができる。発光装置は自発光型であるためバックライトが必要なく、液晶ディスプレイよりも薄い表示部とすることができる。なお、発光素子表示装置は、パソコン用、ＴＶ放送受信用、広告表示用などの全ての情報表示用表示装置が含まれる。
【０４１４】
図２４（Ｂ）はデジタルスチルカメラであり、本体２１０１、表示部２１０２、受像部２１０３、操作キー２１０４、外部接続ポート２１０５、シャッター２１０６等を含む。本発明の発光装置は表示部２１０２に用いることができる。
【０４１５】
図２４（Ｃ）はノート型パーソナルコンピュータであり、本体２２０１、筐体２２０２、表示部２２０３、キーボード２２０４、外部接続ポート２２０５、ポインティングマウス２２０６等を含む。本発明の発光装置は表示部２２０３に用いることができる。
【０４１６】
図２４（Ｄ）はモバイルコンピュータであり、本体２３０１、表示部２３０２、スイッチ２３０３、操作キー２３０４、赤外線ポート２３０５等を含む。本発明の発光装置は表示部２３０２に用いることができる。
【０４１７】
図２４（Ｅ）は記録媒体を備えた携帯型の画像再生装置（具体的にはＤＶＤ再生装置）であり、本体２４０１、筐体２４０２、表示部Ａ２４０３、表示部Ｂ２４０４、記録媒体（ＤＶＤ等）読み込み部２４０５、操作キー２４０６、スピーカー部２４０７等を含む。表示部Ａ２４０３は主として画像情報を表示し、表示部Ｂ２４０４は主として文字情報を表示するが、本発明の発光装置はこれら表示部Ａ、Ｂ２４０３、２４０４に用いることができる。なお、記録媒体を備えた画像再生装置には家庭用ゲーム機器なども含まれる。
【０４１８】
図２４（Ｆ）はゴーグル型ディスプレイ（ヘッドマウントディスプレイ）であり、本体２５０１、表示部２５０２、アーム部２５０３を含む。本発明の発光装置は表示部２５０２に用いることができる。
【０４１９】
図２４（Ｇ）はビデオカメラであり、本体２６０１、表示部２６０２、筐体２６０３、外部接続ポート２６０４、リモコン受信部２６０５、受像部２６０６、バッテリー２６０７、音声入力部２６０８、操作キー２６０９、接眼部２６１０等を含む。本発明の発光装置は表示部２６０２に用いることができる。
【０４２０】
ここで図２４（Ｈ）は携帯電話であり、本体２７０１、筐体２７０２、表示部２７０３、音声入力部２７０４、音声出力部２７０５、操作キー２７０６、外部接続ポート２７０７、アンテナ２７０８等を含む。本発明の発光装置は表示部２７０３に用いることができる。なお、表示部２７０３は黒色の背景に白色の文字を表示することで携帯電話の消費電流を抑えることができる。
【０４２１】
なお、将来的に有機発光材料の発光輝度が高くなれば、出力した画像情報を含む光をレンズ等で拡大投影してフロント型若しくはリア型のプロジェクターに用いることも可能となる。
【０４２２】
また、上記電子機器はインターネットやＣＡＴＶ（ケーブルテレビ）などの電子通信回線を通じて配信された情報を表示することが多くなり、特に動画情報を表示する機会が増してきている。有機発光材料の応答速度は非常に高いため、発光装置は動画表示に好ましい。
【０４２３】
また、発光装置は発光している部分が電力を消費するため、発光部分が極力少なくなるように情報を表示することが望ましい。従って、携帯情報端末、特に携帯電話や音響再生装置のような文字情報を主とする表示部に発光装置を用いる場合には、非発光部分を背景として文字情報を発光部分で形成するように駆動することが望ましい。
【０４２４】
以上の様に、本発明の適用範囲は極めて広く、あらゆる分野の電子機器に用いることが可能である。また、本実施例の電子機器は実施例１〜９に示したいずれの構成の発光装置を用いても良い。
【０４２５】
（実施例１１）
本実施例では、図２に示した発光装置が有する画素１０１の構成について説明する。
【０４２６】
図２８に、図２で示した画素１０１の詳しい構成を示す。図２８に示す画素１０１は、信号線Ｓｉ（Ｓ１〜Ｓｘのうちの１つ）、第１走査線Ｇｊ（Ｇ１〜Ｇｙのうちの１つ）、第２走査線Ｐｊ（Ｐ１〜Ｐｙのうちの１つ）、第３走査線Ｒｊ（Ｒ１〜Ｒｙのうちの１つ）及び電源線Ｖｉ（Ｖ１〜Ｖｘのうちの１つ）を有している。
【０４２７】
また画素１０１は、トランジスタＴｒ１、トランジスタＴｒ２、トランジスタＴｒ３、トランジスタＴｒ４、トランジスタＴｒ５、トランジスタＴｒ６、発光素子７０１及び保持容量７０２を有している。保持容量７０２はトランジスタＴｒ１及びＴｒ２のゲートとソースの間の電圧（ゲート電圧）をより確実に保持するために設けられているが、必ずしも設ける必要はない。
【０４２８】
トランジスタＴｒ３のゲートは第１走査線Ｇｊに接続されている。そしてトランジスタＴｒ３のソースとドレインは、一方は信号線Ｓｉに接続されており、もう一方はトランジスタＴｒ１のドレインに接続されている。
【０４２９】
トランジスタＴｒ４のゲートは、第２走査線Ｐｊに接続されている。そしてトランジスタＴｒ４のソースとドレインは、一方はトランジスタＴｒ１のドレインに、もう一方はトランジスタＴｒ１及びＴｒ２のゲートに接続されている。
【０４３０】
トランジスタＴｒ６のゲートは、トランジスタＴｒ１及びＴｒ２のゲートに接続されている。そしてトランジスタＴｒ６のソースとドレインは、一方はトランジスタＴｒ１のドレインに、もう一方はトランジスタＴｒ５のソースまたはドレインに接続されている。
【０４３１】
トランジスタＴｒ５のゲートは、第３走査線Ｒｊに接続されている。そしてトランジスタＴｒ５のソースとドレインは、一方はトランジスタＴｒ２のドレインに、もう一方はトランジスタＴｒ６のソースまたはドレインに接続されている。
【０４３２】
トランジスタＴｒ１とトランジスタＴｒ２とＴｒ６のゲートは、互いに接続されている。トランジスタＴｒ１とトランジスタＴｒ２のソースは、共に電源線Ｖｉに接続されている。そして、トランジスタＴｒ２のドレインは、発光素子７０１の画素電極に接続されている。
【０４３３】
保持容量７０２が有する２つの電極は、一方はトランジスタＴｒ１とトランジスタＴｒ２のゲートに、もう一方は電源線Ｖｉに接続されている。
【０４３４】
電源線Ｖｉの電圧（電源電圧）は一定の高さに保たれている。また対向電極の電圧も、一定の高さに保たれている。
【０４３５】
なお、トランジスタＴｒ１、Ｔｒ２及びＴｒ６はｎチャネル型トランジスタとｐチャネル型トランジスタのどちらでも良い。ただし、トランジスタＴｒ１、Ｔｒ２及びＴｒ６の極性は同じである。なお、陽極を画素電極として用い、陰極を対向電極として用いる場合、トランジスタＴｒ１及びＴｒ２はｐチャネル型トランジスタであるのが望ましい。逆に、陽極を対向電極として用い、陰極を画素電極として用いる場合、トランジスタＴｒ１及びＴｒ２はｎチャネル型トランジスタであるのが望ましい。
【０４３６】
トランジスタＴｒ３、Ｔｒ４、Ｔｒ５は、ｎチャネル型トランジスタとｐチャネル型トランジスタのどちらでも良い。
【０４３７】
次に、本実施例の発光装置の動作について説明する。図２８に示した画素を有する発光装置の動作は、図３に示した画素の場合と同様に、書き込み期間Ｔａと表示期間Ｔｄとに分けて説明することが可能である。
【０４３８】
また、第１〜３走査線に印加される電圧については、図４に示したタイミングチャートを参照することができる。また図２９は、図２８に示した画素の、書き込み期間Ｔａと表示期間ＴｄにおけるトランジスタＴｒ１とトランジスタＴｒ２の接続を、簡単に示した図である。
【０４３９】
書き込み期間Ｔａが開始されると、第１走査線Ｇ、第２走査線Ｐが選択される。よって、トランジスタＴｒ３とトランジスタＴｒ４がオンになる。なお、第３走査線Ｒは選択されていないので、トランジスタＴｒ５はオフになっている。
【０４４０】
そして、信号線駆動回路１０２に入力されるビデオ信号に基づき、信号線Ｓ１〜Ｓｘと電源線Ｖ１〜Ｖｘの間に、それぞれビデオ信号に応じた信号電流Ｉｃが流れる。
【０４４１】
図２９（Ａ）に、書き込み期間Ｔａにおいて、信号線Ｓｉにビデオ信号に応じた信号電流Ｉｃが流れた場合の、画素１０１の概略図を示す。７０６は対向電極に電圧を与える電源との接続用の端子を意味している。また、７０７は信号線駆動回路１０２が有する定電流源を意味する。
【０４４２】
トランジスタＴｒ３はオンの状態にあるので、信号線Ｓｉにビデオ信号に応じた信号電流Ｉｃが流れると、信号電流ＩｃはトランジスタＴｒ１のドレインとソースの間に流れる。このときトランジスタＴｒ１は、ゲートとドレインが接続されているので飽和領域で動作しており、式１が成り立つ。よって、トランジスタＴｒ１のゲート電圧Ｖ_GSは電流値Ｉｃによって定まる。
【０４４３】
そしてトランジスタＴｒ２のゲートは、トランジスタＴｒ１のゲートに接続されている。また、トランジスタＴｒ２のソースは、トランジスタＴｒ１のソースに接続されている。したがって、トランジスタＴｒ１のゲート電圧は、そのままトランジスタＴｒ２のゲート電圧となる。よって、トランジスタＴｒ２のドレイン電流は、トランジスタＴｒ１のドレイン電流に比例する。特に、μＣ₀Ｗ／Ｌ及びＶ_THが互いに等しいとき、トランジスタＴｒ１とトランジスタＴｒ２のドレイン電流は互いに等しくなり、Ｉ₂＝Ｉｃとなる。
【０４４４】
そして、トランジスタＴｒ２のドレイン電流Ｉ₂は発光素子７０４に流れる。発光素子に流れる電流は、定電流源７０７において定められた信号電流Ｉｃに応じた大きさであり、流れる電流の大きさに見合った輝度で発光素子７０４は発光する。発光素子に流れる電流が０に限りなく近かったり、発光素子に流れる電流が逆バイアスの方向に流れたりする場合は、発光素子７０４は発光しない。
【０４４５】
書き込み期間Ｔａが終了すると、第１走査線Ｇ、第２走査線Ｐの選択が終了する。このとき、第２走査線Ｐの選択が、第１走査線Ｇよりも先に終了するのが望ましい。なぜならトランジスタＴｒ３が先にオフになってしまうと、保持容量７０５の電荷がＴｒ４を通って漏れてしまうからである。
【０４４６】
書き込み期間Ｔａが終了すると、次に表示期間Ｔｄが開始される。表示期間Ｔｄが開始されると、第３走査線Ｒが選択されトランジスタＴｒ５がオンになる。なお、第１走査線Ｇ及び第２走査線Ｐは選択されていないので、トランジスタＴｒ３及びＴｒ４はオフになっている。
【０４４７】
図２９（Ｂ）に、表示期間Ｔｄにおける画素の概略図を示す。トランジスタＴｒ３及びトランジスタＴｒ４はオフの状態にある。また、トランジスタＴｒ１及びトランジスタＴｒ２のソースは電源線Ｖｉに接続されており、一定の電圧（電源電圧）が与えられている。
【０４４８】
一方トランジスタＴｒ１、Ｔｒ２においては、書き込み期間Ｔａにおいて定められたＶ_GSがそのまま保持されている。さらに、トランジスタＴｒ６のゲートはトランジスタＴｒ１及びＴｒ２のゲートと接続されている。そのため、トランジスタＴｒ１のドレイン電流とトランジスタＴｒ６のドレイン電流は同じ大きさに保たれる。そして、式１より、トランジスタＴｒ１のドレイン電流は、トランジスタＴｒ６のチャネル長及びチャネル幅に左右される。
【０４４９】
トランジスタＴｒ１とＴｒ６のゲート電圧、移動度、単位面積あたりのゲート容量、閾値、チャネル幅が等しいと仮定すると、式１より以下の式２が導き出される。なお、式２においてトランジスタＴｒ１のチャネル長をＬ１、Ｔｒ６のチャネル長をＬ６、Ｔｒ１及びＴｒ６のドレイン電流をＩ₃とする。
【０４５０】
【式２】
Ｉ₃＝Ｉ₁×Ｌ１／（Ｌ１＋Ｌ６）
【０４５１】
一方、トランジスタＴｒ２のドレイン電流Ｉ₂の値は、信号電流Ｉｃに応じた大きさに維持されたままである。
【０４５２】
そして、トランジスタＴｒ５がオンなので、トランジスタＴｒ１及びＴｒ６のドレイン電流Ｉ₃と、トランジスタＴｒ２のドレイン電流Ｉ₂は、共に発光素子７０４に流れる。よって、ドレイン電流Ｉ₃と、ドレイン電流Ｉ₂を合わせた電流の大きさに見合った輝度で、発光素子７０４は発光する。
【０４５３】
なお、発光素子に流れる電流の大きさに見合った輝度で発光素子７０４が発光するので、各画素の階調は、表示期間Ｔｄにおける発光素子に流れる電流の大きさで決まる。なお、書き込み期間Ｔａにおいても、ドレイン電流Ｉ₁の大きさに見合った輝度で発光しているが、その階調に与える影響は、実際のパネルでは無視できる程度に小さいと考えられる。なぜなら、例えばＶＧＡだと４８０ラインの画素が画素部に設けられており、１ラインの画素の書き込み期間Ｔａは１フレーム期間の１／４８０程度と非常に小さいからである。もちろん、書き込み期間Ｔａにおける発光素子に流れる電流の階調への影響を考慮に入れて、信号電流Ｉｃの大きさを補正するようにしても良い。
【０４５４】
本発明の画素では、表示期間において発光素子に流れる電流はドレイン電流Ｉ₂と、ドレイン電流Ｉ₃の和である。よって、発光素子に流れる電流がドレイン電流Ｉ₂のみに依存していない。そのため、トランジスタＴｒ１とトランジスタＴｒ２の特性がずれて、トランジスタＴｒ２のドレイン電流Ｉ₂と信号電流Ｉｃの比が画素間で異なっても、発光素子に流れる電流の値が画素間でずれるのを抑え、輝度のばらつきが視認されるのを防ぐことができる。
【０４５５】
また、本発明の画素では、書き込み期間ＴａにおいてトランジスタＴｒ１のドレイン電流は発光素子に流れていない。よって信号線駆動回路によって画素に電流が供給され、トランジスタＴｒ１のドレイン電流が流れることでゲート電圧が変化しはじめてから、その値が安定するまでの時間は、発光素子の容量に左右されない。したがって、従来の画素と比べて、供給された電流から変換される電圧が早く安定するので、電流を書き込む時間を短くすることができ、動画表示において残像が視認されてしまうのを防ぐことができる。
【０４５６】
また、従来と同様に、電流入力型の発光装置の利点も兼ね備えている。すなわち、ＴＦＴの特性が画素毎にばらついていても、電圧入力型の発光装置に比べて画素間で発光素子の輝度にばらつきが生じるのを防ぐことができる。また、図２５に示した電圧入力型の画素のＴＦＴ５１を線形領域で動作させたときに比べて、発光素子の劣化による輝度の低下を抑えることができる。また、有機発光層の温度が外気温や発光パネル自身が発する熱等に左右されても、発光素子の輝度が変化するのを抑えることができ、また温度の上昇に伴って消費電流が大きくなるのを防ぐことができる。
【０４５７】
さらに、本実施例の画素では、図３、図５、図７、図９、図１０及び図１１に示した画素に比べて、書き込み期間におけるトランジスタＴｒ１のドレイン電流よりも、表示期間におけるＴｒ１のドレイン電流が小さいため、信号電流Ｉｃに対する発光素子に流れる電流の比が小さくなる。よって、信号電流Ｉｃをより大きくすることができるので、雑音の影響を受けにくい。
【０４５８】
なお、本実施例において、トランジスタＴｒ４のソースとドレインは、一方はトランジスタＴｒ１のドレインに、もう一方はトランジスタＴｒ１のゲート及びトランジスタＴｒ２のゲートに接続されている。しかし本実例はこの構成に限定されない。本発明の画素は、書き込み期間ＴａにおいてトランジスタＴｒ１のゲートとドレインを接続し、表示期間においてトランジスタＴｒ１のゲートとドレインを切り離すことができるように、トランジスタＴｒ４が他の素子または配線と接続されていれば良い。
【０４５９】
また本実施例において、トランジスタＴｒ５のソースとドレインは、一方はＴｒ１のドレインに、もう一方はＴｒ６のソースまたはドレインに接続されている。しかし本実例はこの構成に限定されない。本発明の画素は、書き込み期間ＴａにおいてトランジスタＴｒ１のドレインと画素電極とを切り離し、表示期間においてトランジスタＴｒ２のドレインと画素電極とを接続することができるように、トランジスタＴｒ５が他の素子または配線と接続されていれば良い。例えば、トランジスタＴｒ５のソースとドレインが、一方はＴｒ１のドレインに、もう一方はＴｒ６のソースまたはドレインに接続されていても良い。
【０４６０】
つまり、Ｔｒ３、Ｔｒ４、Ｔｒ５は、Ｔａでは図２９（Ａ）のように接続され、Ｔｄでは図２９（Ｂ）のように接続されていれば良い。また、Ｇｊ、Ｐｊ、Ｒｊは３本が別の配線となっているが、まとめて１本や２本にしても良い。
【０４６１】
つまり、ＴａにおいてＴｒ１を流れる電流は全て電流源で制御されていれば良い。ＴｄにおいてはＴｒ１とＴｒ２を流れる電流は発光素子に流れれば良い。
【０４６２】
なお、本実施例の構成は、実施例４〜実施例１０のいずれの構成とも自由に組み合わせて実施することが可能である。
【０４６３】
（実施例１２）
本実施例では、図２に示した発光装置が有する画素１０１の構成について説明する。
【０４６４】
図３０に、図２で示した画素１０１の詳しい構成を示す。図３０に示す画素１０１は、信号線Ｓｉ（Ｓ１〜Ｓｘのうちの１つ）、第１走査線Ｇｊ（Ｇ１〜Ｇｙのうちの１つ）、第２走査線Ｐｊ（Ｐ１〜Ｐｙのうちの１つ）、第３走査線Ｒｊ（Ｒ１〜Ｒｙのうちの１つ）及び電源線Ｖｉ（Ｖ１〜Ｖｘのうちの１つ）を有している。
【０４６５】
また画素１０１は、トランジスタＴｒ１、トランジスタＴｒ２、トランジスタＴｒ３、トランジスタＴｒ４、トランジスタＴｒ５、発光素子７３０及び保持容量７３１を有している。保持容量７３１はトランジスタＴｒ１及びＴｒ２のゲートとソースの間の電圧（ゲート電圧）をより確実に保持するために設けられているが、必ずしも設ける必要はない。
【０４６６】
トランジスタＴｒ３のゲートは第１走査線Ｇｊに接続されている。そしてトランジスタＴｒ３のソースとドレインは、一方は信号線Ｓｉに接続されており、もう一方はトランジスタＴｒ１のドレインに接続されている。
【０４６７】
トランジスタＴｒ４のゲートは、第２走査線Ｐｊに接続されている。そしてトランジスタＴｒ４のソースとドレインは、一方はトランジスタＴｒ１のドレインに、もう一方はトランジスタＴｒ１及びＴｒ２のゲートに接続されている。
【０４６８】
トランジスタＴｒ５のゲートは、第３走査線Ｒｊに接続されている。そしてトランジスタＴｒ５のソースとドレインは、一方はトランジスタＴｒ２のドレイン及び電源線Ｖｉに、もう一方はトランジスタＴｒ１のドレインに接続されている。
【０４６９】
トランジスタＴｒ１とトランジスタＴｒ２のゲートは、互いに接続されている。トランジスタＴｒ１とトランジスタＴｒ２のソースは、共に発光素子７３０の画素電極に接続されている。
【０４７０】
保持容量７３１が有する２つの電極は、一方はトランジスタＴｒ１とトランジスタＴｒ２のゲートに、もう一方は発光素子７３０の画素電極に接続されている。
【０４７１】
電源線Ｖｉの電圧（電源電圧）は一定の高さに保たれている。また対向電極の電圧も、一定の高さに保たれている。
【０４７２】
なお、トランジスタＴｒ１及びＴｒ２はｎチャネル型トランジスタとｐチャネル型トランジスタのどちらでも良い。ただし、トランジスタＴｒ１及びＴｒ２の極性は同じである。なお、陽極を画素電極として用い、陰極を対向電極として用いる場合、トランジスタＴｒ１及びＴｒ２はｎチャネル型トランジスタであるのが望ましい。逆に、陽極を対向電極として用い、陰極を画素電極として用いる場合、トランジスタＴｒ１及びＴｒ２はｐチャネル型トランジスタであるのが望ましい。
【０４７３】
トランジスタＴｒ３、Ｔｒ４、Ｔｒ５は、ｎチャネル型トランジスタとｐチャネル型トランジスタのどちらでも良い。
【０４７４】
図３０に示した画素を有する発光装置の動作は、図３に示した画素の場合と同様に、書き込み期間Ｔａと表示期間Ｔｄとに分けて説明することが可能である。また、第１〜３走査線に印加される電圧については、図４に示したタイミングチャートを参照することができる。また図３１は、図３０に示した画素の、書き込み期間Ｔａと表示期間ＴｄにおけるトランジスタＴｒ１とトランジスタＴｒ２の接続を、簡単に示した図である。
【０４７５】
書き込み期間Ｔａが開始されると、第１走査線Ｇ、第２走査線Ｐが選択される。よって、トランジスタＴｒ３とトランジスタＴｒ４がオンになる。なお、第３走査線Ｒは選択されていないので、トランジスタＴｒ５はオフになっている。
【０４７６】
そして、信号線駆動回路１０２に入力されるビデオ信号に基づき、信号線Ｓ１〜Ｓｘと電源線Ｖ１〜Ｖｘの間に、それぞれビデオ信号に応じた信号電流Ｉｃが流れる。
【０４７７】
図３１（Ａ）に、書き込み期間Ｔａにおいて、信号線Ｓｉにビデオ信号に応じた信号電流Ｉｃが流れた場合の、画素１０１の概略図を示す。７３６は対向電極に電圧を与える電源との接続用の端子を意味している。また、７３７は信号線駆動回路１０２が有する定電流源を意味する。
【０４７８】
トランジスタＴｒ３はオンの状態にあるので、信号線Ｓｉにビデオ信号に応じた信号電流Ｉｃが流れると、信号電流ＩｃはトランジスタＴｒ１のドレインとソースの間に流れる。このときトランジスタＴｒ１は、ゲートとドレインが接続されているので飽和領域で動作しており、式１が成り立つ。よって、トランジスタＴｒ１のゲート電圧Ｖ_GSは電流値Ｉｃによって定まる。
【０４７９】
そしてトランジスタＴｒ２のゲートは、トランジスタＴｒ１のゲートに接続されている。また、トランジスタＴｒ２のソースは、トランジスタＴｒ１のソースに接続されている。したがって、トランジスタＴｒ１のゲート電圧は、そのままトランジスタＴｒ２のゲート電圧となる。よって、トランジスタＴｒ２のドレイン電流は、トランジスタＴｒ１のドレイン電流に比例する。特に、μＣ₀Ｗ／Ｌ及びＶ_THが互いに等しいとき、トランジスタＴｒ１とトランジスタＴｒ２のドレイン電流は互いに等しくなり、Ｉ₂＝Ｉｃとなる。
【０４８０】
そして、トランジスタＴｒ２のドレイン電流Ｉ₂は発光素子７３０に流れる。発光素子に流れる電流は、定電流源７３７において定められた信号電流Ｉｃに応じた大きさであり、流れる電流の大きさに見合った輝度で発光素子７３０は発光する。発光素子に流れる電流が０に限りなく近かったり、発光素子に流れる電流が逆バイアスの方向に流れたりする場合は、発光素子７３０は発光しない。
【０４８１】
書き込み期間Ｔａが終了すると、第１走査線Ｇ、第２走査線Ｐの選択が終了する。このとき、第２走査線Ｐの選択が、第１走査線Ｇよりも先に終了するのが望ましい。なぜならトランジスタＴｒ３が先にオフになってしまうと、保持容量７３１の電荷がＴｒ４を通って漏れてしまうからである。
【０４８２】
書き込み期間Ｔａが終了すると、次に表示期間Ｔｄが開始される。表示期間Ｔｄが開始されると、第３走査線Ｒが選択されトランジスタＴｒ５がオンになる。なお、第１走査線Ｇ及び第２走査線Ｐは選択されていないので、トランジスタＴｒ３及びＴｒ４はオフになっている。
【０４８３】
図３１（Ｂ）に、表示期間Ｔｄにおける画素の概略図を示す。トランジスタＴｒ３及びトランジスタＴｒ４はオフの状態にある。また、トランジスタＴｒ１及びトランジスタＴｒ２のソースは発光素子７３０の画素電極に接続されている。
【０４８４】
一方トランジスタＴｒ１、Ｔｒ２においては、書き込み期間Ｔａにおいて定められたＶ_GSがそのまま保持されている。そして、トランジスタＴｒ２のゲートは、トランジスタＴｒ１のゲートに接続されている。また、トランジスタＴｒ２のソースは、トランジスタＴｒ１のソースに接続されている。よって、トランジスタＴｒ１のゲート電圧は、そのままトランジスタＴｒ２のゲート電圧となる。さらに、トランジスタＴｒ１のドレイン及びトランジスタＴｒ２のドレインは電源線Ｖｉに接続されているので、トランジスタＴｒ２のドレイン電流Ｉ₂は、トランジスタＴｒ１のドレイン電流Ｉ₁に比例する大きさになる。特に、μＣ₀Ｗ／Ｌ及びＶ_THが互いに等しいとき、トランジスタＴｒ１とトランジスタＴｒ２のドレイン電流は互いに等しくなり、Ｉ₂＝Ｉ₁＝Ｉｃとなる。
【０４８５】
また、トランジスタＴｒ５がオンなので、トランジスタＴｒ１のドレイン電流Ｉ₁と、トランジスタＴｒ２のドレイン電流Ｉ₂は、共に発光素子に流れる電流として発光素子７３０に流れる。よって、表示期間Ｔｄでは、ドレイン電流Ｉ₁と、ドレイン電流Ｉ₂を合わせた大きさの電流が発光素子７３０に流れ、該発光素子に流れる電流の大きさに見合った輝度で、発光素子７３０が発光する。
【０４８６】
そして１ライン目の画素において表示期間Ｔｄが開始されると、次に２ライン目の画素において表示期間Ｔｄが開始される。そして１ライン目の画素と同様に、第３走査線Ｒ２が選択され、トランジスタＴｒ５、Ｔｒ６がオンになる。なお、第１走査線Ｇ２及び第２走査線Ｐ２は選択されていないので、トランジスタＴｒ３及びＴｒ４はオフになっている。よって、ドレイン電流Ｉ₁と、ドレイン電流Ｉ₂を合わせた電流の大きさに見合った輝度で、発光素子７３０は発光する。
【０４８７】
そして、２ライン目の画素において表示期間Ｔｄが開始されると、３ライン目からｙライン目の画素まで順に表示期間Ｔｄが開始され、上述した動作が繰り返される。
【０４８８】
書き込み期間Ｔａと、表示期間Ｔｄが終了すると１フレーム期間が終了する。１つのフレーム期間において１つの画像が表示される。そして、次のフレーム期間が開始され、再び書き込み期間Ｔａが開始されて、上述した動作が繰り返される。
【０４８９】
なお、発光素子に流れる電流の大きさに見合った輝度で発光素子７３０が発光するので、各画素の階調は、表示期間Ｔｄにおける発光素子に流れる電流の大きさで決まる。
【０４９０】
なお、発光素子に流れる電流の大きさに見合った輝度で発光素子７３０が発光するので、各画素の階調は、表示期間Ｔｄにおける発光素子に流れる電流の大きさで決まる。
【０４９１】
本発明の画素では、表示期間において発光素子に流れる電流はドレイン電流Ｉ₁と、ドレイン電流Ｉ₂の和である。よって、発光素子に流れる電流がドレイン電流Ｉ₂のみに依存していない。そのため、トランジスタＴｒ１とトランジスタＴｒ２の特性がずれて、トランジスタＴｒ２のドレイン電流Ｉ₂と信号電流Ｉｃの比が画素間で異なっても、発光素子に流れる電流の値が画素間でずれるのを抑え、輝度のばらつきが視認されるのを防ぐことができる。
【０４９２】
また、本発明の画素では、書き込み期間ＴａにおいてトランジスタＴｒ１のドレイン電流は発光素子に流れていない。よって信号線駆動回路によって画素に電流が供給され、トランジスタＴｒ１のドレイン電流が流れることでゲート電圧が変化しはじめてから、その値が安定するまでの時間は、発光素子の容量に左右されない。したがって、従来の画素と比べて、供給された電流から変換される電圧が早く安定するので、電流を書き込む時間を短くすることができ、動画表示において残像が視認されてしまうのを防ぐことができる。
【０４９３】
また、従来と同様に、電流入力型の発光装置の利点も兼ね備えている。すなわち、ＴＦＴの特性が画素毎にばらついていても、電圧入力型の発光装置に比べて画素間で発光素子の輝度にばらつきが生じるのを防ぐことができる。また、図２５に示した電圧入力型の画素のＴＦＴ５１を線形領域で動作させたときに比べて、発光素子の劣化による輝度の低下を抑えることができる。また、有機発光層の温度が外気温や発光パネル自身が発する熱等に左右されても、発光素子の輝度が変化するのを抑えることができ、また温度の上昇に伴って消費電流が大きくなるのを防ぐことができる。
【０４９４】
なお、本実施例において、トランジスタＴｒ４のソースとドレインは、一方はトランジスタＴｒ１のドレインに、もう一方はトランジスタＴｒ１のゲート及びトランジスタＴｒ２のゲートに接続されている。しかし本実例はこの構成に限定されない。本発明の画素は、書き込み期間ＴａにおいてトランジスタＴｒ１のゲートとドレインを接続し、表示期間においてトランジスタＴｒ１のゲートとドレインを切り離すことができるように、トランジスタＴｒ４が他の素子または配線と接続されていれば良い。
【０４９５】
また本実施例において、トランジスタＴｒ５のソースとドレインは、一方はＴｒ２のドレインに、もう一方はＴｒ３のソースまたはドレインに接続されている。しかし本実例はこの構成に限定されない。
【０４９６】
つまり、Ｔｒ３、Ｔｒ４、Ｔｒ５は、Ｔａでは図３１（Ａ）のように接続され、Ｔｄでは図３１（Ｂ）のように接続されていれば良い。また、Ｇｊ、Ｐｊ、Ｒｊは３本が別の配線となっているが、まとめて１本や２本にしても良い。
【０４９７】
つまり、ＴａにおいてＴｒ１を流れる電流は全て電流源で制御されていれば良い。ＴｄにおいてはＴｒ１とＴｒ２を流れる電流は発光素子に流れれば良い。
【０４９８】
なお、本実施例の構成は、実施例４〜実施例１１のいずれの構成とも自由に組み合わせて実施することが可能である。
【０４９９】
（実施例１３）
本実施例では、図２に示した発光装置が有する画素１０１の構成について説明する。
【０５００】
図３２に、図２で示した画素１０１の詳しい構成を示す。図３２に示す画素１０１は、信号線Ｓｉ（Ｓ１〜Ｓｘのうちの１つ）、第１走査線Ｇｊ（Ｇ１〜Ｇｙのうちの１つ）、第２走査線Ｐｊ（Ｐ１〜Ｐｙのうちの１つ）、第３走査線Ｒｊ（Ｒ１〜Ｒｙのうちの１つ）及び電源線Ｖｉ（Ｖ１〜Ｖｘのうちの１つ）を有している。
【０５０１】
また画素１０１は、トランジスタＴｒ１、トランジスタＴｒ２、トランジスタＴｒ３、トランジスタＴｒ４、トランジスタＴｒ５、トランジスタＴｒ６、発光素子７６０及び保持容量７６１を有している。保持容量７６１はトランジスタＴｒ１及びＴｒ２のゲートとソースの間の電圧（ゲート電圧）をより確実に保持するために設けられているが、必ずしも設ける必要はない。
【０５０２】
トランジスタＴｒ３のゲートは第１走査線Ｇｊに接続されている。そしてトランジスタＴｒ３のソースとドレインは、一方は信号線Ｓｉに接続されており、もう一方はトランジスタＴｒ１のドレインに接続されている。
【０５０３】
トランジスタＴｒ４のゲートは、第２走査線Ｐｊに接続されている。そしてトランジスタＴｒ４のソースとドレインは、一方はトランジスタＴｒ１のドレインに、もう一方はトランジスタＴｒ１及びＴｒ２のゲートに接続されている。
【０５０４】
トランジスタＴｒ５のゲートは、第３走査線Ｒｊに接続されている。そしてトランジスタＴｒ５のソースとドレインは、一方はトランジスタＴｒ２のドレイン及び電源線Ｖｉに、もう一方はトランジスタＴｒ６のソースまたはドレインに接続されている。
【０５０５】
トランジスタＴｒ６のゲートは、トランジスタＴｒ１及びＴｒ２のゲートに接続されている。そしてトランジスタＴｒ６のソースとドレインは、一方はトランジスタＴｒ１のドレインに、もう一方はトランジスタＴｒ５のソースまたはドレインに接続されている。
【０５０６】
トランジスタＴｒ１とトランジスタＴｒ２のゲートは、互いに接続されている。トランジスタＴｒ１とトランジスタＴｒ２のソースは、共に発光素子７６０の画素電極に接続されている。
【０５０７】
保持容量７６１が有する２つの電極は、一方はトランジスタＴｒ１とトランジスタＴｒ２のゲートに、もう一方は発光素子７６０の画素電極に接続されている。
【０５０８】
電源線Ｖｉの電圧（電源電圧）は一定の高さに保たれている。また対向電極の電圧も、一定の高さに保たれている。
【０５０９】
なお、トランジスタＴｒ１及びＴｒ２はｎチャネル型トランジスタとｐチャネル型トランジスタのどちらでも良い。ただし、トランジスタＴｒ１及びＴｒ２の極性は同じである。なお、陽極を画素電極として用い、陰極を対向電極として用いる場合、トランジスタＴｒ１及びＴｒ２はｎチャネル型トランジスタであるのが望ましい。逆に、陽極を対向電極として用い、陰極を画素電極として用いる場合、トランジスタＴｒ１及びＴｒ２はｐチャネル型トランジスタであるのが望ましい。
【０５１０】
トランジスタＴｒ３、Ｔｒ４、Ｔｒ５、Ｔｒ６は、ｎチャネル型トランジスタとｐチャネル型トランジスタのどちらでも良い。
【０５１１】
図３２に示した画素を有する発光装置の動作は、図３に示した画素の場合と同様に、書き込み期間Ｔａと表示期間Ｔｄとに分けて説明することが可能である。また、第１〜３走査線に印加される電圧については、図４に示したタイミングチャートを参照することができる。また図３３は、図３２に示した画素の、書き込み期間Ｔａと表示期間ＴｄにおけるトランジスタＴｒ１とトランジスタＴｒ２の接続を、簡単に示した図である。
【０５１２】
書き込み期間Ｔａが開始されると、第１走査線Ｇ、第２走査線Ｐが選択される。よって、トランジスタＴｒ３とトランジスタＴｒ４がオンになる。なお、第３走査線Ｒは選択されていないので、トランジスタＴｒ５はオフになっている。
【０５１３】
そして、信号線駆動回路１０２に入力されるビデオ信号に基づき、信号線Ｓ１〜Ｓｘと電源線Ｖ１〜Ｖｘの間に、それぞれビデオ信号に応じた信号電流Ｉｃが流れる。
【０５１４】
図３３（Ａ）に、書き込み期間Ｔａにおいて、信号線Ｓｉにビデオ信号に応じた信号電流Ｉｃが流れた場合の、画素１０１の概略図を示す。７６６は対向電極に電圧を与える電源との接続用の端子を意味している。また、７６５は信号線駆動回路１０２が有する定電流源を意味する。
【０５１５】
トランジスタＴｒ３はオンの状態にあるので、信号線Ｓｉにビデオ信号に応じた信号電流Ｉｃが流れると、信号電流ＩｃはトランジスタＴｒ１のドレインとソースの間に流れる。このときトランジスタＴｒ１は、ゲートとドレインが接続されているので飽和領域で動作しており、式１が成り立つ。よって、トランジスタＴｒ１のゲート電圧Ｖ_GSは電流値Ｉｃによって定まる。
【０５１６】
そしてトランジスタＴｒ２のゲートは、トランジスタＴｒ１のゲートに接続されている。また、トランジスタＴｒ２のソースは、トランジスタＴｒ１のソースに接続されている。したがって、トランジスタＴｒ１のゲート電圧は、そのままトランジスタＴｒ２のゲート電圧となる。よって、トランジスタＴｒ２のドレイン電流は、トランジスタＴｒ１のドレイン電流に比例する。特に、μＣ₀Ｗ／Ｌ及びＶ_THが互いに等しいとき、トランジスタＴｒ１とトランジスタＴｒ２のドレイン電流は互いに等しくなり、Ｉ₂＝Ｉｃとなる。
【０５１７】
そして、トランジスタＴｒ２のドレイン電流Ｉ₂は発光素子７６０に流れる。発光素子に流れる電流は、定電流源７６５において定められた信号電流Ｉｃに応じた大きさであり、流れる電流の大きさに見合った輝度で発光素子７６０は発光する。発光素子に流れる電流が０に限りなく近かったり、発光素子に流れる電流が逆バイアスの方向に流れたりする場合は、発光素子７６０は発光しない。
【０５１８】
書き込み期間Ｔａが終了すると、第１走査線Ｇ、第２走査線Ｐの選択が終了する。このとき、第２走査線Ｐの選択が、第１走査線Ｇよりも先に終了するのが望ましい。なぜならトランジスタＴｒ３が先にオフになってしまうと、保持容量７６１の電荷がＴｒ４を通って漏れてしまうからである。
【０５１９】
書き込み期間Ｔａが終了すると、次に表示期間Ｔｄが開始される。表示期間Ｔｄが開始されると、第３走査線Ｒが選択されトランジスタＴｒ５がオンになる。なお、第１走査線Ｇ及び第２走査線Ｐは選択されていないので、トランジスタＴｒ３及びＴｒ４はオフになっている。
【０５２０】
図３３（Ｂ）に、表示期間Ｔｄにおける画素の概略図を示す。トランジスタＴｒ３及びトランジスタＴｒ４はオフの状態にある。また、トランジスタＴｒ１及びトランジスタＴｒ２のソースは発光素子７６０の画素電極に接続されている。
【０５２１】
一方トランジスタＴｒ１、Ｔｒ２においては、書き込み期間Ｔａにおいて定められたＶ_GSがそのまま保持されている。さらに、トランジスタＴｒ６のゲートはトランジスタＴｒ１及びＴｒ２のゲートと接続されている。そのため、トランジスタＴｒ１のドレイン電流とトランジスタＴｒ６のドレイン電流は同じ大きさに保たれる。そして、式１より、トランジスタＴｒ１のドレイン電流は、トランジスタＴｒ６のチャネル長及びチャネル幅に左右される。
【０５２２】
上述したように、トランジスタＴｒ１とＴｒ６のゲート電圧、移動度、単位面積あたりのゲート容量、閾値、チャネル幅が等しいと仮定すると、式１より式２が導き出される。
【０５２３】
一方、トランジスタＴｒ２のドレイン電流Ｉ₂の値は、信号電流Ｉｃに応じた大きさに維持されたままである。
【０５２４】
そして、トランジスタＴｒ５がオンなので、トランジスタＴｒ１及びＴｒ６のドレイン電流Ｉ₃と、トランジスタＴｒ２のドレイン電流Ｉ₂は、共に発光素子７６０に流れる。よって、ドレイン電流Ｉ₃と、ドレイン電流Ｉ₂を合わせた電流の大きさに見合った輝度で、発光素子７６０は発光する。
【０５２５】
そして１ライン目の画素において表示期間Ｔｄが開始されると、次に２ライン目の画素において表示期間Ｔｄが開始される。そして１ライン目の画素と同様に、第３走査線Ｒ２が選択され、トランジスタＴｒ５、Ｔｒ６がオンになる。なお、第１走査線Ｇ２及び第２走査線Ｐ２は選択されていないので、トランジスタＴｒ３及びＴｒ４はオフになっている。よって、ドレイン電流Ｉ₂と、ドレイン電流Ｉ₃を合わせた電流の大きさに見合った輝度で、発光素子７６０は発光する。
【０５２６】
そして、２ライン目の画素において表示期間Ｔｄが開始されると、３ライン目からｙライン目の画素まで順に表示期間Ｔｄが開始され、上述した動作が繰り返される。
【０５２７】
書き込み期間Ｔａと、表示期間Ｔｄが終了すると１フレーム期間が終了する。１つのフレーム期間において１つの画像が表示される。そして、次のフレーム期間が開始され、再び書き込み期間Ｔａが開始されて、上述した動作が繰り返される。
【０５２８】
なお、発光素子に流れる電流の大きさに見合った輝度で発光素子７６０が発光するので、各画素の階調は、表示期間Ｔｄにおける発光素子に流れる電流の大きさで決まる。
【０５２９】
本発明の画素では、表示期間において発光素子に流れる電流はドレイン電流Ｉ₁と、ドレイン電流Ｉ₂の和である。よって、発光素子に流れる電流がドレイン電流Ｉ₂のみに依存していない。そのため、トランジスタＴｒ１とトランジスタＴｒ２の特性がずれて、トランジスタＴｒ２のドレイン電流Ｉ₂と信号電流Ｉｃの比が画素間で異なっても、発光素子に流れる電流の値が画素間でずれるのを抑え、輝度のばらつきが視認されるのを防ぐことができる。
【０５３０】
また、本発明の画素では、書き込み期間ＴａにおいてトランジスタＴｒ１のドレイン電流は発光素子に流れていない。よって信号線駆動回路によって画素に電流が供給され、トランジスタＴｒ１のドレイン電流が流れることでゲート電圧が変化しはじめてから、その値が安定するまでの時間は、発光素子の容量に左右されない。したがって、従来の画素と比べて、供給された電流から変換される電圧が早く安定するので、電流を書き込む時間を短くすることができ、動画表示において残像が視認されてしまうのを防ぐことができる。
【０５３１】
また、従来と同様に、電流入力型の発光装置の利点も兼ね備えている。すなわち、ＴＦＴの特性が画素毎にばらついていても、電圧入力型の発光装置に比べて画素間で発光素子の輝度にばらつきが生じるのを防ぐことができる。また、図２５に示した電圧入力型の画素のＴＦＴ５１を線形領域で動作させたときに比べて、発光素子の劣化による輝度の低下を抑えることができる。また、有機発光層の温度が外気温や発光パネル自身が発する熱等に左右されても、発光素子の輝度が変化するのを抑えることができ、また温度の上昇に伴って消費電流が大きくなるのを防ぐことができる。
【０５３２】
さらに、本実施例の画素では、図２、図５、図７、図９、図１０及び図１１に示した画素に比べて、書き込み期間におけるトランジスタＴｒ１のドレイン電流よりも、表示期間におけるＴｒ１のドレイン電流が小さいため、信号電流Ｉｃに対する発光素子に流れる電流の比が小さくなる。よって、信号電流Ｉｃをより大きくすることができるので、雑音の影響を受けにくい。
【０５３３】
なお、本実施例において、トランジスタＴｒ４のソースとドレインは、一方はトランジスタＴｒ１のドレインに、もう一方はトランジスタＴｒ１のゲート及びトランジスタＴｒ２のゲートに接続されている。しかし本実例はこの構成に限定されない。本発明の画素は、書き込み期間ＴａにおいてトランジスタＴｒ１のゲートとドレインを接続し、表示期間においてトランジスタＴｒ１のゲートとドレインを切り離すことができるように、トランジスタＴｒ４が他の素子または配線と接続されていれば良い。
【０５３４】
また本実施例において、トランジスタＴｒ５のソースとドレインは、一方はＴｒ２のドレインに、もう一方はＴｒ６のソースまたはドレインに接続されている。しかし本実施例はこの構成に限定されない。本発明の画素は、書き込み期間ＴａにおいてトランジスタＴｒ２のドレインと画素電極とを切り離し、表示期間においてトランジスタＴｒ２のドレインと電源線Ｖｉとを接続することができるように、トランジスタＴｒ５が他の素子または配線と接続されていれば良い。
【０５３５】
つまり、Ｔｒ３、Ｔｒ４、Ｔｒ５、Ｔｒ６は、Ｔａでは図３１（Ａ）のように接続され、Ｔｄでは図３１（Ｂ）のように接続されていれば良い。また、Ｇｊ、Ｐｊ、Ｒｊは３本が別の配線となっているが、まとめて１本や２本にしても良い。
【０５３６】
つまり、ＴａにおいてＴｒ１を流れる電流は全て電流源で制御されていれば良い。ＴｄにおいてはＴｒ１とＴｒ２を流れる電流は発光素子に流れれば良い。
【０５３７】
なお、本実施例の構成は、実施例４〜実施例１２のいずれの構成とも自由に組み合わせて実施することが可能である。
【０５３８】
（実施例１４）
本実施例では、図２に示した発光装置が有する画素１０１の構成について説明する。
【０５３９】
図３４に、図２で示した画素１０１の詳しい構成を示す。図３４に示す画素１０１は、信号線Ｓｉ（Ｓ１〜Ｓｘのうちの１つ）、第１走査線Ｇｊ（Ｇ１〜Ｇｙのうちの１つ）、第２走査線Ｐｊ（Ｐ１〜Ｐｙのうちの１つ）、第３走査線Ｒｊ（Ｒ１〜Ｒｙのうちの１つ）及び電源線Ｖｉ（Ｖ１〜Ｖｘのうちの１つ）を有している。
【０５４０】
また画素１０１は、トランジスタＴｒ１、トランジスタＴｒ２、トランジスタＴｒ３、トランジスタＴｒ４、トランジスタＴｒ５、発光素子７８０及び保持容量７８１を有している。保持容量７８１はトランジスタＴｒ１及びＴｒ２のゲートとソースの間の電圧（ゲート電圧）をより確実に保持するために設けられているが、必ずしも設ける必要はない。
【０５４１】
トランジスタＴｒ３のゲートは第１走査線Ｇｊに接続されている。そしてトランジスタＴｒ３のソースとドレインは、一方は信号線Ｓｉに接続されており、もう一方はトランジスタＴｒ１のソースに接続されている。
【０５４２】
トランジスタＴｒ４のゲートは、第２走査線Ｐｊに接続されている。そしてトランジスタＴｒ４のソースとドレインは、一方はトランジスタＴｒ１のドレインに、もう一方はトランジスタＴｒ１及びＴｒ２のゲートに接続されている。
【０５４３】
トランジスタＴｒ５のゲートは、第３走査線Ｒｊに接続されている。そしてトランジスタＴｒ５のソースとドレインは、一方はトランジスタＴｒ２のソース及び発光素子７８０の画素電極に、もう一方はトランジスタＴｒ１のソースに接続されている。
【０５４４】
トランジスタＴｒ１とトランジスタＴｒ２のゲートは、互いに接続されている。トランジスタＴｒ２のソースは、発光素子７８０の画素電極に接続されている。トランジスタＴｒ１とトランジスタＴｒ２のドレインは、共に電源線Ｖｉに接続されている。
【０５４５】
保持容量７８１が有する２つの電極は、一方はトランジスタＴｒ１とトランジスタＴｒ２のゲートに、もう一方はＴｒ１のソースの画素電極に接続されている。
【０５４６】
電源線Ｖｉの電圧（電源電圧）は一定の高さに保たれている。また対向電極の電圧も、一定の高さに保たれている。
【０５４７】
なお、トランジスタＴｒ１及びＴｒ２はｎチャネル型トランジスタとｐチャネル型トランジスタのどちらでも良い。ただし、トランジスタＴｒ１及びＴｒ２の極性は同じである。なお、陽極を画素電極として用い、陰極を対向電極として用いる場合、トランジスタＴｒ１及びＴｒ２はｎチャネル型トランジスタであるのが望ましい。逆に、陽極を対向電極として用い、陰極を画素電極として用いる場合、トランジスタＴｒ１及びＴｒ２はｐチャネル型トランジスタであるのが望ましい。
【０５４８】
トランジスタＴｒ３、Ｔｒ４、Ｔｒ５は、ｎチャネル型トランジスタとｐチャネル型トランジスタのどちらでも良い。
【０５４９】
図３４に示した画素を有する発光装置の動作は、図３に示した画素の場合と同様に、書き込み期間Ｔａと表示期間Ｔｄとに分けて説明することが可能である。また、第１〜３走査線に印加される電圧については、図４に示したタイミングチャートを参照することができる。また図３５は、図３４に示した画素の、書き込み期間Ｔａと表示期間ＴｄにおけるトランジスタＴｒ１とトランジスタＴｒ２の接続を、簡単に示した図である。
【０５５０】
書き込み期間Ｔａが開始されると、第１走査線Ｇ、第２走査線Ｐが選択される。よって、トランジスタＴｒ３とトランジスタＴｒ４がオンになる。なお、第３走査線Ｒは選択されていないので、トランジスタＴｒ５はオフになっている。
【０５５１】
そして、信号線駆動回路１０２に入力されるビデオ信号に基づき、信号線Ｓ１〜Ｓｘと電源線Ｖ１〜Ｖｘの間に、それぞれビデオ信号に応じた信号電流Ｉｃが流れる。
【０５５２】
図３５（Ａ）に、書き込み期間Ｔａにおいて、信号線Ｓｉにビデオ信号に応じた信号電流Ｉｃが流れた場合の、画素１０１の概略図を示す。７８６は対向電極に電圧を与える電源との接続用の端子を意味している。また、７８７は信号線駆動回路１０２が有する定電流源を意味する。
【０５５３】
トランジスタＴｒ３はオンの状態にあるので、信号線Ｓｉにビデオ信号に応じた信号電流Ｉｃが流れると、信号電流ＩｃはトランジスタＴｒ１のドレインとソースの間に流れる。このときトランジスタＴｒ１は、ゲートとドレインが接続されているので飽和領域で動作しており、式１が成り立つ。よって、トランジスタＴｒ１のゲート電圧Ｖ_GSは電流値Ｉｃによって定まる。
【０５５４】
そしてトランジスタＴｒ２のゲートは、トランジスタＴｒ１のゲートに接続されている。
【０５５５】
書き込み期間Ｔａが終了すると、第１走査線Ｇ、第２走査線Ｐの選択が終了する。このとき、第２走査線Ｐの選択が、第１走査線Ｇよりも先に終了するのが望ましい。なぜならトランジスタＴｒ３が先にオフになってしまうと、保持容量７８１の電荷がＴｒ４を通って漏れてしまうからである。
【０５５６】
書き込み期間Ｔａが終了すると、次に表示期間Ｔｄが開始される。表示期間Ｔｄが開始されると、第３走査線Ｒが選択されトランジスタＴｒ５がオンになる。なお、第１走査線Ｇ及び第２走査線Ｐは選択されていないので、トランジスタＴｒ３及びＴｒ４はオフになっている。
【０５５７】
図３５（Ｂ）に、表示期間Ｔｄにおける画素の概略図を示す。トランジスタＴｒ３及びトランジスタＴｒ４はオフの状態にある。また、トランジスタＴｒ１及びトランジスタＴｒ２のソースは発光素子７８０の画素電極に接続されている。
【０５５８】
一方トランジスタＴｒ１、Ｔｒ２においては、書き込み期間Ｔａにおいて定められたＶ_GSがそのまま保持されている。そして、トランジスタＴｒ２のゲートは、トランジスタＴｒ１のゲートに接続されている。また、トランジスタＴｒ２のソースは、トランジスタＴｒ１のソースに接続されている。よって、トランジスタＴｒ１のゲート電圧は、そのままトランジスタＴｒ２のゲート電圧となる。さらに、トランジスタＴｒ１のドレイン及びトランジスタＴｒ２のドレインは電源線Ｖｉに接続されているので、トランジスタＴｒ２のドレイン電流Ｉ₂は、トランジスタＴｒ１のドレイン電流Ｉ₁に比例する大きさになる。特に、μＣ₀Ｗ／Ｌ及びＶ_THが互いに等しいとき、トランジスタＴｒ１とトランジスタＴｒ２のドレイン電流は互いに等しくなり、Ｉ₂＝Ｉ₁＝Ｉｃとなる。
【０５５９】
また、トランジスタＴｒ５がオンなので、トランジスタＴｒ１のドレイン電流Ｉ₁と、トランジスタＴｒ２のドレイン電流Ｉ₂は、共に発光素子に流れる電流として発光素子７８０に流れる。よって、表示期間Ｔｄでは、ドレイン電流Ｉ₁と、ドレイン電流Ｉ₂を合わせた大きさの電流が発光素子７８０に流れ、該発光素子に流れる電流の大きさに見合った輝度で、発光素子７８０が発光する。
【０５６０】
そして１ライン目の画素において表示期間Ｔｄが開始されると、次に２ライン目の画素において表示期間Ｔｄが開始される。そして１ライン目の画素と同様に、第３走査線Ｒ２が選択され、トランジスタＴｒ５がオンになる。なお、第１走査線Ｇ２及び第２走査線Ｐ２は選択されていないので、トランジスタＴｒ３及びＴｒ４はオフになっている。よって、ドレイン電流Ｉ₁と、ドレイン電流Ｉ₂を合わせた電流の大きさに見合った輝度で、発光素子７８０は発光する。
【０５６１】
そして、２ライン目の画素において表示期間Ｔｄが開始されると、３ライン目からｙライン目の画素まで順に表示期間Ｔｄが開始され、上述した動作が繰り返される。
【０５６２】
書き込み期間Ｔａと、表示期間Ｔｄが終了すると１フレーム期間が終了する。１つのフレーム期間において１つの画像が表示される。そして、次のフレーム期間が開始され、再び書き込み期間Ｔａが開始されて、上述した動作が繰り返される。
【０５６３】
なお、発光素子に流れる電流の大きさに見合った輝度で発光素子７８０が発光するので、各画素の階調は、表示期間Ｔｄにおける発光素子に流れる電流の大きさで決まる。なお、書き込み期間Ｔａにおいても、Ｔｒ２のドレイン電流の大きさに見合った輝度で発光しているが、その階調に与える影響は、実際のパネルでは無視できる程度に小さいと考えられる。なぜなら、例えばＶＧＡだと４８０ラインの画素が画素部に設けられており、１ラインの画素の書き込み期間Ｔａは１フレーム期間の１／４８０程度と非常に小さいからである。
【０５６４】
本発明の画素では、表示期間において発光素子に流れる電流はドレイン電流Ｉ₁と、ドレイン電流Ｉ₂の和である。よって、発光素子に流れる電流がドレイン電流Ｉ₂のみに依存していない。そのため、トランジスタＴｒ１とトランジスタＴｒ２の特性がずれて、トランジスタＴｒ２のドレイン電流Ｉ₂と信号電流Ｉｃの比が画素間で異なっても、発光素子に流れる電流の値が画素間でずれるのを抑え、輝度のばらつきが視認されるのを防ぐことができる。
【０５６５】
また、本発明の画素では、書き込み期間ＴａにおいてトランジスタＴｒ１のドレイン電流は発光素子に流れていない。よって信号線駆動回路によって画素に電流が供給され、トランジスタＴｒ１のドレイン電流が流れることでゲート電圧が変化しはじめてから、その値が安定するまでの時間は、発光素子の容量に左右されない。したがって、従来の画素と比べて、供給された電流から変換される電圧が早く安定するので、電流を書き込む時間を短くすることができ、動画表示において残像が視認されてしまうのを防ぐことができる。
【０５６６】
また、従来と同様に、電流入力型の発光装置の利点も兼ね備えている。すなわち、ＴＦＴの特性が画素毎にばらついていても、電圧入力型の発光装置に比べて画素間で発光素子の輝度にばらつきが生じるのを防ぐことができる。また、図２５に示した電圧入力型の画素のＴＦＴ５１を線形領域で動作させたときに比べて、発光素子の劣化による輝度の低下を抑えることができる。また、有機発光層の温度が外気温や発光パネル自身が発する熱等に左右されても、発光素子の輝度が変化するのを抑えることができ、また温度の上昇に伴って消費電流が大きくなるのを防ぐことができる。
【０５６７】
なお、本実施例において、トランジスタＴｒ４のソースとドレインは、一方はトランジスタＴｒ１のドレインに、もう一方はトランジスタＴｒ１のゲート及びトランジスタＴｒ２のゲートに接続されている。しかし本実例はこの構成に限定されない。本発明の画素は、書き込み期間ＴａにおいてトランジスタＴｒ１のゲートとドレインを接続し、表示期間においてトランジスタＴｒ１のゲートとドレインを切り離すことができるように、トランジスタＴｒ４が他の素子または配線と接続されていれば良い。
【０５６８】
また本実施例において、トランジスタＴｒ５のソースとドレインは、一方はＴｒ２のソースに、もう一方はＴｒ１のソースに接続されている。しかし本実例はこの構成に限定されない。本発明の画素は、書き込み期間ＴａにおいてトランジスタＴｒ１のソースと画素電極とを切り離し、表示期間においてトランジスタＴｒ１のソースと画素電極とを接続することができるように、トランジスタＴｒ５が他の素子または配線と接続されていれば良い。
【０５６９】
つまり、Ｔｒ３、Ｔｒ４、Ｔｒ５は、Ｔａでは図３５（Ａ）のように接続され、Ｔｄでは図３５（Ｂ）のように接続されていれば良い。また、Ｇｊ、Ｐｊ、Ｒｊは３本が別の配線となっているが、まとめて１本や２本にしても良い。
【０５７０】
つまり、ＴａにおいてＴｒ１を流れる電流は全て電流源で制御されていれば良い。ＴｄにおいてはＴｒ１とＴｒ２を流れる電流は発光素子に流れれば良い。
【０５７１】
また、発光素子の画素電極をＴｒ２のソースに接続するのではなく、Ｔｒ１のソースに接続するようにしても良い。ただしこの場合、Ｔｒ１のソースと画素電極とが書き込み期間において切り離され、表示期間において接続されるように、接続を制御する別途トランジスタを用意する必要がある。なおこのＴｒ１のソースと画素電極の接続を制御するトランジスタを、Ｔｒ５と異なる極性とし、互いのゲートを接続するようにしても良い。
【０５７２】
なお、本実施例の構成は、実施例４〜実施例１３のいずれの構成とも自由に組み合わせて実施することが可能である。
【０５７３】
【発明の効果】
本発明の第１の構成の画素では、表示期間において発光素子に流れる電流はドレイン電流Ｉ₁と、ドレイン電流Ｉ₂の和である。よって、発光素子に流れる電流がドレイン電流Ｉ₂のみに依存していない。そのため、トランジスタＴｒ１とトランジスタＴｒ２の特性がずれて、トランジスタＴｒ１のドレイン電流Ｉ₁に対するトランジスタＴｒ２のドレイン電流Ｉ₂の比が画素間で異なっても、発光素子に流れる電流の値が画素間でずれるのを抑え、輝度のばらつきが視認されるのを防ぐことができる。
【０５７４】
本発明の第２の構成の画素では、図２７（Ａ）に示した画素のように、第１の手段と第２の手段のいずれか一方の手段の特性がずれることにより、２つの手段における特性のバランスが崩れ、駆動部から発光素子に供給される電流Ｉ₂の大きさが所望の値に保たれなくなることがある。しかし、２つの変換部Ａ、Ｂを共に用いることで変換された電圧を平均化することができ、そして駆動部から発光素子に供給される電流Ｉ₂は該平均化された電圧に応じた大きさであるので、特性のずれに起因する発光素子に供給される電流量のばらつきを、図２７（Ａ）に示した画素に比べ約半分程度に抑えることができる。よって、画素間の輝度のばらつきを抑えることができる。また、画素に供給された電流は、電流Ｉ₂よりも大きい。そのため、電流を書き込む時間を短くすることができる。
【０５７５】
また、本発明の画素では、書き込み期間ＴａにおいてトランジスタＴｒ１のドレイン電流は発光素子に流れていない。よって信号線駆動回路によって画素に電流が供給され、トランジスタＴｒ１のドレイン電流が流れることでゲート電圧が変化しはじめてから、その値が安定するまでの時間は、発光素子の容量に左右されない。したがって、従来の画素と比べて、供給された電流から変換される電圧が早く安定するので、電流を書き込む時間を短くすることができ、動画表示において残像が視認されてしまうのを防ぐことができる。
【０５７６】
また、従来と同様に、電流入力型の発光装置の利点も兼ね備えている。すなわち、ＴＦＴの特性が画素毎にばらついていても、電圧入力型の発光装置に比べて画素間で発光素子の輝度にばらつきが生じるのを防ぐことができる。また、図２５に示した電圧入力型の画素のＴＦＴ５１を線形領域で動作させたときに比べて、発光素子の劣化による輝度の低下を抑えることができる。また、有機発光層の温度が外気温や発光パネル自身が発する熱等に左右されても、発光素子の輝度が変化するのを抑えることができ、また温度の上昇に伴って消費電流が大きくなるのを防ぐことができる。
【図面の簡単な説明】
【図１】 本願の電流入力型の画素のブロック図。
【図２】 本発明の発光装置の上面ブロック図。
【図３】 本発明の発光装置の画素の回路図。
【図４】 走査線に入力される信号のタイミングチャート。
【図５】 駆動における画素の概略図。
【図６】 本発明の発光装置の画素の回路図。
【図７】 駆動における画素の概略図。
【図８】 本発明の発光装置の画素の回路図。
【図９】 駆動における画素の概略図。
【図１０】 本発明の発光装置の画素の回路図。
【図１１】 本発明の発光装置の画素の回路図。
【図１２】 本発明の発光装置の画素の回路図。
【図１３】 本発明の発光装置の作製方法を示す図。
【図１４】 本発明の発光装置の作製方法を示す図。
【図１５】 本発明の発光装置の作製方法を示す図。
【図１６】 本発明の発光装置の作製方法を示す図。
【図１７】 本発明の発光装置の画素の上面図。
【図１８】 アナログ駆動法における信号線駆動回路の詳細図。
【図１９】 走査線駆動回路のブロック図。
【図２０】 デジタル駆動法における信号線駆動回路のブロック図。
【図２１】 デジタル駆動法における信号線駆動回路の詳細図。
【図２２】 デジタル駆動法における電流設定回路の回路図。
【図２３】 本発明の発光装置の外観図及び断面図。
【図２４】 本発明の発光装置を用いた電子機器の図。
【図２５】 電圧入力型の画素の回路図。
【図２６】 従来の電流入力型の画素の回路図。
【図２７】 従来の電流入力型の画素のブロック図。
【図２８】 本発明の発光装置の画素の回路図。
【図２９】 駆動における画素の概略図。
【図３０】 本発明の発光装置の画素の回路図。
【図３１】 駆動における画素の概略図。
【図３２】 本発明の発光装置の画素の回路図。
【図３３】 駆動における画素の概略図。
【図３４】 本発明の発光装置の画素の回路図。
【図３５】 駆動における画素の概略図。
【図３６】 本願の電流入力型の画素のブロック図。
【図３７】 駆動における画素の概略図。
【図３８】 駆動における画素の概略図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a light emitting panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material. The present invention also relates to a light emitting module in which an IC including a controller is mounted on the light emitting panel. Note that in this specification, the light-emitting panel and the light-emitting module are collectively referred to as a light-emitting device. The present invention also relates to a driving method of the light emitting device and an electronic apparatus using the light emitting device. Furthermore, the present invention relates to an element substrate corresponding to one mode before the light emitting element is completed in the process of manufacturing the light emitting device, and the element substrate includes a unit for supplying current to the light emitting element. Prepare for.
[0002]
[Prior art]
Since the light emitting element emits light by itself, the visibility is high, a backlight necessary for a liquid crystal display (LCD) is not necessary, and it is optimal for thinning, and the viewing angle is not limited. Therefore, in recent years, light emitting devices using light emitting elements have attracted attention as display devices that replace CRTs and LCDs.
[0003]
Note that in this specification, a light-emitting element means an element whose luminance is controlled by current or voltage, and an MIM type electron used in an OLED (Organic Light Emitting Diode) or an FED (Field Emission Display). Source elements (electron emitting elements) and the like are included.
[0004]
The OLED has a layer (hereinafter, referred to as an organic light emitting layer) containing an organic compound (organic light emitting material) capable of obtaining luminescence generated by applying an electric field, an anode layer, and a cathode layer. . Luminescence in organic compounds includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Any one of the above-described light emission may be used, or both light emission may be used.
[0005]
In this specification, all layers provided between the anode and the cathode of the OLED are defined as organic light emitting layers. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, the OLED has a structure in which an anode / light emitting layer / cathode is laminated in this order. In addition to this structure, the anode / hole injection layer / light emitting layer / cathode and the anode / hole injection layer / The light emitting layer / electron transport layer / cathode may be stacked in this order. In some cases, these layers contain an inorganic compound.
[0006]
[Problems to be solved by the invention]
FIG. 25 illustrates a pixel configuration of a general light-emitting device. The pixel shown in FIG. 25 includes TFTs 50 and 51, a storage capacitor 52, and a light emitting element 53.
[0007]
The TFT 50 has a gate connected to the scanning line 55, one of the source and drain connected to the signal line 54, and the other connected to the gate of the TFT 51. The TFT 51 has a source connected to the power source 56 and a drain connected to the anode of the light emitting element 53. The cathode of the light emitting element 53 is connected to the power source 57. The storage capacitor 52 is provided to hold the voltage between the gate and source of the TFT 51.
[0008]
When the TFT 50 is turned on by the voltage of the scanning line 55, the video signal input to the signal line 54 is input to the gate of the TFT 51. When a video signal is input, the gate voltage (voltage difference between the gate and the source) of the TFT 51 is determined according to the voltage of the input video signal. Then, the drain current of the TFT 51 flowing by the gate voltage is supplied to the light emitting element 53, and the light emitting element 53 emits light by the supplied current.
[0009]
By the way, a TFT formed of polysilicon has a higher field effect mobility and a higher on-current than a TFT formed of amorphous silicon, and thus is more suitable as a transistor of a light-emitting element panel.
[0010]
However, even if a TFT is formed using polysilicon, the electrical characteristics are not comparable to the characteristics of a MOS transistor formed on a single crystal silicon substrate. For example, the field effect mobility is 1/10 or less of single crystal silicon. In addition, TFTs using polysilicon have a problem that their characteristics are likely to vary due to defects formed at crystal grain boundaries.
[0011]
In the pixel shown in FIG. 25, if the characteristics of the TFT 51, such as the threshold value and the on-current, vary from pixel to pixel, the magnitude of the drain current of the TFT 51 varies from pixel to pixel even when the video signal voltage is the same. Variations in the brightness of the image.
[0012]
In order to avoid the above-described problems, various types of current input pixel configurations have been devised that can control the magnitude of the current flowing through the light emitting element without being influenced by the characteristics of the TFT. In the following, two typical current input type pixels will be exemplified and their configurations will be described.
[0013]
First, a structure of a current input pixel described in Japanese Patent Application Laid-Open No. 2001-147659 will be described with reference to FIG.
[0014]
The pixel illustrated in FIG. 26A includes TFTs 11, 12, 13, and 14, a storage capacitor 15, and a light emitting element 16.
[0015]
The TFT 11 has a gate connected to the terminal 18, one of the source and the drain connected to the current source 17, and the other connected to the drain of the TFT 13. The TFT 12 has a gate connected to the terminal 19, one of the source and the drain connected to the drain of the TFT 13, and the other connected to the gate of the TFT 13. The gates of the TFT 13 and TFT 14 are connected to each other, and the sources are both connected to the terminal 20. The drain of the TFT 14 is connected to the anode of the light emitting element 16, and the cathode of the light emitting element 16 is connected to the terminal 21. The holding capacitor 15 is provided so as to hold the voltage between the gate and the source of the TFTs 13 and 14. A predetermined voltage is applied to each of the terminals 20 and 21 from the power supply, and there is a voltage difference between them.
[0016]
After the TFTs 11 and 12 are turned on by the voltage applied to the terminals 18 and 19, the drain current of the TFT 13 is controlled by the current source 17. Here, the TFT 13 operates in the saturation region because the gate and the drain are connected, and the drain current is expressed by the following Equation 1. V _GS Is the gate voltage, μ is the mobility, C ₀ Is the gate capacitance per unit area, W / L is the ratio of the channel width W to the channel length L of the channel formation region, V _TH Is a threshold and drain current is I.
[0017]
[Formula 1]
I = μC ₀ W / L (V _GS -V _TH ) ² / 2
[0018]
In equation 1, μ, C ₀ , W / L, V _TH Are all fixed values determined by individual transistors. From Equation 1, the drain current of the TFT 13 is the gate voltage V _GS It turns out that it changes by. Therefore, according to Equation 1, the gate voltage V has a value commensurate with the drain current. _GS Is generated in the TFT 13.
[0019]
At this time, since the gate and the source of the TFT 13 and the TFT 14 are connected to each other, the gate voltage of the TFT 14 is maintained at the same level as the gate voltage of the TFT 13.
[0020]
Therefore, the drain currents of the TFT 13 and the TFT 14 are in a proportional relationship. In particular, μ, C ₀ , W / L, V _TH If the values of are the same, the drain currents of the TFT 13 and the TFT 14 are the same. The drain current flowing through the TFT 14 is supplied to the light emitting element 16, and the light emitting element 16 emits light with a luminance corresponding to the magnitude of the drain current.
[0021]
Even after the TFTs 11 and 12 are turned off by the voltage applied to the terminals 18 and 19, the light emitting element 16 continues to emit light as long as the gate voltage of the TFT 14 is held by the holding capacitor 15.
[0022]
As described above, the pixel illustrated in FIG. 26A includes a unit that converts the current supplied to the pixel into a voltage and holds it, and a unit that flows a current having a magnitude corresponding to the held voltage to the light-emitting element. And have. FIG. 27A is a block diagram illustrating a relationship between a unit included in the pixel illustrated in FIG. 26A and the light-emitting element. The pixel 80 includes a conversion unit 81 that is a unit that converts the current supplied to the pixel into a voltage and holds the voltage, and a drive unit 82 that is a unit that flows a current having a magnitude corresponding to the held voltage to the light emitting element. And a light emitting element 83. The current supplied to the pixel 80 is converted into a voltage by the conversion unit 81, and the voltage is supplied to the drive unit 82. The driving unit 82 supplies a current having a magnitude corresponding to the applied voltage to the light emitting element 83.
[0023]
Specifically, in FIG. 26A, the TFT 12, the TFT 13, and the storage capacitor 15 correspond to means for converting the supplied current into a voltage and holding it. Further, it corresponds to means for flowing a current having a magnitude corresponding to the voltage held by the TFT 14 to the light emitting element.
[0024]
Next, a configuration of a current input type pixel described in Tech. Digest IEDM 98, 875. RMA Dawson etc. will be described with reference to FIG. A pixel illustrated in FIG. 26B includes TFTs 31, 32, 33, and 34, a storage capacitor 35, and a light emitting element 36.
[0025]
The TFT 31 has a gate connected to the terminal 38, one of the source and the drain connected to the current source 37, and the other connected to the source of the TFT 33. The TFT 34 has a gate connected to the terminal 38, one of the source and the drain connected to the gate of the TFT 33, and the other connected to the drain of the TFT 33. The TFT 32 has a gate connected to the terminal 39, a source and a drain, one connected to the terminal 40, and the other connected to the source of the TFT 33. The drain of the TFT 34 is connected to the anode of the light emitting element 36, and the cathode of the light emitting element 36 is connected to the terminal 41. The holding capacitor 35 is provided so as to hold the voltage between the gate and the source of the TFT 33. A predetermined voltage is applied to each of the terminals 40 and 41 from the power supply, and there is a voltage difference between them.
[0026]
After the TFTs 31 and 34 are turned on by the voltage applied to the terminal 38 and the TFT 32 is turned off by the voltage applied to the terminal 39, the drain current of the TFT 33 is controlled by the current source 37. Here, the TFT 33 operates in the saturation region because the gate and the drain are connected, and the drain current thereof is expressed by the above-described Expression 1. From Equation 1, the drain current of the TFT 33 is the gate voltage V _GS It turns out that it changes by. Therefore, according to Equation 1, the gate voltage V has a value commensurate with the drain current. _GS Occurs in the TFT 33.
[0027]
The drain current flowing through the TFT 33 is supplied to the light emitting element 36, and the light emitting element 36 emits light with a luminance corresponding to the magnitude of the drain current.
[0028]
Then, after the TFTs 31 and 34 are turned off by the voltage applied to the terminal 38, the TFT 32 is turned on by the voltage applied to the terminal 39. At this time, as long as the gate voltage of the TFT 33 is held by the holding capacitor 35, the light emitting element 36 continues to emit light with the same luminance as when the TFTs 31 and 34 are on.
[0029]
As described above, the pixel illustrated in FIG. 26B has a unit that converts the current supplied to the pixel into a voltage, holds the current, and flows a current having a magnitude corresponding to the held voltage to the light-emitting element. is doing. That is, in the case of the pixel shown in FIG. 26B, the function of the two means provided in FIG. 26A is covered by one means. FIG. 27B is a block diagram illustrating the relationship between the means included in the pixel illustrated in FIG. 26B and the light-emitting element. In FIG. 27B, the function of the conversion unit and the function of the drive unit are covered by one means. That is, the current supplied to the pixel 85 is converted into a voltage by the means 86 which is a conversion unit and is also a drive unit, and then a current having a magnitude corresponding to the voltage is supplied to the light emitting element 87.
[0030]
Specifically, in FIG. 26B, the TFT 33, the TFT 34, and the storage capacitor 35 convert the supplied current into a voltage and hold it, and flow a current having a magnitude corresponding to the held voltage to the light emitting element. It corresponds to.
[0031]
The pixels shown in FIGS. 26A and 26B described above control the magnitude of the current flowing to the light emitting element by the current source even if characteristics such as the threshold value of the TFT and the on-current vary from pixel to pixel. It is possible to prevent variation in luminance of the light emitting element between pixels.
[0032]
In general, the light emitting element emits light while keeping the voltage between the electrodes constant, and the case where light is emitted while keeping the current between the electrodes constant, the latter is due to deterioration of the organic light emitting material. A decrease in luminance can be suppressed. Therefore, in the case of the two current input type pixels illustrated in FIGS. 26A and 26B, the current flowing through the light emitting element can be always maintained at a desired value without being affected by the deterioration of the organic light emitting material. Therefore, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in the linear region, a decrease in luminance due to deterioration of the light emitting element can be suppressed.
[0033]
Further, the luminance of the light emitting element and the magnitude of the current flowing through the organic light emitting layer are in a proportional relationship. Even if the temperature of the organic light emitting layer depends on the outside air temperature or the heat generated by the light emitting panel itself, the current input type light emitting device can keep the current flowing through the light emitting element constant, so the luminance of the light emitting element changes. In addition, it is possible to prevent current consumption from increasing as the temperature rises.
[0034]
However, the two pixels described above also have problems.
[0035]
As represented by FIG. 26A, there are two means: a means for converting the current supplied to the pixel into a voltage and holding it, and a means for sending a current having a magnitude corresponding to the held voltage to the light emitting element. In the case of a pixel having means, the characteristic balance between the two means may be lost due to the deviation of the characteristic of one of the means. Then, the magnitude of the current supplied from the driving unit to the light emitting element cannot be maintained at a desired value, and the luminance of the light emitting element varies among pixels.
[0036]
Specifically, in FIG. 26A, in the TFT 13 or TFT 14, μ, C, which are characteristics inherent to the TFT, ₀ , V _TH If the W / L is shifted, the ratio of the drain current of the TFT 14 to the drain current of the TFT 13 differs between pixels, resulting in variations in luminance of the light emitting elements between pixels.
[0037]
On the other hand, as represented by FIG. 26B, there is means for converting the current supplied to the pixel into a voltage and holding it, and flowing a current having a magnitude corresponding to the held voltage to the light emitting element. In the case of a pixel, a current flows through the light emitting element when the current supplied to the pixel is converted into a voltage. The light emitting element has a relatively large capacity. Therefore, for example, in the case where the display changes from a low gradation to a high gradation, the value of the voltage converted from the current is not stable until charge is accumulated in the capacitor of the light emitting element. Therefore, it takes time for the display to change from a low gradation to a high gradation. On the other hand, when the display changes from a high gradation to a low gradation, the value of the voltage converted from the current is not stable until the extra charge of the capacitor of the light emitting element is released. Therefore, it takes time for the display to change from a high gradation to a low gradation.
[0038]
Specifically, in FIG. 26B, when the value of the current supplied from the current source 37 changes, it takes time for the gate voltage of the TFT 33 to stabilize, and the time for writing the current becomes longer. As a result, for example, an afterimage may be visually recognized in moving image display. Therefore, the feature of the light-emitting element that is suitable for moving image display with high-speed response cannot be fully utilized.
[0039]
In view of the above, the present invention provides a current-driven light-emitting device that can further suppress variations in luminance of light-emitting elements between pixels due to a difference in characteristics of TFTs and that hardly causes an afterimage to be visually recognized. Let it be an issue.
[0040]
[Means for Solving the Problems]
A light emitting device having a first configuration according to the present invention includes first means for converting a current supplied to a pixel into a voltage and holding the current, and flowing a current having a magnitude corresponding to the held voltage to the light emitting element. The pixel includes second means for flowing a current having a magnitude corresponding to the voltage held in the first means to the light emitting element.
[0041]
FIG. 1 is a block diagram showing the relationship between the means included in the pixel having the first structure of the present invention and its light emitting element. The pixel 90 of the present invention converts the current supplied to the pixel 90 into a voltage and holds the first current, and flows a current having a magnitude corresponding to the held voltage to the light emitting element 93 included in the pixel 90. Means 91 are provided. That is, the first means 91 is both a conversion unit and a drive unit. Hereinafter, the driving unit included in the first means 91 is referred to as a driving unit A. Further, the pixel 90 includes second means for causing a current to flow through the light emitting element 93 in accordance with the magnitude of the voltage converted and held in the first means. Hereinafter, the driving unit which is the second means 92 is referred to as a driving unit B.
[0042]
That is, in the pixel having the first configuration according to the present invention, the current I from the first means 91 which is both the conversion unit and the driving unit A. ₁ And the current I from the second means 92 which is the driving unit B ₂ Are supplied to the light emitting element 93. The light emitting element 93 has a current I ₁ And current I ₂ The luminance is determined by a current having a combined size.
[0043]
Also in the pixel having the first structure according to the present invention, two means can be obtained by shifting the characteristic of one of the first means and the second means as in the pixel shown in FIG. The current balance supplied to the light emitting element from the drive unit B is lost due to the loss of the balance of the characteristics of ₂ May not be maintained at a desired value. However, the current I supplied to the light emitting element 93 from the second means 91 which is both the conversion unit and the driving unit A is provided. ₁ Is maintained at a desired value without being influenced by a deviation in characteristics. The light emitting element has a current I. ₁ And current I ₂ Thus, the variation in the amount of current supplied to the light-emitting element due to the characteristic deviation can be suppressed to about half that of the pixel shown in FIG. . Therefore, variation in luminance between pixels can be suppressed.
[0044]
A light emitting device having a second configuration according to the present invention has a first means for converting a current supplied to a pixel into a voltage and holding the voltage, a current supplied to the pixel converted into a voltage and holding the voltage, and the The pixel includes second means for flowing a current having a magnitude corresponding to the held voltage to the light emitting element.
[0045]
FIG. 36 is a block diagram showing the relationship between the means included in the pixel having the second structure of the present invention and the light emitting element. The pixel 60 of the present invention has a first means 61 that converts the current supplied to the pixel 60 into a voltage and holds it. Hereinafter, the conversion unit which is the first means 61 is referred to as a conversion unit A. In addition, the pixel 60 includes second means 62 that converts the current supplied to the pixel into a voltage and holds it, and flows a current having a magnitude corresponding to the held voltage to the light emitting element 63. Yes. That is, the second means 62 is both a conversion unit and a drive unit. Hereinafter, the conversion unit included in the second means 62 is referred to as a conversion unit B.
[0046]
That is, in the pixel having the second configuration of the present invention, the current supplied to the pixel is converted into a voltage by both the first means and the second means, and the current I corresponding to the voltage is converted. ₂ Is supplied to the light emitting element 63 from the driving unit of the second means. The light emitting element 63 has a current I ₂ The brightness is determined by.
[0047]
In the pixel having the second structure of the present invention, as in the pixel shown in FIG. 27A, the characteristic of either the first means or the second means is shifted, so that the two means The current I supplied from the drive unit to the light emitting element is lost due to the imbalance of characteristics. ₂ May not be maintained at a desired value. However, by using the two converters A and B together, the converted voltage can be averaged, and the current I supplied from the driver to the light emitting element ₂ Since the magnitude corresponds to the averaged voltage, the variation in the amount of current supplied to the light-emitting element due to the characteristic deviation is suppressed to about half that of the pixel shown in FIG. be able to. Therefore, variation in luminance between pixels can be suppressed. In addition, the current supplied to the pixel is the current I ₂ Bigger than. Therefore, the time for writing current can be shortened.
[0048]
Note that an element substrate corresponding to a mode before a light-emitting element is completed only needs to include the first means and the second means described above in each pixel, and does not need to have a light-emitting element. Specifically, the element substrate may be in a state where only the pixel electrode of the light emitting element is formed, or after the conductive film to be the pixel electrode is formed and before the pixel electrode is formed by patterning. It can be in a state, and all forms apply.
[0049]
In the pixel of the present invention having the first and second configurations, the current supplied to the pixel does not flow to the light emitting element when the first means converts the current supplied to the pixel into a voltage. Therefore, the time until the voltage converted from the supplied current is stabilized does not depend on the capacity of the light emitting element. Therefore, compared to the pixel shown in FIG. 27B, the voltage converted from the supplied current is stabilized quickly, so that the time for writing the current can be shortened, and the afterimage is visually recognized in the moving image display. Can be prevented.
[0050]
Further, as in the prior art, it also has the advantages of a current input type light emitting device. In other words, even when the TFT characteristics vary from pixel to pixel, it is possible to prevent variations in luminance of the light emitting elements between the pixels as compared with the voltage input type light emitting device. Further, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.
[0051]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 2 is a block diagram showing the structure of the light-emitting panel of the present invention. Reference numeral 100 denotes a pixel portion, and a plurality of pixels 101 are formed in a matrix. Reference numeral 102 denotes a signal line driver circuit, and 103 denotes a scanning line driver circuit.
[0052]
In FIG. 2, the signal line driver circuit 102 and the scanning line driver circuit 103 are formed over the same substrate as the pixel portion 100; however, the present invention is not limited to this structure. The signal line driver circuit 102 and the scan line driver circuit 103 may be formed over a different substrate from the pixel unit 100 and connected to the pixel unit 100 via a connector such as an FPC. In FIG. 2, one signal line driver circuit 102 and one scanning line driver circuit 103 are provided, but the present invention is not limited to this structure. The number of the signal line driver circuits 102 and the scanning line driver circuits 103 can be arbitrarily set by a designer.
[0053]
In this specification, connection means an electrical connection unless otherwise specified. On the other hand, disconnecting means not connected.
[0054]
In FIG. 2, although not shown in the pixel portion 100, the signal lines S1 to Sx, the power supply lines V1 to Vx, the first scanning lines G1 to Gy, the second scanning lines P1 to Py, and the third scanning line R1. ~ Ry are provided. Note that the number of signal lines and power supply lines is not necessarily the same. Further, the numbers of the first scanning line, the second scanning line, and the third scanning line are not necessarily the same. Further, it is not always necessary to have all of these wirings, and other different wirings may be provided in addition to these wirings.
[0055]
The power supply lines V1 to Vx are kept at a predetermined voltage. Although FIG. 2 shows the structure of a light emitting device that displays a monochrome image, the present invention may be a light emitting device that displays a color image. In that case, the voltage levels of the power supply lines V1 to Vx need not be kept all the same, and may be changed for each corresponding color.
[0056]
Note that the voltage in this specification means a potential difference from the ground unless otherwise specified.
[0057]
FIG. 3 shows a detailed configuration of the pixel 101 shown in FIG. 3 includes a signal line Si (one of S1 to Sx), a first scanning line Gj (one of G1 to Gy), and a second scanning line Pj (P1 to Py). 1), a third scanning line Rj (one of R1 to Ry) and a power supply line Vi (one of V1 to Vx).
[0058]
The pixel 101 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a transistor Tr5, a light emitting element 104, and a storage capacitor 105. The storage capacitor 105 is provided in order to hold the voltage (gate voltage) between the gate and source of the transistors Tr1 and Tr2 more reliably, but it is not always necessary to provide the storage capacitor 105.
[0059]
The gate of the transistor Tr3 is connected to the first scanning line Gj. One of the source and the drain of the transistor Tr3 is connected to the signal line Si, and the other is connected to the drain of the transistor Tr1.
[0060]
Note that in this specification, the voltage applied to the source of the n-channel transistor is lower than the voltage applied to the drain. The voltage applied to the source of the p-channel transistor is higher than the voltage applied to the drain.
[0061]
The gate of the transistor Tr4 is connected to the second scanning line Pj. One of the source and the drain of the transistor Tr4 is connected to the signal line Si, and the other is connected to the gate of the transistor Tr1 and the gate of the transistor Tr2.
[0062]
The gate of the transistor Tr5 is connected to the third scanning line Rj. One of the source and the drain of the transistor Tr5 is connected to the drain of the transistor Tr1, and the other is connected to the drain of the transistor Tr2.
[0063]
The gates of the transistor Tr1 and the transistor Tr2 are connected to each other. The sources of the transistors Tr1 and Tr2 are both connected to the power supply line Vi. The drain of the transistor Tr2 is connected to the pixel electrode of the light emitting element 104.
[0064]
One of the two electrodes of the storage capacitor 105 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the power supply line Vi.
[0065]
The light-emitting element 104 includes an anode and a cathode. In this specification, when the anode is used as a pixel electrode, the cathode is called a counter electrode, and when the cathode is used as a pixel electrode, the anode is called a counter electrode.
[0066]
The voltage (power supply voltage) of the power supply line Vi is kept at a constant height. The voltage of the counter electrode is also maintained at a constant height.
[0067]
Note that the transistors Tr1 and Tr2 may be either n-channel transistors or p-channel transistors. However, the transistors Tr1 and Tr2 have the same polarity. Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors.
[0068]
The transistors Tr3, Tr4, and Tr5 may be either n-channel transistors or p-channel transistors.
[0069]
Next, the operation of the light-emitting device of this embodiment will be described with reference to FIGS. The operation of the light-emitting device having the first structure according to the present invention can be described by dividing the writing period Ta and the display period Td for each pixel of each line. FIG. 4 shows a timing chart of the first to third scanning lines. A period during which a scan line is selected, in other words, a period in which all transistors whose gates are connected to the scan line is in an ON state. Conversely, a period in which no scan line is selected, in other words, a period in which all transistors whose gates are connected to the scan line is in an OFF state, is indicated by OFF. FIG. 5 is a diagram simply showing the connection between the transistor Tr1 and the transistor Tr2 in the writing period Ta and the display period Td.
[0070]
First, the writing period Ta is started in the pixels on the first line. When the writing period Ta is started, the first scanning line G1 and the second scanning line P1 are selected. Accordingly, the transistor Tr3 and the transistor Tr4 are turned on. Note that since the third scanning line R1 is not selected, the transistor Tr5 is off.
[0071]
Then, based on the video signal input to the signal line driver circuit 102, currents (hereinafter, signal current Ic) corresponding to the video signals flow between the signal lines S1 to Sx and the power supply lines V1 to Vx, respectively. In the present specification, the signal current Ic is referred to as a signal current.
[0072]
FIG. 5A is a schematic diagram of the pixel 101 when a signal current Ic corresponding to a video signal flows through the signal line Si in the writing period Ta. Reference numeral 106 denotes a terminal for connection with a power source for applying a voltage to the counter electrode. Reference numeral 107 denotes a constant current source included in the signal line driver circuit 102.
[0073]
Since the transistor Tr3 is in the on state, when the signal current Ic corresponding to the video signal flows through the signal line Si, the signal current Ic flows between the drain and the source of the transistor Tr1. At this time, the transistor Tr1 operates in the saturation region because the gate and the drain are connected, and Equation 1 is satisfied. Therefore, the gate voltage V of the transistor Tr1 _GS Is determined by the current value Ic.
[0074]
The gate of the transistor Tr2 is connected to the gate of the transistor Tr1. The source of the transistor Tr2 is connected to the source of the transistor Tr1. Therefore, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2 as it is. Therefore, the drain current of the transistor Tr2 is proportional to the drain current of the transistor Tr1. In particular, μC ₀ W / L and V _TH Are equal to each other, the drain currents of the transistors Tr1 and Tr2 are equal to each other, and I ₂ = Ic.
[0075]
Then, the drain current I of the transistor Tr2 ₂ Flows to the light emitting element 104. The current flowing through the light emitting element has a magnitude corresponding to the signal current Ic determined by the constant current source 107, and the light emitting element 104 emits light with a luminance corresponding to the magnitude of the flowing current. The light emitting element 104 does not emit light when the current flowing through the light emitting element is as close as possible to zero or when the current flowing through the light emitting element flows in the reverse bias direction.
[0076]
When the writing period Ta ends in the pixels on the first line, the selection of the first scanning line G1 and the second scanning line P1 ends. At this time, it is desirable that the selection of the second scanning line P1 is finished before the first scanning line G1. This is because if the transistor Tr3 is turned off first, the charge of the storage capacitor 105 leaks through the Tr4. Then, the writing period Ta is started in the pixels on the second line, and the first scanning line G2 and the second scanning line P2 are selected. Accordingly, the transistor Tr3 and the transistor Tr4 are turned on in the pixels on the second line. Since the third scanning line R2 is not selected, the transistor Tr5 is turned off.
[0077]
Based on the video signal input to the signal line driver circuit 102, a signal current Ic flows between the signal lines S1 to Sx and the power supply lines V1 to Vx. Then, a current having a magnitude corresponding to the signal current Ic flows through the light emitting element 104, and the light emitting element 104 emits light according to the magnitude of the current.
[0078]
Next, the writing period Ta ends in the pixels on the second line, and then the writing period Ta starts in order from the pixels on the second line to the pixels on the y line, and the above-described operation is repeated.
[0079]
On the other hand, when the writing period Ta ends in the pixels on the first line, the display period Td starts next. When the display period Td is started, the third scanning line R1 is selected, and the transistor Tr5 is turned on in the pixels on the first line. Since the first scanning line G1 and the second scanning line P1 are not selected, the transistors Tr3 and Tr4 are turned off.
[0080]
FIG. 5B shows a schematic diagram of a pixel in the display period Td. The transistors Tr3 and Tr4 are in an off state. The sources of the transistors Tr1 and Tr2 are connected to the power supply line Vi, and a constant voltage (power supply voltage) is applied.
[0081]
On the other hand, in the transistors Tr1 and Tr2, V V determined in the writing period Ta _GS Is held as it is. Therefore, the drain current I of the transistor Tr1 ₁ And the drain current I of the transistor Tr2 ₂ The values of are both maintained at a magnitude corresponding to the signal current Ic. Since the transistor Tr5 is on, the drain current I of the transistor Tr1 ₁ And the drain current I of the transistor Tr2 ₂ Both flow to the light emitting element 104. Therefore, drain current I ₁ And drain current I ₂ The light emitting element 104 emits light with a luminance corresponding to the magnitude of the combined current.
[0082]
When the writing period Ta ends in the pixels on the second line, the display period Td starts on the pixels on the second line. Then, like the pixels on the first line, the third scanning line R2 is selected, and the transistor Tr5 is turned on. Since the first scanning line G2 and the second scanning line P2 are not selected, the transistors Tr3 and Tr4 are turned off. And drain current I ₁ And drain current I ₂ The combined current flows through the light-emitting element 104, and the light-emitting element 104 emits light with luminance corresponding to the magnitude of the current flowing through the light-emitting element.
[0083]
When the display period Td is started in the pixels on the second line, the display period Td is subsequently started from the third line to the pixels on the y line, and the above-described operation is repeated.
[0084]
When the writing period Ta and the display period Td end, one frame period ends. One image is displayed in one frame period. Then, the next frame period is started, the writing period Ta is started again, and the above-described operation is repeated.
[0085]
Note that since the light-emitting element 104 emits light with luminance corresponding to the magnitude of current flowing through the light-emitting element, the gray level of each pixel is determined by the magnitude of current flowing through the light-emitting element in the display period Td. Even during the writing period Ta, the drain current I ₁ It emits light with a luminance corresponding to the size of the light, but its influence on the gradation is considered to be negligibly small in an actual panel. This is because, for example, in the case of VGA, pixels of 480 lines are provided in the pixel portion, and the writing period Ta of the pixels of one line is very small, about 1/480 of one frame period. Of course, the magnitude of the signal current Ic may be corrected in consideration of the influence of the current flowing through the light emitting element in the writing period Ta on the gradation.
[0086]
In the pixel having the first structure of the present invention, the current flowing through the light emitting element in the display period is the drain current I. ₁ And drain current I ₂ Is the sum of Therefore, the current flowing through the light emitting element is the drain current I ₂ Not only depend on. Therefore, the characteristics of the transistor Tr1 and the transistor Tr2 are shifted, and the drain current I of the transistor Tr1 ₁ Drain current I of the transistor Tr2 with respect to ₂ Even if the ratio is different between pixels, the value of the current flowing through the light-emitting element can be prevented from being shifted between pixels, and variations in luminance can be prevented from being visually recognized.
[0087]
In the pixel of the present invention, the drain current of the transistor Tr1 does not flow to the light emitting element during the writing period Ta. Therefore, the time from when the gate voltage starts to change due to the current supplied to the pixel by the signal line driver circuit and the drain current of the transistor Tr1 flowing does not depend on the capacitance of the light emitting element. Therefore, compared with the conventional pixel, the voltage converted from the supplied current is stabilized quickly, so that the time for writing the current can be shortened and the afterimage can be prevented from being visually recognized in the moving image display. .
[0088]
Further, as in the prior art, it also has the advantages of a current input type light emitting device. In other words, even when the TFT characteristics vary from pixel to pixel, it is possible to prevent variations in luminance of the light emitting elements between the pixels as compared with the voltage input type light emitting device. Further, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.
[0089]
In the present embodiment, one of the source and the drain of the transistor Tr4 is connected to the signal line Si, and the other is connected to the gate of the transistor Tr1 and the gate of the transistor Tr2. However, the present embodiment is not limited to this configuration. In the pixel having the first structure of the present invention, the transistor Tr4 is connected to another element or wiring so that the gate and drain of the transistor Tr1 can be connected in the writing period Ta and the gate and drain of the transistor Tr1 can be disconnected in the display period. As long as it is connected.
[0090]
That is, Tr3, Tr4, and Tr5 may be connected as shown in FIG. 5A for Ta and as shown in FIG. 5B for Td. In addition, although Gj, Pj, and Rj have three separate wirings, they may be combined into one or two.
[0091]
(Embodiment 2)
In this embodiment mode, a structure different from that in FIG. 3 of the pixel 101 included in the light-emitting device illustrated in FIG. 2 is described.
[0092]
FIG. 6 shows a detailed configuration of the pixel 101 shown in FIG. 6 includes a signal line Si (one of S1 to Sx), a first scanning line Gj (one of G1 to Gy), and a second scanning line Pj (P1 to Py). 1), a third scanning line Rj (one of R1 to Ry) and a power supply line Vi (one of V1 to Vx).
[0093]
The pixel 101 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a transistor Tr5, a transistor Tr6, a light emitting element 214, and a storage capacitor 215. Although the storage capacitor 215 is provided in order to hold the gate voltages of the transistors Tr1 and Tr2 more reliably, it is not always necessary to provide the storage capacitor 215.
[0094]
The gate of the transistor Tr3 is connected to the first scanning line Gj. One of the source and the drain of the transistor Tr3 is connected to the signal line Si, and the other is connected to the sources of the transistors Tr1 and Tr2.
[0095]
The gate of the transistor Tr4 is connected to the second scanning line Pj. One of the source and drain of the transistor Tr4 is connected to the power supply line Vi, and the other is connected to the gates of the transistors Tr1 and Tr2.
[0096]
The gate of the transistor Tr5 is connected to the third scanning line Rj. One of the source and the drain of the transistor Tr5 is connected to the sources of the transistors Tr1 and Tr2, and the other is connected to the pixel electrode of the light emitting element 214.
[0097]
The gate of the transistor Tr6 is connected to the third scanning line Rj. One of the source and the drain of the transistor Tr6 is connected to the power supply line, and the other is connected to the drain of the transistor Tr2.
[0098]
The gates of the transistor Tr1 and the transistor Tr2 are connected to each other. The drain of the transistor Tr1 is connected to the power supply line Vi.
[0099]
One of the two electrodes of the storage capacitor 215 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the sources of the transistors Tr1 and Tr2.
[0100]
The voltage (power supply voltage) of the power supply line Vi is kept at a constant height. The voltage of the counter electrode is also maintained at a constant height.
[0101]
Note that the transistors Tr1 and Tr2 may be either n-channel transistors or p-channel transistors. However, the transistors Tr1 and Tr2 have the same polarity. Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors.
[0102]
The transistors Tr3, Tr4, Tr5, Tr6 may be either n-channel transistors or p-channel transistors. However, the transistors Tr5 and Tr6 have the same polarity because their gates are connected to the third scanning line Rj. When the gates of the transistors Tr5 and Tr6 are not connected to the same wiring, the polarities thereof do not have to be the same.
[0103]
Next, the operation of the light emitting device of this embodiment will be described. The operation of the light-emitting device having the pixel shown in FIG. 6 can be described by being divided into the writing period Ta and the display period Td, as in the case of the pixel shown in FIG.
[0104]
For the voltage applied to the first to third scan lines, the timing chart shown in FIG. 4 can be referred to. FIG. 7 is a diagram simply showing the connection between the transistor Tr1 and the transistor Tr2 in the writing period Ta and the display period Td of the pixel shown in FIG.
[0105]
First, the writing period Ta is started in the pixels on the first line. When the writing period Ta is started, the first scanning line G1 and the second scanning line P1 are selected. Therefore, the transistors Tr3 and Tr4 are turned on. Since the third scanning line R1 is not selected, the transistors Tr5 and Tr6 are turned off.
[0106]
A signal current Ic corresponding to the video signal flows between the signal lines S1 to Sx and the power supply lines V1 to Vx based on the video signal input to the signal line driver circuit 102.
[0107]
FIG. 7A shows a schematic diagram of the pixel 101 when the signal current Ic flows through the signal line Si in the writing period Ta. Reference numeral 216 denotes a terminal for connection with a power source for applying a voltage to the counter electrode. Reference numeral 217 denotes a constant current source included in the signal line driver circuit 102.
[0108]
Since the transistor Tr3 is in the on state, when the signal current Ic flows through the signal line Si, the signal current Ic flows between the drain and source of the transistor Tr1. At this time, the transistor Tr1 operates in the saturation region because the gate and the drain are connected, and Equation 1 is satisfied. Therefore, the gate voltage V of the transistor Tr1 _GS Is determined by the current value Ic.
[0109]
The gate of the transistor Tr2 is connected to the gate of the transistor Tr1. The source of the transistor Tr2 is connected to the source of the transistor Tr1. Therefore, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2 as it is.
[0110]
Note that in the writing Ta, the drain of the transistor Tr2 is in a so-called floating state in which no voltage is applied from another wiring, a power source, or the like. Therefore, no drain current flows through the transistor Tr2.
[0111]
When the writing period Ta ends in the pixels on the first line, the selection of the first scanning line G1 and the second scanning line P1 ends. At this time, it is desirable that the selection of the second scanning line P1 is finished before the first scanning line G1. This is because if the transistor Tr3 is turned off first, the charge in the storage capacitor 215 leaks through the Tr4. Then, the writing period Ta is started in the pixels on the second line, and the first scanning line G2 and the second scanning line P2 are selected. Accordingly, the transistor Tr3 and the transistor Tr4 are turned on in the pixels on the second line. Since the third scanning line R2 is not selected, the transistors Tr5 and Tr6 are turned off.
[0112]
Based on the video signal input to the signal line driver circuit 102, a signal current Ic flows between the signal lines S1 to Sx and the power supply lines V1 to Vx. The gate voltage of the transistor Tr1 is determined by the signal current Ic.
[0113]
Then, the writing period Ta ends in the pixels on the second line, and then the writing period Ta starts in order from the third line to the pixels on the y line, and the above-described operation is repeated.
[0114]
On the other hand, when the writing period Ta ends in the pixels on the first line, the display period Td starts next. When the display period Td is started, the third scanning line R1 is selected. Therefore, the transistors Tr5 and Tr6 are turned on in the pixels on the first line. Since the first scanning line G1 and the second scanning line P1 are not selected, the transistors Tr3 and Tr4 are turned off.
[0115]
FIG. 7B shows a schematic diagram of a pixel in the display period Td. The transistors Tr3 and Tr4 are in an off state. The drains of the transistors Tr1 and Tr2 are connected to the power supply line Vi, and a constant voltage (power supply voltage) is applied.
[0116]
On the other hand, in the transistors Tr1 and Tr2, V V determined in the writing period Ta _GS Is held as it is. Therefore, the same gate voltage as that of the transistor Tr1 is applied to the transistor Tr2. Furthermore, since the transistor Tr6 is turned on and the drain of the transistor Tr2 is connected to the power supply line Vi, the drain current of the transistor Tr2 becomes proportional to the drain current of the transistor Tr1. In particular, μC ₀ W / L and V _TH Are equal to each other, the drain currents of the transistors Tr1 and Tr2 are equal to each other, and I ₂ = I ₁ = Ic.
[0117]
Since the transistor Tr5 is on, the drain current I of the transistor Tr1 ₁ And the drain current I of the transistor Tr2 ₂ Both flow in the light emitting element 214 as a current flowing in the light emitting element. Therefore, in the display period Td, the drain current I ₁ And drain current I ₂ A current having a combined magnitude flows through the light emitting element 214, and the light emitting element 214 emits light with a luminance corresponding to the magnitude of the current flowing through the light emitting element.
[0118]
When the display period Td starts in the pixels on the first line, the display period Td starts next on the pixels in the second line. Then, like the pixels on the first line, the third scanning line R2 is selected, and the transistors Tr5 and Tr6 are turned on. Since the first scanning line G2 and the second scanning line P2 are not selected, the transistors Tr3 and Tr4 are turned off. Therefore, drain current I ₁ And drain current I ₂ The light emitting element 214 emits light with a luminance corresponding to the magnitude of the combined current.
[0119]
Then, after the display period Td is started in the pixels on the second line, the display period Td is started in order from the pixels on the third line to the pixels on the y line, and the above-described operation is repeated.
[0120]
When the writing period Ta and the display period Td end, one frame period ends. One image is displayed in one frame period. Then, the next frame period is started, the writing period Ta is started again, and the above-described operation is repeated.
[0121]
Note that since the light-emitting element 214 emits light with luminance corresponding to the magnitude of current flowing through the light-emitting element, the gray level of each pixel is determined by the magnitude of current flowing through the light-emitting element in the display period Td.
[0122]
In the pixel having the first structure of the present invention, the current flowing through the light emitting element during the display period is the drain current I. ₁ And drain current I ₂ Is the sum of Therefore, the current flowing through the light emitting element is the drain current I ₂ Not only depend on. Therefore, the characteristics of the transistor Tr1 and the transistor Tr2 are shifted, and the drain current I of the transistor Tr1 ₁ Drain current I of the transistor Tr2 with respect to ₂ Even if the ratio is different between pixels, the value of the current flowing through the light-emitting element can be prevented from being shifted between pixels, and variations in luminance can be prevented from being visually recognized.
[0123]
In the pixel of the present invention, the drain current of the transistor Tr1 does not flow to the light emitting element during the writing period Ta. Therefore, the time from when the gate voltage starts to change due to the current supplied to the pixel by the signal line driver circuit and the drain current of the transistor Tr1 flowing does not depend on the capacitance of the light emitting element. Therefore, compared with the conventional pixel, the voltage converted from the supplied current is stabilized quickly, so that the time for writing the current can be shortened and the afterimage can be prevented from being visually recognized in the moving image display. .
[0124]
Further, as in the prior art, it also has the advantages of a current input type light emitting device. In other words, even when the TFT characteristics vary from pixel to pixel, it is possible to prevent variations in luminance of the light emitting elements between the pixels as compared with the voltage input type light emitting device. Further, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.
[0125]
Note that in this embodiment, the source and the drain of the transistor Tr4 are connected to the drain of the transistor Tr1 and the other is connected to the gate of the transistor Tr1 and the gate of the transistor Tr2. However, the present embodiment is not limited to this configuration. In the pixel having the first structure of the present invention, the transistor Tr4 is connected to another element or the transistor Tr1 so that the gate and drain of the transistor Tr1 can be connected in the writing period Ta and the gate and drain of the transistor Tr1 can be disconnected in the display period Td. What is necessary is just to be connected with wiring.
[0126]
That is, Tr3, Tr4, Tr5, and Tr6 may be connected as shown in FIG. 7A for Ta and as shown in FIG. 7B for Td. In addition, although Gj, Pj, and Rj have three separate wirings, they may be combined into one or two.
[0127]
The transistor Tr5 has a signal current Ic and a drain current I of the transistor Tr1 in the writing period Ta. ₁ Is provided to approximate the same value. One of the source and the drain of the transistor Tr5 is not necessarily connected to the sources of the transistors Tr1 and Tr2, and the other is not necessarily connected to the pixel electrode of the light-emitting element 214. The transistor Tr5 may be connected to another wiring or element so that the source of the transistor Tr2 is connected to either the pixel electrode of the light-emitting element 214 or the signal line Si in the writing period Ta.
[0128]
That is, all the current flowing through Tr1 in Ta need only be controlled by the current source. In Td, the current flowing through Tr1 and Tr2 may flow through the light emitting element.
[0129]
(Embodiment 3)
In this embodiment, a structure different from those in FIGS. 3 and 6 of the pixel 101 included in the light-emitting device illustrated in FIGS. In this embodiment, the positions of Tr5 and Tr6 in FIG. 6 are changed. Only one of them may be changed.
[0130]
FIG. 8 shows a detailed configuration of the pixel 101 shown in FIG. 8 includes a signal line Si (one of S1 to Sx), a first scanning line Gj (one of G1 to Gy), and a second scanning line Pj (P1 to Py). 1), a third scanning line Rj (one of R1 to Ry) and a power supply line Vi (one of V1 to Vx).
[0131]
The pixel 101 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a transistor Tr5, a transistor Tr6, a light emitting element 224, and a storage capacitor 225. The storage capacitor 225 is provided in order to hold the gate voltages of the transistors Tr1 and Tr2 more reliably, but is not necessarily provided.
[0132]
The gate of the transistor Tr3 is connected to the first scanning line Gj. One of the source and the drain of the transistor Tr3 is connected to the signal line Si, and the other is connected to the source of the transistor Tr1.
[0133]
The gate of the transistor Tr4 is connected to the second scanning line Pj. One of the source and drain of the transistor Tr4 is connected to the power supply line Vi, and the other is connected to the gates of the transistors Tr1 and Tr2.
[0134]
The gate of the transistor Tr6 is connected to the third scanning line Rj. One of the source and the drain of the transistor Tr6 is connected to the source of the transistor Tr2, and the other is connected to the pixel electrode of the light emitting element 224.
[0135]
The gate of the transistor Tr5 is connected to the third scanning line Rj. One of the source and the drain of the transistor Tr5 is connected to the source of the transistor Tr1, and the other is connected to the pixel electrode of the light emitting element 224.
[0136]
The gates of the transistor Tr1 and the transistor Tr2 are connected to each other. The drains of the transistors Tr1 and Tr2 are connected to the power supply line Vi.
[0137]
One of the two electrodes of the storage capacitor 225 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the source of the transistor Tr1.
[0138]
The voltage (power supply voltage) of the power supply line Vi is kept at a constant height. The voltage of the counter electrode is also maintained at a constant height.
[0139]
Note that the transistors Tr1 and Tr2 may be either n-channel transistors or p-channel transistors. However, the transistors Tr1 and Tr2 have the same polarity. Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors.
[0140]
The transistors Tr3, Tr4, Tr5, Tr6 may be either n-channel transistors or p-channel transistors. However, the transistors Tr5 and Tr6 have the same polarity because their gates are connected to the third scanning line Rj. When the gates of the transistors Tr5 and Tr6 are not connected to the same wiring, the polarities thereof do not have to be the same.
[0141]
Next, the operation of the light emitting device of this embodiment will be described. The operation of the light-emitting device having the pixel shown in FIG. 8 can be described by being divided into the writing period Ta and the display period Td, as in the case of the pixels shown in FIGS.
[0142]
For the voltage applied to the first to third scan lines, the timing chart shown in FIG. 4 can be referred to. FIG. 9 is a diagram simply showing the connection between the transistor Tr1 and the transistor Tr2 in the writing period Ta and the display period Td of the pixel shown in FIG.
[0143]
First, the writing period Ta is started in the pixels on the first line. When the writing period Ta is started, the first scanning line G1 and the second scanning line P1 are selected. Therefore, the transistors Tr3 and Tr4 are turned on. Since the third scanning line R1 is not selected, the transistors Tr5 and Tr6 are turned off.
[0144]
A signal current Ic corresponding to the video signal flows between the signal lines S1 to Sx and the power supply lines V1 to Vx based on the video signal input to the signal line driver circuit 102.
[0145]
FIG. 9A is a schematic diagram of the pixel 101 when the signal current Ic flows through the signal line Si in the writing period Ta. Reference numeral 226 denotes a terminal for connection to a power source for applying a voltage to the counter electrode. Reference numeral 227 denotes a constant current source included in the signal line driver circuit 102.
[0146]
Since the transistor Tr3 is in the on state, when the signal current Ic flows through the signal line Si, the signal current Ic flows between the drain and source of the transistor Tr1. At this time, the transistor Tr1 operates in the saturation region because the gate and the drain are connected, and Equation 1 is satisfied. Therefore, the gate voltage V of the transistor Tr1 _GS Is determined by the current value Ic.
[0147]
Note that since the transistor Tr6 is off in the writing period Ta, the source of the transistor Tr2 is in a so-called floating state in which no voltage is applied from another wiring, a power source, or the like. Therefore, no drain current flows through the transistor Tr2.
[0148]
When the writing period Ta ends in the pixels on the first line, the selection of the first scanning line G1 and the second scanning line P1 ends. At this time, it is desirable that the selection of the second scanning line P1 is finished before the first scanning line G1. This is because if the transistor Tr3 is turned off first, the charge in the storage capacitor 225 leaks through the Tr4. Then, the writing period Ta is started in the pixels on the second line, and the first scanning line G2 and the second scanning line P2 are selected. Accordingly, the transistor Tr3 and the transistor Tr4 are turned on in the pixels on the second line. Since the third scanning line R2 is not selected, the transistors Tr5 and Tr6 are turned off.
[0149]
Based on the video signal input to the signal line driver circuit 102, a signal current Ic flows between the signal lines S1 to Sx and the power supply lines V1 to Vx. The gate voltage of the transistor Tr1 is determined by the signal current Ic.
[0150]
Then, the writing period Ta ends in the pixels on the second line, and then the writing period Ta starts in order from the third line to the pixels on the y line, and the above-described operation is repeated.
[0151]
On the other hand, when the writing period Ta ends in the pixels on the first line, the display period Td starts next. When the display period Td is started, the third scanning line R1 is selected. Therefore, the transistors Tr5 and Tr6 are turned on in the pixels on the first line. Since the first scanning line G1 and the second scanning line P1 are not selected, the transistors Tr3 and Tr4 are turned off.
[0152]
FIG. 9B shows a schematic diagram of a pixel in the display period Td. The transistors Tr3 and Tr4 are in an off state. The drains of the transistors Tr1 and Tr2 are connected to the power supply line Vi, and a constant voltage (power supply voltage) is applied.
[0153]
On the other hand, in the transistor Tr1, V V determined in the writing period Ta _GS Is held as it is. The gate of the transistor Tr2 is connected to the gate of the transistor Tr1. The source of the transistor Tr2 is connected to the source of the transistor Tr1. Therefore, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2 as it is. Furthermore, since the drain of the transistor Tr2 is connected to the power supply line Vi, the drain current I of the transistor Tr2 ₂ Is proportional to the drain current of the transistor Tr1. In particular, μC ₀ W / L and V _TH Are equal to each other, the drain currents of the transistors Tr1 and Tr2 are equal to each other, and I ₂ = I ₁ = Ic.
[0154]
Since the transistor Tr5 is on, the drain current I of the transistor Tr1 ₁ And the drain current I of the transistor Tr2 ₂ Both flow to the light emitting element 224 as a current flowing to the light emitting element. Therefore, in the display period Td, the drain current I ₁ And drain current I ₂ A current having a combined size flows through the light-emitting element 224, and the light-emitting element 224 emits light with luminance corresponding to the magnitude of the current flowing through the light-emitting element.
[0155]
When the display period Td starts in the pixels on the first line, the display period Td starts next on the pixels in the second line. Then, like the pixels on the first line, the third scanning line R2 is selected, and the transistors Tr5 and Tr6 are turned on. Since the first scanning line G2 and the second scanning line P2 are not selected, the transistors Tr3 and Tr4 are turned off. Therefore, drain current I ₁ And drain current I ₂ The light emitting element 214 emits light with a luminance corresponding to the magnitude of the combined current.
[0156]
When the display period Td is started in the pixels on the second line, the display period Td is started in order from the pixels on the third line to the pixels on the y line, and the above-described operation is repeated.
[0157]
When the writing period Ta and the display period Td end, one frame period ends. One image is displayed in one frame period. Then, the next frame period is started, the writing period Ta is started again, and the above-described operation is repeated.
[0158]
Note that since the light emitting element 224 emits light with luminance corresponding to the magnitude of current flowing through the light emitting element, the gradation of each pixel is determined by the magnitude of current flowing through the light emitting element in the display period Td.
[0159]
In the pixel having the first structure of the present invention, the current flowing through the light emitting element during the display period is the drain current I. ₁ And drain current I ₂ Is the sum of Therefore, the current flowing through the light emitting element is the drain current I ₂ Not only depend on. Therefore, the characteristics of the transistor Tr1 and the transistor Tr2 are shifted, and the drain current I of the transistor Tr1 ₁ Drain current I of the transistor Tr2 with respect to ₂ Even if the ratio is different between pixels, the value of the current flowing through the light-emitting element can be prevented from being shifted between pixels, and variations in luminance can be prevented from being visually recognized.
[0160]
In the pixel of the present invention, the drain current of the transistor Tr1 does not flow to the light emitting element during the writing period Ta. Therefore, the time from when the gate voltage starts to change due to the current supplied to the pixel by the signal line driver circuit and the drain current of the transistor Tr1 flowing does not depend on the capacitance of the light emitting element. Therefore, compared with the conventional pixel, the voltage converted from the supplied current is stabilized quickly, so that the time for writing the current can be shortened and the afterimage can be prevented from being visually recognized in the moving image display. .
[0161]
Further, as in the prior art, it also has the advantages of a current input type light emitting device. In other words, even when the TFT characteristics vary from pixel to pixel, it is possible to prevent variations in luminance of the light emitting elements between the pixels as compared with the voltage input type light emitting device. Further, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.
[0162]
Note that in this embodiment, the source and the drain of the transistor Tr4 are connected to the drain of the transistor Tr1 and the other is connected to the gate of the transistor Tr1 and the gate of the transistor Tr2. However, the present embodiment is not limited to this configuration. In the pixel having the first structure of the present invention, the transistor Tr4 is connected to another element or wiring so that the gate and drain of the transistor Tr1 can be connected in the writing period Ta and the gate and drain of the transistor Tr1 can be disconnected in the display period. As long as it is connected.
[0163]
That is, Tr3, Tr4, Tr5, and Tr6 may be connected as shown in FIG. 9A for Ta and as shown in FIG. 9B for Td. In addition, although Gj, Pj, and Rj have three separate wirings, they may be combined into one or two.
[0164]
It is only necessary that the current flowing through Tr1 in Ta is controlled by the current source. In Td, the current flowing through Tr1 and Tr2 may flow through the light emitting element.
[0165]
(Embodiment 4)
In this embodiment mode, a structure of a pixel included in a light-emitting device having a second structure of the present invention will be described.
[0166]
FIG. 37A shows a circuit diagram of a pixel of this embodiment mode. The pixel shown in FIG. 37 includes transistors Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, a light emitting element 6008, and a storage capacitor 6000. The storage capacitor 6000 is provided to hold the gate voltages of the transistors Tr1 and Tr2 more reliably, but is not necessarily provided.
[0167]
The gate of the transistor Tr3 is connected to the terminal 6002. One of the source and the drain of the transistor Tr3 is connected to the terminal 6001, and the other is connected to the drain of the transistor Tr1.
[0168]
The gate of the transistor Tr4 is connected to the terminal 6003. One of the source and the drain of the transistor Tr4 is connected to the terminal 6001, and the other is connected to the gates of the transistors Tr1 and Tr2.
[0169]
The gate of the transistor Tr5 is connected to the terminal 6004. One of the source and the drain of the transistor Tr5 is connected to the drain of the transistor Tr1, and the other is connected to the drain of the transistor Tr2.
[0170]
The gate of the transistor Tr6 is connected to the terminal 6007. One of the source and the drain of the transistor Tr6 is connected to the drain of the transistor Tr2, and the other is connected to the pixel electrode of the light emitting element 6008.
[0171]
The gates of the transistor Tr1 and the transistor Tr2 are connected to each other. The sources of the transistors Tr1 and Tr2 are both connected to the terminal 6005.
[0172]
One of the two electrodes of the storage capacitor 6000 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the sources of the transistors Tr1 and Tr2.
[0173]
A counter electrode of the light emitting element 6008 is connected to the terminal 6006. A voltage is applied to the terminal 6005 and the terminal 6006 by a power supply, and a predetermined voltage difference is always generated.
[0174]
Note that FIG. 37A shows a case where both Tr1 and Tr2 are p-channel TFTs, and the polarity of the transistors Tr1 and Tr2 is always the same. Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors.
[0175]
The transistors Tr3 to Tr6 may be either n-channel transistors or p-channel transistors. This can be determined in consideration of the voltage applied to each terminal.
[0176]
Next, the operation of the light emitting device of this embodiment will be described. The operation of the light-emitting device including the pixel illustrated in FIG. 37A can be described by being divided into a writing period Ta and a display period Td.
[0177]
The connection of the transistors Tr1 and Tr2 in the pixel shown in FIG. 37A at the start of the writing period Ta is simply shown in FIG. At the start of the writing period Ta, Tr3 to Tr5 are turned on and Tr6 is turned off. Then, based on the video signal input to the terminal 6001, a signal current Ic corresponding to the video signal flows between the terminal 6001 and the terminal 6005.
[0178]
Due to the signal current Ic, the drain current I between the source and drain of Tr1 ₁ However, the drain current I between the source and drain of Tr2 ₂ Flows. That is, the signal current Ic is equal to the drain current I ₁ And drain current I ₂ Is equivalent to the sum of At this time, the transistor Tr1 operates in the saturation region because the gate and the drain are connected, and Equation 1 is satisfied. Therefore, the gate voltage V of the transistor Tr1 _GS Is the current I ₁ It depends on.
[0179]
The gate of the transistor Tr2 is connected to the gate of the transistor Tr1. The source of the transistor Tr2 is connected to the source of the transistor Tr1. Therefore, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2 as it is.
[0180]
The gate voltages of Tr1 and Tr2 are the same, but μ, C ₀ , W / L is different between Tr1 and Tr2, I ₁ And I ₂ Are not necessarily equal.
[0181]
It is desirable to turn off Tr4 before the writing period Ta ends. The connection between the transistors Tr1 and Tr2 when Tr4 is turned off is simply shown in FIG. This is because if the transistor Tr3 is turned off first, the charge of the storage capacitor 6000 leaks through the Tr4.
[0182]
Next, when the writing period Ta ends, the display period Td starts. When the display period Td is started, Tr3 to Tr5 are turned off and Tr6 is turned on.
[0183]
FIG. 37D is a schematic diagram of a pixel in the display period Td. In the transistor Tr2, V determined by the writing period Ta _GS Is held by the holding capacitor 6000 as it is. Further, since Tr6 is turned on, the drain current I of Tr2 ₂ Is supplied to the light emitting element 6008. The light emitting element 6008 has a current I supplied to the light emitting element. ₂ It emits light with a brightness suitable for the size of the. That is, since the light emitting element 6008 emits light with luminance corresponding to the magnitude of current flowing through the light emitting element, the gradation of each pixel is determined by the magnitude of current flowing through the light emitting element in the display period Td.
[0184]
When the writing period Ta and the display period Td end, one frame period ends. One image is displayed in one frame period. Then, the next frame period is started, the writing period Ta is started again, and the above-described operation is repeated.
[0185]
In the pixel of the second configuration according to the present invention, the current I supplied from the driving unit to the light emitting element due to the characteristics of the transistors Tr1 and Tr2 being shifted. ₂ May not be maintained at a desired value. However, since the current is converted into the voltage by using both Tr1 and Tr2, the converted voltage can be averaged, and the current I supplied from the drive unit to the light emitting element ₂ Since the magnitude corresponds to the averaged voltage, the variation in the amount of current supplied to the light-emitting element due to the characteristic deviation is suppressed to about half that of the pixel shown in FIG. be able to. Therefore, variation in luminance between pixels can be suppressed. In addition, the current supplied to the pixel is the current I ₂ Bigger than. Therefore, the time for writing current can be shortened.
[0186]
In the pixel of the present invention, no signal current flows through the light emitting element in the writing period Ta. Therefore, the time from when the gate voltage starts to change due to the current supplied to the pixel by the signal line driver circuit and the drain current of the transistor Tr1 flowing does not depend on the capacitance of the light emitting element. Therefore, compared with the conventional pixel, the voltage converted from the supplied current is stabilized quickly, so that the time for writing the current can be shortened and the afterimage can be prevented from being visually recognized in the moving image display. .
[0187]
Further, as in the prior art, it also has the advantages of a current input type light emitting device. In other words, even when the TFT characteristics vary from pixel to pixel, it is possible to prevent variations in luminance of the light emitting elements between the pixels as compared with the voltage input type light emitting device. Further, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.
[0188]
Note that the connection of the transistors Tr3, Tr4, Tr5, and Tr6 is not limited to the structure illustrated in FIG. The connections of Tr3, Tr4, Tr5, and Tr6 may be determined so that Tr1 and Tr2 are connected as shown in FIGS. 37B to 37D in each period.
[0189]
That is, at the start of the writing period, as shown in FIG. 37B, the sources of Tr1 and Tr2 are both connected to the terminal 6005, and the gates and drains of Tr1 and Tr2 are both connected to the terminal 6001. One of the two electrodes of the storage capacitor is connected to the terminal 6005 and the other is connected to the gates of Tr1 and Tr2. Before the end of the writing period, the gates of Tr1 and Tr2 are connected as shown in FIG. 37C, the sources of Tr1 and Tr2 are connected to the terminal 6005, and the drains of Tr1 and Tr2 are connected to the terminal 6001. To do. One of the two electrodes of the storage capacitor is connected to the terminal 6005 and the other is connected to the gate of Tr2. Thereby, the charge of the storage capacitor 6000 can be held. Note that the gates of Tr1 and Tr2 do not necessarily have to be connected as long as the charge of the storage capacitor is held. When the gates of Tr1 and Tr2 are not connected, the gate and drain of Tr1 may be connected.
[0190]
In the display period, as shown in FIG. 37D, the gates of Tr1 and Tr2 are connected, the sources of Tr1 and Tr2 are connected to a terminal 6005, the drain or source of Tr1 is floated, and the drain of Tr2 is a light emitting element. To the pixel electrode. One of the two electrodes of the storage capacitor is connected to the terminal 6005 and the other is connected to the gate of Tr2. At this time, the gates of Tr1 and Tr2 need not be connected. In this case, the gate and drain of Tr1 may be connected.
[0191]
For example, one of the source and drain of Tr3 is always connected to the terminal 6001, but the other is not necessarily connected to the drain of Tr1, and may be connected to the drain of Tr2. One of the source and the drain of Tr4 is always connected to the gates of Tr1 and Tr2, but the other is not necessarily connected to the terminal 6001 and is connected to the drain of Tr1 or the drain of Tr2. Also good. One of the source and the drain of Tr5 is always connected to the drain of Tr2, but the other is not necessarily connected to the drain of Tr1, and may be connected to the terminal 6001.
[0192]
(Embodiment 5)
In this embodiment mode, a structure of a pixel included in a light-emitting device having a second structure of the present invention will be described.
[0193]
FIG. 38A shows a circuit diagram of a pixel of this embodiment mode. The pixel shown in FIG. 38 includes transistors Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, a light emitting element 6108, and a storage capacitor 6100. The storage capacitor 6100 is provided to hold the gate voltages of Tr1 and Tr2 more reliably, but is not necessarily provided.
[0194]
The gate of the transistor Tr3 is connected to the terminal 6102. One of the source and the drain of the transistor Tr3 is connected to the terminal 6101, and the other is connected to the source of the transistor Tr1.
[0195]
The gate of the transistor Tr4 is connected to the terminal 6103. One of the source and the drain of the transistor Tr4 is connected to the terminal 6105, and the other is connected to the gates of the transistors Tr1 and Tr2.
[0196]
The gate of the transistor Tr5 is connected to the terminal 6104. One of the source and the drain of the transistor Tr5 is connected to the source of the transistor Tr1, and the other is connected to the source of the transistor Tr2.
[0197]
The gate of the transistor Tr6 is connected to the terminal 6107. One of the source and the drain of the transistor Tr6 is connected to the source of the transistor Tr2, and the other is connected to the pixel electrode of the light emitting element 6108.
[0198]
The gates of the transistor Tr1 and the transistor Tr2 are connected to each other. The drains of the transistors Tr1 and Tr2 are both connected to the terminal 6105.
[0199]
One of the two electrodes of the storage capacitor 6100 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the sources of the transistors Tr1 and Tr2.
[0200]
A counter electrode of the light emitting element 6108 is connected to the terminal 6106. A voltage is applied to the terminal 6105 and the terminal 6106 by the power supply, respectively, and a predetermined voltage difference is always generated.
[0201]
Note that FIG. 38A shows the case where both Tr1 and Tr2 are n-channel TFTs, and the polarities of the transistors Tr1 and Tr2 are always the same. Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors.
[0202]
The transistors Tr3 to Tr6 may be either n-channel transistors or p-channel transistors. This can be determined in consideration of the voltage applied to each terminal.
[0203]
Next, the operation of the light emitting device of this embodiment will be described. The operation of the light-emitting device including the pixel illustrated in FIG. 38A can be described by being divided into a writing period Ta and a display period Td.
[0204]
The connection between the transistors Tr1 and Tr2 in the pixel shown in FIG. 38A at the start of the writing period Ta is simply shown in FIG. At the start of the writing period Ta, Tr3 to Tr5 are turned on and Tr6 is turned off. Based on the video signal input to the terminal 6101, a signal current Ic corresponding to the video signal flows between the terminal 6101 and the terminal 6105.
[0205]
Due to the signal current Ic, the drain current I between the source and drain of Tr1 ₁ However, the drain current I between the source and drain of Tr2 ₂ Flows. That is, the signal current Ic is equal to the drain current I ₁ And drain current I ₂ Is equivalent to the sum of At this time, the transistor Tr1 operates in the saturation region because the gate and the drain are connected, and Equation 1 is satisfied. Therefore, the gate voltage V of the transistor Tr1 _GS Is the current I ₁ It depends on.
[0206]
The gate of the transistor Tr2 is connected to the gate of the transistor Tr1. The source of the transistor Tr2 is connected to the source of the transistor Tr1. Therefore, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2 as it is.
[0207]
The gate voltages of Tr1 and Tr2 are the same, but μ, C ₀ , W / L is different between Tr1 and Tr2, I ₁ And I ₂ Are not necessarily equal.
[0208]
It is desirable to turn off Tr4 before the writing period Ta ends. The connection between the transistors Tr1 and Tr2 when Tr4 is turned off is simply shown in FIG. This is because if the transistor Tr3 is turned off first, the charge of the storage capacitor 6100 leaks through Tr4.
[0209]
Next, when the writing period Ta ends, the display period Td starts. When the display period Td is started, Tr3 to Tr5 are turned off and Tr6 is turned on.
[0210]
FIG. 38D is a schematic diagram of pixels in the display period Td. In the transistor Tr2, V determined by the writing period Ta _GS Is held by the holding capacitor 6100 as it is. Further, since Tr6 is turned on, the drain current I of Tr2 ₂ Is supplied to the light emitting element 6108. The light emitting element 6108 has a current I supplied to the light emitting element. ₂ It emits light with a brightness suitable for the size of the. In other words, since the light-emitting element 6108 emits light with luminance corresponding to the magnitude of current flowing through the light-emitting element, the gray level of each pixel is determined by the magnitude of current flowing through the light-emitting element in the display period Td.
[0211]
When the writing period Ta and the display period Td end, one frame period ends. One image is displayed in one frame period. Then, the next frame period is started, the writing period Ta is started again, and the above-described operation is repeated.
[0212]
In the pixel of the second configuration according to the present invention, the current I supplied from the driving unit to the light emitting element due to the characteristics of the transistors Tr1 and Tr2 being shifted. ₂ May not be maintained at a desired value. However, since the current is converted into the voltage by using both Tr1 and Tr2, the converted voltage can be averaged, and the current I supplied from the drive unit to the light emitting element ₂ Since the magnitude corresponds to the averaged voltage, the variation in the amount of current supplied to the light-emitting element due to the characteristic deviation is suppressed to about half that of the pixel shown in FIG. be able to. Therefore, variation in luminance between pixels can be suppressed. In addition, the current supplied to the pixel is the current I ₂ Bigger than. Therefore, the time for writing current can be shortened.
[0213]
In the pixel of the present invention, the signal current Ic does not flow through the light emitting element during the writing period Ta. Therefore, the time from when the gate voltage starts to change due to the current supplied to the pixel by the signal line driver circuit and the drain current of the transistor Tr1 flowing does not depend on the capacitance of the light emitting element. Therefore, compared with the conventional pixel, the voltage converted from the supplied current is stabilized quickly, so that the time for writing the current can be shortened and the afterimage can be prevented from being visually recognized in the moving image display. .
[0214]
Further, as in the prior art, it also has the advantages of a current input type light emitting device. In other words, even when the TFT characteristics vary from pixel to pixel, it is possible to prevent variations in luminance of the light emitting elements between the pixels as compared with the voltage input type light emitting device. Further, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.
[0215]
Note that the connection of the transistors Tr3, Tr4, Tr5, and Tr6 is not limited to the structure illustrated in FIG. The connections of Tr3, Tr4, Tr5, and Tr6 may be determined so that Tr1 and Tr2 are connected as shown in FIGS. 38B to 38D in each period.
[0216]
That is, at the start of the writing period, the sources of Tr1 and Tr2 are both connected to the terminal 6101 as shown in FIG. 38B, and the gates and drains of Tr1 and Tr2 are both connected to the terminal 6105. One of the two electrodes of the storage capacitor is connected to the terminal 6101 and the other is connected to the gates of Tr1 and Tr2. Before the end of the writing period, the gates of Tr1 and Tr2 are connected as shown in FIG. 38C, and the drains of Tr1 and Tr2 are both connected to the terminal 6105. One of the two electrodes of the storage capacitor is connected to the source of Tr2, and the other is connected to the gate of Tr2. Thereby, the charge of the storage capacitor 6100 can be held. Note that the gates of Tr1 and Tr2 do not necessarily have to be connected as long as the charge of the storage capacitor is held. When the gates of Tr1 and Tr2 are not connected, the gate and drain of Tr1 may be connected.
[0217]
In the display period, as shown in FIG. 38D, the gates of Tr1 and Tr2 are connected, the drains of Tr1 and Tr2 are both connected to a terminal 6105, the source or drain of Tr1 is floated, and the source of Tr2 is set as a light emitting element. To the pixel electrode. One of the two electrodes of the storage capacitor is connected to the source of Tr2, and the other is connected to the gate of Tr2. At this time, the gates of Tr1 and Tr2 need not be connected. In this case, the gate and drain of Tr1 may be connected.
[0218]
For example, one of the source and drain of Tr3 is always connected to the terminal 6101, but the other is not necessarily connected to the source of Tr1, and may be connected to the source of Tr2. One of the source and the drain of Tr5 is always connected to the drain of Tr2, but the other is not necessarily connected to the drain of Tr1, and may be connected to the terminal 6101.
[0219]
(Embodiment 6)
In Embodiments 1 to 5, the case where the video signal is analog has been described, but it is also possible to drive using a digital video signal.
[0220]
In the case of a time gradation driving method (digital driving method) using a digital video signal, one image can be displayed by repeatedly appearing a writing period Ta and a display period Td in one frame period. is there.
[0221]
For example, when an image is displayed by an n-bit video signal, at least n writing periods and n display periods are provided in one frame period. The n writing periods (Ta1 to Tan) and the n display periods (Td1 to Tdn) correspond to each bit of the video signal.
[0222]
Next to the writing period Tam (m is an arbitrary number from 1 to n), a display period corresponding to the same number of bits, in this case Tdm, appears. The writing period Ta and the display period Td are collectively called a subframe period SF. A subframe period having a writing period Tam and a display period Tdm corresponding to the m-th bit is SFm.
[0223]
The lengths of the subframe periods SF1 to SFn are SF1: SF2:...: SFn = 2 ⁰ : 2 ¹ : ...: 2 ^n-1 Meet.
[0224]
Whether each light emitting element emits light in each subframe period is selected by each bit of the digital video signal. Then, the number of gradations can be controlled by controlling the sum of the lengths of the display periods during which light is emitted during one frame period.
[0225]
Note that a subframe period having a long display period may be divided into several parts in order to improve image quality on display. The specific division method is disclosed in Japanese Patent Application No. 2000-267164, and can be referred to.
[0226]
Further, gradation may be displayed in combination with area gradation.
[0227]
Note that in the light-emitting device of the present invention, the transistor used for the pixel may be a transistor formed using single crystal silicon, or a thin film transistor using polysilicon or amorphous silicon.
[0228]
【Example】
Examples of the present invention will be described below.
[0229]
Example 1
In this embodiment, a structure of the pixel 101 included in the light-emitting device illustrated in FIG. 2 which is different from those in FIGS. 3, 6, and 8 will be described.
[0230]
FIG. 10 shows a detailed configuration of the pixel 101 shown in FIG. The pixel 101 shown in FIG. 10 includes a signal line Si (one of S1 to Sx), a first scanning line Gj (one of G1 to Gy), and a second scanning line Pj (P1 to Py). 1), a third scanning line Rj (one of R1 to Ry) and a power supply line Vi (one of V1 to Vx).
[0231]
The pixel 101 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a transistor Tr5, a light emitting element 234, and a storage capacitor 235. The storage capacitor 235 is provided in order to hold the voltage (gate voltage) between the gates and the sources of the transistors Tr1 and Tr2 more reliably, but is not necessarily provided.
[0232]
The gate of the transistor Tr3 is connected to the first scanning line Gj. One of the source and the drain of the transistor Tr3 is connected to the signal line Si, and the other is connected to the drain of the transistor Tr1.
[0233]
The gate of the transistor Tr4 is connected to the second scanning line Pj. One of the source and the drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gates of the transistors Tr1 and Tr2.
[0234]
The gate of the transistor Tr5 is connected to the third scanning line Rj. One of the source and the drain of the transistor Tr5 is connected to the drain of the transistor Tr1, and the other is connected to the drain of the transistor Tr2.
[0235]
The gates of the transistor Tr1 and the transistor Tr2 are connected to each other. The sources of the transistors Tr1 and Tr2 are both connected to the power supply line Vi. The drain of the transistor Tr2 is connected to the pixel electrode of the light emitting element 234.
[0236]
One of the two electrodes of the storage capacitor 235 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the power supply line Vi.
[0237]
The light-emitting element 234 includes an anode and a cathode. In this specification, when the anode is used as a pixel electrode, the cathode is called a counter electrode, and when the cathode is used as a pixel electrode, the anode is called a counter electrode.
[0238]
The voltage (power supply voltage) of the power supply line Vi is kept at a constant height. The voltage of the counter electrode is also maintained at a constant height.
[0239]
Note that the transistors Tr1 and Tr2 may be either n-channel transistors or p-channel transistors. However, the transistors Tr1 and Tr2 have the same polarity. Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors.
[0240]
The transistors Tr3, Tr4, and Tr5 may be either n-channel transistors or p-channel transistors. In addition, although Gj, Pj, and Rj have three separate wirings, they may be combined into one or two.
[0241]
The operation of the light-emitting device having the pixel shown in FIG. 10 can be described by being divided into the writing period Ta and the display period Td, similarly to the case of the pixel shown in FIG. The operation of the pixel in the writing period Ta and the display period Td is the same as that in the case of the pixel shown in FIG. 3 and can be referred to FIGS. To do.
[0242]
(Example 2)
In this example, a structure of a pixel in the case where the gate of the transistor Tr5 is connected to the first scan line in the light-emitting device described in Embodiment 1 will be described.
[0243]
FIG. 11 shows a detailed configuration of the pixel 101 shown in FIG. The pixel 101 shown in FIG. 11 includes a signal line Si (one of S1 to Sx), a first scanning line Gj (one of G1 to Gy), and a second scanning line Pj (P1 to Py). 1) and a power supply line Vi (one of V1 to Vx).
[0244]
The pixel 101 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a transistor Tr5, a light emitting element 244, and a storage capacitor 245. The storage capacitor 245 is provided in order to hold the voltage (gate voltage) between the gates and the sources of the transistors Tr1 and Tr2 more reliably, but is not necessarily provided.
[0245]
The gate of the transistor Tr3 is connected to the first scanning line Gj. One of the source and the drain of the transistor Tr3 is connected to the signal line Si, and the other is connected to the drain of the transistor Tr1.
[0246]
The gate of the transistor Tr4 is connected to the second scanning line Pj. One of the source and the drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gate of the transistor Tr1 and the gate of the transistor Tr2.
[0247]
The gate of the transistor Tr5 is connected to the first scanning line Gj. One of the source and the drain of the transistor Tr5 is connected to the drain of the transistor Tr1, and the other is connected to the drain of the transistor Tr2.
[0248]
The gates of the transistor Tr1 and the transistor Tr2 are connected to each other. The sources of the transistors Tr1 and Tr2 are both connected to the power supply line Vi. The drain of the transistor Tr2 is connected to the pixel electrode of the light emitting element 244.
[0249]
One of the two electrodes of the storage capacitor 245 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the power supply line Vi.
[0250]
The voltage (power supply voltage) of the power supply line Vi is kept at a constant height. The voltage of the counter electrode is also maintained at a constant height.
[0251]
In this embodiment, the transistors Tr1 and Tr2 are p-channel transistors. The transistors Tr1 and Tr2 may be n-channel transistors. However, the transistors Tr1 and Tr2 have the same polarity.
[0252]
Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors.
[0253]
In this embodiment, since the gate of the transistor Tr3 and the gate of the transistor Tr5 are connected, the polarities of the transistors Tr3 and Tr5 are different.
[0254]
In this embodiment, the transistors Tr3 and Tr4 are both n-channel transistors. The transistors Tr3 and Tr4 may be p-channel transistors. However, the transistors Tr3 and Tr4 have the same polarity. In the present embodiment, the gates of the transistors Tr3 and Tr4 are connected to different wirings so that the transistor Tr4 can be turned off before the Tr3 when the writing period ends. By turning off the transistor Tr4 before Tr3, the charge of the storage capacitor 245 can be prevented from leaking through the transistor Tr4.
[0255]
The operation of the light-emitting device including the pixel illustrated in FIG. 11 can be described by being divided into the writing period Ta and the display period Td, as in the case of the pixel illustrated in FIG. The operation of the pixel in the writing period Ta and the display period Td is the same as that of the pixel shown in FIG. 3, and FIG. 5 of Embodiment 1 can be referred to; therefore, description thereof is omitted here.
[0256]
In the case of the light-emitting device of this example, as compared to the light-emitting device described in Embodiment Mode 1, one wiring can be omitted. Therefore, the yield in the manufacturing process can be increased. In addition, since the aperture ratio can be increased, the screen can be brightened even with the same current consumption when light from the light-emitting element is emitted to the substrate side on which the wiring or the like is formed.
[0257]
Example 3
In this example, a structure of a pixel in the case where the gates of the transistors Tr3, Tr4, and Tr5 are connected to the same scanning line in the light-emitting device described in Embodiment 1 will be described.
[0258]
FIG. 12 shows a detailed configuration of the pixel 101 shown in FIG. The pixel 101 shown in FIG. 12 includes a signal line Si (one of S1 to Sx), a scanning line Gj (one of G1 to Gy), and a power supply line Vi (one of V1 to Vx). Have.
[0259]
In addition, the pixel 101 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a transistor Tr5, a light emitting element 254, and a storage capacitor 255. The storage capacitor 255 is provided in order to hold the voltage (gate voltage) between the gates and sources of the transistors Tr1 and Tr2 more reliably, but is not necessarily provided.
[0260]
The gate of the transistor Tr3 is connected to the scanning line Gj. One of the source and the drain of the transistor Tr3 is connected to the signal line Si, and the other is connected to the drain of the transistor Tr1.
[0261]
The gate of the transistor Tr4 is connected to the scanning line Gj. One of the source and the drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gates of the transistors Tr1 and Tr2.
[0262]
The gate of the transistor Tr5 is connected to the scanning line Gj. One of the source and the drain of the transistor Tr5 is connected to the drain of the transistor Tr1, and the other is connected to the drain of the transistor Tr2.
[0263]
The gates of the transistor Tr1 and the transistor Tr2 are connected to each other. The sources of the transistors Tr1 and Tr2 are both connected to the power supply line Vi. The drain of the transistor Tr2 is connected to the pixel electrode of the light emitting element 254.
[0264]
One of the two electrodes of the storage capacitor 255 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the power supply line Vi.
[0265]
The voltage (power supply voltage) of the power supply line Vi is kept at a constant height. The voltage of the counter electrode is also maintained at a constant height.
[0266]
In this embodiment, the transistors Tr1 and Tr2 are p-channel transistors. The transistors Tr1 and Tr2 may be n-channel transistors. However, the transistors Tr1 and Tr2 have the same polarity.
[0267]
Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors.
[0268]
In this embodiment, the transistors Tr3 and Tr4 are both n-channel transistors, and the transistor Tr5 is a p-channel transistor. The transistors Tr3, Tr4, and Tr5 may be n-channel transistors or p-channel transistors. However, the transistors Tr3 and Tr4 have the same polarity, and the transistor Tr5 has the opposite polarity to the transistors Tr3 and Tr4.
[0269]
The operation of the light-emitting device having the pixel shown in FIG. 12 can be described by being divided into the writing period Ta and the display period Td, as in the case of the pixel shown in FIG. The operation of the pixel in the writing period Ta and the display period Td is the same as that of the pixel shown in FIG. 3, and FIG. 5 of Embodiment 1 can be referred to; therefore, description thereof is omitted here.
[0270]
In this embodiment, one of the source and drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gate of the transistor Tr1 and the gate of the transistor Tr2. However, the present embodiment is not limited to this configuration. In the pixel of the present invention, the transistor Tr4 is connected to another element or wiring so that the gate and drain of the transistor Tr1 can be connected in the writing period Ta and the gate and drain of the transistor Tr1 can be disconnected in the display period. It ’s fine. That is, Tr3, Tr4, and Tr5 may be connected as shown in FIG. 5A for Ta and as shown in FIG. 5B for Td.
[0271]
In the case of the light-emitting device of this example, two wirings included in each pixel can be omitted as compared with the light-emitting device described in Embodiment Mode 1. Further, as compared with the light-emitting device described in Embodiment 2, one pixel can be omitted. Therefore, the yield in the manufacturing process can be increased. In addition, since the aperture ratio can be increased, the screen can be brightened even with the same current consumption when light from the light-emitting element is emitted to the substrate side on which the wiring or the like is formed.
[0272]
Example 4
An example of a method for manufacturing a light-emitting device of the present invention will be described with reference to FIGS. In this example, a method for manufacturing a light-emitting device having the pixel shown in FIGS. Note that here, transistors Tr3 and Tr5 and a transistor of a driving portion provided around the pixel portion are typically shown. Note that the transistors Tr1, Tr2, and Tr4 are not particularly illustrated, but can be manufactured according to the manufacturing method of this embodiment. In addition to the light-emitting device shown in FIG. 3, the light-emitting device of the present invention can be manufactured by using the manufacturing method shown in this embodiment. In addition, regarding the drive unit, a TFT of a CMOS circuit which is a basic unit is illustrated.
[0273]
First, as shown in FIG. 13A, a silicon oxide film is formed on a substrate 5001 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass. A base film 5002 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. For example, SiH by plasma CVD method _Four , NH _Three , N ₂ A silicon oxynitride film 5002a made of O is formed to 10 to 200 nm (preferably 50 to 100 nm) and similarly SiH _Four , N ₂ A silicon oxynitride silicon nitride film 5002b formed from O is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm). Although the base film 5002 is shown as a two-layer structure in this embodiment, it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.
[0274]
The island-shaped semiconductor layers 5003 to 5006 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a known thermal crystallization method. The island-like semiconductor layers 5003 to 5006 are formed to a thickness of 25 to 80 nm (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy.
[0275]
When a crystalline semiconductor film is formed by laser crystallization, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO _Four Use a laser. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. Crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 400 mJ / cm. ² (Typically 200-300mJ / cm ² ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is set to 30 to 300 kHz, and the laser energy density is set to 300 to 600 mJ / cm. ² (Typically 350-500mJ / cm ² ) Then, laser light condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 50 to 90%.
[0276]
As the laser, a continuous wave or pulsed gas laser or solid-state laser can be used. There are excimer laser, Ar laser, Kr laser, etc. as gas laser, and YAG laser, YVO as solid laser. _Four Laser, YLF laser, YAlO _Three A laser, a glass laser, a ruby laser, an alexandride laser, a Ti: sapphire laser, and the like can be given. Solid lasers include YAG, YVO doped with Cr, Nd, Er, Ho, Ce, Co, Ti or Tm. _Four , YLF, YAlO _Three Lasers using crystals such as can also be used. The fundamental wave of the laser differs depending on the material to be doped, and a laser beam having a fundamental wave of about 1 μm can be obtained. The harmonic with respect to the fundamental wave can be obtained by using a nonlinear optical element.
[0277]
In crystallization of the amorphous semiconductor film, in order to obtain a crystal with a large grain size, it is preferable to apply a second to fourth harmonic of the fundamental wave using a solid-state laser capable of continuous oscillation. Typically, Nd: YVO _Four It is desirable to apply the second harmonic (532 nm) or the third harmonic (355 nm) of the laser (fundamental wave 1064 nm). Specifically, continuous output YVO with an output of 10 W _Four Laser light emitted from the laser is converted into a harmonic by a non-linear optical element. Also, YVO in the resonator _Four There is also a method of emitting harmonics by inserting a crystal and a nonlinear optical element. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the object to be processed. The energy density at this time is 0.01 to 100 MW / cm. ² Degree (preferably 0.1-10 MW / cm ² )is required. Then, irradiation is performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.
[0278]
Next, a gate insulating film 5007 is formed to cover the island-shaped semiconductor layers 5003 to 5006. The gate insulating film 5007 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 nm. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ And a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., a high frequency (13.56 MHz), and a power density of 0.5 to 0.8 W / cm. ² It can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.
[0279]
Then, a first conductive film 5008 and a second conductive film 5009 for forming a gate electrode (gate) are formed over the gate insulating film 5007. In this embodiment, the first conductive film 5008 is formed with Ta to a thickness of 50 to 100 nm, and the second conductive film 5009 is formed with W to a thickness of 100 to 300 nm.
[0280]
The Ta film is formed by sputtering, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used as a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for a gate electrode. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to that of the Ta α-phase is formed on a Ta base with a thickness of about 10 to 50 nm, so that an α-phase Ta film can be easily obtained. I can do it.
[0281]
When forming a W film, it is formed by sputtering using W as a target. In addition, tungsten hexafluoride (WF ₆ It can also be formed by a thermal CVD method using In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. Although the resistivity of the W film can be reduced by increasing the crystal grains, if the impurity element such as oxygen is large in W, the crystallization is hindered and the resistance is increased. Therefore, when sputtering is used, a W target having a purity of 99.9999 or 99.99% is used, and a W film is formed with sufficient consideration so that impurities are not mixed in the gas phase during film formation. Thus, a resistivity of 9 to 20 μΩcm can be realized.
[0282]
Note that in this embodiment, the first conductive film 5008 is Ta and the second conductive film 5009 is W, but there is no particular limitation, and any of them is selected from Ta, W, Ti, Mo, Al, Cu, and the like. Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polysilicon film doped with an impurity element such as phosphorus may be used. As another example of a combination other than the present embodiment, a combination in which the first conductive film 5008 is formed of tantalum nitride (TaN) and the second conductive film 5009 is W is used. Is made of tantalum nitride (TaN), the second conductive film 5009 is made of Al, the first conductive film 5008 is made of tantalum nitride (TaN), and the second conductive film 5009 is made of Cu. Can be mentioned.
[0283]
Next, a resist mask 5010 is formed, and a first etching process is performed to form electrodes and wirings. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, and CF is used as an etching gas. _Four And Cl ₂ And 500 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ When W is mixed, the W film and the Ta film are etched to the same extent.
[0284]
Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layers 5011 to 5016 (the first conductive layers 5011a to 5016a and the second conductive layers 5011b to 5016b) formed of the first conductive layer and the second conductive layer by the first etching treatment. Form. At this time, in the gate insulating film 5007, regions that are not covered with the first shape conductive layers 5011 to 5016 are etched and thinned by about 20 to 50 nm. (Fig. 13B)
[0285]
Then, an impurity element imparting N-type is added by performing a first doping process. As a doping method, an ion doping method or an ion implantation method may be used. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁴ atoms / cm ² The acceleration voltage is set to 60 to 100 keV. As an impurity element imparting N-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 5011 to 5014 serve as a mask for the impurity element imparting N-type, and the first impurity regions 5017 to 5025 are formed in a self-aligning manner. The first impurity regions 5017 to 5024 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three An impurity element imparting N-type is added in a concentration range of. (Fig. 13B)
[0286]
Next, as shown in FIG. 13C, a second etching process is performed without removing the resist mask. CF as etching gas _Four And Cl ₂ And O ₂ Then, the W film is selectively etched. At this time, second shape conductive layers 5026 to 5031 (first conductive layers 5026a to 5031a and second conductive layers 5026b to 5031b) are formed by the second etching process. At this time, in the gate insulating film 5007, regions that are not covered with the second shape conductive layers 5026 to 5031 are further etched and thinned by about 20 to 50 nm.
[0287]
CF of W film and Ta film _Four And Cl ₂ The etching reaction by the mixed gas can be estimated from the generated radical or ion species and the vapor pressure of the reaction product. Comparing the vapor pressure of fluoride and chloride of W and Ta, WF, which is fluoride of W ₆ Is extremely high, other WCl _Five , TaF _Five , TaCl _Five Are comparable. Therefore, CF _Four And Cl ₂ With this mixed gas, both the W film and the Ta film are etched. However, an appropriate amount of O is added to this mixed gas. ₂ When CF is added _Four And O ₂ Reacts to CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Further, since Ta is more easily oxidized than W, O ₂ When Ta is added, the surface of Ta is oxidized. Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.
[0288]
Then, a second doping process is performed as shown in FIG. In this case, the impurity amount imparting N-type is doped as a condition of a high acceleration voltage by lowering the dose than the first doping treatment. For example, the acceleration voltage is 70 to 120 keV and 1 × 10 ¹³ atoms / cm ² A new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. 13B. Doping is performed using the second shape conductive layers 5026 to 5029 as masks against the impurity elements so that the impurity elements are also added to the regions below the first conductive layers 5026a to 5029a. Thus, third impurity regions 5032 to 5035 are formed. The concentration of phosphorus (P) added to the third impurity regions 5032 to 5035 has a gradual concentration gradient according to the thickness of the tapered portion of the first conductive layers 5026a to 5029a. Note that, in the semiconductor layer overlapping the tapered portions of the first conductive layers 5026a to 5029a, although the impurity concentration slightly decreases inward from the end portions of the tapered portions of the first conductive layers 5026a to 5029a, it is almost The concentration is similar.
[0289]
A third etching process is performed as shown in FIG. CHF as etching gas ₆ And using a reactive ion etching method (RIE method). By the third etching treatment, the tapered portions of the first conductive layers 5026a to 5031a are partially etched, and a region where the first conductive layer overlaps with the semiconductor layer is reduced. Through the third etching treatment, third-shaped conductive layers 5037 to 5042 (first conductive layers 5037a to 5042a and second conductive layers 5037b to 5042b) are formed. At this time, in the gate insulating film 5007, a region that is not covered with the third shape conductive layers 5037 to 5042 is further etched and thinned by about 20 to 50 nm.
[0290]
By the third etching process, in the third impurity regions 5032 to 5035, the third impurity regions 5032a to 5035a overlapping with the first conductive layers 5037a to 5040a, the first impurity regions, and the third impurity regions Second impurity regions 5032b to 5035b are formed.
[0291]
Then, as shown in FIG. 14C, fourth impurity regions 5043 to 5054 having a conductivity type opposite to the first conductivity type are formed in the island-like semiconductor layers 5004 and 5006 forming the P-channel TFT. . Using the third shape conductive layers 5038b and 5040b as masks against the impurity element, impurity regions are formed in a self-aligning manner. At this time, the island-like semiconductor layers 5003 and 5005 and the wiring portions 5041 and 5042 forming the N-channel TFT are entirely covered with a resist mask 5200. Although the concentration of phosphorus added to the impurity regions 5043 to 5054 is not uniform, diborane (B ₂ H ₆ ), And the impurity concentration in each region is 2 × 10 ²⁰ ~ 2x10 ^{twenty one} atoms / cm ^Three To be.
[0292]
Through the above steps, impurity regions are formed in each island-like semiconductor layer. The third shape conductive layers 5037 to 5040 overlapping with the island-shaped semiconductor layers function as gate electrodes. Reference numeral 5042 functions as an island-shaped first scanning line. Reference numeral 5041 functions as a wiring connecting the island-shaped third scanning line and the third shape conductive layer 5040.
[0293]
After removing the resist mask 5200, a process of activating the impurity element added to each island-like semiconductor layer is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. The thermal annealing method is performed in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, at 400 to 700 ° C., typically 500 to 600 ° C. In this embodiment, the temperature is 500 ° C. for 4 hours. Heat treatment is performed. However, when the wiring material used for the third shape conductive layers 5037 to 5042 is weak against heat, activation is performed after an interlayer insulating film (mainly composed of silicon) is formed to protect the wiring and the like. Preferably it is done. When the laser annealing method is used, it is possible to use a laser used for crystallization. In the case of activation, the moving speed is the same as that of crystallization, and 0.01-100 MW / cm. ² Degree (preferably 0.01 to 10 MW / cm ² ) Energy density is required.
[0294]
Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0295]
Next, as shown in FIG. 15A, a first interlayer insulating film 5055 is formed with a thickness of 100 to 200 nm from a silicon oxynitride film. A second interlayer insulating film 5056 made of an organic insulating material is formed thereon, and then contact holes are formed in the first interlayer insulating film 5055, the second interlayer insulating film 5056, and the gate insulating film 5007. After the wirings 5057 to 5062 are formed by patterning, the pixel electrode 5064 in contact with the connection wiring 5062 is formed by patterning.
[0296]
As the second interlayer insulating film 5056, a film made of an organic resin is used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 5056 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. The thickness is preferably 1 to 5 μm (more preferably 2 to 4 μm).
[0297]
The contact holes are formed by dry etching or wet etching. The contact holes reach N-type impurity regions 5017, 5018, 5021, and 5022 or P-type impurity regions 5043, 5048, 5049, and 5054, and contact holes reach the wiring 5042. (Not shown), a contact hole (not shown) reaching the power supply line, and a contact hole (not shown) reaching the gate electrode are formed.
[0298]
In addition, as wirings (including connection wirings and signal lines) 5057 to 5062, a laminated film having a three-layer structure in which a Ti film is formed to 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film 150 nm is continuously formed by sputtering is formed in a desired shape. The one patterned is used. Of course, other conductive films may be used.
[0299]
In this example, an ITO film having a thickness of 110 nm was formed as the pixel electrode 5064 and patterned. A contact is made by arranging the pixel electrode 5064 so as to be in contact with and overlapping with the connection wiring 5062. Alternatively, a transparent conductive film in which 2 to 20% zinc oxide (ZnO) is mixed with indium oxide may be used. This pixel electrode 5064 becomes the anode of the light emitting element. (Fig. 15 (A))
[0300]
FIG. 17 shows a top view of the pixel at the time when the process up to the step of FIG. Note that the insulating film and the interlayer insulating film are omitted in order to clarify the position of the wiring and the position of the semiconductor layer. A cross-sectional view taken along the line AA ′ in FIG. 17 corresponds to the portion indicated by AA ′ in FIG. Further, the cross-sectional view taken along the line BB ′ in FIG. 17 corresponds to the part indicated by BB ′ in FIG. FIG. 16 is a cross-sectional view taken along the line CC ′ of FIG.
[0301]
The transistor Tr3 includes a semiconductor layer 5005 and a gate electrode 5039 connected to the first scan line Gj (5042). The impurity region 5021 (not shown in particular in FIG. 17) included in the semiconductor layer 5005 is connected to the signal line Si (5060), and the impurity region 5022 (not shown in FIG. 17 in particular) is connected to the wiring 5061. .
[0302]
The transistor Tr4 includes a semiconductor layer 5100 and a gate electrode 5101. One of two impurity regions (not particularly shown in FIG. 17) included in the semiconductor layer 5100 is connected to the wiring 5102, and the other is connected to the signal line Si 5060. The gate electrode 5101 is connected to the wiring 5107, and the wiring 5107 is connected to the second scanning line Pj.
[0303]
The transistor Tr1 includes a semiconductor layer 5103 and a gate electrode 5104. One of two impurity regions (not particularly shown in FIG. 17) included in the semiconductor layer 5103 is connected to the power supply line Vi (5110), and the other is connected to the wiring 5061. The gate electrode 5104 is connected to the capacitor electrode 5109.
[0304]
The transistor Tr2 includes a semiconductor layer 5105 and a gate electrode 5106. One of two impurity regions (not particularly shown in FIG. 17) included in the semiconductor layer 5105 is connected to the power supply line Vi (5110), and the other is connected to the wiring 5062. The gate electrode 5106 is connected to the capacitor electrode 5109.
[0305]
The transistor Tr5 includes a semiconductor layer 5006 and a gate electrode 5040. One of two impurity regions (not particularly shown in FIG. 17) included in the semiconductor layer 5006 is connected to the wiring 5061 and the other is connected to the wiring 5062. The gate electrode 5040 is connected to the third scanning line Rj through the wiring 5041.
[0306]
The wiring 5062 is connected to the pixel electrode 5064.
[0307]
Reference numeral 5108 denotes a capacitor semiconductor layer formed by adding an impurity to the semiconductor layer, and overlaps the capacitor electrode 5109 with a gate insulating film 5007 (not particularly shown in FIG. 17) interposed therebetween. The capacitor electrode 5109 overlaps the power supply line Vi (5110) with the first interlayer insulating film 5055 and the second interlayer insulating film 5056 interposed therebetween. The power supply line Vi (5110) is connected to the impurity region 5111 included in the capacitor semiconductor layer 5108 and the contact hole formed in the gate insulating film 5007, the first interlayer insulating film 5055, and the second interlayer insulating film 5056. Connected.
[0308]
Next, as shown in FIG. 15B, an insulating film containing silicon (silicon oxide film in this embodiment) is formed to a thickness of 500 nm, and an opening is formed at a position corresponding to the pixel electrode 5064. A third interlayer insulating film 5065 functioning as a bank is formed. When the opening is formed, a tapered sidewall can be easily formed by using a wet etching method. If the side wall of the opening is not sufficiently gentle, the deterioration of the organic light emitting layer due to the step becomes a significant problem, so care must be taken.
[0309]
Next, the organic light emitting layer 5066 and the cathode (MgAg electrode) 5067 are continuously formed by using a vacuum evaporation method without releasing to the atmosphere. Note that the thickness of the organic light emitting layer 5066 may be 80 to 200 nm (typically 100 to 120 nm), and the thickness of the cathode 5067 may be 180 to 300 nm (typically 200 to 250 nm).
[0310]
In this step, the organic light emitting layer is sequentially formed on the pixel corresponding to red, the pixel corresponding to green, and the pixel corresponding to blue. However, since the organic light emitting layer has poor resistance to a solution, it must be formed for each color individually without using a photolithography technique. Therefore, it is preferable to use a metal mask to hide other than the desired pixels and to selectively form the organic light emitting layer only at necessary portions.
[0311]
That is, first, a mask that hides all pixels other than those corresponding to red is set, and an organic light emitting layer that emits red light is selectively formed using the mask. Next, a mask that hides all but the pixels corresponding to green is set, and an organic light emitting layer that emits green light is selectively formed using the mask. Next, similarly, a mask for hiding all but the pixels corresponding to blue is set, and a blue light emitting organic light emitting layer is selectively formed using the mask. Note that although all the different masks are described here, the same mask may be used.
[0312]
Here, a method of forming three types of light emitting elements corresponding to RGB was used, but a method of combining a white light emitting element and a color filter, a blue or blue green light emitting element and a phosphor (fluorescent color conversion). Layer: CCM), a method of using a transparent electrode as a cathode (counter electrode), and a method of superimposing light emitting elements corresponding to RGB may be used.
[0313]
A known material can be used for the organic light emitting layer 5066. As the known material, it is preferable to use an organic material in consideration of the driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the organic light emitting layer.
[0314]
Next, a cathode 5067 is formed using a metal mask. In this embodiment, MgAg is used as the cathode 5067, but the present invention is not limited to this. Other known materials may be used for the cathode 5067.
[0315]
Finally, a passivation film 5068 made of a silicon nitride film is formed to a thickness of 300 nm. By forming the passivation film 5068, the organic light emitting layer 5066 can be protected from moisture and the like, and the reliability of the light emitting element can be further improved.
[0316]
Thus, a light emitting device having a structure as shown in FIG. 15B is completed.
[0317]
By the way, the light emitting device of this embodiment can exhibit extremely high reliability and improve operating characteristics by arranging TFTs having an optimum structure not only in the pixel portion but also in the drive circuit portion. In addition, it is possible to increase the crystallinity by adding a metal catalyst such as Ni in the crystallization step. Accordingly, the driving frequency of the signal line driver circuit can be 10 MHz or more.
[0318]
First, a TFT having a structure that reduces hot carrier injection so as not to decrease the operating speed as much as possible is used as an N-channel TFT of a CMOS circuit that forms a drive circuit portion. Note that the driving circuit here includes a shift register, a buffer, a level shifter, a latch in line sequential driving, a transmission gate in dot sequential driving, and the like.
[0319]
In this embodiment, the active layer of the N-channel TFT has an overlap LDD region (L) that overlaps the gate electrode with the source region (source), drain region (drain), and gate insulating film interposed therebetween. _OV Region), an offset LDD region (L _OFF Region) and a channel formation region.
[0320]
In addition, since the P-channel TFT of the CMOS circuit is hardly concerned about deterioration due to hot carrier injection, it is not particularly necessary to provide an LDD region. Of course, it is also possible to provide an LDD region as in the case of the N-channel TFT and take measures against hot carriers.
[0321]
In addition, when the driving circuit uses a CMOS circuit in which a current flows bidirectionally in the channel formation region, that is, a CMOS circuit in which the roles of the source region and the drain region are switched, an N-channel TFT that forms the CMOS circuit In this case, it is preferable to form the LDD region in such a manner that the channel formation region is sandwiched between both sides of the channel formation region. An example of this is a transmission gate used for dot sequential driving. In the case where a CMOS circuit that needs to keep off current as low as possible is used in the driver circuit, the N-channel TFT forming the CMOS circuit is L _OV It is preferable to have a region. As such an example, there is a transmission gate used for dot sequential driving.
[0322]
In addition, when the state shown in FIG. 15B is actually completed, a protective film (laminate film, ultraviolet curable resin film, etc.) or a light-transmitting material having high hermeticity and less degassing so as not to be exposed to the outside air. It is preferable to package (enclose) with a sealing material. At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the light emitting element is improved.
[0323]
In addition, when the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting the terminal drawn from the element or circuit formed on the substrate and the external signal terminal is attached. Completed as a product. In this specification, such a state that can be shipped is referred to as a light emitting device.
[0324]
Further, according to the steps shown in this embodiment, the number of photomasks necessary for manufacturing a light-emitting device can be suppressed. As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.
[0325]
The manufacturing method of the light-emitting device of the present invention is not limited to the manufacturing method described in this embodiment. The light emitting device of the present invention can be manufactured using a known method.
[0326]
This embodiment can be implemented by freely combining with the first to third embodiments.
[0327]
(Example 5)
In this embodiment, a structure of a driver circuit (a signal line driver circuit and a scan line driver circuit) included in the light-emitting device of the present invention driven by an analog driving method will be described.
[0328]
FIG. 18A shows a block diagram of the signal line driver circuit 401 of this embodiment. Reference numeral 402 denotes a shift register, 403 denotes a buffer, 404 denotes a sampling circuit, and 405 denotes a current conversion circuit.
[0329]
A clock signal (CLK) and a start pulse signal (SP) are input to the shift register 402. When a clock signal (CLK) and a start pulse signal (SP) are input to the shift register 402, a timing signal is generated.
[0330]
The generated timing signal is amplified or buffer amplified in the buffer 403 and input to the sampling circuit 404. Note that a level shifter may be provided instead of the buffer to amplify the timing signal. Further, both a buffer and a level shifter may be provided.
[0331]
FIG. 18B shows specific structures of the sampling circuit 404 and the current conversion circuit 405. Note that the sampling circuit 404 is connected to the buffer 403 at a terminal 410.
[0332]
The sampling circuit 404 is provided with a plurality of switches 411. An analog video signal is input to the sampling circuit 404 from the video signal line 406, and the switch 411 samples the analog video signal in synchronization with the timing signal and inputs the analog video signal to the subsequent current conversion circuit 405. Note that in FIG. 18B, only the current conversion circuit connected to one of the switches 411 included in the sampling circuit 404 is shown as the current conversion circuit 405. However, in FIG. It is assumed that the current conversion circuit 405 as shown in FIG.
[0333]
In this embodiment, only one transistor is used for the switch 411. However, the switch 411 may be any switch that can sample an analog video signal in synchronization with the timing signal, and is not limited to the configuration of this embodiment.
[0334]
The sampled analog video signal is input to a current output circuit 412 included in the current conversion circuit 405. The current output circuit 412 outputs a current (signal current) having a value corresponding to the voltage of the input video signal. In FIG. 18, a current output circuit is formed by using an amplifier and a transistor. However, the present invention is not limited to this configuration, and a circuit that can output a current having a value corresponding to the voltage of an input signal. I just need it.
[0335]
The signal current is input to a reset circuit 417 included in the current conversion circuit 405. The reset circuit 417 includes two analog switches 413 and 414, an inverter 416, and a power source 415.
[0336]
A reset signal (Res) is input to the analog switch 414, and a reset signal (Res) inverted by the inverter 416 is input to the analog switch 413. The analog switch 413 and the analog switch 414 operate in synchronization with the inverted reset signal and the reset signal, respectively, and when one is on, one is off.
[0337]
When the analog switch 413 is on, the signal current is input to the corresponding signal line. Conversely, when the analog switch 414 is on, the voltage of the power source 415 is applied to the signal line, and the signal line is reset. Note that the voltage of the power supply 415 is preferably substantially the same as the voltage of the power supply line provided in the pixel, and the closer the current that can flow to the signal line when the signal line is reset, the better. .
[0338]
Note that the signal line is desirably reset during the return period. However, if it is outside the period during which the image is displayed, it can be reset to a period other than the blanking period as necessary.
[0339]
Instead of the shift register, another circuit capable of selecting a signal line such as a decoder circuit may be used.
[0340]
Next, the configuration of the scanning line driving circuit will be described.
[0341]
FIG. 19 is a block diagram showing a configuration of the scanning line driving circuit 641. The scanning line driver circuit 641 includes a shift register 642 and a buffer 643, respectively. In some cases, a level shifter may be provided.
[0342]
In the scan line driver circuit 641, when the clock CLK and the start pulse signal SP are input to the shift register 642, a timing signal is generated. The generated timing signal is buffered and amplified in the buffer 643 and supplied to the corresponding scanning line.
[0343]
The gate of the transistor of the pixel for one line is connected to the scanning line. Since the transistors of the pixels for one line must be turned on all at once, a buffer 643 that can flow a large current is used.
[0344]
Instead of the shift register, another circuit that can select a scanning line such as a decoder circuit may be used.
[0345]
Note that the voltages of the first to third scanning lines may be controlled by a plurality of scanning line driving circuits respectively corresponding to the scanning lines, or the voltages of several scanning lines or all of the scanning lines may be set to 1. You may control by one scanning line drive circuit.
[0346]
The signal line driver circuit and the scan line driver circuit for driving the light-emitting device of the present invention are not limited to the structures shown in this embodiment. The configuration of the present embodiment can be implemented by freely combining the configurations shown in Embodiments 1 to 4.
[0347]
(Example 6)
In this embodiment, a structure of a signal line driver circuit included in a light emitting device driven by the digital driving method of the present invention will be described. Note that the structure shown in Embodiment 5 can be used as the structure of the scanning line driver circuit, and thus the description thereof is omitted here.
[0348]
FIG. 20 is a block diagram illustrating the configuration of the signal line driver circuit 601. Reference numeral 602 denotes a shift register, reference numeral 603 denotes a storage circuit A, reference numeral 604 denotes a storage circuit B, and reference numeral 605 denotes a constant current circuit.
[0349]
A clock signal CLK and a start pulse signal SP are input to the shift register 602. A digital video signal (Digital Video Signals) is input to the memory circuit A 603, and a latch signal (Latch Signals) is input to the memory circuit B 604. A signal current Ic corresponding to the video signal output from the constant current circuit 605 is input to the signal line.
[0350]
FIG. 21 shows a more detailed configuration of the signal line driver circuit 601.
[0351]
When the clock signal CLK and the start pulse signal SP are input to the shift register 602 from a predetermined wiring, a timing signal is generated. The timing signal is input to each of the plurality of latches A (LATA_1 to LATA_x) included in the memory circuit A603. Note that at this time, the timing signal generated in the shift register 602 may be buffered and amplified by a buffer or the like and then input to the plurality of latches A (LATA_1 to LATA_x) included in the memory circuit A603.
[0352]
When a timing signal is input to the memory circuit A 603, a 1-bit digital video signal input to the video signal line 610 is sequentially input to each of the plurality of latches A (LATA — 1 to LATA_x) in synchronization with the timing signal. Written and retained.
[0353]
In this embodiment, when a digital video signal is taken into the memory circuit A603, the digital video signal is sequentially input to the plurality of latches A (LATA_1 to LATA_x) included in the memory circuit A603. It is not limited to. A plurality of stages of latches included in the memory circuit A 603 may be divided into several groups, and so-called divided driving may be performed in which digital video signals are input simultaneously in parallel for each group. Note that the number of groups at this time is called the number of divisions. For example, when the latches are divided into groups for every four stages, it is said that the driving is divided into four.
[0354]
The time until the digital video signal is completely written to the latches of all the stages of the memory circuit A 603 is called a line period. Actually, the line period may include a period in which a horizontal blanking period is added to the line period.
[0355]
When one line period ends, a latch signal (Latch Signal) is supplied to the plurality of latches B (LATB_1 to LATB_x) included in the memory circuit B604 through the latch signal line 609. At this moment, the digital video signals held in the plurality of latches A (LATA_1 to LATA_x) included in the memory circuit A603 are simultaneously written and held in the plurality of latches B (LATB_1 to LATB_x) included in the memory circuit B604. .
[0356]
After the digital video signal has been sent to the storage circuit B 604, the next 1-bit digital video signal is sequentially written on the basis of the timing signal from the shift register 602.
[0357]
During the second line period, the digital video signal written and held in the memory circuit B 604 is input to the constant current circuit 605.
[0358]
The constant current circuit 605 has a plurality of current setting circuits (C1 to Cx). When a digital video signal is input to each of the current setting circuits (C1 to Cx), the signal current Ic flows through the signal line or the power supply line V1 through the signal line depending on 1 or 0 information included in the digital video signal. The voltage of ~ Vx is given or any one is selected.
[0359]
FIG. 22 shows an example of a specific configuration of the current setting circuit C1. The current setting circuits C2 to Cx have the same configuration.
[0360]
The current setting circuit C1 includes a constant current source 631, four transmission gates SW1 to SW4, and two inverters Inb1 and Inb2. Note that the polarity of the transistor 650 included in the constant current source 631 is the same as the polarity of the transistors Tr1 and Tr2 included in the pixel.
[0361]
Switching of SW1 to SW4 is controlled by a digital video signal output from LATB_1 included in the memory circuit B604. The digital video signal input to SW1 and SW3 and the digital video signal input to SW2 and SW4 are inverted by Inb1 and Inb2. Therefore, SW2 and SW4 are off when SW1 and SW3 are on, and SW2 and SW4 are on when SW1 and SW3 are off.
[0362]
When SW1 and SW3 are ON, a current Id having a predetermined value other than 0 is input from the constant current source 631 to the signal line S1 as the signal current Ic via SW1 and SW3.
[0363]
Conversely, when SW2 and SW4 are on, the current Id from the constant current source 631 is grounded through SW2. Further, the power supply voltages of the power supply lines V1 to Vx are supplied to the signal line S1 through SW4, and Ic≈0.
[0364]
Referring to FIG. 21 again, the above operation is simultaneously performed in all the current setting circuits (C1 to Cx) included in constant current circuit 605 within one line period. Therefore, the value of the signal current Ic input to all the signal lines is selected by the digital video signal.
[0365]
The drive circuit used in the present invention is not limited to the configuration shown in this embodiment. Furthermore, the constant current circuit shown in this embodiment is not limited to the configuration shown in FIG. The constant current circuit used in the present invention can select any one of the binary values that can be taken by the signal current Ic by a digital video signal, and can cause any signal current having the selected value to flow through the signal line. You may have a structure.
[0366]
Instead of the shift register, another circuit capable of selecting a signal line such as a decoder circuit may be used.
[0367]
The structure of a present Example can be implemented in combination freely with Examples 1-4.
[0368]
(Example 7)
In the present invention, by using an organic light emitting material that can utilize phosphorescence from triplet excitons for light emission, the external light emission quantum efficiency can be dramatically improved. This makes it possible to reduce the power consumption, extend the life, and reduce the weight of the light emitting element.
[0369]
Here, a report of using triplet excitons to improve the external emission quantum efficiency is shown.
(T. Tsutsui, C. Adachi, S. Saito, Photochemical Processes in Organized Molecular Systems, ed. K. Honda, (Elsevier Sci. Pub., Tokyo, 1991) p.437.)
[0370]
The molecular formula of the organic light-emitting material (coumarin dye) reported by the above paper is shown below.
[0371]
[Chemical 1]

[0372]
(MABaldo, DFO'Brien, Y.You, A.Shoustikov, S.Sibley, METhompson, SRForrest, Nature 395 (1998) p.151.)
[0373]
The molecular formula of the organic light-emitting material (Pt complex) reported by the above paper is shown below.
[0374]
[Chemical 2]

[0375]
(MABaldo, S. Lamansky, PEBurrrows, METhompson, SRForrest, Appl.Phys.Lett., 75 (1999) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)
[0376]
The molecular formula of the organic light-emitting material (Ir complex) reported by the above paper is shown below.
[0377]
[Chemical 3]

[0378]
As described above, if phosphorescence emission from triplet excitons can be used, in principle, it is possible to realize an external emission quantum efficiency that is 3 to 4 times higher than that in the case of using fluorescence emission from singlet excitons.
[0379]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Example 1- Example 6. FIG.
[0380]
(Example 8)
In this example, an example in which a light-emitting device is manufactured using the present invention will be described with reference to FIGS.
[0381]
23 is a top view of a light-emitting device formed by sealing an element substrate over which a transistor is formed with a sealing material, and FIG. 23B is a cross-sectional view taken along line AA ′ in FIG. FIG. 23C is a cross-sectional view taken along the line BB ′ of FIG.
[0382]
A sealant 4009 is provided so as to surround the pixel portion 4002 provided over the substrate 4001, the signal line driver circuit 4003, and the first and second scan line driver circuits 4004a and 4004b. In addition, a sealing material 4008 is provided over the pixel portion 4002, the signal line driver circuit 4003, and the first and second scan line driver circuits 4004a and 4004b. Therefore, the pixel portion 4002, the signal line driver circuit 4003, and the first and second scan line driver circuits 4004 a and 400 b are sealed with the filler 4210 by the substrate 4001, the sealant 4009, and the sealant 4008. .
[0383]
The pixel portion 4002, the signal line driver circuit 4003, and the first and second scan line driver circuits 4004a and 4004b provided over the substrate 4001 include a plurality of TFTs. In FIG. 23B, typically, a driving TFT (here, an n-channel TFT and a p-channel TFT are illustrated) 4201 included in the signal line driver circuit 4003 formed over the base film 4010 and a pixel The transistor Tr5 4202 included in the portion 4002 is illustrated.
[0384]
In this embodiment, a p-channel TFT or an n-channel TFT manufactured by a known method is used for the driving TFT 4201, and a p-channel TFT manufactured by a known method is used for the transistor Tr5 4202.
[0385]
An interlayer insulating film (planarization film) 4301 is formed over the driving TFT 4201 and the transistor Tr5 4202, and a pixel electrode (anode) 4203 electrically connected to the drain of the transistor Tr5 4202 is formed thereon. As the pixel electrode 4203, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.
[0386]
An insulating film 4302 is formed over the pixel electrode 4203, and an opening is formed over the pixel electrode 4203 in the insulating film 4302. In this opening, an organic light emitting layer 4204 is formed on the pixel electrode 4203. A known organic light emitting material or inorganic light emitting material can be used for the organic light emitting layer 4204. The organic light emitting material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.
[0387]
As a method for forming the organic light emitting layer 4204, a known vapor deposition technique or coating technique may be used. The structure of the organic light emitting layer may be a laminated structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0388]
On the organic light emitting layer 4204, a cathode 4205 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper or silver as a main component or a laminated film of these with another conductive film) is formed. The In addition, it is desirable to remove moisture and oxygen present at the interface between the cathode 4205 and the organic light emitting layer 4204 as much as possible. Therefore, it is necessary to devise a method in which the organic light emitting layer 4204 is formed in a nitrogen or rare gas atmosphere and the cathode 4205 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus. The cathode 4205 is given a predetermined voltage.
[0389]
As described above, the light emitting element 4303 including the pixel electrode (anode) 4203, the organic light emitting layer 4204, and the cathode 4205 is formed. A protective film 4209 is formed over the insulating film 4302 so as to cover the light emitting element 4303. The protective film 4209 is effective in preventing oxygen, moisture, and the like from entering the light emitting element 4303.
[0390]
Reference numeral 4005a denotes a lead wiring connected to the power supply line, which is electrically connected to the source of the transistor Tr5 4202. The lead wiring 4005 a passes between the sealant 4009 and the substrate 4001 and is electrically connected to the FPC wiring 4301 included in the FPC 4006 through the anisotropic conductive film 4300.
[0390]
As the sealing material 4008, a glass material, a metal material (typically a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. As the plastic material, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.
[0392]
However, when the light emission direction from the light emitting element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.
[0393]
As the filler 4210, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.
[0394]
In order to expose the filler 4210 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, a recess 4007 is provided on the surface of the sealing material 4008 on the substrate 4001 side to adsorb the hygroscopic substance or oxygen. A possible substance 4207 is arranged. In order to prevent the hygroscopic substance or the substance 4207 capable of adsorbing oxygen from scattering, the concave part cover material 4208 holds the hygroscopic substance or the substance 4207 capable of adsorbing oxygen in the concave part 4007. Note that the concave cover material 4208 has a fine mesh shape, and is configured to allow air and moisture to pass therethrough but not a hygroscopic substance or a substance 4207 capable of adsorbing oxygen. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the light-emitting element 4303 can be suppressed.
[0395]
As shown in FIG. 23C, the conductive film 4203a is formed so as to be in contact with the lead wiring 4005a at the same time as the pixel electrode 4203 is formed.
[0396]
The anisotropic conductive film 4300 has a conductive filler 4300a. By thermally pressing the substrate 4001 and the FPC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.
[0397]
The configuration of the present embodiment can be implemented by freely combining the configurations shown in Embodiments 1 to 7.
[0398]
Example 9
Organic light-emitting materials used for light-emitting elements are broadly classified into low molecular weight and high molecular weight materials. The light emitting device of the present invention can be used with either a low molecular weight organic light emitting material or a high molecular weight organic light emitting material.
[0399]
The low molecular weight organic light emitting material is formed by a vapor deposition method. Therefore, it is easy to take a laminated structure, and it is easy to increase the efficiency by laminating films having different functions such as a hole transport layer and an electron transport layer.
[0400]
Low molecular weight organic light-emitting materials include aluminum complex Alq with quinolinol as a ligand. _Three And triphenylamine derivative (TPD).
[0401]
On the other hand, a high molecular organic light emitting material has higher physical strength and higher device durability than a low molecular material. In addition, since the film can be formed by coating, the device can be manufactured relatively easily.
[0402]
The structure of a light emitting element using a high molecular weight organic light emitting material is basically the same as that when a low molecular weight organic light emitting material is used, and is a cathode / organic light emitting layer / anode. However, when forming an organic light emitting layer using a high molecular weight organic light emitting material, it is difficult to form a laminated structure as in the case of using a low molecular weight organic light emitting material. The two-layer structure is famous. Specifically, the structure is cathode / light-emitting layer / hole transport layer / anode. In the case of a light emitting element using a polymer organic light emitting material, Ca can also be used as a cathode material.
[0403]
Note that since the color of light emitted from the element is determined by the material for forming the light-emitting layer, a light-emitting element exhibiting desired light emission can be formed by selecting them. Typical examples of the polymer organic light emitting material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.
[0404]
The polyparaphenylene vinylene system includes derivatives of poly (paraphenylene vinylene) [PPV], poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like.
[0405]
The polyparaphenylene series includes derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like.
[0406]
The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOPT] and the like.
[0407]
Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.
[0408]
Note that when a hole-transporting polymer organic light-emitting material is sandwiched between the anode and the light-emitting polymer organic light-emitting material, hole injection from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material.
[0409]
Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. It is done.
[0410]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Example 1- Example 8. FIG.
[0411]
(Example 10)
Since a light-emitting device using a light-emitting element is a self-luminous type, it has excellent visibility in a bright place and a wide viewing angle compared to a liquid crystal display. Therefore, it can be used for display portions of various electronic devices.
[0412]
As an electronic device using the light emitting device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device, Play back a recording medium such as a portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.) or recording medium (specifically, Digital Versatile Disc (DVD)) A device having a display capable of displaying). In particular, it is desirable to use a light-emitting device for a portable information terminal that often has an opportunity to see a screen from an oblique direction because the wide viewing angle is important. Specific examples of these electronic devices are shown in FIGS.
[0413]
FIG. 24A illustrates a light-emitting element display device including a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The light emitting device of the present invention can be used for the display portion 2003. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. The light emitting element display device includes all information display devices such as a personal computer, a TV broadcast receiver, and an advertisement display.
[0414]
FIG. 24B shows a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The light emitting device of the present invention can be used for the display portion 2102.
[0415]
FIG. 24C shows a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The light-emitting device of the present invention can be used for the display portion 2203.
[0416]
FIG. 24D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The light emitting device of the present invention can be used for the display portion 2302.
[0417]
FIG. 24E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the light-emitting device of the present invention can be used for the display portions A, B 2403, and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0418]
FIG. 24F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The light emitting device of the present invention can be used for the display portion 2502.
[0419]
FIG. 24G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control reception portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and an eyepiece. Part 2610 and the like. The light-emitting device of the present invention can be used for the display portion 2602.
[0420]
Here, FIG. 24H shows a cellular phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The light emitting device of the present invention can be used for the display portion 2703. Note that the display portion 2703 can suppress current consumption of the mobile phone by displaying white characters on a black background.
[0421]
If the light emission luminance of the organic light emitting material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used in a front type or rear type projector.
[0422]
In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the organic light emitting material has a very high response speed, the light emitting device is preferable for displaying moving images.
[0423]
In addition, since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background It is desirable to do.
[0424]
As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic device of this embodiment may use the light emitting device having any configuration shown in Embodiments 1 to 9.
[0425]
(Example 11)
In this embodiment, a structure of the pixel 101 included in the light-emitting device illustrated in FIG. 2 is described.
[0426]
FIG. 28 shows a detailed configuration of the pixel 101 shown in FIG. 28 includes a signal line Si (one of S1 to Sx), a first scanning line Gj (one of G1 to Gy), and a second scanning line Pj (P1 to Py). 1), a third scanning line Rj (one of R1 to Ry) and a power supply line Vi (one of V1 to Vx).
[0427]
The pixel 101 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a transistor Tr5, a transistor Tr6, a light emitting element 701, and a storage capacitor 702. The storage capacitor 702 is provided to more reliably hold the voltage (gate voltage) between the gates and the sources of the transistors Tr1 and Tr2, but it is not always necessary to provide the storage capacitor 702.
[0428]
The gate of the transistor Tr3 is connected to the first scanning line Gj. One of the source and the drain of the transistor Tr3 is connected to the signal line Si, and the other is connected to the drain of the transistor Tr1.
[0429]
The gate of the transistor Tr4 is connected to the second scanning line Pj. One of the source and the drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gates of the transistors Tr1 and Tr2.
[0430]
The gate of the transistor Tr6 is connected to the gates of the transistors Tr1 and Tr2. One of the source and drain of the transistor Tr6 is connected to the drain of the transistor Tr1, and the other is connected to the source or drain of the transistor Tr5.
[0431]
The gate of the transistor Tr5 is connected to the third scanning line Rj. One of the source and drain of the transistor Tr5 is connected to the drain of the transistor Tr2, and the other is connected to the source or drain of the transistor Tr6.
[0432]
The gates of the transistors Tr1, Tr2 and Tr6 are connected to each other. The sources of the transistors Tr1 and Tr2 are both connected to the power supply line Vi. The drain of the transistor Tr2 is connected to the pixel electrode of the light emitting element 701.
[0433]
One of the two electrodes of the storage capacitor 702 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the power supply line Vi.
[0434]
The voltage (power supply voltage) of the power supply line Vi is kept at a constant height. The voltage of the counter electrode is also maintained at a constant height.
[0435]
Note that the transistors Tr1, Tr2, and Tr6 may be either n-channel transistors or p-channel transistors. However, the transistors Tr1, Tr2, and Tr6 have the same polarity. Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors.
[0436]
The transistors Tr3, Tr4, and Tr5 may be either n-channel transistors or p-channel transistors.
[0437]
Next, the operation of the light emitting device of this example will be described. The operation of the light-emitting device having the pixel shown in FIG. 28 can be described by being divided into the writing period Ta and the display period Td, as in the case of the pixel shown in FIG.
[0438]
For the voltage applied to the first to third scan lines, the timing chart shown in FIG. 4 can be referred to. FIG. 29 is a diagram simply showing the connection between the transistor Tr1 and the transistor Tr2 in the writing period Ta and the display period Td of the pixel shown in FIG.
[0439]
When the writing period Ta is started, the first scanning line G and the second scanning line P are selected. Accordingly, the transistor Tr3 and the transistor Tr4 are turned on. Since the third scanning line R is not selected, the transistor Tr5 is turned off.
[0440]
A signal current Ic corresponding to the video signal flows between the signal lines S1 to Sx and the power supply lines V1 to Vx based on the video signal input to the signal line driver circuit 102.
[0441]
FIG. 29A is a schematic diagram of the pixel 101 when the signal current Ic corresponding to the video signal flows through the signal line Si in the writing period Ta. Reference numeral 706 denotes a terminal for connection to a power source for applying a voltage to the counter electrode. Reference numeral 707 denotes a constant current source included in the signal line driver circuit 102.
[0442]
Since the transistor Tr3 is in the on state, when the signal current Ic corresponding to the video signal flows through the signal line Si, the signal current Ic flows between the drain and the source of the transistor Tr1. At this time, the transistor Tr1 operates in the saturation region because the gate and the drain are connected, and Equation 1 is satisfied. Therefore, the gate voltage V of the transistor Tr1 _GS Is determined by the current value Ic.
[0443]
The gate of the transistor Tr2 is connected to the gate of the transistor Tr1. The source of the transistor Tr2 is connected to the source of the transistor Tr1. Therefore, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2 as it is. Therefore, the drain current of the transistor Tr2 is proportional to the drain current of the transistor Tr1. In particular, μC ₀ W / L and V _TH Are equal to each other, the drain currents of the transistors Tr1 and Tr2 are equal to each other, and I ₂ = Ic.
[0444]
Then, the drain current I of the transistor Tr2 ₂ Flows to the light emitting element 704. The current flowing through the light emitting element has a magnitude corresponding to the signal current Ic determined by the constant current source 707, and the light emitting element 704 emits light with a luminance corresponding to the magnitude of the flowing current. The light emitting element 704 does not emit light when the current flowing through the light emitting element is as close as possible to zero or when the current flowing through the light emitting element flows in the reverse bias direction.
[0445]
When the writing period Ta ends, the selection of the first scanning line G and the second scanning line P ends. At this time, it is preferable that the selection of the second scanning line P is completed before the first scanning line G. This is because if the transistor Tr3 is turned off first, the charge in the storage capacitor 705 leaks through the Tr4.
[0446]
When the writing period Ta ends, the display period Td starts next. When the display period Td is started, the third scanning line R is selected and the transistor Tr5 is turned on. Since the first scanning line G and the second scanning line P are not selected, the transistors Tr3 and Tr4 are turned off.
[0447]
FIG. 29B shows a schematic diagram of a pixel in the display period Td. The transistors Tr3 and Tr4 are in an off state. The sources of the transistors Tr1 and Tr2 are connected to the power supply line Vi, and a constant voltage (power supply voltage) is applied.
[0448]
On the other hand, in the transistors Tr1 and Tr2, V V determined in the writing period Ta _GS Is held as it is. Further, the gate of the transistor Tr6 is connected to the gates of the transistors Tr1 and Tr2. Therefore, the drain current of the transistor Tr1 and the drain current of the transistor Tr6 are kept the same. From Equation 1, the drain current of the transistor Tr1 depends on the channel length and channel width of the transistor Tr6.
[0449]
Assuming that the gate voltage, mobility, gate capacitance per unit area, threshold value, and channel width of the transistors Tr1 and Tr6 are equal, the following equation 2 is derived from the equation 1. In Equation 2, the channel length of the transistor Tr1 is L1, the channel length of Tr6 is L6, and the drain currents of Tr1 and Tr6 are I _Three And
[0450]
[Formula 2]
I _Three = I ₁ × L1 / (L1 + L6)
[0451]
On the other hand, the drain current I of the transistor Tr2 ₂ The value of is maintained at a magnitude corresponding to the signal current Ic.
[0452]
Since the transistor Tr5 is on, the drain current I of the transistors Tr1 and Tr6 _Three And the drain current I of the transistor Tr2 ₂ Both flow to the light emitting element 704. Therefore, drain current I _Three And drain current I ₂ The light emitting element 704 emits light with a luminance corresponding to the magnitude of the combined current.
[0453]
Note that since the light-emitting element 704 emits light with luminance corresponding to the magnitude of current flowing through the light-emitting element, the gradation of each pixel is determined by the magnitude of current flowing through the light-emitting element in the display period Td. Even during the writing period Ta, the drain current I ₁ It emits light with a luminance corresponding to the size of the light, but its influence on the gradation is considered to be negligibly small in an actual panel. This is because, for example, in the case of VGA, pixels of 480 lines are provided in the pixel portion, and the writing period Ta of the pixels of one line is very small, about 1/480 of one frame period. Of course, the magnitude of the signal current Ic may be corrected in consideration of the influence of the current flowing through the light emitting element in the writing period Ta on the gradation.
[0454]
In the pixel of the present invention, the current flowing through the light emitting element during the display period is the drain current I. ₂ And drain current I _Three Is the sum of Therefore, the current flowing through the light emitting element is the drain current I ₂ Not only depend on. For this reason, the characteristics of the transistor Tr1 and the transistor Tr2 are shifted, and the drain current I of the transistor Tr2 ₂ Even if the ratio of the signal current Ic differs between the pixels, the value of the current flowing through the light emitting element can be prevented from shifting between the pixels, and variations in luminance can be prevented from being visually recognized.
[0455]
In the pixel of the present invention, the drain current of the transistor Tr1 does not flow to the light emitting element during the writing period Ta. Therefore, the time from when the gate voltage starts to change due to the current supplied to the pixel by the signal line driver circuit and the drain current of the transistor Tr1 flowing does not depend on the capacitance of the light emitting element. Therefore, compared with the conventional pixel, the voltage converted from the supplied current is stabilized quickly, so that the time for writing the current can be shortened and the afterimage can be prevented from being visually recognized in the moving image display. .
[0456]
Further, as in the prior art, it also has the advantages of a current input type light emitting device. In other words, even when the TFT characteristics vary from pixel to pixel, it is possible to prevent variations in luminance of the light emitting elements between the pixels as compared with the voltage input type light emitting device. Further, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.
[0457]
Further, in the pixel of this embodiment, the transistor Tr1 in the display period is larger than the drain current of the transistor Tr1 in the writing period, as compared with the pixels shown in FIGS. 3, 5, 7, 9, 10, and 11. Since the drain current is small, the ratio of the current flowing through the light emitting element to the signal current Ic is small. Therefore, since the signal current Ic can be further increased, it is not easily affected by noise.
[0458]
In this embodiment, one of the source and drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gate of the transistor Tr1 and the gate of the transistor Tr2. However, this example is not limited to this configuration. In the pixel of the present invention, the transistor Tr4 is connected to another element or wiring so that the gate and drain of the transistor Tr1 can be connected in the writing period Ta and the gate and drain of the transistor Tr1 can be disconnected in the display period. It ’s fine.
[0459]
In this embodiment, one of the source and drain of the transistor Tr5 is connected to the drain of Tr1, and the other is connected to the source or drain of Tr6. However, this example is not limited to this configuration. In the pixel of the present invention, the transistor Tr5 is connected to another element or wiring so that the drain of the transistor Tr1 and the pixel electrode can be disconnected in the writing period Ta and the drain of the transistor Tr2 and the pixel electrode can be connected in the display period. It only has to be connected. For example, one of the source and drain of the transistor Tr5 may be connected to the drain of Tr1, and the other to the source or drain of Tr6.
[0460]
That is, Tr3, Tr4, and Tr5 may be connected as shown in FIG. 29A for Ta and as shown in FIG. 29B for Td. In addition, although Gj, Pj, and Rj have three separate wirings, they may be combined into one or two.
[0461]
That is, all the current flowing through Tr1 in Ta need only be controlled by the current source. In Td, the current flowing through Tr1 and Tr2 may flow through the light emitting element.
[0462]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Example 4-Example 10. FIG.
[0463]
(Example 12)
In this embodiment, a structure of the pixel 101 included in the light-emitting device illustrated in FIG. 2 is described.
[0464]
FIG. 30 shows a detailed configuration of the pixel 101 shown in FIG. 30 includes a signal line Si (one of S1 to Sx), a first scanning line Gj (one of G1 to Gy), and a second scanning line Pj (P1 to Py). 1), a third scanning line Rj (one of R1 to Ry) and a power supply line Vi (one of V1 to Vx).
[0465]
The pixel 101 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a transistor Tr5, a light emitting element 730, and a storage capacitor 731. The storage capacitor 731 is provided in order to hold the voltage (gate voltage) between the gates and the sources of the transistors Tr1 and Tr2 more reliably, but it is not always necessary to provide the storage capacitor 731.
[0466]
The gate of the transistor Tr3 is connected to the first scanning line Gj. One of the source and the drain of the transistor Tr3 is connected to the signal line Si, and the other is connected to the drain of the transistor Tr1.
[0467]
The gate of the transistor Tr4 is connected to the second scanning line Pj. One of the source and the drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gates of the transistors Tr1 and Tr2.
[0468]
The gate of the transistor Tr5 is connected to the third scanning line Rj. One of the source and the drain of the transistor Tr5 is connected to the drain of the transistor Tr2 and the power supply line Vi, and the other is connected to the drain of the transistor Tr1.
[0469]
The gates of the transistor Tr1 and the transistor Tr2 are connected to each other. The sources of the transistors Tr1 and Tr2 are both connected to the pixel electrode of the light emitting element 730.
[0470]
One of the two electrodes of the storage capacitor 731 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the pixel electrode of the light-emitting element 730.
[0471]
The voltage (power supply voltage) of the power supply line Vi is kept at a constant height. The voltage of the counter electrode is also maintained at a constant height.
[0472]
Note that the transistors Tr1 and Tr2 may be either n-channel transistors or p-channel transistors. However, the transistors Tr1 and Tr2 have the same polarity. Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors.
[0473]
The transistors Tr3, Tr4, and Tr5 may be either n-channel transistors or p-channel transistors.
[0474]
The operation of the light-emitting device having the pixel shown in FIG. 30 can be described by being divided into the writing period Ta and the display period Td, as in the case of the pixel shown in FIG. For the voltage applied to the first to third scan lines, the timing chart shown in FIG. 4 can be referred to. FIG. 31 is a diagram simply showing the connection between the transistor Tr1 and the transistor Tr2 in the writing period Ta and the display period Td of the pixel shown in FIG.
[0475]
When the writing period Ta is started, the first scanning line G and the second scanning line P are selected. Accordingly, the transistor Tr3 and the transistor Tr4 are turned on. Since the third scanning line R is not selected, the transistor Tr5 is turned off.
[0476]
A signal current Ic corresponding to the video signal flows between the signal lines S1 to Sx and the power supply lines V1 to Vx based on the video signal input to the signal line driver circuit 102.
[0477]
FIG. 31A is a schematic diagram of the pixel 101 when a signal current Ic corresponding to a video signal flows through the signal line Si in the writing period Ta. Reference numeral 736 denotes a terminal for connection to a power source for applying a voltage to the counter electrode. Reference numeral 737 denotes a constant current source included in the signal line driver circuit 102.
[0478]
Since the transistor Tr3 is in the on state, when the signal current Ic corresponding to the video signal flows through the signal line Si, the signal current Ic flows between the drain and the source of the transistor Tr1. At this time, the transistor Tr1 operates in the saturation region because the gate and the drain are connected, and Equation 1 is satisfied. Therefore, the gate voltage V of the transistor Tr1 _GS Is determined by the current value Ic.
[0479]
The gate of the transistor Tr2 is connected to the gate of the transistor Tr1. The source of the transistor Tr2 is connected to the source of the transistor Tr1. Therefore, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2 as it is. Therefore, the drain current of the transistor Tr2 is proportional to the drain current of the transistor Tr1. In particular, μC ₀ W / L and V _TH Are equal to each other, the drain currents of the transistors Tr1 and Tr2 are equal to each other, and I ₂ = Ic.
[0480]
Then, the drain current I of the transistor Tr2 ₂ Flows to the light emitting element 730. The current flowing through the light emitting element has a magnitude corresponding to the signal current Ic determined by the constant current source 737, and the light emitting element 730 emits light with a luminance corresponding to the magnitude of the flowing current. The light emitting element 730 does not emit light when the current flowing through the light emitting element is as close as possible to zero or when the current flowing through the light emitting element flows in the reverse bias direction.
[0481]
When the writing period Ta ends, the selection of the first scanning line G and the second scanning line P ends. At this time, it is preferable that the selection of the second scanning line P is completed before the first scanning line G. This is because if the transistor Tr3 is turned off first, the charge of the storage capacitor 731 leaks through Tr4.
[0482]
When the writing period Ta ends, the display period Td starts next. When the display period Td is started, the third scanning line R is selected and the transistor Tr5 is turned on. Since the first scanning line G and the second scanning line P are not selected, the transistors Tr3 and Tr4 are turned off.
[0483]
FIG. 31B shows a schematic diagram of a pixel in the display period Td. The transistors Tr3 and Tr4 are in an off state. The sources of the transistors Tr1 and Tr2 are connected to the pixel electrode of the light emitting element 730.
[0484]
On the other hand, in the transistors Tr1 and Tr2, V V determined in the writing period Ta _GS Is held as it is. The gate of the transistor Tr2 is connected to the gate of the transistor Tr1. The source of the transistor Tr2 is connected to the source of the transistor Tr1. Therefore, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2 as it is. Furthermore, since the drain of the transistor Tr1 and the drain of the transistor Tr2 are connected to the power supply line Vi, the drain current I of the transistor Tr2 ₂ Is the drain current I of the transistor Tr1 ₁ The size is proportional to. In particular, μC ₀ W / L and V _TH Are equal to each other, the drain currents of the transistors Tr1 and Tr2 are equal to each other, and I ₂ = I ₁ = Ic.
[0485]
Since the transistor Tr5 is on, the drain current I of the transistor Tr1 ₁ And the drain current I of the transistor Tr2 ₂ Both flow in the light emitting element 730 as a current flowing in the light emitting element. Therefore, in the display period Td, the drain current I ₁ And drain current I ₂ A current having a combined size flows through the light emitting element 730, and the light emitting element 730 emits light with a luminance corresponding to the magnitude of the current flowing through the light emitting element.
[0486]
When the display period Td starts in the pixels on the first line, the display period Td starts next on the pixels in the second line. Then, like the pixels on the first line, the third scanning line R2 is selected, and the transistors Tr5 and Tr6 are turned on. Since the first scanning line G2 and the second scanning line P2 are not selected, the transistors Tr3 and Tr4 are turned off. Therefore, drain current I ₁ And drain current I ₂ The light emitting element 730 emits light with a luminance suitable for the magnitude of the combined current.
[0487]
When the display period Td is started in the pixels on the second line, the display period Td is started in order from the pixels on the third line to the pixels on the y line, and the above-described operation is repeated.
[0488]
When the writing period Ta and the display period Td end, one frame period ends. One image is displayed in one frame period. Then, the next frame period is started, the writing period Ta is started again, and the above-described operation is repeated.
[0489]
Note that since the light-emitting element 730 emits light with luminance corresponding to the magnitude of current flowing through the light-emitting element, the gray level of each pixel is determined by the magnitude of current flowing through the light-emitting element in the display period Td.
[0490]
Note that since the light-emitting element 730 emits light with luminance corresponding to the magnitude of current flowing through the light-emitting element, the gray level of each pixel is determined by the magnitude of current flowing through the light-emitting element in the display period Td.
[0491]
In the pixel of the present invention, the current flowing through the light emitting element during the display period is the drain current I. ₁ And drain current I ₂ Is the sum of Therefore, the current flowing through the light emitting element is the drain current I ₂ Not only depend on. For this reason, the characteristics of the transistor Tr1 and the transistor Tr2 are shifted, and the drain current I of the transistor Tr2 ₂ Even if the ratio of the signal current Ic differs between the pixels, the value of the current flowing through the light emitting element can be prevented from shifting between the pixels, and variations in luminance can be prevented from being visually recognized.
[0492]
In the pixel of the present invention, the drain current of the transistor Tr1 does not flow to the light emitting element during the writing period Ta. Therefore, the time from when the gate voltage starts to change due to the current supplied to the pixel by the signal line driver circuit and the drain current of the transistor Tr1 flowing does not depend on the capacitance of the light emitting element. Therefore, compared with the conventional pixel, the voltage converted from the supplied current is stabilized quickly, so that the time for writing the current can be shortened and the afterimage can be prevented from being visually recognized in the moving image display. .
[0493]
Further, as in the prior art, it also has the advantages of a current input type light emitting device. In other words, even when the TFT characteristics vary from pixel to pixel, it is possible to prevent variations in luminance of the light emitting elements between the pixels as compared with the voltage input type light emitting device. Further, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.
[0494]
In this embodiment, one of the source and drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gate of the transistor Tr1 and the gate of the transistor Tr2. However, this example is not limited to this configuration. In the pixel of the present invention, the transistor Tr4 is connected to another element or wiring so that the gate and drain of the transistor Tr1 can be connected in the writing period Ta and the gate and drain of the transistor Tr1 can be disconnected in the display period. It ’s fine.
[0495]
In this embodiment, one of the source and drain of the transistor Tr5 is connected to the drain of Tr2, and the other is connected to the source or drain of Tr3. However, this example is not limited to this configuration.
[0496]
That is, Tr3, Tr4, and Tr5 may be connected as shown in FIG. 31A for Ta and as shown in FIG. 31B for Td. In addition, although Gj, Pj, and Rj have three separate wirings, they may be combined into one or two.
[0497]
That is, all the current flowing through Tr1 in Ta need only be controlled by the current source. In Td, the current flowing through Tr1 and Tr2 may flow through the light emitting element.
[0498]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Example 4-11.
[0499]
(Example 13)
In this embodiment, a structure of the pixel 101 included in the light-emitting device illustrated in FIG. 2 is described.
[0500]
FIG. 32 shows a detailed configuration of the pixel 101 shown in FIG. 32 includes a signal line Si (one of S1 to Sx), a first scanning line Gj (one of G1 to Gy), and a second scanning line Pj (P1 to Py). 1), a third scanning line Rj (one of R1 to Ry) and a power supply line Vi (one of V1 to Vx).
[0501]
The pixel 101 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a transistor Tr5, a transistor Tr6, a light emitting element 760, and a storage capacitor 761. The storage capacitor 761 is provided in order to hold the voltage (gate voltage) between the gate and source of the transistors Tr1 and Tr2 more reliably, but it is not always necessary to provide the storage capacitor 761.
[0502]
The gate of the transistor Tr3 is connected to the first scanning line Gj. One of the source and the drain of the transistor Tr3 is connected to the signal line Si, and the other is connected to the drain of the transistor Tr1.
[0503]
The gate of the transistor Tr4 is connected to the second scanning line Pj. One of the source and the drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gates of the transistors Tr1 and Tr2.
[0504]
The gate of the transistor Tr5 is connected to the third scanning line Rj. One of the source and drain of the transistor Tr5 is connected to the drain of the transistor Tr2 and the power supply line Vi, and the other is connected to the source or drain of the transistor Tr6.
[0505]
The gate of the transistor Tr6 is connected to the gates of the transistors Tr1 and Tr2. One of the source and drain of the transistor Tr6 is connected to the drain of the transistor Tr1, and the other is connected to the source or drain of the transistor Tr5.
[0506]
The gates of the transistor Tr1 and the transistor Tr2 are connected to each other. The sources of the transistors Tr1 and Tr2 are both connected to the pixel electrode of the light emitting element 760.
[0507]
One of the two electrodes of the storage capacitor 761 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the pixel electrode of the light-emitting element 760.
[0508]
The voltage (power supply voltage) of the power supply line Vi is kept at a constant height. The voltage of the counter electrode is also maintained at a constant height.
[0509]
Note that the transistors Tr1 and Tr2 may be either n-channel transistors or p-channel transistors. However, the transistors Tr1 and Tr2 have the same polarity. Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors.
[0510]
The transistors Tr3, Tr4, Tr5, Tr6 may be either n-channel transistors or p-channel transistors.
[0511]
The operation of the light-emitting device having the pixel shown in FIG. 32 can be described by being divided into the writing period Ta and the display period Td, as in the case of the pixel shown in FIG. For the voltage applied to the first to third scan lines, the timing chart shown in FIG. 4 can be referred to. FIG. 33 is a diagram simply showing the connection between the transistor Tr1 and the transistor Tr2 in the writing period Ta and the display period Td of the pixel shown in FIG.
[0512]
When the writing period Ta is started, the first scanning line G and the second scanning line P are selected. Accordingly, the transistor Tr3 and the transistor Tr4 are turned on. Since the third scanning line R is not selected, the transistor Tr5 is turned off.
[0513]
A signal current Ic corresponding to the video signal flows between the signal lines S1 to Sx and the power supply lines V1 to Vx based on the video signal input to the signal line driver circuit 102.
[0514]
FIG. 33A shows a schematic diagram of the pixel 101 when a signal current Ic corresponding to a video signal flows through the signal line Si in the writing period Ta. Reference numeral 766 denotes a terminal for connection to a power source for applying a voltage to the counter electrode. Reference numeral 765 denotes a constant current source included in the signal line driver circuit 102.
[0515]
Since the transistor Tr3 is in the on state, when the signal current Ic corresponding to the video signal flows through the signal line Si, the signal current Ic flows between the drain and the source of the transistor Tr1. At this time, the transistor Tr1 operates in the saturation region because the gate and the drain are connected, and Equation 1 is satisfied. Therefore, the gate voltage V of the transistor Tr1 _GS Is determined by the current value Ic.
[0516]
The gate of the transistor Tr2 is connected to the gate of the transistor Tr1. The source of the transistor Tr2 is connected to the source of the transistor Tr1. Therefore, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2 as it is. Therefore, the drain current of the transistor Tr2 is proportional to the drain current of the transistor Tr1. In particular, μC ₀ W / L and V _TH Are equal to each other, the drain currents of the transistors Tr1 and Tr2 are equal to each other, and I ₂ = Ic.
[0517]
Then, the drain current I of the transistor Tr2 ₂ Flows to the light emitting element 760. The current flowing through the light emitting element has a magnitude corresponding to the signal current Ic determined by the constant current source 765, and the light emitting element 760 emits light with a luminance corresponding to the magnitude of the flowing current. The light emitting element 760 does not emit light when the current flowing through the light emitting element is as close as possible to zero or when the current flowing through the light emitting element flows in the reverse bias direction.
[0518]
When the writing period Ta ends, the selection of the first scanning line G and the second scanning line P ends. At this time, it is preferable that the selection of the second scanning line P is completed before the first scanning line G. This is because if the transistor Tr3 is turned off first, the charge of the storage capacitor 761 leaks through Tr4.
[0519]
When the writing period Ta ends, the display period Td starts next. When the display period Td is started, the third scanning line R is selected and the transistor Tr5 is turned on. Since the first scanning line G and the second scanning line P are not selected, the transistors Tr3 and Tr4 are turned off.
[0520]
FIG. 33B is a schematic diagram of a pixel in the display period Td. The transistors Tr3 and Tr4 are in an off state. The sources of the transistors Tr1 and Tr2 are connected to the pixel electrode of the light emitting element 760.
[0521]
On the other hand, in the transistors Tr1 and Tr2, V V determined in the writing period Ta _GS Is held as it is. Further, the gate of the transistor Tr6 is connected to the gates of the transistors Tr1 and Tr2. Therefore, the drain current of the transistor Tr1 and the drain current of the transistor Tr6 are kept the same. From Equation 1, the drain current of the transistor Tr1 depends on the channel length and channel width of the transistor Tr6.
[0522]
As described above, assuming that the gate voltages, the mobility, the gate capacitance per unit area, the threshold value, and the channel width of the transistors Tr1 and Tr6 are equal, Expression 2 is derived from Expression 1.
[0523]
On the other hand, the drain current I of the transistor Tr2 ₂ The value of is maintained at a magnitude corresponding to the signal current Ic.
[0524]
Since the transistor Tr5 is on, the drain current I of the transistors Tr1 and Tr6 _Three And the drain current I of the transistor Tr2 ₂ Both flow to the light emitting element 760. Therefore, drain current I _Three And drain current I ₂ The light emitting element 760 emits light with a luminance corresponding to the magnitude of the combined current.
[0525]
When the display period Td starts in the pixels on the first line, the display period Td starts next on the pixels in the second line. Then, like the pixels on the first line, the third scanning line R2 is selected, and the transistors Tr5 and Tr6 are turned on. Since the first scanning line G2 and the second scanning line P2 are not selected, the transistors Tr3 and Tr4 are turned off. Therefore, drain current I ₂ And drain current I _Three The light emitting element 760 emits light with a luminance corresponding to the magnitude of the combined current.
[0526]
When the display period Td is started in the pixels on the second line, the display period Td is started in order from the pixels on the third line to the pixels on the y line, and the above-described operation is repeated.
[0527]
When the writing period Ta and the display period Td end, one frame period ends. One image is displayed in one frame period. Then, the next frame period is started, the writing period Ta is started again, and the above-described operation is repeated.
[0528]
Note that since the light-emitting element 760 emits light with luminance corresponding to the magnitude of current flowing through the light-emitting element, the gray level of each pixel is determined by the magnitude of current flowing through the light-emitting element in the display period Td.
[0529]
In the pixel of the present invention, the current flowing through the light emitting element during the display period is the drain current I. ₁ And drain current I ₂ Is the sum of Therefore, the current flowing through the light emitting element is the drain current I ₂ Not only depend on. For this reason, the characteristics of the transistor Tr1 and the transistor Tr2 are shifted, and the drain current I of the transistor Tr2 ₂ Even if the ratio of the signal current Ic differs between the pixels, the value of the current flowing through the light emitting element can be prevented from shifting between the pixels, and variations in luminance can be prevented from being visually recognized.
[0530]
In the pixel of the present invention, the drain current of the transistor Tr1 does not flow to the light emitting element during the writing period Ta. Therefore, the time from when the gate voltage starts to change due to the current supplied to the pixel by the signal line driver circuit and the drain current of the transistor Tr1 flowing does not depend on the capacitance of the light emitting element. Therefore, compared with the conventional pixel, the voltage converted from the supplied current is stabilized quickly, so that the time for writing the current can be shortened and the afterimage can be prevented from being visually recognized in the moving image display. .
[0531]
Further, as in the prior art, it also has the advantages of a current input type light emitting device. In other words, even when the TFT characteristics vary from pixel to pixel, it is possible to prevent variations in luminance of the light emitting elements between the pixels as compared with the voltage input type light emitting device. Further, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.
[0532]
Further, in the pixel of this example, the drain current of the transistor Tr1 in the display period is larger than the drain current of the transistor Tr1 in the writing period as compared with the pixels shown in FIGS. 2, 5, 7, 9, 10, and 11. Since the drain current is small, the ratio of the current flowing through the light emitting element to the signal current Ic is small. Therefore, since the signal current Ic can be further increased, it is not easily affected by noise.
[0533]
In this embodiment, one of the source and drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gate of the transistor Tr1 and the gate of the transistor Tr2. However, this example is not limited to this configuration. In the pixel of the present invention, the transistor Tr4 is connected to another element or wiring so that the gate and drain of the transistor Tr1 can be connected in the writing period Ta and the gate and drain of the transistor Tr1 can be disconnected in the display period. It ’s fine.
[0534]
In this embodiment, one of the source and drain of the transistor Tr5 is connected to the drain of Tr2, and the other is connected to the source or drain of Tr6. However, the present embodiment is not limited to this configuration. In the pixel of the present invention, the transistor Tr5 is connected to another element or wiring so that the drain of the transistor Tr2 and the pixel electrode can be disconnected in the writing period Ta and the drain of the transistor Tr2 and the power supply line Vi can be connected in the display period. As long as it is connected.
[0535]
That is, Tr3, Tr4, Tr5, and Tr6 may be connected as shown in FIG. 31A for Ta and as shown in FIG. 31B for Td. In addition, although Gj, Pj, and Rj have three separate wirings, they may be combined into one or two.
[0536]
That is, all the current flowing through Tr1 in Ta need only be controlled by the current source. In Td, the current flowing through Tr1 and Tr2 may flow through the light emitting element.
[0537]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Example 4-12.
[0538]
(Example 14)
In this embodiment, a structure of the pixel 101 included in the light-emitting device illustrated in FIG. 2 is described.
[0539]
FIG. 34 shows a detailed configuration of the pixel 101 shown in FIG. 34 includes a signal line Si (one of S1 to Sx), a first scanning line Gj (one of G1 to Gy), and a second scanning line Pj (P1 to Py). 1), a third scanning line Rj (one of R1 to Ry) and a power supply line Vi (one of V1 to Vx).
[0540]
The pixel 101 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a transistor Tr5, a light emitting element 780, and a storage capacitor 781. The storage capacitor 781 is provided to more reliably hold the voltage (gate voltage) between the gate and source of the transistors Tr1 and Tr2, but it is not always necessary to provide the storage capacitor 781.
[0541]
The gate of the transistor Tr3 is connected to the first scanning line Gj. One of the source and the drain of the transistor Tr3 is connected to the signal line Si, and the other is connected to the source of the transistor Tr1.
[0542]
The gate of the transistor Tr4 is connected to the second scanning line Pj. One of the source and the drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gates of the transistors Tr1 and Tr2.
[0543]
The gate of the transistor Tr5 is connected to the third scanning line Rj. One of the source and the drain of the transistor Tr5 is connected to the source of the transistor Tr2 and the pixel electrode of the light emitting element 780, and the other is connected to the source of the transistor Tr1.
[0544]
The gates of the transistor Tr1 and the transistor Tr2 are connected to each other. The source of the transistor Tr2 is connected to the pixel electrode of the light emitting element 780. The drains of the transistors Tr1 and Tr2 are both connected to the power supply line Vi.
[0545]
One of the two electrodes of the storage capacitor 781 is connected to the gates of the transistors Tr1 and Tr2, and the other is connected to the source pixel electrode of the Tr1.
[0546]
The voltage (power supply voltage) of the power supply line Vi is kept at a constant height. The voltage of the counter electrode is also maintained at a constant height.
[0547]
Note that the transistors Tr1 and Tr2 may be either n-channel transistors or p-channel transistors. However, the transistors Tr1 and Tr2 have the same polarity. Note that in the case where the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are preferably n-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are preferably p-channel transistors.
[0548]
The transistors Tr3, Tr4, and Tr5 may be either n-channel transistors or p-channel transistors.
[0549]
The operation of the light-emitting device including the pixel illustrated in FIG. 34 can be described by being divided into the writing period Ta and the display period Td, as in the case of the pixel illustrated in FIG. For the voltage applied to the first to third scan lines, the timing chart shown in FIG. 4 can be referred to. FIG. 35 is a diagram simply showing the connection between the transistor Tr1 and the transistor Tr2 in the writing period Ta and the display period Td of the pixel shown in FIG.
[0550]
When the writing period Ta is started, the first scanning line G and the second scanning line P are selected. Accordingly, the transistor Tr3 and the transistor Tr4 are turned on. Since the third scanning line R is not selected, the transistor Tr5 is turned off.
[0551]
A signal current Ic corresponding to the video signal flows between the signal lines S1 to Sx and the power supply lines V1 to Vx based on the video signal input to the signal line driver circuit 102.
[0552]
FIG. 35A is a schematic diagram of the pixel 101 when a signal current Ic corresponding to a video signal flows through the signal line Si in the writing period Ta. Reference numeral 786 denotes a terminal for connection with a power source for applying a voltage to the counter electrode. Reference numeral 787 denotes a constant current source included in the signal line driver circuit 102.
[0553]
Since the transistor Tr3 is in the on state, when the signal current Ic corresponding to the video signal flows through the signal line Si, the signal current Ic flows between the drain and the source of the transistor Tr1. At this time, the transistor Tr1 operates in the saturation region because the gate and the drain are connected, and Equation 1 is satisfied. Therefore, the gate voltage V of the transistor Tr1 _GS Is determined by the current value Ic.
[0554]
The gate of the transistor Tr2 is connected to the gate of the transistor Tr1.
[0555]
When the writing period Ta ends, the selection of the first scanning line G and the second scanning line P ends. At this time, it is preferable that the selection of the second scanning line P is completed before the first scanning line G. This is because if the transistor Tr3 is turned off first, the charge of the storage capacitor 781 leaks through Tr4.
[0556]
When the writing period Ta ends, the display period Td starts next. When the display period Td is started, the third scanning line R is selected and the transistor Tr5 is turned on. Since the first scanning line G and the second scanning line P are not selected, the transistors Tr3 and Tr4 are turned off.
[0557]
FIG. 35B is a schematic diagram of a pixel in the display period Td. The transistors Tr3 and Tr4 are in an off state. The sources of the transistors Tr1 and Tr2 are connected to the pixel electrode of the light emitting element 780.
[0558]
On the other hand, in the transistors Tr1 and Tr2, V V determined in the writing period Ta _GS Is held as it is. The gate of the transistor Tr2 is connected to the gate of the transistor Tr1. The source of the transistor Tr2 is connected to the source of the transistor Tr1. Therefore, the gate voltage of the transistor Tr1 becomes the gate voltage of the transistor Tr2 as it is. Furthermore, since the drain of the transistor Tr1 and the drain of the transistor Tr2 are connected to the power supply line Vi, the drain current I of the transistor Tr2 ₂ Is the drain current I of the transistor Tr1 ₁ The size is proportional to. In particular, μC ₀ W / L and V _TH Are equal to each other, the drain currents of the transistors Tr1 and Tr2 are equal to each other, and I ₂ = I ₁ = Ic.
[0559]
Since the transistor Tr5 is on, the drain current I of the transistor Tr1 ₁ And the drain current I of the transistor Tr2 ₂ Both flow to the light emitting element 780 as a current flowing to the light emitting element. Therefore, in the display period Td, the drain current I ₁ And drain current I ₂ A current having a combined size flows to the light emitting element 780, and the light emitting element 780 emits light with luminance corresponding to the magnitude of the current flowing through the light emitting element.
[0560]
When the display period Td starts in the pixels on the first line, the display period Td starts next on the pixels in the second line. Then, like the pixels on the first line, the third scanning line R2 is selected, and the transistor Tr5 is turned on. Since the first scanning line G2 and the second scanning line P2 are not selected, the transistors Tr3 and Tr4 are turned off. Therefore, drain current I ₁ And drain current I ₂ The light emitting element 780 emits light with a luminance corresponding to the magnitude of the combined current.
[0561]
When the display period Td is started in the pixels on the second line, the display period Td is started in order from the pixels on the third line to the pixels on the y line, and the above-described operation is repeated.
[0562]
When the writing period Ta and the display period Td end, one frame period ends. One image is displayed in one frame period. Then, the next frame period is started, the writing period Ta is started again, and the above-described operation is repeated.
[0563]
Note that since the light-emitting element 780 emits light with luminance corresponding to the magnitude of current flowing through the light-emitting element, the gray level of each pixel is determined by the magnitude of current flowing through the light-emitting element in the display period Td. Note that even during the writing period Ta, light is emitted with luminance corresponding to the magnitude of the drain current of Tr2, but the influence on the gray level is considered to be negligible in an actual panel. This is because, for example, in the case of VGA, pixels of 480 lines are provided in the pixel portion, and the writing period Ta of the pixels of one line is very small, about 1/480 of one frame period.
[0564]
In the pixel of the present invention, the current flowing through the light emitting element during the display period is the drain current I. ₁ And drain current I ₂ Is the sum of Therefore, the current flowing through the light emitting element is the drain current I ₂ Not only depend on. For this reason, the characteristics of the transistor Tr1 and the transistor Tr2 are shifted, and the drain current I of the transistor Tr2 ₂ Even if the ratio of the signal current Ic differs between the pixels, the value of the current flowing through the light emitting element can be prevented from shifting between the pixels, and variations in luminance can be prevented from being visually recognized.
[0565]
In the pixel of the present invention, the drain current of the transistor Tr1 does not flow to the light emitting element during the writing period Ta. Therefore, the time from when the gate voltage starts to change due to the current supplied to the pixel by the signal line driver circuit and the drain current of the transistor Tr1 flowing does not depend on the capacitance of the light emitting element. Therefore, compared with the conventional pixel, the voltage converted from the supplied current is stabilized quickly, so that the time for writing the current can be shortened and the afterimage can be prevented from being visually recognized in the moving image display. .
[0566]
Further, as in the prior art, it also has the advantages of a current input type light emitting device. In other words, even when the TFT characteristics vary from pixel to pixel, it is possible to prevent variations in luminance of the light emitting elements between the pixels as compared with the voltage input type light emitting device. Further, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.
[0567]
In this embodiment, one of the source and drain of the transistor Tr4 is connected to the drain of the transistor Tr1, and the other is connected to the gate of the transistor Tr1 and the gate of the transistor Tr2. However, this example is not limited to this configuration. In the pixel of the present invention, the transistor Tr4 is connected to another element or wiring so that the gate and drain of the transistor Tr1 can be connected in the writing period Ta and the gate and drain of the transistor Tr1 can be disconnected in the display period. It ’s fine.
[0568]
In this embodiment, one of the source and drain of the transistor Tr5 is connected to the source of Tr2, and the other is connected to the source of Tr1. However, this example is not limited to this configuration. In the pixel of the present invention, the transistor Tr5 is connected to another element or wiring so that the source of the transistor Tr1 and the pixel electrode can be disconnected in the writing period Ta and the source of the transistor Tr1 and the pixel electrode can be connected in the display period. It only has to be connected.
[0569]
That is, Tr3, Tr4, and Tr5 may be connected as shown in FIG. 35A for Ta and as shown in FIG. 35B for Td. In addition, although Gj, Pj, and Rj have three separate wirings, they may be combined into one or two.
[0570]
That is, all the current flowing through Tr1 in Ta need only be controlled by the current source. In Td, the current flowing through Tr1 and Tr2 may flow through the light emitting element.
[0571]
Further, the pixel electrode of the light emitting element may be connected to the source of Tr1 instead of being connected to the source of Tr2. However, in this case, it is necessary to prepare a separate transistor for controlling connection so that the source of Tr1 and the pixel electrode are separated in the writing period and are connected in the display period. The transistor for controlling the connection between the source of Tr1 and the pixel electrode may have a polarity different from that of Tr5, and the gates may be connected to each other.
[0572]
In addition, the structure of a present Example can be implemented in combination with any structure of Example 4-Example 13 freely.
[0573]
【The invention's effect】
In the pixel having the first structure of the present invention, the current flowing through the light emitting element during the display period is the drain current I. ₁ And drain current I ₂ Is the sum of Therefore, the current flowing through the light emitting element is the drain current I ₂ Not only depend on. Therefore, the characteristics of the transistor Tr1 and the transistor Tr2 are shifted, and the drain current I of the transistor Tr1 ₁ Drain current I of the transistor Tr2 with respect to ₂ Even if the ratio is different between pixels, the value of the current flowing through the light-emitting element can be prevented from being shifted between pixels, and variations in luminance can be prevented from being visually recognized.
[0574]
In the pixel having the second structure of the present invention, as in the pixel shown in FIG. 27A, the characteristic of either the first means or the second means is shifted, so that the two means The current I supplied from the drive unit to the light emitting element is lost due to the imbalance of characteristics. ₂ May not be maintained at a desired value. However, by using the two converters A and B together, the converted voltage can be averaged, and the current I supplied from the driver to the light emitting element ₂ Since the magnitude corresponds to the averaged voltage, the variation in the amount of current supplied to the light-emitting element due to the characteristic deviation is suppressed to about half that of the pixel shown in FIG. be able to. Therefore, variation in luminance between pixels can be suppressed. In addition, the current supplied to the pixel is the current I ₂ Bigger than. Therefore, the time for writing current can be shortened.
[0575]
In the pixel of the present invention, the drain current of the transistor Tr1 does not flow to the light emitting element during the writing period Ta. Therefore, the time from when the gate voltage starts to change due to the current supplied to the pixel by the signal line driver circuit and the drain current of the transistor Tr1 flowing does not depend on the capacitance of the light emitting element. Therefore, compared with the conventional pixel, the voltage converted from the supplied current is stabilized quickly, so that the time for writing the current can be shortened and the afterimage can be prevented from being visually recognized in the moving image display. .
[0576]
Further, as in the prior art, it also has the advantages of a current input type light emitting device. In other words, even when the TFT characteristics vary from pixel to pixel, it is possible to prevent variations in luminance of the light emitting elements between the pixels as compared with the voltage input type light emitting device. Further, compared with the case where the TFT 51 of the voltage input type pixel shown in FIG. 25 is operated in a linear region, a reduction in luminance due to deterioration of the light emitting element can be suppressed. Even if the temperature of the organic light emitting layer depends on the outside air temperature, heat generated by the light emitting panel itself, etc., it is possible to suppress the luminance of the light emitting element from changing, and the current consumption increases as the temperature increases. Can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram of a current input type pixel of the present application.
FIG. 2 is a top block diagram of a light emitting device of the present invention.
FIG. 3 is a circuit diagram of a pixel of the light emitting device of the present invention.
FIG. 4 is a timing chart of signals input to scanning lines.
FIG. 5 is a schematic diagram of a pixel in driving.
FIG. 6 is a circuit diagram of a pixel of a light emitting device of the present invention.
FIG. 7 is a schematic diagram of a pixel in driving.
FIG. 8 is a circuit diagram of a pixel of the light emitting device of the present invention.
FIG. 9 is a schematic diagram of a pixel in driving.
FIG. 10 is a circuit diagram of a pixel of a light emitting device of the present invention.
FIG. 11 is a circuit diagram of a pixel of a light emitting device of the present invention.
FIG. 12 is a circuit diagram of a pixel of a light emitting device of the present invention.
13A to 13C illustrate a method for manufacturing a light-emitting device of the present invention.
14A to 14C illustrate a method for manufacturing a light-emitting device of the present invention.
FIGS. 15A to 15C illustrate a method for manufacturing a light-emitting device of the present invention. FIGS.
FIG. 16 illustrates a method for manufacturing a light-emitting device of the present invention.
FIG. 17 is a top view of a pixel of a light-emitting device of the present invention.
FIG. 18 is a detailed diagram of a signal line driver circuit in an analog driving method.
FIG. 19 is a block diagram of a scan line driver circuit.
FIG. 20 is a block diagram of a signal line driver circuit in a digital driving method.
FIG. 21 is a detailed diagram of a signal line driver circuit in a digital driving method.
FIG. 22 is a circuit diagram of a current setting circuit in the digital driving method.
FIGS. 23A and 23B are an external view and a cross-sectional view of a light-emitting device of the present invention. FIGS.
FIG. 24 is a diagram of an electronic device using the light-emitting device of the present invention.
FIG. 25 is a circuit diagram of a voltage input type pixel.
FIG. 26 is a circuit diagram of a conventional current input type pixel.
FIG. 27 is a block diagram of a conventional current input type pixel.
FIG. 28 is a circuit diagram of a pixel of a light-emitting device of the present invention.
FIG. 29 is a schematic diagram of a pixel in driving.
FIG. 30 is a circuit diagram of a pixel of a light-emitting device of the present invention.
FIG. 31 is a schematic diagram of a pixel in driving.
FIG. 32 is a circuit diagram of a pixel of the light emitting device of the invention.
FIG. 33 is a schematic diagram of a pixel in driving.
FIG. 34 is a circuit diagram of a pixel of a light emitting device of the present invention.
FIG. 35 is a schematic diagram of a pixel in driving.
FIG. 36 is a block diagram of a current input type pixel of the present application.
FIG. 37 is a schematic diagram of a pixel in driving.
FIG. 38 is a schematic diagram of a pixel in driving.

Claims (8)

A plurality of pixels each including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a light emitting element; a power supply line; a signal line; A light-emitting device having a scanning line and a second scanning line,
Both the first transistor and the second transistor have their sources connected to the power supply line,
The first transistor and the second transistor have the same polarity and the gates are connected to each other,
One of the source and the drain of the third transistor is connected to the signal line, and the other is connected to the drain of the first transistor.
One of the source and the drain of the fourth transistor is connected to the drain of the first transistor or the signal line, and the other is connected to the gates of the first transistor and the second transistor,
One of the source and the drain of the fifth transistor is connected to the drain of the first transistor, and the other is connected to the drain of the second transistor.
The drain of the second transistor is connected to the pixel electrode of the light emitting element,
A gate of the third transistor and a gate of the fifth transistor are connected to the first scan line;
A gate of the fourth transistor is connected to the second scan line;
The polarities of the third transistor and the fifth transistor are different,
The light emitting device according to claim 1, wherein a signal that turns on the third transistor when the fourth transistor is on is input to the first scanning line and the second scanning line. A plurality of pixels each including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a light-emitting element, a power supply line, a signal line, and a scan line A light emitting device comprising:
Both the first transistor and the second transistor have their sources connected to the power supply line,
The first transistor and the second transistor have the same polarity and the gates are connected to each other,
One of the source and the drain of the third transistor is connected to the signal line, and the other is connected to the drain of the first transistor.
One of the source and the drain of the fourth transistor is connected to the drain of the first transistor or the signal line, and the other is connected to the gates of the first transistor and the second transistor,
One of the source and the drain of the fifth transistor is connected to the drain of the first transistor, and the other is connected to the drain of the second transistor.
The drain of the second transistor is connected to the pixel electrode of the light emitting element,
The third transistor, the fourth transistor, and the fifth transistor have gates connected to each other and connected to the scan line,
The third transistor and the fourth transistor have the same polarity;
The light emitting device according to claim 5, wherein the fifth transistor has a polarity different from that of the third transistor and the fourth transistor. A plurality of pixels each including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a light-emitting element; a power supply line; A light emitting device having a signal line,
The first transistor and the second transistor have the same polarity and the gates are connected to each other,
The drain of the first transistor is connected to the power line;
One of the source and the drain of the third transistor is connected to the signal line, and the other is connected to the sources of the first transistor and the second transistor,
One of the source and the drain of the fourth transistor is connected to the gates of the first transistor and the second transistor, and the other is connected to the power line.
One of the source and drain of the sixth transistor is connected to the power supply line, and the other is connected to the drain of the second transistor,
One of the source and the drain of the fifth transistor is connected to the sources of the first transistor and the second transistor, and the other is connected to the pixel electrode of the light emitting element.
When one of the third transistor and the fifth transistor is on, the other is off;
When one of the fifth transistor and the sixth transistor is on, the other is on; when one is off, the other is off;
The light-emitting device is characterized in that the third transistor is turned on when the fourth transistor is on. A plurality of pixels each including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a light-emitting element; a power supply line; A light emitting device having a signal line,
The first transistor and the second transistor have the same polarity and the gates are connected to each other,
The drains of the first transistor and the second transistor are both connected to the power supply line,
One of the source and the drain of the third transistor is connected to the signal line, and the other is connected to the source of the first transistor,
One of the source and the drain of the fourth transistor is connected to the gates of the first transistor and the second transistor, and the other is connected to the power line.
One of the source and the drain of the fifth transistor is connected to the source of the first transistor, and the other is connected to the pixel electrode of the light emitting element.
One of the source and the drain of the sixth transistor is connected to the source of the second transistor, and the other is connected to the pixel electrode of the light emitting element,
When one of the third transistor and the fifth transistor is on, the other is off;
When one of the fifth transistor and the sixth transistor is on, the other is on; when one is off, the other is off;
The light-emitting device is characterized in that the third transistor is turned on when the fourth transistor is on. A plurality of pixels each including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a light-emitting element; a power supply line; A light emitting device having a signal line,
Both the first transistor and the second transistor have their sources connected to the power supply line,
The gates of the first transistor and the second transistor are connected to each other,
The first transistor, the second transistor, and the sixth transistor have the same polarity;
One of the source and the drain of the third transistor is connected to the signal line, and the other is connected to the drain of the first transistor.
One of the source and the drain of the fourth transistor is connected to the drain of the first transistor or the signal line, and the other is connected to the gates of the first transistor and the second transistor,
One of the source and the drain of the fifth transistor is connected to the drain of the sixth transistor, and the other is connected to the drain of the second transistor.
The gate of the sixth transistor is connected to the gates of the first transistor and the second transistor;
A source of the sixth transistor is connected to a drain of the first transistor;
The drain of the second transistor is connected to the pixel electrode of the light emitting element,
When one of the third transistor and the fifth transistor is on, the other is off;
The light-emitting device is characterized in that the third transistor is turned on when the fourth transistor is on. A plurality of pixels each including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a light-emitting element; a power supply line; A light emitting device having a signal line,
Both the first transistor and the second transistor have their sources connected to the power supply line,
The gates of the first transistor and the second transistor are connected to each other,
The first transistor, the second transistor, and the sixth transistor have the same polarity;
One of the source and the drain of the third transistor is connected to the signal line, and the other is connected to the drain of the first transistor.
One of the source and the drain of the fourth transistor is connected to the drain of the first transistor or the signal line, and the other is connected to the gates of the first transistor and the second transistor,
One of the source and the drain of the fifth transistor is connected to the drain of the first transistor, and the other is connected to the source of the sixth transistor.
The gate of the sixth transistor is connected to the gates of the first transistor and the second transistor;
The drain of the sixth transistor is connected to the drain of the second transistor;
The drain of the second transistor is connected to the pixel electrode of the light emitting element,
When one of the third transistor and the fifth transistor is on, the other is off;
The light-emitting device is characterized in that the third transistor is turned on when the fourth transistor is on. Light emission including a plurality of pixels each including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a light-emitting element, a power supply line, and a signal line A device,
The first transistor and the second transistor have the same polarity and the gates are connected to each other,
One of the source and the drain of the third transistor is connected to the signal line, and the other is connected to the drain of the first transistor.
One of the source and the drain of the fourth transistor is connected to the drain of the first transistor or the signal line, and the other is connected to the gates of the first transistor and the second transistor,
One of the source and the drain of the fifth transistor is connected to the drain and the power supply line of the second transistor, and the other is connected to the drain of the first transistor.
Sources of the first transistor and the second transistor are connected to a pixel electrode of the light emitting element,
When one of the third transistor and the fifth transistor is on, the other is off;
The light-emitting device is characterized in that the third transistor is turned on when the fourth transistor is on. In any one of claims 1 to 7, the electronic device characterized by using the light emitting device.

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