KR20160063446A - Array substrate - Google Patents

Abstract

The present invention provides an array substrate having a thin film transistor having an oxide semiconductor layer having excellent device characteristic stability, and having a structure capable of suppressing generation of hump while controlling a movement of a threshold voltage in a negative voltage direction. The array substrate includes an oxide semiconductor layer including an active region and conducted regions on both sides of the active region on a substrate in which a plurality of pixel regions are defined, and a first part having a first width a second part having a second width smaller than the first width; a gate insulating layer and a gate electrode sequentially formed on the oxide semiconductor layer corresponding to the active region; an interlayer insulating layer having a first semiconductor layer contact hole exposing the conducted regions positioned on both sides of the active region, and provided in the first part to have a first length in a first width direction, and a second semiconductor layer contact hole provided in the second part to have a second length smaller than the first length in a second width direction; and a source electrode and a drain electrode contacting the oxide semiconductor layer through the first and second semiconductor layer contact holes on the interlayer insulating layer, and formed to be spaced apart from each other.

Description

[0001]

The present invention relates to an array substrate and more particularly to a thin film transistor having an oxide semiconductor layer excellent in stability of device characteristics and capable of suppressing the movement of a threshold voltage in a negative voltage direction and suppressing the generation of a hump To an array substrate having transistors.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, The ability is excellent and is getting the most attention.

In addition, since the organic electroluminescent device has a high luminance and a low operating voltage characteristic and is a self-luminous type that emits light by itself, it has a large contrast ratio, can realize an ultra-thin display, has a response time of several microseconds Mu s), has no limitation of viewing angles, is stable at low temperatures, and is driven at a low voltage of 5 to 15 V DC, making it easy to manufacture and design a driving circuit, and has recently attracted attention as a flat panel display device.

In such a liquid crystal display device and an organic electroluminescent device, an array substrate including a thin film transistor, which is a switching element, is provided in order to commonly control ON / OFF of each pixel.

FIG. 1 is a plan view of a portion of a conventional array substrate where a thin film transistor, which is a switching element, is formed in one pixel region.

As shown in the drawing, the array substrate 1 is provided with a plurality of pixel regions which are defined as regions where a plurality of gate wirings (not shown) and a plurality of data wirings (not shown) cross each other and are captured. At least one thin film transistor Tr is provided inside.

Although the thin film transistor Tr is typically provided with a semiconductor layer having a bilayer structure of pure amorphous silicon and impurity amorphous silicon, in recent years, an oxide semiconductor having excellent mobility characteristics compared with a thin film transistor having such an amorphous silicon- A thin film transistor Tr provided with a layer 5 is mainly used.

The thin film transistor Tr having the oxide semiconductor layer 5 is provided with a rectangular or square oxide semiconductor layer 5 made of an oxide semiconductor material and having a first width w1, A gate electrode 16 is formed through a gate insulating film (not shown) in correspondence with the central portion of the oxide semiconductor layer 5.

At this time, the oxide semiconductor layer 5 exposed to the outside of the gate insulating film (not shown) is electrically conductive and has a semiconductor characteristic different from that of the oxide semiconductor layer corresponding to the gate electrode 16. The portion of the oxide semiconductor layer 5 to which no conductive property is imparted is referred to as the active region 5a and the portion to which the conductive characteristic is imparted is referred to as the source and drain regions 5b and 5c.

An interlayer insulating film (not shown) is formed of an inorganic insulating material to cover the gate electrode 16 and the source and drain regions 5b and 5c exposed to the outside of the gate insulating film (not shown). First and second semiconductor layer contact holes 22a and 22b exposing the source region 5b and the drain region 5c to both sides of the gate electrode 16 are formed in the interlayer insulating film (not shown) And are in contact with the source region 5b and the drain region 5c via the first and second semiconductor layer contact holes 22a and 22b on the interlayer insulating film (not shown) Source and drain electrodes 33 and 36 are formed.

At this time, the first and second semiconductor layer contact holes 22a and 22b are formed to have a width of a channel (source and drain electrodes facing each other) to maximize the channel ratio (ratio of length to channel width) of the thin film transistor Tr 33, and 36), that is, the longitudinal direction of the gate electrode 16. The oxide semiconductor layer 5 is exposed at the maximum.

In the thin film transistor Tr having such a structure, the source region 5b and the drain region 5c located on both sides of the active region 5a as a reference are symmetrically configured to have the same area The first semiconductor layer contact hole 22a and the second semiconductor layer contact hole 22b which respectively expose the source region 5b and the drain region 5c are also formed with the same area and more exactly the same second width w2 And is formed to have the same first length 11.

In the figure, the longitudinal direction of the gate electrode 16 is defined as a first direction dn1 and the spacing direction between the source and drain electrodes 33 and 36 which are perpendicular to the first direction dn1 is defined as a second direction dn2 The first semiconductor layer contact hole 22a and the second semiconductor layer contact hole 22b have the same first length l1 in the first direction dn1 and are the same in the second direction dn2. And has a second width w2.

However, in the thin film transistor Tr having such a structure, the dry etching is performed on the interlayer insulating film (not shown) to expose the source and drain regions 5b of the oxide semiconductor layer 5, A plurality of electrons are introduced into the first and second semiconductor layer contact holes 22a and 22b in the process of forming the semiconductor layer contact holes 22a and 22b, Is concentrated on the side surface of the oxide semiconductor layer (5) adjacent to the oxide semiconductor layer (16), and finally, the oxide semiconductor layer (5) is subjected to electric shock or damage due to generation of static electricity or the like.

2, which is a graph showing the voltage-current characteristic curve of the thin film transistor Tr having the above-described configuration, the voltage-current characteristic curve has a tendency to move in the negative direction, The threshold voltage of the transistor Tr is shifted in the negative direction, and the characteristics of the thin film transistor Tr are deteriorated.

At this time, although it is shown in the drawing that the threshold voltage (Vth) of the thin film transistor is formed near -3.5 V, it has been experimentally found that the threshold voltage (Vth) tends to be shifted to the maximum degree of conductorization.

On the other hand, when the voltage-current characteristic curve is studied in detail, the change is not linear but the abrupt portion exists in the portion where the oxide semiconductor layer is damaged or linearly changed in the voltage-current curve due to electron accumulation And this portion becomes a portion where a hump is generated. In such a hump, when the thin film transistor Tr operates as a switching element, it takes a long time to be delayed on / off The characteristics of the switching device deteriorate.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, There is provided an array substrate including a thin film transistor (Tr) having a structure capable of suppressing damage to the oxide semiconductor layer itself due to accumulation and further suppressing the occurrence of a phenomenon in which a threshold voltage shifts in a negative voltage direction and the occurrence of a hump phenomenon For that purpose.

According to an aspect of the present invention, there is provided an array substrate comprising a plurality of pixel regions on a substrate on which a plurality of pixel regions are defined, the active regions being formed on both sides of the active region, A gate insulating film and a gate electrode sequentially formed on the oxide semiconductor layer in correspondence with the active region, and a gate electrode formed on the gate insulating film and the gate electrode, A first semiconductor layer contact hole exposing the conductive region located on both sides of the active region on the gate electrode and provided in the first portion and having a first length in the first width direction and a second semiconductor layer contact hole provided in the second portion, And a second semiconductor layer contact hole having a second length smaller than the first length in the second width direction; Includes the first and the second semiconductor layer and the oxide semiconductor layer and source and drain electrodes contact and spaced from each other and each of which is formed through a contact hole over the interlayer insulating film group.

Wherein the first portion includes one conductive region located on one side of the active region and the opposite side of the active region and the second portion includes one conductive region located on the other side of the active region, .

And the second length is 30 to 80% of the first length.

The first and second semiconductor layer contact holes may be configured such that one side end or one side end of each of the first and second semiconductor layer contact holes is located on the same line in the first and second longitudinal directions, 2 semiconductor layer contact holes are arranged in the first and second longitudinal directions with their respective one ends on different lines and at the same time their respective other ends are also arranged on different lines .

Furthermore, the source and drain electrodes are characterized in that, in the first and second longitudinal directions, the width of the electrode contacting the first portion is greater than the width of the electrode contacting the second portion.

In the array substrate according to the embodiment of the present invention, the phenomenon that the threshold voltage of the thin film transistor shifts in the negative voltage direction is suppressed and hump generation is suppressed in the voltage-current characteristic curve of the thin film transistor itself, It has an effect of having characteristics of an excellent thin film transistor.

In addition, the array substrate according to the embodiment of the present invention has the same channel ratio as that of the conventional thin film transistor, even though the area of the thin film transistor is reduced compared to the conventional array substrate, so that the operation as a switching or driving element is smooth The area of the thin film transistor occupied by the thin film transistor in the pixel region is reduced due to the area reduction of the thin film transistor without lowering the characteristics of the thin film transistor due to the decrease in the area of the thin film transistor.

FIG. 1 is a plan view of a portion of a conventional array substrate where a thin film transistor, which is a switching element, is formed in one pixel region. FIG.
2 is a graph showing a voltage-current characteristic curve of a thin film transistor provided in a conventional array substrate.
FIG. 3 is a plan view of a portion where a thin film transistor is provided in one pixel region of an array substrate including an oxide semiconductor layer according to an embodiment of the present invention. FIG.
4 is a graph showing voltage-current characteristics of a thin film transistor provided in an array substrate according to an embodiment of the present invention.
5A and 5B illustrate various plan views of a thin film transistor provided in an array substrate according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view of a portion cut along line VI-VI of FIG. 3; FIG.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

FIG. 3 is a plan view of a portion where a thin film transistor is provided in one pixel region of an array substrate including an oxide semiconductor layer according to an embodiment of the present invention. Referring to FIG. For convenience of explanation, the longitudinal direction of the gate electrode, which is one component of the thin film transistor, is defined as a first direction, and the direction of separation between the source electrode and the drain electrode perpendicular to the first direction is defined as a second direction, Dn1 for the direction and dn2 for the second direction are given.

As shown in the drawing, an array substrate 101 including a thin film transistor (Tr) having an oxide semiconductor layer 105 according to an embodiment of the present invention includes a gate wiring (not shown) And data lines (not shown) are provided.

At this time, in addition, common wiring (not shown) and power wiring (not shown) may be further provided. This is due to the fact that it is used as an array substrate for a liquid crystal display device or an organic electroluminescent device. Further, the configuration of the wiring can be changed depending on which mode of the liquid crystal display device is operated.

The gate wirings (not shown) and the data wirings (not shown) are basically wirings that are commonly provided regardless of the array substrate for a liquid crystal display device and the array substrate for an organic electroluminescent device, and common wirings (not shown) (Not shown) is provided on an array substrate for an organic electroluminescent device, and a common wiring (not shown) is provided in the case of an array substrate for a liquid crystal display Wiring or the like and is provided on an array substrate for an organic electroluminescence element.

A thin film transistor Tr having an oxide semiconductor layer 105 is formed in each pixel region.

The thin film transistor Tr is connected to the gate wiring (not shown) and the data wiring (not shown) when the array substrate 101 is an array substrate for a liquid crystal display device.

When the array substrate 101 is an array substrate for an organic electroluminescent device, the organic electroluminescent device includes a switching thin film transistor serving as a switching element and a driving thin film transistor serving as a driving element in each pixel region. The thin film transistor Tr may be connected to the gate wiring (not shown) and the data wiring (not shown), or the gate wiring (not shown) and the data wiring (not shown) (Not shown) or the scan line (not shown) without being connected to the scan line, and may be connected to one electrode of the thin film transistor and the power line (not shown) or the scan line

Therefore, the gate electrode 116 of the thin film transistor Tr may be connected to the gate wiring (not shown) or may be connected to other components without being connected to the gate wiring (not shown) have.

The thin film transistor Tr having the oxide semiconductor layer 105 having the most characteristic structure in the array substrate 101 according to the embodiment of the present invention is a thin film transistor having the oxide semiconductor layer 105, Tr at the bottom of the constituent elements.

In this case, the planar shape of the oxide semiconductor layer 105 has a third width w3 different from that of a conventional array substrate (1 in Fig. 1) having a rectangular or square shape having the same first width (w1 in Fig. 1) And a second portion A2 having a fourth width w4 that is smaller than the third width w3. At this time, the third width w3 is set in the first direction dn1, which is the longitudinal direction of the gate electrode 116 of the oxide semiconductor layer 105 of the thin film transistor Tr included in the conventional array substrate (1 in Fig. 1) (W1 in Fig. 1).

The oxide semiconductor layer 105 is provided so as to have a shape having the two-dimensional width w3 and w4 as described above, will be described later in detail.

Next, the gate electrode 116 overlaps with the oxide semiconductor layer 105 having such a structure and through a gate insulating film (not shown). At this time, the gate electrode 116 is formed corresponding to the first portion A1 having the third width w3 of the oxide semiconductor layer 105.

In the oxide semiconductor layer 105, a portion overlapping the gate electrode 116 is a region where a channel is formed.

In this case, when the gate electrode 116 is formed in a rectangular shape as shown in the drawing, the longitudinal direction of the gate electrode 116 in the channel formed in the oxide semiconductor layer 105, that is, And the width of such a channel is a very important factor for the characteristics of the thin film transistor Tr. As the channel width increases, the channel ratio defined by the width of the channel divided by the channel length (the width of the region where the gate electrode and the oxide semiconductor layer overlap in the second direction overlap) increases, do.

Therefore, in the array substrate 101 according to the embodiment of the present invention, the gate electrode 116 is disposed so as to overlap with the first portion A1 having the third width w3 of the oxide semiconductor layer 105 This is to make the channel ratio equal to that of the thin film transistor Tr provided in the conventional array substrate (1 in FIG. 1).

An interlayer insulating film (not shown) is formed on the entire surface of the array substrate 101 above the gate electrode 116. A first semiconductor layer contact hole 122a and a second semiconductor layer contact hole 122b are formed in the interlayer insulating layer (not shown) to expose the oxide semiconductor layer 105 exposed on both sides of the gate electrode 116, Layer contact hole 122b.

At this time, the first semiconductor layer contact hole 122a is located corresponding to the first portion A1 having the third width w3 of the oxide semiconductor layer 105, and the second semiconductor layer contact hole 122b ) Is located in the second portion (A2) having the fourth width (w4) of the oxide semiconductor layer (105).

The first semiconductor layer contact hole 122a has a second length 12 in the first direction dn1 in the first portion A1 of the oxide semiconductor layer 105. [ 1) of the first and second semiconductor layer contact holes (22a and 22b in FIG. 1) and the second length (12 in FIG. 1) of the first and second semiconductor layer contact holes The same level.

The second semiconductor layer contact hole 122b may have a third length l3 smaller than the second length l2 in the second direction A2 of the oxide semiconductor layer 105 in the first direction dn1. ). In this case, the third length 13 is preferably 30 to 80% of the second length 12.

When the third length 13 is smaller than 30% of the second length 12, the channel width is reduced, so that it does not have the same channel ratio as the conventional thin film transistor (Tr in FIG. 1) 1) is provided at a level similar to that of the thin film transistor (Tr in FIG. 1) provided in the conventional array substrate (1 in FIG. 1) when the second length is larger than 80% It has been experimentally found that the voltage Vth is shifted to a negative voltage or a hump occurs.

The third length 13 of the second semiconductor layer contact hole 122b is 30 to 80% of the second length 12 of the first semiconductor layer contact hole 122a, Level characteristic and a threshold voltage of the thin film transistor Tr are shifted in the negative voltage direction and suppresses the occurrence of a hump.

At this time, the first and second semiconductor layer contact holes 122b are formed in the first and second semiconductor layer contact holes 122b in the direction perpendicular to the second and first lengths 12 and 13, And each width has the same size as the fifth width w5. At this time, the fifth width w5 is equal to the second width (w2 in Fig. 1) of the first and second semiconductor layer contact holes (22a and 22b in Fig. 1) of the conventional array substrate .

 The first semiconductor layer contact hole 122a and the second semiconductor layer contact hole 122b have different lengths 12 and 13 in the first and second semiconductor layer contact holes 122a and 122b The oxide semiconductor layer 105 itself is prevented from being damaged due to the electrons accumulated in the generation of static electricity, and at the same time, the oxide film of the thin film transistor Tr itself Suppresses the development of the voltage-current characteristic curve itself or the threshold voltage to shift in the negative voltage direction (negative direction), and suppresses the generation of the hump in the voltage-current characteristic curve of the thin film transistor Tr.

In the case of the conventional array substrate (1 in FIG. 1), when forming the first and second semiconductor layer contact holes (22a and 22b in FIG. 1) for exposing the oxide semiconductor layer (5 in FIG. 1) 1) are positioned adjacent to each other in the longitudinal direction of the gate electrode (16 in Fig. 1) near both ends of the first and second semiconductor layer contact holes (22a, 22b in Fig. 1) The accumulation at both ends of the gate electrode (16 in Fig.

However, in the case of the array substrate 101 according to the embodiment of the present invention, the second semiconductor layer contact hole 122b has the third length 13 and the second semiconductor layer contact hole 122b, The second portion A2 of the oxide semiconductor layer 105 provided therein is relatively very thin from one end of the gate electrode 116 to the thin film transistor (Tr in FIG. 1) configured in the conventional array substrate 1 It is positioned with a large spacing.

Accordingly, in the process of forming the first and second semiconductor layer contact holes 122a and 122b exposing the surface of the oxide semiconductor layer 105, the amount of electrons accumulated on both ends of the gate electrode 116 is reduced Thereby preventing damage to the oxide semiconductor layer 105 due to static electricity and suppressing the voltage-current characteristic curve of the thin film transistor Tr itself, that is, suppressing the shift of the threshold voltage in the negative voltage direction At the same time, the voltage-current characteristic curve is linearly increased and decreased, thereby suppressing the occurrence of the hump.

4 is a graph illustrating voltage-current characteristics of a thin film transistor provided in an array substrate according to an embodiment of the present invention.

As shown in the figure, a voltage-current characteristic curve of a thin film transistor provided in an array substrate according to an embodiment of the present invention includes a portion where a sudden current is generated due to a change in gate voltage applied to a gate electrode, A portion having a magnitude of about -12 to -10 W-7 A (1E-12 to 1E-07 (A)) is located at about 0 V and more precisely at about 0.2 V.

Therefore, the thin film transistor provided on the array substrate according to the embodiment of the present invention has a voltage-current characteristic curve or a threshold voltage (Vth) which is a minimum gate voltage capable of turning on the thin film transistor, V level, which means that it is not shifted in the negative voltage direction.

In addition, in the portion where the current value linearly changes according to the gate voltage change, that is, the current value is about -7 V to 10 -4 V-A (1E-07 to 1E-04 (A) It can be seen that a portion where the curve does not change linearly is not generated in the portion having the curve. This would mean that the hump was not generated.

Next, referring to FIG. 3, the first and second semiconductor layer contact holes 122a and 122b are formed on the interlayer insulating layer (not shown) having the first and second semiconductor layer contact holes 122a and 122b, And source and drain electrodes 133 and 136 which are in contact with the oxide semiconductor layer 105 and are spaced apart from each other.

The source electrode 133 is formed in contact with the oxide semiconductor layer 105 through the first semiconductor layer contact hole 122a and the oxide semiconductor layer 105 is formed through the second semiconductor layer contact hole 122b, The source electrode 133 and the drain electrode 136 may be arranged to correspond to the first semiconductor layer contact hole 122a by changing the positions of the source electrode 133 and the drain electrode 136. [ The drain electrode 136 may be formed and the source electrode 133 may be provided corresponding to the second semiconductor layer contact hole 122b.

In this case, the array substrate 101 according to the embodiment of the present invention is formed such that the oxide semiconductor layer 105 has a first portion A1 having a third width w3 and a second portion w2 having a fourth width w4 The source electrode 133 is formed in the electrode diagram of the source and drain electrodes 133 and 136 overlapped with the first portion A1 of the oxide semiconductor layer 105 And the width w6 of the source electrode 133 overlapping with the first portion A1 of the oxide semiconductor layer 105 overlaps the drain electrode of the oxide semiconductor layer 105 overlapping the second portion A2 of the oxide semiconductor layer 105 136 has a larger size than the width w7 of the first and second electrodes 136 and 136. [

Although the width w6 of the source electrode 133 is larger than the width w7 of the drain electrode 136 in the figure, the source and drain electrodes 133 and 136 The drain electrode 136 has a width larger than the width of the source electrode 133. [

On the other hand, the oxide semiconductor layer 105, the gate insulating film (not shown), the gate electrode 116, the interlayer insulating film (not shown), and the source and drain electrodes 133 and 136, Film transistor Tr.

In the case of the array substrate 101 according to the embodiment of the present invention having the thin film transistor Tr having such a structure, the phenomenon that the threshold voltage of the thin film transistor Tr shifts in the negative voltage direction is suppressed, The hump occurrence is suppressed in the voltage-current characteristic curve (see FIG. 4) of the thin film transistor Tr itself, thereby realizing the advantageous effect of the characteristics of the thin film transistor Tr as compared with the conventional array substrate 1 Able to know.

In the case of the array substrate 101 according to the embodiment of the present invention, the area of the thin film transistor Tr is more precisely the sum of the area of the oxide semiconductor layer 105 and one of the source and drain electrodes 133 and 136 The area occupied by the thin film transistor Tr in the pixel region is reduced by reducing the area of the pixel region compared with the thin film transistor (Tr in FIG. 1) provided on the conventional array substrate (1 in FIG. 1) 1) of the first embodiment.

When the area of the thin film transistor Tr itself becomes small, a desired level of characteristics may not be obtained as a switching or driving element due to a change in a channel ratio. However, the array substrate 101 according to the embodiment of the present invention Though the area of the thin film transistor Tr is reduced compared to the conventional one, the TFT has the same channel ratio as that of the conventional thin film transistor (Tr in FIG. 1), so that the thin film transistor Tr, There is no problem caused by area reduction.

Meanwhile, in the array substrate 101 according to the embodiment of the present invention, a protective layer (not shown) is formed to cover the thin film transistor Tr.

Although not shown in the figure, the pixel electrode (not shown) is connected to one electrode of the thin film transistor Tr, that is, one of the source and drain electrodes 133 and 136, (Not shown) or a first electrode (not shown).

That is, when the array substrate 101 is an array substrate for a liquid crystal display device, the pixel electrode (not shown) may be formed in contact with the drain electrode 136 of the thin film transistor Tr.

In the case where the array substrate 101 is an array substrate for an organic electroluminescent device, when the thin film transistor Tr is a driving thin film transistor, the source electrode or the drain electrode 133 and 136 are connected to the first electrode An organic light emitting layer (not shown) and a second electrode (not shown) may be formed on the first electrode (not shown) so as to form an organic light emitting diode (not shown) together with the first electrode Not shown) may be further provided.

In the exemplary embodiment of the present invention, one end of the second semiconductor layer contact hole 122b and one end of the first semiconductor layer contact hole 122a are arranged on the same line And the other ends of the first and second semiconductor layer contact holes 122a and 122b are not located on the same line, this can be modified in various forms.

5A and 5B showing various plan views of the thin film transistor Tr included in the array substrate 101 according to the embodiment of the present invention, The second semiconductor layer contact hole 122b is located at the center of the first semiconductor layer contact hole 122a so that the first and second semiconductor layer contact holes 122a, 2 semiconductor layer contact holes 122b may not be located on the same line.

5B, the other end of the second semiconductor layer contact hole 122b and the other end of the first semiconductor layer contact hole 122a are formed in the same linear shape as the planar structure of the thin film transistor Tr, And one end of each of the first and second semiconductor layer contact holes 122a and 122b may not be located on the same line.

In this case, in the case of the array substrate (301 in FIG. 5A, 301 in FIG. 5B) according to the modified example of this embodiment, the second semiconductor layer contact hole 122b is formed with the change in the position of the second semiconductor layer contact hole 122b. The position of the second portion A2 of the oxide semiconductor layer 105 necessary for realizing the positional change of the oxide semiconductor layer 105 and the electrode contacting the oxide semiconductor layer 105 through the second semiconductor layer contact hole 122b (The second portion A2 of the oxide semiconductor layer 105 and the second semiconductor layer contact hole 122b and the drain electrode 136) in addition to the positional change of the component (the drain electrode 136 in FIG. The positions and sizes of the other components except for the elements are the same as those of the array substrate 101 (refer to FIG. 3) according to the embodiment of the present invention.

In the case of the array substrate (301 in FIG. 5A, 301 in FIG. 5B) according to various modifications of the embodiment of the present invention having the planar shape of the thin film transistor Tr shown in FIGS. 5A and 5B, It is obvious that the same effects as those of the array substrate 101 according to the embodiment of the present invention are realized.

Hereinafter, the cross-sectional structure of the array substrate according to the embodiment of the present invention will be described. Since the sectional structure of the array substrate according to various modified embodiments of the present invention is the same as that of the array substrate according to the embodiment of the present invention, the sectional structure of the array substrate according to the embodiment of the present invention will be mainly described.

Fig. 6 is a cross-sectional view of the portion cut along the cutting line VI-VI of Fig. 3; Fig. At this time, for convenience, a region where the thin film transistor Tr is formed in each pixel region is defined as an element region DA.

As shown in the drawing, the array substrate 101 according to the embodiment of the present invention is provided with a light shielding pattern 102 in each device area DA on a transparent insulating substrate 100 made of glass or plastic, A buffer layer 103 is formed on the entire surface of the substrate 100 so as to cover the light shielding pattern 102.

The thin film transistor Tr having the oxide semiconductor layer 105 tends to react sensitively to light and when the oxide semiconductor layer 105 is continuously exposed to the light, The ON / OFF characteristic of the thin film transistor Tr tends to be changed by generating a parasitic current caused by the light incident on the oxide semiconductor layer 105. Therefore, the light shielding pattern 102 is formed to prevent external light from entering the oxide semiconductor layer 105 .

However, the light-shielding pattern 102 is not necessarily provided, and may be omitted. If the light-shielding pattern 102 is omitted, the buffer layer 103 provided on the light-shielding pattern 102 may be omitted.

The shielding pattern 102 and the buffer layer 103 are shown as an example in the array substrate 101 according to the embodiment of the present invention. However, as described above, the shielding pattern 102 and the buffer layer 103 are omitted .

The device region DA above the buffer layer 103 is provided with an active region 105a corresponding to a central portion of the device region DA and is made conductive on both sides of the active region 105a. And an oxide semiconductor layer 105 composed of source and drain regions 105b and 105c.

3, the active region 105a and the source region 105b form a first portion A1 having a third width w3 in plan view, and the drain region 105a and the source region 105b form a first portion A1, And the region 105c forms a second portion A2 having a fourth width w4 that is smaller than the third width w3. Since the planar shape of the oxide semiconductor layer 105 has been described in detail with reference to FIG. 3, further description is omitted.

6, the oxide semiconductor layer 105 having such a structure may be formed of any one of oxide semiconductor materials such as IGZO (Indium Gallium Zinc Oxide), ZTO (Zinc Tin Oxide), and ZIO (Zinc Indium Oxide) .

Such an oxide semiconductor material is characterized in that the conductive characteristic is improved upon exposure to a plasma having a reaction atmosphere containing any one or more of a specific reaction gas such as helium (He), argon (Ar), and nitrogen (N ₂ ) to be.

Next, an active region (105a) and the source and drain regions (105b, 105c), wherein the oxide semiconductor active region (105a) and the substrate 100 over the inorganic insulating material, for example silicon oxide layer 105 is made of a (SiO ₂ ) Or a silicon nitride (SiNx) film.

At this time, the gate insulating film 109 is formed in the same plane shape as the gate electrode 116 and the gate wiring (not shown) positioned on the gate insulating film 109. This is because the gate insulating film 109 and the gate electrode 116 and the gate wiring (not shown) located on the gate insulating film 109 are patterned by the same mask process. Thus, the gate insulating film 109 and the gate electrode 116 The source and drain regions 105b and 105c, which are a component of the oxide semiconductor layer 105, are formed to have the same planar shape.

Next, the device region DA is provided with a rectangular gate electrode 116 which overlaps the center portion of the oxide semiconductor layer 105, that is, the active region 105a of the first portion A1, have.

The gate electrode 116 may be branched from a gate line (not shown). In the case of an array substrate for an organic electroluminescent device, the gate electrode 116 is not connected to a gate line (not shown) And may be connected to one electrode of a switching thin film transistor (not shown) operating as a switching element.

Next, an interlayer insulating film 120 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the entire surface of the substrate 100 over the gate wiring (not shown) and the gate electrode 116 .

The first and second semiconductor layer contact holes are formed in the interlayer insulating layer 120 to expose the source region 105b and the drain region 105c respectively located on both sides of the active region 105a of the oxide semiconductor layer 105, (122a, 122b).

3, the first semiconductor layer contact hole 122a has a second length 12 in the longitudinal direction of the gate electrode 116, that is, in the first direction dn1, The second semiconductor layer contact hole 122b has a third length 13 smaller than the second length 12 and is formed in parallel with the first semiconductor layer contact hole 122a. Since the planar shapes of the first and second semiconductor layer contact holes 122a and 122b are also described in detail with reference to FIG. 3, further description is omitted.

Referring to FIG. 6, on the interlayer insulating layer 120 having the first and second semiconductor layer contact holes 122a and 122b, data defining the pixel region intersect with the gate wiring (not shown) Wiring (not shown) is formed.

Next, in the element region DA, the source region 105b of the oxide semiconductor layer 105 is exposed through the first semiconductor layer contact hole 122a having the second length (12 in FIG. 3) An electrode 133 is formed on the first semiconductor layer 105 and the second semiconductor layer contact hole 122b which is spaced apart from the source electrode 133 and has the third length (13 in FIG. 3) And the drain electrode 136 is formed in contact with the drain region 105c.

In this case, the source electrode 133 may be connected to the data line (not shown). When the array substrate 101 is an array substrate (not shown) for an organic light emitting diode, (Not shown) or the like. When the power wiring (not shown) is provided, the power wiring (not shown) is formed on the same layer on which the gate wiring (not shown) or the data wiring (not shown) is formed.

On the other hand, the oxide semiconductor layer 105, the gate insulating film 109, the gate electrode 116, and the first semiconductor having the second length (12 in Fig. 3), which are sequentially stacked in the device region DA, An interlayer insulating film 120 provided with a first semiconductor layer contact hole 122a having a first contact hole 122a and a third contact hole 123 and a source electrode 133 and a drain electrode 136 Form a thin film transistor Tr.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) or an organic insulating material such as benzocyclobutene (BCB) is formed on the entire surface of the substrate 100 over the thin film transistor Tr. ) Or a photo-acryl.

Although not shown, a drain contact hole is formed in the passivation layer 140 to expose the drain electrode 136. The drain contact hole may be formed on the passivation layer 140 having the drain contact hole. And the pixel electrode or the first electrode may be formed in each pixel region.

In addition, when the array substrate 101 is an array substrate for a liquid crystal display device that performs lateral electric field driving, a common electrode may be further provided on the array substrate 101. In this case, And a plurality of common electrodes are formed in each pixel region, and the common electrode may be configured to alternate with the bar-shaped pixel electrode in each pixel region.

In addition, when the array substrate 101 is an array substrate for a liquid crystal display device that performs fringe field driving, an insulating layer is further provided on the pixel electrodes, and a common electrode is formed on the entire surface of the insulating layer, The common electrode may include a plurality of openings having a bar shape corresponding to the pixel electrodes provided in the pixel regions. At this time, the positions of the pixel electrode and the common electrode may be changed. In this case, a bar-shaped opening is omitted in the common electrode, and a bar-shaped opening is formed in the pixel electrode located above the common electrode do.

In addition, when the array substrate 101 is an array substrate for an organic electroluminescence device, the organic light emitting layer and the second electrode may be further formed on the first electrode.

In the array substrate 101 according to the embodiment of the present invention having such a configuration, the phenomenon that the threshold voltage of the thin film transistor Tr shifts in the negative voltage direction is suppressed, and the voltage-current The occurrence of the hump in the characteristic curve is suppressed, so that it has an advantageous effect of the characteristics of the thin film transistor Tr as compared with the conventional array substrate (1 in Fig. 1).

The array substrate 101 according to the embodiment of the present invention has the same level as the conventional thin film transistor Tr even though the area of the thin film transistor Tr is smaller than that of the conventional array substrate 1 The operation as a switching or driving element can be smoothly performed. As a result, the characteristics of the thin film transistor Tr are not deteriorated due to the reduction of the area of the thin film transistor Tr, The area occupied by the thin film transistor Tr in the region is reduced and the aperture ratio is improved.

The present invention is not limited to the above-described embodiments and modifications, and various changes and modifications can be made without departing from the spirit of the present invention.

101: array substrate
105: oxide semiconductor layer
105a: active region (of the oxide semiconductor layer)
105b and 105c: source and drain regions (of the oxide semiconductor layer)
116: gate electrode
122a and 122b: first and second semiconductor layer contact holes
133: source electrode
136: drain electrode
A1, A2: first and second portions (of the oxide semiconductor layer)
dn1, dn2: first and second directions
l2, l3: the second and third lengths
Tr: thin film transistor
w3: width of the first part (third width)
w4: width of the second part (fourth width)
w5: width of the first and second semiconductor layer contact holes (fifth width)
w6: width of the source electrode (sixth width)
w7: width of the drain electrode (seventh width)

Claims (6)

A first portion having a first width and a second portion having a second width smaller than the first width, the first portion having a first width and a second portion having a second width smaller than the first width, the pixel portion having an active region and a region made conductive on both sides of the active region, An oxide semiconductor layer having two portions;
A gate insulating film and a gate electrode sequentially formed on the oxide semiconductor layer in correspondence with the active region;
A first semiconductor layer contact hole exposing a conductive region located on both sides of the active region on the gate electrode and provided in the first portion and having a first length in the first width direction, And a second semiconductor layer contact hole having a second length smaller than the first length in the second width direction;
A source electrode and a drain electrode which are in contact with the oxide semiconductor layer through the first and second semiconductor layer contact holes,
≪ / RTI >
The method according to claim 1,
Wherein the first portion includes one active region and one electrically conductive region located on one side of the active region and the second portion is a conductive region located on the other side of the active region .
The method according to claim 1,
Wherein the second length is 30-80% of the first length.
The method according to claim 1,
Wherein the first and second semiconductor layer contact holes are configured so that one side end or one side end of each one of the first and second semiconductor layer contact holes is positioned on the same line in the first and second longitudinal directions.
The method according to claim 1,
The first and second semiconductor layer contact holes are arranged in the first and second longitudinal directions with their respective one ends on different lines and at the same time their respective other ends are also arranged on different lines And an array substrate.
The method according to claim 1,
Wherein the source and drain electrodes are arranged such that the width of the electrode in contact with the first portion in the first and second longitudinal directions is greater than the width of the electrode in contact with the second portion.

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