JP2014186341A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device reduced in electric resistance of wiring.SOLUTION: A display device includes a thin film transistor formed on the upper part of a substrate and wiring which is formed on the upper part of the substrate, is provided along the sides of a display part of the substrate and is electrically connected to a flat cable and the thin film transistor. The wiring has first wiring formed on the same layer as the source electrode or the drain electrode of the thin film transistor and second wiring formed on the upper part of the first wiring via an insulating film. The first wiring is provided in parallel with the second wiring and electrically connected to the second wiring via a plurality of contact holes bored in the insulating film.

Description

The present invention relates to a wiring structure of an integrated circuit formed using a thin film transistor (hereinafter referred to as TFT) on a substrate having an insulating surface.
The present invention relates to a wiring structure of a peripheral circuit integrated liquid crystal display device formed using a TFT on a substrate having an insulating substrate.

A technique is known in which a silicon film having crystallinity is formed on a glass substrate or a quartz substrate, and a thin film transistor (hereinafter referred to as TFT) is manufactured using the silicon film.

This thin film transistor is called a high temperature polysilicon TFT or a low temperature polysilicon TFT.

The high-temperature polysilicon TFT is formed on a substrate having high heat resistance, for example, a quartz substrate, in order to obtain a crystalline silicon film constituting the active layer by heating at 800 ° C. to 900 ° C.

On the other hand, the low-temperature polysilicon TFT is formed on a substrate having a relatively low heat resistance such as glass using a process of 600 ° C. or lower.

In addition, high-temperature polysilicon TFTs are easy to integrate TFTs with uniform characteristics on a substrate.
In addition, various process conditions and manufacturing apparatuses in the conventional IC process can be used. On the other hand, the low-temperature polysilicon TFT has a feature that it can use a glass substrate that is inexpensive and easy to enlarge as a substrate.

In the current technology, there is no significant difference in characteristics between the high-temperature polysilicon TFT and the low-temperature polysilicon TFT.

That is, in terms of mobility, the S value is about 200 to 400 (mV), about 50 to 100 (cm ² / Vs).
/ dec) (V _D = 1V) is obtained in both cases.

Research is being conducted on a technique for constructing a so-called peripheral circuit integrated liquid crystal display device in which an integrated circuit, an active matrix circuit, and a peripheral circuit for driving the circuit are formed on the same substrate using such TFTs. Has been.

However, conventional high-temperature polysilicon TFTs and low-temperature polysilicon TFTs are greatly inferior to the characteristics of MOS transistors using single crystal silicon wafers. Generally, the S value of a MOS transistor using a single crystal silicon wafer is 60-7.
0 (mV / dec).

Even if it is a low-temperature polysilicon TFT or a high-temperature polysilicon TFT, since the mobility is low, the driving frequency of the TFT alone is about several MHz or less.

For example, even if the peripheral circuit of the liquid crystal display device is configured, it is several tens of MH required for display.
A clock signal or video signal of z or more cannot be directly input and driven.

For this reason, the wiring for transmitting the clock signal and the video signal is divided into a plurality of wirings, and the frequency of the signal is lowered and supplied to the TFT (referred to as divided driving). For example, a 10 MHz clock signal is divided into four lines, each line is set to 2.5 MHz, and each TFT is driven at this low frequency. Therefore, problems such as an increase in the installation area due to an increase in the number of wires and the number of TFTs occur.

On the other hand, a TFT having a performance comparable to that of a MOS transistor using a single crystal silicon wafer has been developed by a study by the present inventors, although it is a TFT using a crystalline silicon film.

This TFT uses, as an active layer, a crystalline silicon film having a crystal structure having continuity in a predetermined direction, for example, a source / drain direction, and having a crystal grain boundary extending in the predetermined direction. .

In this crystalline silicon film, a small amount of a metal element that promotes crystallinity, such as nickel, is introduced into the amorphous silicon film, heated at a temperature of 500 ° C. to 630 ° C., for example 600 ° C., and laterally grown, and then thermally oxidized. It is obtained by forming a film.

This TFT has extremely excellent characteristics such as an S value of 100 (mV / dec) or less and a mobility of 200 (cm ² / Vs) or more. And it can drive by the frequency of several dozen MHz-several hundred MHz or more by itself. By using such TFTs, TFTs capable of high-speed driving can be integrated and formed on a large-area substrate.

As a result, not only a circuit with extremely excellent performance can be obtained, but also the number of thin film transistors and wirings required for driving can be greatly reduced as compared with the prior art, which greatly contributes to downsizing and high integration of the device. Can do.

However, like the peripheral matrix integrated active matrix liquid crystal display device,
When an integrated circuit is configured with TFTs over a large area such as several tens of cm □, when the integrated circuit is driven at a high frequency such as several tens of MHz to several hundreds of MHz or more, the “round” of the waveform of the high-frequency signal transmitted through the wiring is extremely high. It becomes a big problem.

Here, a peripheral circuit of the liquid crystal display device will be described as an example. FIG. 5 shows a top view of a peripheral circuit integrated active matrix liquid crystal display device.

In FIG. 5, a counter substrate 902 having a counter electrode (not shown) on the inside is provided through a liquid crystal (not shown) so as to face the substrate 901.

A data line (source line) driving peripheral circuit 903, a scanning line (gate line) driving peripheral circuit 904, a pixel electrode and a switching thin film transistor connected to the electrode are provided on a substrate 901. An active matrix display portion 905 is provided.

A flat cable 9 extending from an external circuit for supplying a signal to the liquid crystal display device
06 is electrically connected to the peripheral wiring 907 at the end of the substrate 901. The peripheral wiring 907 is connected to the wirings 908 and 909 in the peripheral circuits 903 and 904.

The peripheral wiring 907 and the wirings 908 and 909 in the peripheral circuit are a plurality of wirings arranged in parallel or substantially in parallel with a line width and interval of about several tens of μm to several hundreds of μm.

These wirings are simultaneously formed in the step of forming the thin film transistors of the peripheral circuits 903 and 904 and the active matrix circuit of the display portion 905, and are made of a conductive material, for example, an aluminum thin film.

Among these wirings, there are those that transmit signals having a very high frequency, for example, 10 MHz or more. A video signal line for transmitting a video signal and a clock signal line for supplying a clock signal are typical.

Generally, the clock frequency is 12.5 in VGA (640 × 480 × 3 (RGB three colors)).
The video signal has a higher frequency as the resolution of the image increases in accordance with the clock signal.

In particular, in a peripheral circuit integrated liquid crystal display device, the peripheral circuits 903 and 904 for driving the display unit 905 having a size of several cm □ to several tens of cm □ are usually provided along each side of the display unit. , And has a length of several centimeters to several tens of centimeters along the side.

Each of the peripheral circuits 903 and 904 has wiring provided through the circuit from end to end. Clock signal lines and video signal lines are also such wiring. Therefore, these wirings have a length of several centimeters to several tens of centimeters inside the peripheral circuit.

If the wiring has such a length, even if the wiring is made of a material having high electrical conductivity such as aluminum, the electrical resistance of each wiring becomes very large.

Also, peripheral wiring 90 for transmitting signals from the flat cable 906 to the peripheral circuit.
7 also has a line width of several tens of μm to several hundreds of μm and a length of several centimeters to several tens of centimeters in some cases.

Therefore, considering the length of the peripheral wiring 907 and the lengths of the wirings 908 and 909 in the peripheral circuit, signals are transmitted by extremely long wiring that cannot be considered on a scale like a conventional IC chip. Become.

On the other hand, since the wirings arranged in parallel are separated by only about several tens of μm to several hundreds of μm, capacitive coupling tends to occur when a high frequency is applied.

Further, in the case of a liquid crystal display device, a counter electrode (not shown) provided on the entire surface of the counter substrate 907.
Exists. From the viewpoint of protecting the peripheral circuits 903 and 904 and simplifying the manufacturing process, not only the display portion 905 but also the peripheral circuits 903 and 904 and the peripheral wiring 907 are often arranged on a surface facing the counter substrate.

Therefore, a counter electrode exists facing the peripheral wiring 907 and the wirings 908 and 909 in the peripheral circuit, and capacitive coupling occurs between these wiring and the counter electrode.

As a result, the transmission signal waveform is deteriorated due to the capacitance between the wirings, the capacitance between the wirings and the counter electrode (the electrode on the inner side of the substrate provided opposite to the liquid crystal) and the high electric resistance of each wiring, so-called “Margin” occurs.

In other words, the waveform of the signal transmitted by the wiring has a good shape (for example, a rectangle) at the input stage.
Even if it has, the rounding will occur as it approaches the end of the wiring, and the rise of the waveform will be delayed or the waveform will be disturbed.

When the rounding of the signal waveform increases, the operation timing of the circuit is delayed, or erroneous video information is transmitted to the pixel, resulting in malfunction or image disturbance.

In the liquid crystal display device, this problem becomes more important as the size of the display unit increases and as the display resolution is increased and the drive frequency is increased.

In particular, in a circuit 903 that drives a data line (source line) among peripheral circuits, a high-frequency signal such as several tens of MHz to several hundreds of MHz is applied to an extremely long wiring.
The effect of “namari” was significant and a serious problem.

Incidentally, even in an integrated circuit composed of chips using a single crystal silicon wafer, several tens to several ones.
Those operating at a drive frequency of 00 MHz are becoming more common, but this is 1-2 cm.
Since all the integrated circuits are arranged in a chip of about □, the length of the wiring is short, and “margin” is not so much a problem as compared with such a large-area liquid crystal display device.

In order to reduce the capacitance between the wirings, it is necessary to increase the distance between the wirings and lower the dielectric constant between the wirings.

However, in order to increase the distance between the wirings, the area necessary for arranging the wirings and the circuits using the wirings increases, resulting in an increase in the size of the entire apparatus. Further, if the width of the wiring is reduced, the electrical resistance increases even if the distance between the wirings is increased, which is not preferable.

Further, the distance between the wiring and the counter electrode is relatively small (the interlayer insulating film is 1 to 2 μm, the liquid crystal layer is 3 to 8 μm, and the total is about 10 μm). The cell gap cannot be increased due to optical problems. Even if it is attempted to adjust the distance between the wiring and the counter electrode depending on the thickness of the interlayer insulating film, it is difficult to increase the distance to sufficiently reduce the capacitance.

  Therefore, it is difficult for the current technology to effectively reduce the capacitance between the wirings.

Further, it is considered that the electrical resistance can be reduced by increasing the line width of the wiring and increasing the thickness of the wiring. However, if the line width of the wiring is increased, the distance between the adjacent wirings is reduced and the possibility of a short circuit is increased. In addition, the capacitance between the wires also increases. Furthermore, the capacity with the counter electrode increases.

On the other hand, it is not preferable to increase the thickness of the wiring because hillocks are easily generated by heating during the manufacturing process and a short circuit with the wiring intersecting with the interlayer insulating film is likely to occur.

The present invention solves this problem. That is, a high-frequency signal of several MHz to several tens of MHz or more is applied to an integrated circuit using a thin film transistor formed on a substrate having a relatively large insulating surface, particularly a peripheral circuit integrated liquid crystal display device. An object of the present invention is to reduce the electrical resistance of a wiring without increasing the capacitance.

In order to solve the above problems, one of the inventions disclosed in this specification is:
A thin film transistor formed over a substrate having an insulating surface;
A silicon nitride film formed on the gate electrode of the thin film transistor;
An organic resin film formed on the silicon nitride film;
A first wiring formed on the organic resin film,
The first wiring is electrically connected to a second wiring made of the same material as the gate electrode through a contact hole provided in the silicon nitride film and the organic resin film. To do.

A thin film transistor formed over a substrate having an insulating surface;
A silicon nitride film formed on the thin film transistor;
An organic resin film formed on the silicon nitride film;
Wiring formed on the organic resin film,
The wiring is characterized in that it is electrically connected to a gate electrode of the thin film transistor through a contact hole provided in the silicon nitride film and the organic resin film.

  The above configuration is particularly effective when a high frequency is applied to the wiring.

According to the present invention, in an integrated circuit using a thin film transistor, particularly a peripheral circuit integrated liquid crystal display device, signal waveform rounding can be remarkably reduced in a wiring to which a signal having a high frequency of several tens of MHz or more is applied. Moreover, the structure of the present invention could be obtained without increasing the number of steps compared to the conventional manufacturing steps.

The configuration of the semiconductor device of the present invention can be applied to any wiring in an integrated circuit configured using a thin film transistor on a substrate having a large area of several cm □, and the signal waveform is rounded and deteriorated. Therefore, the operation speed can be improved, and the image quality can be improved in an apparatus for displaying an image.

The invention disclosed in this specification not only constitutes a peripheral circuit formed on the same substrate as the active matrix circuit of the transmissive and reflective active matrix liquid crystal display devices,
In addition, it can be used in a display device using an EL (electroluminescence) element and other various circuits using a thin film transistor.

FIG. 10 illustrates a configuration example of a semiconductor device using the present invention. FIG. 6 shows a manufacturing process of the example. FIG. 6 shows a manufacturing process of the example. FIG. 6 shows a manufacturing process of the example. FIG. 6 is a top view of a peripheral circuit integrated active matrix liquid crystal display device.

FIG. 1 shows a configuration example of a semiconductor device using the present invention. Fig.1 (a) shows wiring and TFT
The longitudinal cross-sectional view of (thin film transistor) is shown. In FIG. 1A, a base film 102 made of a silicon oxide film is formed on a substrate 101. A TFT is provided thereon.

The TFT includes an active layer 103 made of a crystalline silicon film, a gate insulating film 104, and a gate electrode 105.
, Source electrode 109 and drain electrode 110. Reference numerals 107 and 112 denote interlayer insulating films, and a contact hole 108 is formed in 107.

In FIG. 1A, the wiring 111 is electrically connected in parallel to the auxiliary wiring 106 through a plurality of contact holes with an interlayer insulating film 107 interposed therebetween. A first wiring 106 is provided over the substrate 101 having an insulating surface, an interlayer insulating film 107 is provided over the first wiring 106, a second wiring 111 is provided over the interlayer insulating film 107, and It can also be expressed that the wiring 106 and the second wiring 111 are electrically connected in parallel through a contact hole 108 formed in the interlayer insulating film 107.

That is, the conventional wiring is composed of only one layer of the wiring 111, but in the configuration of FIG. 1, an auxiliary electrode is provided in the same layer as the gate electrode 105. Then, the interlayer insulating film 107 is
A plurality of contact holes 108 provided along the line direction of the wiring 111 allow the wiring 111
And the auxiliary wiring 106 are electrically connected in parallel to form a two-layer structure. Needless to say, an auxiliary wiring electrically connected in parallel to the wiring 111 via another interlayer insulating film, for example, 112 may be provided.

The auxiliary wiring 106 shown in FIG. 1 can be formed simultaneously with the gate electrode 105.
That is, when patterning a thin film of a conductive material to be the gate electrode 105, the auxiliary wiring can be obtained by patterning at the same time. Therefore, in the configuration of FIG. 1, the gate electrode 105 and the auxiliary wiring 106 are made of the same material.

FIG.1 (b) is AA 'sectional drawing of Fig.1 (a). As shown in FIG.
The wiring 111 and the auxiliary wiring 106 are in electrical contact at a plurality of locations and are electrically connected in parallel.

The larger the number of contact holes forming the connection between the wiring 111 and the auxiliary wiring 106, the better the electrical connection between the wiring 111 and the auxiliary wiring 106, and the contact resistance is reduced. As a result, the wiring 111 and the auxiliary wiring 106 are reduced. It is possible to further reduce the electrical resistance.

The higher the contact at the contact point between the wiring 111 and the auxiliary wiring 106, the better the overall electrical resistance can be reduced. In the case where the auxiliary wiring 106 is made of aluminum, it is effective to form the wiring 111 by laminating a titanium film and an aluminum film thereon in order to obtain a good contact.

In FIG. 1B, reference numeral 113 denotes a wiring that intersects the lower side of the wiring 111 as shown in FIG. For example, in the case of a liquid crystal display device integrated with a peripheral circuit, such a structure is used in a clock signal line of the peripheral circuit and a gate wiring of a thin film transistor constituting the peripheral circuit connected to the clock signal line.

A wiring 1 that intersects the wiring in the same layer as the auxiliary wiring 106 that reduces the electrical resistance of the wiring 111.
13 is arranged, the crossing portion and the auxiliary wiring 106 in the vicinity thereof as shown in FIG.
The electrical resistance can be sufficiently reduced if wirings that intersect are arranged between them, and the process is not different from the conventional process even if auxiliary wiring is formed.

With the configuration of the present invention as described above, the electrical resistance of the wiring can be greatly reduced. In addition, since the area and line width required for wiring can be made the same as in the prior art, the capacitance between adjacent wirings is almost the same as in the past. Further, in the peripheral circuit integrated liquid crystal display device, the capacitance between the wiring and the counter electrode does not increase.

As a result, waveform rounding can be effectively reduced in wiring of 1 cm or more, more preferably 3 cm or more (the upper limit depends on the size of the panel) to which a high frequency signal of several MHz, for example, 1 MHz or more is applied.

As a result, in a circuit including thin film transistors, circuit malfunction can be avoided, operation timing margins can be reduced, and accurate signal transmission can be realized.

Further, the auxiliary electrode can be manufactured by simply changing the mask pattern in the process of manufacturing the scanning line (gate line) and the data line (source line). As a result, the resistance of the wiring can be reduced without increasing the number of manufacturing steps.

Further, in the semiconductor device having the wiring structure of the present invention, the thin film transistor is a top gate type,
Any configuration of the bottom gate type can be adopted.

Further, when the wiring structure of the present invention is implemented in all the wirings in the peripheral circuit, a place where the wirings are intricately arranged vertically and horizontally may cause a short circuit.

However, even if the wiring structure of the present invention is applied only to a part of the wiring to which a high frequency is applied, the effect of reducing electric resistance can be obtained. Therefore, it is only necessary to provide an auxiliary wiring only in a necessary portion instead of the entire wiring and realize parallel connection.

At this time, in a plurality of wirings to which high-frequency signals of the same type (for example, a clock signal and its inverted signal, a divided clock signal, a video signal, etc.) are applied, the resistance values of the wirings should be approximately the same. Is important. Thereby, the degree of rounding of the signal waveform can be made uniform in each wiring.

Further, for example, only the wiring provided in the peripheral wiring 907 portion in FIG. 5 may be provided with an auxiliary wiring over the entire length of the wiring, and the peripheral circuit wirings 908 and 909 may be provided with no auxiliary wiring. Since the peripheral wiring 907 has no wiring that intersects until it is input to the peripheral circuit and can be configured without dividing the auxiliary wiring, the electrical resistance can be effectively reduced as compared with the case where the auxiliary wiring is formed on other wiring. Can be reduced.

In addition, the formation of the auxiliary wiring is not the same layer and the same process as other wirings such as scanning lines and data lines, but the number of processes is increased, but a layer for forming only the auxiliary wiring is provided if necessary, Needless to say, the electrical resistance may be further reduced.

In the present invention, as long as the wiring and the auxiliary wiring are provided with an interlayer insulating film therebetween, it is arbitrary which layer is provided.

If the line width of the auxiliary wiring is approximately the same as or less than the wiring connected to the auxiliary wiring,
In particular, the liquid crystal display device is preferable because an increase in capacitance with the counter electrode due to the presence of the auxiliary wiring can be prevented.

In this embodiment, an example in which wiring having a structure with reduced electric resistance is simultaneously formed in a step of forming a thin film transistor capable of high-frequency driving over a substrate having an insulating surface. Here, an example of manufacturing a circuit-side substrate of an active matrix liquid crystal display device is shown.

2 to 4 show a manufacturing process of this embodiment. 2 to 4 show cross sections of the manufacturing process. In each figure, the left side is a region where a wiring having a structure with reduced electric resistance is formed (wiring portion), and the center is a thin film transistor having a complementary configuration that forms a peripheral circuit. A region (peripheral circuit portion) to be formed, and a region on the right side (pixel portion) where a thin film transistor constituting an active matrix circuit is formed.

A liquid crystal display device formed using a panel manufactured in this embodiment has a VGA (640 (× 3 colors) × 480 pixels) configuration in which a pixel portion including an active matrix circuit is 10 cm wide.

In this embodiment, the wiring having a structure with reduced electric resistance is the clock signal line (
A line that transmits the input clock signal to the entire peripheral circuit) is configured (corresponding to the wiring 908 in FIG. 5). Of course, the present invention may be applied to wiring to which other high frequency is applied, for example, a video signal line.

In addition, this structure may be applied to all the peripheral circuit wirings. In this case, however, in the case where there are many wirings that intersect the wirings to which the auxiliary wirings are connected in the layer in which the auxiliary wirings are provided, the auxiliary wirings There are also many parts of the division. As a result, it is necessary to be careful because the effect of reducing the electrical resistance of the wiring cannot be obtained sufficiently, or the degree of signal rounding for each wiring may not be uniform, resulting in inconvenience.

First, a silicon oxide film having a thickness of 300 nm is formed on the quartz substrate 201 as the base film 202. Note that the base film 202 is not particularly necessary if the surface of the quartz substrate has good smoothness and sufficient cleaning.

Note that the use of a quartz substrate as a substrate is a preferable choice at present, but the substrate is not limited to quartz as long as the substrate can withstand the heat treatment temperature.

Next, an amorphous silicon film 203 serving as a starting film for the crystalline silicon film is formed by a low pressure thermal CVD method.
The film is formed to a thickness of nm.

Next, a silicon oxide film (not shown) is formed to a thickness of 150 nm and patterned to form a mask indicated by 204. This mask has an opening formed in a region indicated by 205. In the region where the opening 205 is formed, the amorphous silicon film 20
3 is exposed.

The opening 205 has an elongated rectangle having a longitudinal direction in the depth direction and the front direction of the drawing. The width of the opening 203 is suitably 20 μm or more. Further, the length in the longitudinal direction may be formed with a required length.

Since nickel is introduced as a metal element that promotes crystallinity, it is 10 p in terms of weight.
A nickel acetate solution containing pm nickel element is applied. Then, spin drying is performed using a spinner (not shown) to remove excess solution. The amount of nickel element introduced can be controlled by the concentration of nickel element contained in the solution.

Examples of metal elements that promote crystallinity include Ni, Fe, Co, Ru, Rh, Pd, Os, I
One or more kinds selected from r, Pt, Cu, and Au can be used.

In this way, a state is obtained in which the nickel element is present in the state shown by the dotted line 206 in FIG. In this state, a state is obtained in which the nickel element is selectively held in contact with a part of the amorphous silicon film at the bottom of the opening 205.

Note that nickel element may be introduced by ion implantation. In this case, the introduction position of the nickel element can be controlled with higher accuracy than when the nickel element solution is applied. Therefore, it is particularly effective when the width of the nickel element introduction region is extremely narrow, such as several μm or less, or when the shape of the introduction region is complicated.

Next, heat treatment is performed at 600 ° C. for 8 hours in a nitrogen atmosphere containing 3% of hydrogen and containing as little oxygen as possible (also in a nitrogen atmosphere). Then, crystal growth in a direction parallel to the substrate 201 as indicated by reference numeral 207 in FIG.

This crystal growth proceeds from the region of the opening 205 into which nickel element is introduced toward the periphery. This crystal growth in a direction parallel to the substrate is referred to as lateral growth or lateral growth.

The surface of the laterally grown crystalline silicon film obtained by this crystal growth has a very smooth surface compared to conventional low-temperature polysilicon and high-temperature polysilicon. This is considered due to the fact that the extending directions of the crystal grain boundaries are roughly aligned.

A general silicon film called polycrystalline silicon or polysilicon has a surface roughness of ± 10 nm or more. However, when the lateral growth as shown in this embodiment is performed, the surface irregularities are ± 3n.
It has been observed that it is less than or equal to m. This unevenness deteriorates the interface characteristics with the gate insulating film, and is preferably as small as possible.

In the heat treatment conditions for the above crystallization, this lateral growth can be performed over 100 μm or more. Thus, a silicon film 208 having a laterally grown region is obtained.

The heat treatment for crystal growth can be performed at 450 ° C. to 1100 ° C. (the upper limit is regulated by the heat resistance of the substrate). If a certain lateral growth distance is ensured, the temperature of the heat treatment is preferably set to 500 ° C. or higher. However, the crystal growth distance and crystallinity improvement by raising the temperature beyond that is not so great. (Thus, considering economic efficiency and process simplification, a heat treatment of 590 ° C. to 630 ° C., for example, about 600 ° C. is sufficient)

Then, the mask 204 made of a silicon oxide film for selectively introducing nickel element is removed.

In this state, nickel element is unevenly distributed in the film. In particular, the nickel element is present at a relatively high concentration in the region where the opening 205 is formed and the tip portion of the crystal growth indicated by 207.

Therefore, it is important to avoid these regions in forming the active layer. That is, it is important that there is no region in which the nickel element is unevenly distributed in the active layer.

Laser irradiation may be further performed after crystallization. That is, crystallization may be further promoted by laser light irradiation. This laser light irradiation has the effect of dispersing the mass of nickel elements present in the film and facilitating removal of the nickel elements later. Note that even if laser light irradiation is performed at this stage, the lateral growth does not proceed further.

As the laser light, an excimer laser having a wavelength in the ultraviolet region can be used. For example, KrF excimer laser (wavelength 248 nm) or XeCl excimer laser (
Wavelength 308 nm) can be used.

Next, heat treatment is performed at 950 ° C. in an oxygen atmosphere containing a halogen element, for example, an oxygen atmosphere containing 3% by volume of HCl, and a thermal oxide film 209 is formed to a thickness of 20 nm. As the thermal oxide film is formed, the thickness of the silicon film 208 decreases by about 10 nm. That is,
The film thickness of the silicon film is about 40 nm. (Fig. 2 (C))

In general, a thermal oxide film formed on the surface of a silicon film has substantially the same thickness rising on the surface and the distance of oxidation proceeding inside. Therefore, for example, the surface of a 10 nm silicon film has 10
When a thermal oxide film of nm is formed, the thickness of the silicon film is reduced by 5 nm, resulting in a configuration of a 5 nm thick silicon film and a 10 nm thick thermal oxide film formed on the surface thereof.

In the above process, silicon elements having an unstable bonding state in the film are used for forming the thermal oxide film in accordance with the formation of the thermal oxide film. And the defect in a film | membrane reduces and higher crystallinity can be obtained.

At the same time, formation of a thermal oxide film and gettering of nickel element from the film are effected by the action of a halogen element, here chlorine.

Naturally, nickel element is taken into the thermal oxide film at a relatively high concentration. And the nickel element in the silicon film 208 is relatively reduced. In this way, the state shown in FIG.

When the thermal oxide film 209 is formed, the thermal oxide film 209 is removed. In this way, a crystalline silicon film 208 with a reduced nickel element concentration is obtained.

The crystalline silicon film thus obtained has a structure in which the crystal structure extends in one direction (this direction coincides with the crystal growth direction). That is, it has a structure in which a plurality of elongated cylindrical crystals are arranged in parallel through a plurality of crystal grain boundaries extending in one direction.

Next, by performing patterning, island-like regions 210, 211, 2 formed of lateral growth regions are formed.
12 is formed. These island-like regions 210, 211 and 212 will later become the active layer of the TFT.

Here, the pattern is positioned so that the direction connecting the source region and the drain region and the crystal growth direction match or approximately match. By doing so, the direction in which the carriers move and the direction in which the crystal lattice continuously extends can be matched, resulting in a TFT with high characteristics.
Can be obtained.

Next, a silicon oxide film 213 is formed to a thickness of 100 nm by a plasma CVD method. (Fig. 2 (D))

Thereafter, thermal oxide films 301, 302, and 303 are formed to a thickness of 30 nm. This thermal oxide film is 95% in an oxygen atmosphere containing 0.1 to 10% by volume, eg, 3% by volume of HCl.
It is obtained by performing a heat treatment at 0 ° C.

By forming the thermal oxide films 301, 302, and 303, the thicknesses of the patterns (patterns that become active layers) 210, 211, and 212 become 25 nm.

In this step, the same effect as that in the case where the thermal oxide film 209 is formed can be obtained.
The thermal oxide film 209 becomes a part of the gate insulating film of the TFT.

In this embodiment, the active layers 210, 211, 2 made of a crystalline silicon film finally obtained.
The film thickness of 12 (25 nm) is the film thickness (30 nm) of the second thermal oxide films 301, 302, and 303.
Thinner. By doing so, an effect for obtaining a peculiar crystal structure according to the formation of the thermal oxide film can be obtained. (Fig. 3 (A))

In the TFT shown in this embodiment, the final thickness of the crystalline silicon film constituting the active layer is preferably 10 nm to 75 nm, more preferably 15 nm to 45 nm. By setting such a film thickness, a specific crystal structure in which crystallinity is continuous in one direction can be obtained in a more remarkable form with good reproducibility.

The concentration of nickel element finally remaining in the active layers 210, 211, 212 made of the crystalline silicon film thus produced is currently measured by using SIMS (secondary ion analysis method) and is 1 × 10 ¹⁴ atoms / cm ^{3 to} 5 × 10 ¹⁷ atoms / cm ³ , but the lower, the better.

Of course, it is possible to further reduce the concentration of nickel element remaining in the crystalline silicon film by reviewing the overall manufacturing process, thoroughly cleaning steps, and thoroughly cleaning the apparatus.

In addition, in the process of manufacturing the thermal oxide film, from the relationship that the metal element moves into the thermal oxide film,
A gradient or distribution occurs in the concentration distribution of nickel element in the thickness direction of the obtained crystalline silicon film.

In general, a tendency that the concentration of the metal element increases toward the interface where the thermal oxide film is formed is observed. In addition, depending on the conditions, there is a tendency that the concentration of the metal element increases toward the substrate or the base film, that is, toward the interface on the back side (this difference is caused by the amorphous silicon film serving as a starting film). It depends greatly on the quality of the film).

Further, when a halogen element is included in the atmosphere when forming the thermal oxide film, the halogen element also exhibits a concentration distribution similar to that of the metal element. That is, it shows a concentration distribution in which the content concentration increases toward the front surface and / or back surface of the crystalline silicon film (the difference in the concentration distribution also depends on the film quality of the starting film).

Next, an aluminum film for forming the gate electrode and the auxiliary wiring is formed by sputtering.
The film is formed to a thickness of nm. This aluminum film contains 0.2% by weight of scandium.

The reason why scandium is contained in the aluminum film is to suppress generation of hillocks and whiskers in the subsequent process. Hillocks and whiskers are needle-like or stab-like protrusions resulting from abnormal growth of aluminum during heating.

As a material for forming the gate electrode, in addition to aluminum, tantalum (Ta), polycrystalline silicon doped with a large amount of phosphorus (P), tungsten silicide (WSi), or phosphorous-doped polycrystalline silicon and tungsten silicide A laminated structure or a hybrid structure may be used.

Next, a silicon nitride film is formed to a thickness of 50 nm. Then, resist masks 308 and 309
, 310 and 311 to obtain a state in which an aluminum pattern indicated by 304, 305, 306 and 307 and a silicon nitride film indicated by 351, 352, 353 and 354 are formed. (Fig. 3 (B))

Here, anodization is performed in a state where the resist masks 308, 309, 310, and 311 are arranged. Here, a 3% oxalic acid aqueous solution is used as the electrolytic solution. In this electrolytic solution, by performing anodization using the aluminum patterns 304, 305, 306, and 307 as anodes, porous anodic oxide films indicated by 316, 317, 318, and 319 are formed.

In this step, the resist masks 308, 309, 310, 311 and the silicon nitride films 351, 352, 353, 354 are present on the upper portion, so that the anodic oxide films 316, 317, 318, 319 is formed.

This anodic oxide film can be grown to a thickness of several μm. Here, the film thickness is 600 nm. The growth distance can be controlled by the anodic oxidation time.

Next, a dense anodic oxide film is formed. That is, anodic oxidation using an ethylene glycol solution containing 3% tartaric acid as an electrolytic solution is performed.

In this step, the electrolytic solution enters the porous anodic oxide films 316, 317, 318, 319, and the silicon nitride films 351, 352, 3 on the upper surface of each aluminum pattern.
Because of the presence of 53 and 354, an anodized film having a dense film quality as shown by 320, 321, 322, and 323 is selectively formed only on the side surface of the aluminum pattern.

The dense anodic oxide films 320, 321, 322, and 323 have a thickness of 100 nm. This film thickness is controlled by the applied voltage.

When the formation of the anodic oxide film is completed, the resist masks 308, 309, 310, and 311 are removed.

Here, the exposed silicon oxide film 213 is etched. At the same time, the thermal oxide films 301 and 3
02 and 303 are partially etched. This etching uses dry etching.
In this way, the state shown in FIG.

The porous anodic oxide films 316, 3 are mixed using a mixed acid obtained by mixing acetic acid, nitric acid and phosphoric acid.
Remove 17, 318, 319. Further, the silicon nitride films 351, 352, 353, and 354 are removed. In this way, the state shown in FIG.

As shown in FIG. 3D, in this embodiment, the auxiliary electrode 312 is a gate electrode 313,
314 and 315 are simultaneously formed by the same process. Therefore, the auxiliary electrode 312 can be produced only by changing the mask pattern in the conventional process.

In this embodiment, a dense anodic oxide film 320 is formed on the side surface of the auxiliary electrode 312. A silicon oxide film 213 remains on the lower surface.

After obtaining the state shown in FIG. 3D, impurity ions are implanted. Here, resist masks are alternately arranged, P (phosphorus) ions are applied to the left side of the peripheral circuit portion and the thin film transistor in the pixel portion, and B (boron) ions are applied to the thin film transistor on the right side of the peripheral circuit portion by plasma doping. Do it.

In this step, 331, 333, 335, 337, 339 are heavily doped.
, 341 and lightly doped regions 334, 338, 342 are formed.
This is because the remaining silicon oxide films 325, 326, and 327 function as a semi-transmissive mask, and some of the implanted ions are shielded there.

Then, the region into which the impurity ions are implanted is activated by irradiation with laser light (or strong light using a lamp). Thus, source regions 331, 335, 339, channel formation regions 332, 336, 340, drain regions 333, 337, 341, and low-concentration impurity regions 334, 338, 342 are formed in a self-aligned manner.

Here, regions 334, 338, and 342 are regions called LDD (lightly doped drain) regions. (Fig. 3 (D))

When the thickness of the dense anodic oxide film 309 is increased to 200 nm or more, an offset gate region can be formed outside the channel formation regions 332, 336, and 340 with the film thickness.

In this embodiment, the offset gate region is formed, but since the size thereof is small, the contribution due to its existence is small, and the drawing becomes complicated, so it is not shown in the drawing.

In order to form an anodic oxide film having a dense film quality as thick as 200 nm or more, an applied voltage of 200 V or more is required, so care must be taken regarding reproducibility and safety.

Next, as a first interlayer insulating film, a silicon nitride film 343 is first formed by a plasma CVD method to a thickness of 200 nm. In addition to the silicon nitride film, a silicon oxide film or a stacked film of a silicon nitride film and a silicon oxide film can also be used.

Further, an organic resin film 344 is formed on the silicon nitride film 343 by a spin coating method. As a material for the organic resin, polyimide, polyamide, polyimide amide, or acrylic can be used. (Figure 3 (E))

Next, contact holes are formed in the first interlayer insulating films 343 and 344. Next, after forming a titanium / aluminum / titanium multilayer film to a thickness of 300 nm, patterning is performed to form source electrodes 402 and 407, drain electrodes 406 and 409, source / drain electrodes 404, gate extraction wirings 403 and 405, and wiring 401. To do.

The wiring 401 is formed by a plurality of contact holes provided along the line direction of the wiring 401.
The auxiliary electrode 312 is electrically connected in parallel. The wiring 401 is connected in parallel with the auxiliary electrode 312 so that the electrical resistance is considerably reduced. Therefore, it is possible to greatly reduce the rounding of the transmitted signal waveform even when a high frequency is applied.

Further, when the gate line provided in the same layer as the auxiliary electrode 312 intersects the lower side of the wiring 401 (extending to the gate electrode of the TFT), the auxiliary electrode 312 is 4 to the intersecting gate line.
It is divided so as to be separated by 0 μm (corresponding to the configuration shown in FIG. 1B).

  A part of the drain electrode 409 is used as an electrode for forming an auxiliary capacitance.

  Thus, the thin film transistor and the wiring with reduced electric resistance shown in FIG. 4A are completed.

In the figure, the source / drain electrodes and the gate extraction wiring 403 are on the same cross section.
405, however, the gate wiring is actually formed in a portion extending from the gate electrodes 313 and 314.

Next, as a second interlayer insulating film, a silicon nitride film 410 is formed to a thickness of 100 nm by plasma CV.
Film is formed by D method. Further, an organic resin film 402 is formed by a spin coating method. As the organic resin material, polyamide, polyimide amide, and acrylic can be used in addition to polyimide. In this way, the state shown in FIG.

Next, an opening is formed in the organic resin film 402, and a black matrix (BM) 412 made of a laminated film of a titanium film and an aluminum film is formed. This black matrix 41
2 functions as an electrode for forming an auxiliary capacitance with the silicon nitride film 410 and the drain electrode 409 in addition to the original function as a light shielding film.

When the black matrix 412 is formed, an organic resin film 414 is used as a third interlayer insulating film.
Is deposited. Then, a contact hole to the drain electrode 409 is formed, and a pixel electrode 415 made of ITO (indium tin oxide) is formed.

In this manner, a circuit-side substrate of the active matrix liquid crystal display device is manufactured.
Thereafter, an alignment process is performed on the upper surface of the substrate, and a panel is configured to be disposed opposite to the counter substrate on which ITO is formed on the entire surface, which is also subjected to the alignment process. Inject liquid crystal material into the panel,
The device is completed by sealing.

The TFT shown in this embodiment can have a very high characteristic that has not been obtained in the past.

For example, an NTFT (N-channel TFT) having a mobility of 200 to 300 (cm ² / Vs), S
A high performance value of 75 to 90 (mV / dec) (V _D = 1V) is obtained. PTFT (P-channel TFT) 120-180 (cm ² / Vs), S value 75-100 (mV / dec) (V _D = 1V)
High performance can be obtained.

In particular, the S value is a surprisingly good value of 1/2 or less compared to the values of the conventional high-temperature polysilicon TFT and low-temperature polysilicon TFT.

The TFT can be operated at an extremely high frequency such as several tens of MHz to several hundreds of MHz. For example, when the voltage of the drive signal is 3.3 to 5 V,
An operation of 1 GHz at the ring oscillator level and 100 MHz at the shift register level can be performed.

In addition, a thin film transistor using a crystalline silicon film having a unique crystal structure as described above has a feature that a short channel effect is hardly caused due to the crystal structure. In addition, since an insulator is used as a substrate, there is no problem of the capacity of the substrate, and there is a feature that it is suitable for high-speed operation.

A conventional MOS type transistor using a single crystal silicon wafer has a scaling law. This is because if the size of the transistor is reduced according to a predetermined rule, the performance of the transistor is increased according to this predetermined rule.

However, in the state where the miniaturization has advanced greatly in recent years, according to this scaling law,
It has become difficult to improve the performance of transistors.

For example, the shorter the channel length in order to suppress the short channel effect, the more necessary it is to do impurity doping next to the channel, which increases the difficulty in the manufacturing process. A point can be mentioned.

However, when the crystalline silicon film having the unique crystal structure described above is used, the required characteristics can be obtained with dimensions that do not follow the scaling law.

This is considered to be caused by the following matters.
(1) By aligning the extending direction of the columnar crystal in the direction in which carriers move in the channel, the short channel effect is suppressed.
(2) The use of an insulator for the substrate greatly suppresses the capacity problem.
(3) Since aluminum can be used for the gate electrode, it is advantageous for high-speed operation.

Regarding (1), it can be considered as follows. That is, each of the columnar crystal structures is partitioned by inert crystal grain boundaries, but at this crystal grain boundary part, the energy level is high, so the carriers are in the extending direction of the crystal. The movement is parasitic. Further, by the same concept, the spread of the depletion layer from the source and drain regions into the channel is also suppressed. This is considered to suppress the short channel effect.

Specific examples that do not follow the scaling rule described above include the following examples.

For example, according to the conventional scaling law, the thickness of the gate insulating film must be 10 nm. When a crystalline silicon film as disclosed in this specification is used, the thickness of the gate insulating film is set to 30 nm. Can get the same characteristics. As a result, the antistatic property can be enhanced.

  This is understood to be a factor as shown in (1) to (3) above.

Further, not only the film thickness of the gate insulating film but also the channel length can be obtained under conditions that are looser than the conventional scaling law (conditions one rank lower).

This is useful when a semiconductor circuit capable of high-speed operation is manufactured over a large area at a low cost.

In this embodiment, the long wiring 401 to which a high frequency is applied is connected in parallel with the auxiliary wiring 312 via the interlayer insulating film, so that the electrical resistance of the wiring 401 is drastically reduced. As a result, the rounding of the transmitted signal waveform can be greatly reduced.

As a result, even though the clock signal line provided in the signal line driving peripheral circuit is extremely long, about 10 cm, even if it is operated at a clock frequency of 12.5 MHz, no malfunction occurs and a good display is obtained. Was able to do.

In this embodiment, the configuration of the wiring 401 and the auxiliary wiring 312 shown in the first embodiment is implemented in a peripheral wiring (corresponding to 907 in FIG. 5) connected to the signal line driving peripheral circuit.

That is, in the peripheral wiring conventionally provided only on the first interlayer insulating film, the auxiliary wiring is formed along the peripheral wiring below the peripheral wiring in the same layer as the gate electrode of the TFT.

The peripheral wiring and the auxiliary wiring are connected in parallel by a plurality of contact holes provided in the line direction of the peripheral wiring.

Since the peripheral wiring has no wiring crossing the upper layer or the lower layer, the peripheral wiring can be connected in parallel without dividing the auxiliary wiring. Therefore, the effect of reducing the electrical resistance is extremely large. Even if the auxiliary wiring is provided only in the peripheral wiring and the peripheral circuit has only the conventional single layer structure (that is, the auxiliary wiring is not provided), the signal waveform rounding in the wiring to which the high frequency is applied is greatly reduced compared to the conventional one. Can be reduced.

In this embodiment, in the configuration of the first embodiment, auxiliary wirings are formed on both the signal lines (source lines) and the scanning lines (gate lines) of the active matrix circuit which is a display unit, and the electrical resistance of the wiring is reduced. An example is shown.

The gate line is an extension of the gate electrode 315 of the TFT in the pixel portion, and the source line is an extension of the source electrode 402 of the TFT in the pixel portion.

In this embodiment, an auxiliary wiring of the gate line is formed on the organic resin film 344 in the same layer as the source line and the source electrode 402 with respect to the gate line under the silicon nitride film 343, and along the gate line direction. A plurality of contact holes are connected in parallel. The auxiliary wiring of the gate line is provided separately from the source line provided in the same layer.

On the other hand, in the source line on the organic resin film 344, the auxiliary wiring of the source line is formed by the same layer as the gate line and the gate electrode 315 below the silicon nitride film 343, and is paralleled by a plurality of contact holes provided in the source line direction. It is connected. The auxiliary wiring of the source line is provided separately from the gate line of the same layer.

In any of the auxiliary wirings of the source line and the gate line, it is preferable that the divided portion is separated by several tens of μm or more.

With such a structure, the electrical resistance of the wirings constituting the active matrix portion can be greatly reduced, and good display can be performed even when the display area is enlarged. Moreover, the manufacturing process is not different from the conventional one, and can be realized only by changing the mask pattern.

In this embodiment, the structure shown in Embodiments 1 to 3 is formed of an inverted staggered thin film transistor.
Similar effects can be obtained by using an inverted staggered thin film transistor instead of the planar thin film transistor shown in each embodiment.

Note that it is effective to obtain a high-performance thin film transistor by using a material having high heat resistance, such as polycrystalline silicon doped with a large amount of phosphorus, as the gate electrode of the inverted staggered thin film transistor.

101 Substrate 102 Base film 103 Active layer 104 Gate insulating film 105 Gate electrode 106 Auxiliary electrode 107 Interlayer insulating film 108 Contact hole 109 Source electrode 110 Drain electrode 111 Wiring 112 Interlayer insulating film 113 Cross wiring

Claims (1)

A first region in which a flat cable is disposed;
A second region in which the display unit is disposed;
A third region in which peripheral circuits are arranged;
A fourth region provided with a peripheral wiring for electrically connecting the peripheral circuit and the flat cable,
A plurality of first wirings formed on the substrate;
A first insulating film formed on the plurality of first wirings;
A plurality of first contact holes formed in the first insulating film;
A plurality of second wirings formed on the first insulating film and electrically connected to each of the plurality of first wirings through the plurality of first contact holes;
The plurality of first wirings and the plurality of first contact holes are arranged only in the fourth region of the first to fourth regions,
The plurality of second wirings are arranged only in the third region and the fourth region among the first to fourth regions, and the plurality of second wirings in the third region The length of the wiring is aligned,
The display device according to claim 1, wherein the peripheral wiring includes the plurality of first wirings in the fourth region and the plurality of second wirings in the fourth region.

Images