JP2014175502A - Manufacturing method of thin film transistor element and patterning method of printable semiconductor layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a microfabricated thin film transistor element having high mobility by patterning a semiconductor film by a simple method in a thin film transistor element manufactured by using a painting process; and provide a patterning method of a printable semiconductor layer.SOLUTION: A manufacturing method of a thin film transistor element comprises processes in the following order: a process of forming a hydrophobic region 16 having a water contact angle of 80°-110° by performing a fluorination treatment on an insulation film 13 having a water contact angle of 60°-80° when forming on the insulation film 13, a printable semiconductor layer 17 which becomes an active region; and a process of coating on the insulation film 13a, a semiconductor solution 17a in which a semiconductor material is soluble in an organic solvent and subsequently patterning an active region and a non-active region in a self-organization manner by performing burning, in which a difference between water contact angles of the insulation film 13 and the hydrophobic region 16 is within a range of 20°-30°.

Description

  The present invention relates to a method for manufacturing a thin film transistor element and a method for patterning a coated semiconductor layer.

In recent years, among thin film transistors (TFTs), organic thin film transistors (organic TFTs) and oxide thin film transistors (oxide TFTs) that can be manufactured using a coating or printing process have attracted much attention.
Since an organic device uses an organic material, the organic device has a flexible structure as compared with an inorganic device and can be manufactured by a relatively low temperature process. In particular, it is possible to use various coating processes (spin coating, dip coating, printing method, ink jet method, etc.) by dissolving semiconductor materials, insulating materials, wirings, etc. in organic solvents to form a solution. Various application devices can be manufactured at low cost, and there is a possibility that expansion to a large area may be facilitated. Furthermore, since organic devices are lightweight and flexible, they can be applied to a wide range of devices such as various portable terminals, displays, and IC tags.

Until now, the mobility of organic TFTs is lower than that of conventional silicon TFTs, which has been a serious adverse effect on applications such as displays and sensors. In recent years, however, the mobility of organic TFTs has been dramatically improved due to rapid progress in research.
For example, in the transistors described in Non-Patent Documents 1 to 3, a material in which a coating type low molecular weight semiconductor is solubilized is formed using solution searing, dip coating, or inkjet printing, and the crystal growth and orientation are controlled. As a result, we have reported an example of a dramatic improvement in mobility.

Here, the conventional low molecular weight organic semiconductor material has a mobility value of about 1 cm ² / Vs at the maximum. However, in the example using the coating type low molecular weight semiconductor material described above, it has been reported that a very large crystal film having a grain size of several tens to several hundreds of μm is formed, and a high movement exceeding 10 cm ² / Vs is reported. It is reported that the degree can be secured. Such a high mobility value greatly exceeds the characteristics of the amorphous silicon transistor put into practical use in the conventional flat panel, and can be said to be a result of greatly showing the practicality of the organic transistor.

Hector A. Becerri et al., Advanced Materials, vol.20, pp.2588-2594 (2008) Junshi Soeda et al., Advanced Materials, vol.23, pp.3309 (2012) Hiromi Minemawari et al., Nature, vol. 475, pp. 364 (2012)

However, in the examples of Non-Patent Documents 1 to 3 described above, most of the evaluation results are for single elements having a large device size (channel length), and high mobility has not yet been realized with miniaturized or arrayed elements. Is the current situation. A major cause of this is that a patterning method for a semiconductor film (semiconductor layer) formed by a coating method has not yet been established.
In the case of applying a thin film transistor to active drive such as a display or a sensor, it is required to manufacture an element with a channel length reduced to 10 μm or less. In order to suppress unnecessary leakage current between elements and reduce the off-state current of the element, it is necessary to pattern a semiconductor film in a fine area of 100 μm or less.

  Conventionally, as a method of patterning and forming a semiconductor film in a fine area, a method of previously patterning an insulating film, which is a base of a semiconductor layer, into a TFT formation region and a non-formation region is known. Specifically, a highly hydrophobic material is used for the insulating film, and the wettability (hydrophilicity) is improved by subjecting this insulating film to hydrophilic treatment such as irradiation with ultraviolet light only at the location of the TFT formation region. In the above, a semiconductor layer is formed by applying a coating-type semiconductor material. However, in this method, since the hydrophilic region such as ultraviolet light is directly applied to the region to act as the TFT, there is a possibility that the region where the semiconductor layer is formed is greatly damaged and stable TFT characteristics cannot be obtained.

  The present invention has been made to solve the above problems, and in a thin film transistor element (TFT element) manufactured using a coating manufacturing method, a semiconductor film is patterned by a simple method, whereby a high mobility and fineness are achieved. It is an object to provide a method for manufacturing a thin film transistor element and a patterning method for a coating type semiconductor layer.

As means for solving the above-mentioned problems, the present inventors have studied a patterning method for a semiconductor layer to be an active region formed on an insulating film. As a result, an insulating material suitable for forming a TFT element (good wettability) is used as the insulating film, and the insulating film is subjected to a fluorination treatment so that the insulating film is not damaged. It has been found that the element formation region (hydrophilic region) and the non-formation region (hydrophobic region) can be finely patterned. That is, according to the present invention, in a TFT element manufactured on a substrate, a semiconductor solution in which a coating-type semiconductor material is dissolved in a solvent is dropped onto an insulating film that has been previously patterned in a hydrophilic / hydrophobic region. By collecting the semiconductor solution only in the region and precipitating the crystals, a semiconductor layer having a large crystal size is spontaneously patterned (self-organized).
Note that the thin film transistor of the present invention is more suitable for a semiconductor material solubilized by adding an alkyl chain or the like to a low-molecular or low-molecular material, and an organic thin-film transistor element using a polymer organic semiconductor material. However, the present invention is not limited to the above, and is a technique applicable to a thin film transistor element using a coating type oxide semiconductor, a metal oxide material, a carbon nanotube, graphene, or the like.
The gist of the present invention made based on the results and findings of the inventors as described above is as follows.

[1] In order to solve the above-described problem, a method of manufacturing a thin film transistor element according to the present invention is a method of manufacturing a thin film transistor on a substrate, in which a coated semiconductor layer serving as an active region is formed on an insulating film. A step of forming a hydrophobic region having a water contact angle of 80 ° to 110 ° by subjecting the insulating film having a water contact angle of 60 ° to 80 ° to fluorination treatment, Applying a semiconductor solution in which a semiconductor material is dissolved in an organic solvent, followed by baking to pattern the active region and the non-active region in a self-organized manner in this order, the insulating film and the hydrophobic The difference between the water contact angles of the respective regions is in the range of 20 ° to 30 °.
[2] In the method of manufacturing a thin film transistor element according to [1], the insulating film is a cycloolefin polymer or a cycloolefin derivative.
[3] In the method for manufacturing a thin film transistor element according to [1] or [2], the semiconductor material is an organic semiconductor or an inorganic oxide semiconductor.
[4] In the method of manufacturing a thin film transistor element according to any one of [1] to [3], the concentration of the semiconductor material with respect to the semiconductor solution is 2% by weight or less.
[5] The method for manufacturing a thin film transistor element according to any one of [1] to [4], wherein the fluorination treatment is a plasma treatment using a fluorine-containing gas.
[6] In the method of manufacturing a thin film transistor element according to any one of [1] to [5], an etching depth by the fluorination treatment is limited to 2 nm or less.
[7] In the method of manufacturing a thin film transistor element according to any one of [1] to [6], the firing temperature is ½ or less of a boiling point of the semiconductor material.

[8] In the method of manufacturing a thin film transistor element according to any one of [1] to [7], the hydrophobic region has a hydrophobic property before firing the semiconductor solution applied on the insulating film. By disposing the patterning substrate having the above hydrophobicity on the semiconductor solution, the semiconductor solution is stretched to a uniform thickness over the entire surface of the substrate, and is thinned.
[9] In the method for manufacturing a thin film transistor element according to [8] above, the surface of the patterning substrate is coated with a fluororesin, and a water contact angle of the patterning substrate is 105 ° or more. .
[10] In the method of manufacturing a thin film transistor element according to any one of [8] and [9], after the patterning substrate is disposed on the semiconductor solution, the substrate coated with the semiconductor solution is baked. The patterning substrate is slid in a horizontal direction while being installed in an apparatus for performing the above.
[11] In the method for manufacturing a thin film transistor element according to any one of [8] to [10], a speed at which the patterning substrate is slid is set to 100 mm / second or less.

[12] In the method of manufacturing a thin film transistor element according to any one of [1] to [7] above, before firing the semiconductor solution coated on the insulating film, the substrate is placed in a horizontal direction. The semiconductor solution is tilted to aggregate in a region other than the hydrophobic region, and the aggregated semiconductor solution is tilted.

[13] In the method of manufacturing a thin film transistor element according to any one of [1] to [7], a gas is blown from a side surface of the substrate before firing the semiconductor solution applied onto the insulating film. The semiconductor solution is aggregated in a region other than the hydrophobic region, and the aggregated semiconductor solution is inclined.

[14] In order to solve the above-described problem, a coating type semiconductor layer patterning method according to the present invention is a method for patterning a coating type semiconductor layer on an insulating film, wherein the water contact angle is 60 ° to 80 °. A step of forming a hydrophobic region having a water contact angle of 80 ° to 110 ° by performing a fluorination treatment on the insulating film, and a semiconductor solution in which a semiconductor material is dissolved in an organic solvent is applied on the insulating film. And then, by baking, the step of patterning the coated semiconductor layer in a self-organized manner in this order, and the difference in water contact angle between the insulating film and the hydrophobic region is in the range of 20 ° to 30 ° It is characterized by being inside.

  According to the present invention, in a thin film transistor element manufactured using a coating method, a method for manufacturing a thin film transistor element having high mobility and a patterning method for a coating type semiconductor layer are provided by patterning a semiconductor film by a simple method. It becomes possible to do.

FIG. 1 is a schematic cross-sectional view showing a thin film transistor 10 obtained by the manufacturing method according to the first embodiment. FIG. 2A is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor element 10 according to the first embodiment. FIG. 2B is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor element 10 according to the first embodiment. FIG. 2C is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor element 10 according to the first embodiment. FIG. 2D is a schematic cross-sectional view for describing the method for manufacturing the thin film transistor element 10 according to the first embodiment. FIG. 3A is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor element 20 according to the second embodiment. FIG. 3B is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor element 20 according to the second embodiment. FIG. 3C is a schematic cross-sectional view for explaining the method of manufacturing the thin film transistor element 20 ′ according to the second embodiment. FIG. 3D is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor element 20 ′ according to the second embodiment. FIG. 4A is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor element 30 according to the third embodiment. FIG. 4B is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor element 30 according to the third embodiment. FIG. 4C is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor element 30 according to the third embodiment. FIG. 5 is an optical micrograph of a thin film transistor provided with a coating type semiconductor layer 57 produced by the patterning method according to this example. FIG. 6 is a graph showing the drain current-gate voltage (Id-Vg) characteristics of the thin film transistor device according to this example.

Hereinafter, embodiments of a method for manufacturing a thin film transistor element and a method for patterning a coated semiconductor layer according to the present invention will be described in detail with reference to the drawings.
In addition, in the drawings used in the following description, in order to make the characteristics easy to understand, there are cases where the characteristic portions are enlarged for convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent. In addition, the materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not necessarily limited thereto, and can be appropriately modified and implemented without departing from the scope of the invention. .
The thin film transistor elements described in the following embodiments all have a bottom gate / bottom contact type structure. However, the method of manufacturing the thin film transistor of the present invention is not limited to the bottom gate / bottom contact type structure. -It is applicable also as a manufacturing method of the thin film transistor of a top contact type structure or a top gate type structure.

<Method for Manufacturing Thin Film Transistor Element>
“First Embodiment”
First, a method for manufacturing a thin film transistor element according to the first embodiment will be described with reference to FIGS. 1 to 2D are cross-sectional schematic views of the thin film transistor element according to the present embodiment, but a part of the configuration is omitted in order to make the characteristic part of the thin film transistor element 10 easier to see. Moreover, each of FIG. 2A-FIG. 2D is the schematic for demonstrating the manufacturing method of the thin-film transistor element 10 which concerns on this embodiment, and shows the cross-sectional schematic diagram in each process.
The method of manufacturing the thin film transistor element 10 according to this embodiment is a method of manufacturing a thin film transistor manufactured on the substrate 11, and is a coated semiconductor layer 17 (also simply referred to as a semiconductor layer 17) that becomes an active region on the insulating film 13. ) To form a hydrophobic region 16 having a water contact angle of 80 ° to 110 ° by subjecting the insulating film 13 having a water contact angle of 60 ° to 80 ° to fluorination treatment; A process of patterning active regions and inactive regions in this order by applying a semiconductor solution 17a in which a semiconductor material is dissolved in an organic solvent on the insulating film 13, followed by baking, The difference in water contact angle between the insulating film 13 and the hydrophobic region 16 is set in a range of 20 ° to 30 °.

Here, as described above, the structure of the thin film transistor element 10 shown in FIG. 1 is a bottom gate / bottom contact structure, and the gate electrode 12, the insulating film 13, the source electrode and the drain electrode formed on the surface of the substrate 11. (14 and 15) and a coating type semiconductor layer 17 are provided. In the case of the bottom gate / bottom contact type thin film transistor element 10 shown in FIG. 1, the insulating film 13 functions as a gate insulating film.
Hereinafter, a method for manufacturing the thin film transistor element 10 according to the present embodiment will be described in detail.

  First, as shown in FIG. 2A, the gate electrode 12 is formed on the substrate 11. The gate electrode 12 can be formed by forming the gate electrode 12 on the substrate 11 by, for example, a sputtering method (also simply referred to as sputtering) and then performing etching so as to form a desired pattern of the gate electrode.

  The material of the substrate 11 is not particularly limited and may be composed of various substrates made of an insulating material. For example, a silicon substrate such as a silicon wafer, a glass substrate such as quartz, soda glass, and inorganic alkali glass, polyethylene terephthalate ( PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polyimide (PI), polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE), polypropylene (PP) Plastic films such as nylon and polycarbonate can be used. Further, a metal foil or the like can also be used as the substrate 11 if the surface is treated with an insulating treatment.

  The material of the gate electrode 12 is not particularly limited as long as it is a conductive material. In addition to metal materials such as aluminum, molybdenum, chromium, and copper, these ink materials or conductive polymer materials, tin oxide / antimony, Indium tin oxide (ITO) or the like can be used.

Next, as shown in FIG. 2A, an insulating film 13 is formed on the substrate 11 so as to cover the gate electrode 12. The insulating film 13 according to this embodiment is a gate insulating film that covers the gate electrode 12 and insulates the gate electrode 12.
The material of the insulating film 13 is preferably an insulating film material that can be applied and formed and has good wettability, and is preferably a polymer insulating film material. For example, a cycloolefin polymer or a derivative thereof, a polymer having an alicyclic structure in a main chain synthesized using cycloolefins as a monomer, a methacrylic resin (PMMA) or a derivative thereof, a polycarbonate resin (PC) or a derivative thereof, a polyvinylphenol resin ( PVP) or a derivative thereof, or a hybrid insulating material of these polymer resin and inorganic material can be used.
Here, in the present embodiment, before forming (patterning) the coating type semiconductor layer 17 on the insulating film 13, fluorination is performed on a region (non-formation region) other than the formation region of the coating type semiconductor layer 17 in advance. The hydrophobic region 16 is formed by performing the treatment to make the non-formed region hydrophobic. After that, a semiconductor solution 17a which is a material of the coating type semiconductor layer 17 is applied. Therefore, since the formation region of the coating type semiconductor layer 17 is a region having the original characteristics of the insulating film 13, it is preferable to use a material with good wettability for the insulating film 13. Moreover, since the non-formation area | region of the coating type semiconductor layer 17 performs a fluorination process, there exists a possibility that the surface of a non-formation area | region may become rough. Therefore, it is preferable to use the insulating film 13 having resistance to the fluorination treatment. From these viewpoints, it is particularly preferable to use a cycloolefin polymer or a cycloolefin derivative as the insulating film 13.

The insulating film 13 is formed by applying the material of the insulating film 13 as described above on the substrate 11 on which the gate electrode 12 is formed. Examples of the application method include a drop casting method, a dip coating method, an ink jet method, a spray method, a spin coating method, a roll coating method, a die coating method, a doctor blade method, a spin coating method, a bar coating method, and a screen printing method. Various methods can be employed.
The thickness of the insulating film 13 is not particularly limited, but is preferably 50 to 500 nm, and more preferably 50 to 200 nm.

In this embodiment, the water contact angle on the surface of the insulating film 13 is in the range of 60 ° to 80 °. As a method for adjusting the water contact angle within the range, for example, the temperature and time of the drying process when forming the coating film for forming the insulating film 13 are adjusted to uniformly evaporate the solvent from the coating film surface. To reduce the surface tension change and smooth the surface of the insulating film 13 obtained, or to adjust the balance of hydrophilic groups and hydrophobic groups on the film surface in the molecular structure of the insulating material, etc. There is. By such a method, the water contact angle on the surface of the insulating film 13 can be adjusted to a desired range.
In addition, it is preferable that the water contact angle of the insulating film 13 is 75 ° or less from the viewpoint of improving the stackability of the coating type semiconductor layer 16 formed on the insulating film 13. On the other hand, if the water contact angle of the insulating film 13 is excessively small, the molecular orientation and crystallinity of the coated semiconductor layer 17 may be deteriorated. Therefore, the water contact angle of the insulating film 13 is preferably set to 50 ° or more.

Next, as illustrated in FIG. 2A, the source electrode 14 and the drain electrode 15 are formed on the insulating film 13.
The source electrode 14 and the drain electrode 15 are output electrodes of the thin film transistor and can be made of a conductive material. Examples of the material for the source electrode 14 and the drain electrode 15 include a solution in which metal colloidal particles such as gold, silver, and nickel are dispersed, or a paste using metal particles such as silver as a conductive material. Also, for example, a metal, an alloy, or a transparent conductive film material is formed on the entire surface by sputtering or vapor deposition, and a resist pattern is used to form a desired resist pattern by photolithography or screen printing. A desired pattern can be formed by etching with an etching solution such as the above. In addition, a desired pattern can be directly formed from a metal, an alloy, or a transparent conductive film material by a sputtering method or a vapor deposition method using a mask. Examples of metal materials that can be used for these sputtering and vapor deposition methods include aluminum, molybdenum, chromium, titanium, tantalum, nickel, copper, silver, gold, platinum, and palladium, and examples of the transparent conductive film material include ITO.

  Next, a coating type semiconductor layer 17 to be an active region of the thin film transistor element 10 is formed (patterned) on the insulating film 13. In the patterning process of the coating type semiconductor layer 16 according to the present embodiment, the insulating film 13 is subjected to fluorination treatment to form the hydrophobic region 16 having a water contact angle of 80 ° to 110 °, In addition, a semiconductor solution 17a in which a semiconductor material is dissolved in an organic solvent is applied and then baked to pattern the active region and the inactive region in a self-organized manner.

A process of forming the hydrophobic region 16 will be described.
First, a positive resist film (not shown) is patterned on the insulating film 13 on which the source electrode 14 and the drain electrode 15 are formed so as to cover only a region that is a channel region of the thin film transistor (a region where the coating type semiconductor layer 17 is formed). Form.
Next, fluorination treatment is performed, and the surface of the exposed region (non-formed region) that is not covered by the positive resist film among the surface of the insulating film 13 is fluorinated, and as shown in FIG. Form. After forming the hydrophobic region 16, the positive resist film is peeled off and removed using an organic solvent.
As the fluorination treatment, for example, a plasma treatment using a fluorine-containing gas can be employed, and CF ₄ gas can be exemplified as a gas used in this case.

  When plasma treatment is employed when forming the hydrophobic region 16, the insulating film 13 in the non-formed region may be etched by the plasma irradiation, and the surface of the insulating film 13 may be roughened. However, in this embodiment, since the region other than the region where the coating type semiconductor layer 17 is formed is subjected to fluorination treatment, the region where the coating type semiconductor layer 17 is formed is not affected by plasma irradiation. That is, when the semiconductor solution 17a for forming the coating type semiconductor layer 17 is applied, the wettability of the original insulating film 13 is not affected by the surface roughness of the insulating film 13 caused by plasma irradiation. The semiconductor solution 17a can be applied to the surface of the insulating film 13 in the maintained state.

Further, in the present embodiment, it is preferable to suppress the depth of the etching groove generated by etching the hydrophobic region 16 by plasma irradiation. This is because if the depth of the etching groove is large, the semiconductor solution 17a may be insufficiently aggregated in the formation region of the semiconductor layer 17 when the semiconductor solution 17a is applied on the insulating film 13 in a later step. Because.
Specifically, in the present embodiment, since the semiconductor layer 17 is formed only in the region to be the channel region, the non-formation region of the semiconductor layer 17 is subjected to fluorination treatment to form the hydrophobic region 16, and the channel Patterning is performed into a region where the region is formed and a hydrophobic region 16 which is a non-formed region. Thus, by hydrophobicizing the non-formation region, when the semiconductor solution 17a is applied, the formation region of the semiconductor layer 17 has good wettability that the insulating film 13 has, and the non-formation region Since the hydrophobicity is imparted, the semiconductor solution 17 a spontaneously aggregates in the formation region of the semiconductor layer 17. However, if the etching amount by plasma irradiation to the hydrophobic region 16 is large, a step due to the etching groove formed on the surface of the insulating film 13 becomes large, and this large step inhibits spontaneous aggregation of the semiconductor solution 17a. The patterning property of the semiconductor layer 17 may be deteriorated.
For this reason, in the present embodiment, it is preferable to suppress the depth of the etching groove generated by the plasma irradiation. More specifically, it is more preferable to limit the etching depth to 2 nm or less. More specifically, it is desirable that the etching depth is comparable to or less than the molecular length of the semiconductor material used as the semiconductor layer 17.
Further, in order to reduce the depth of the etching groove in this way, it can be achieved by reducing the output (power) at the time of plasma irradiation and shortening the plasma irradiation time. In addition, although the preferable conditions of plasma irradiation change a little with irradiation apparatuses to be used, it is preferable to set the power in the range of 25 to 100 W and the plasma irradiation time in the range of 10 to 30 seconds.

Further, in the present embodiment, the water contact angle of the hydrophobic region 16 formed by the fluorination treatment is in the range of 80 ° to 110 °, and the difference in water contact angle between the insulating film 13 and the hydrophobic region 16 is different. Is in the range of 20 ° to 30 °.
As described above, the difference in water contact angle between the insulating film 13 that is the formation region of the semiconductor layer 17 that is the active region and the hydrophobic region 16 that is the non-active region is set to 20 ° to 30 ° efficiently. Spontaneous aggregation of the semiconductor solution 17a can be promoted, and the patterning accuracy of the semiconductor layer 16 into a fine region can be increased. As a result, the characteristics of the thin film transistor element can be improved.

Next, a process of forming the coating type semiconductor layer 17 and patterning the active region and the inactive region will be described.
First, as shown in FIG. 2C, a semiconductor solution 17a is applied onto the insulating film 13 whose surface wettability and hydrophobicity are controlled by the fluorination treatment.
As the semiconductor solution 17a, a solution obtained by dissolving a semiconductor material in an organic solvent is used. Note that since the semiconductor layer 17 is formed by a coating method, the semiconductor material to be used is not particularly limited as long as it is soluble in an organic solvent and is a coating type, but an organic semiconductor or an inorganic oxide semiconductor can be used. Specifically, semiconductor materials that have been solubilized by adding alkyl chains to low molecular organic semiconductor materials, polymer organic semiconductor materials, coated oxide semiconductors, metal oxide materials, carbon nanotubes, A solution in which graphene or the like is dispersed can be used. From the viewpoint of controlling the crystal orientation of the semiconductor layer 17 and the solubility of the semiconductor material, it is preferable to use a low molecular organic semiconductor material or a semiconductor solution with high crystallinity.
The semiconductor solution 17a can be obtained by dissolving the semiconductor material as described above in an organic solvent. Note that if the concentration of the semiconductor material with respect to the semiconductor solution 17 is too high, crystals may be deposited in the hydrophobic region 16 when the semiconductor solution 17a is baked and crystallized. It is preferable to be 2% by weight or less.
The film thickness of the semiconductor layer 17 is not particularly limited, but can be controlled by the coating amount of the semiconductor solution 17a. A method for controlling the film thickness of the semiconductor layer 17 includes a method in which a spacer is mixed in advance in the semiconductor solution 17 a and then applied onto the insulating film 13.

Next, after applying the semiconductor solution 17a on the insulating film 13, a baking process is performed. Specifically, the semiconductor solution 17a applied on the insulating film 13 is heated and baked using, for example, a hot plate, an oven, or the like, and the organic solvent is evaporated, so that the region as an active region is formed as described above. A coated semiconductor layer 17 made of a semiconductor material can be formed, and can be patterned into an active region and an inactive region, as shown in FIG. 2D. As a means for baking, in addition to the hot plate and oven, a drying method using a hot air flow, vacuum heating, or the like can be employed.
If the firing temperature is too high, when the semiconductor solution 17a is fired and crystallized, crystals may be deposited in the hydrophobic region 16 and the patterning accuracy between the active region and the inactive region may be deteriorated. Is preferably ½ or less of the boiling point of the semiconductor material used.

The thin film transistor element 10 according to this embodiment can be manufactured by the manufacturing method described above.
The patterning method of the coating type semiconductor layer described above is a patterning method of the coating type semiconductor layer 17 in a thin film transistor having a bottom gate / bottom contact structure. When the thin film transistor is applied, a thin film transistor element can be manufactured by separately forming an insulating film different from the gate insulating film 13 on the substrate 11 before forming the coating type semiconductor layer 17. Become.

  According to the method for manufacturing a thin film transistor according to the present embodiment described above, a semiconductor layer excellent in crystallinity and patternability of a fine region can be patterned using a simple and low-cost coating method. As a result, a thin film transistor element with high mobility can be manufactured, and the element characteristics of the transistor can be improved.

“Second Embodiment”
Next, a method for manufacturing the thin film transistor element 20 according to the second embodiment will be described with reference to FIGS. 3A to 3D. 3A to 3D are schematic cross-sectional views of the thin film transistor elements 20 and 20 'according to the present embodiment. In order to make the characteristic portions of the thin film transistor elements 20 and 20' easier to see, a part of the configuration is omitted. Show. 3A to 3D are bottom gate / bottom contact type transistor elements similar to those of the first embodiment, and the same members as those shown in the first embodiment are denoted by the same reference numerals. Yes.
Since the manufacturing method of the thin film transistor elements 20 and 20 ′ according to the present embodiment is the same up to the step of applying the semiconductor solution 17a in the first embodiment, the subsequent steps will be described in detail.

First, as shown in FIG. 3A, the hydrophobic region 16 formed by fluorination treatment has a semiconductor solution 17a similar to that in the first embodiment and before the firing step in the first embodiment. A patterning substrate 18 having hydrophobicity equal to or higher than hydrophobicity is disposed on the semiconductor solution 17a applied in the previous step. At this time, it is preferable that the patterning substrate 18 disposed so as not to spill the applied semiconductor solution 17a from above the substrate 11 is disposed while being pressed toward the substrate 11. By doing so, spontaneous aggregation of the semiconductor solution 17a can be further promoted.
After that, by performing the same baking process as in the first embodiment and evaporating the organic solvent, the coated semiconductor layer 27 can be formed in the region that becomes the active region, as shown in FIG. It can be patterned into the active region. Further, by disposing the patterning substrate 18 having a large hydrophobicity on the semiconductor solution 17a as in the present embodiment, the semiconductor solution 17a can be spontaneously aggregated more efficiently and the semiconductor solution 17a. Can be stretched to a uniform thickness over the entire surface of the substrate 11 to form a thin film.

  The patterning substrate 18 can be used without particular limitation as long as it is a material having a hydrophobicity equal to or higher than that of the hydrophobic region, but the semiconductor solution 17a is more efficiently applied to the formation region of the semiconductor layer. From the viewpoint of spontaneous aggregation, it is preferable to use a plastic substrate, a glass substrate, or a silicon substrate with high flatness.

The surface of the patterning substrate 18 is preferably coated with a fluororesin. In order to promote spontaneous aggregation of the semiconductor solution 17a, it is effective to increase the hydrophobicity of the surface of the patterning substrate 18 disposed on the semiconductor solution 17a. Therefore, it is preferable to coat the surface of the patterning substrate 11 on the semiconductor solution 17a side with a fluororesin. Coating materials include fluoropolymer resins (for example, Cytop, Teflon (registered trademark), etc.), films using a polymer material with high water repellency such as polystyrene, a substrate coated with these, or a self-assembled single layer having a hydrophobic group. Molecules are preferred.
Further, from the viewpoint of increasing the hydrophobicity of the patterning substrate 18 to promote spontaneous aggregation of the semiconductor solution 17a, the water contact angle of the patterning substrate 18 is preferably 105 ° or more.

3C and 3D, after the patterning substrate 18 is placed on the semiconductor solution 17a, the substrate 11 on which the semiconductor solution 17a is applied is placed on, for example, a baking hot plate that is a baking means. At the same time, it is preferable to slide the patterning substrate 18 in the horizontal direction (in the direction of the arrow in the figure) at a constant speed.
In this way, by performing the baking process while sliding the patterning substrate 18 in the horizontal direction, the surface of the semiconductor solution 17a is gradually exposed by the sliding movement of the patterning substrate 18, and thus the baking is performed sequentially from the exposed surface of the semiconductor solution 17a. In addition, the coated semiconductor layer 27 ′ can be formed by crystallization and agglomerating the crystallized semiconductor solution 17 a into the formation region of the semiconductor layer 27 ′.

  Moreover, it is preferable that the speed | rate which slides the patterning board | substrate 18 shall be 100 mm / sec or less. Since the surface of the semiconductor solution 17a can be slowly and gradually exposed by slowing down the speed (moving speed) at which the patterning substrate 18 is slid, it is agglomerated in the formation region of the semiconductor layer 27 'while measuring the crystallization by firing. Can be made. Therefore, the moving speed of the patterning substrate 18 is preferably set to 100 mm / second or less.

  According to the manufacturing method of the thin film transistors 20 and 20 ′ according to the present embodiment described above, after applying the semiconductor solution 17 a, the patterning substrate 18 having a large hydrophobicity is disposed on the semiconductor solution 17 a, and more spontaneously. In particular, the semiconductor solution 17a can be aggregated into the formation region of the semiconductor layers 27 and 27 ′. Further, by performing the sintering process while sliding the patterning substrate 18, the patterning substrate 18 can be agglomerated to the formation region of the semiconductor layer 27 ′ while gradually crystallizing from the exposed surface of the semiconductor solution 17 a. The semiconductor layer 27 ′ having excellent properties and patterning properties for fine regions can be patterned. As a result, fine thin film transistor elements 20 and 20 'having high mobility can be manufactured, and the element characteristics of the transistor can be improved.

“Third Embodiment”
Next, a method for manufacturing a thin film transistor element according to the third embodiment will be described with reference to FIGS. 4A to 4C. 4A to 4C are schematic cross-sectional views of the thin film transistor element 30 according to the present embodiment. In order to make the characteristic portions of the thin film transistor element 30 easier to see, a part of the configuration is omitted. 4A to 4C are bottom gate / bottom contact type transistor elements similar to those in the first embodiment. The same members as those in the first embodiment are denoted by the same reference numerals. Yes.
Since the manufacturing method of the thin film transistor element 30 according to the present embodiment is the same up to the step of applying the semiconductor solution in the first embodiment, the subsequent steps will be described in detail.

First, as shown in FIG. 4A, after forming the hydrophobic region 16 on the insulating film 13 as in the first embodiment, the semiconductor solution 17a is applied as shown in FIG. 4B.
Next, as shown in FIG. 4C, before the semiconductor solution 17a is heated and baked, the substrate 11 is tilted with respect to the horizontal direction so that the semiconductor solution 17a is formed in the region where the semiconductor layer 37 is formed (other than the hydrophobic region 16). The semiconductor solution 17a is inclined.
Next, the substrate 11 is heated and baked with the substrate 11 tilted. As a result, the organic solvent begins to evaporate from the surface of the semiconductor solution 17a exposed to air, and crystals are deposited in an orientation along the tilt direction of the semiconductor solution 17a.
That is, as shown in FIG. 4C, the substrate 11 is inclined with respect to the ground plane G so that the inclination angle is θ, the semiconductor solution 17a is aggregated in the formation region of the semiconductor layer 37, and the semiconductor solution 17a is inclined at an angle θ. To have. In this state, the agglomerated semiconductor solution 17a is baked to obtain a crystallized semiconductor layer 37 having an inclination angle θ.

The inclination angle θ is preferably adjusted so that the semiconductor solution 17a does not fall from the substrate 11. In addition, since the crystal orientation of the semiconductor layer 37 after crystallization can be controlled by adjusting the tilt angle θ of the semiconductor solution 17a, the tilt angle θ is adjusted so that the desired crystal orientation is obtained when the substrate 11 is tilted. It is desirable to do.
Further, the step of tilting the substrate 11 and the baking step can be performed simultaneously. By simultaneously performing the tilting step and the baking step, the semiconductor solution 17a flows along the tilt direction of the substrate 11, and at the same time, the crystallization of the semiconductor solution 17a proceeds in the same direction as the flow direction. When performing the step of inclining the substrate 11 and the baking step at the same time, it is preferable that the baking temperature is ½ or less of the boiling point of the semiconductor material used so that the semiconductor solution 17a is not baked in the non-forming region 16.

  According to the method of manufacturing a thin film transistor according to the present embodiment described above, the semiconductor solution 17a is applied, and then the substrate 11 is tilted so that the semiconductor solution 17a is aggregated in the formation region of the semiconductor layer 37 and fired. The solution 17 a can be inclined, and the crystal orientation of the semiconductor layer 37 crystallized by firing can be controlled by the inclination angle θ of the substrate 11.

“Fourth Embodiment”
Next, a method for manufacturing the thin film transistor element 40 according to the fourth embodiment will be described. In this embodiment, the same bottom gate / bottom contact type thin film transistor element as in the first embodiment will be described, and the same members as those shown in the first embodiment are denoted by the same reference numerals. I will explain.
Here, as a method for controlling the crystal orientation of the semiconductor layer, the method of inclining the substrate 11 has been described in the third embodiment. However, in this embodiment, after applying the semiconductor solution 17a, the gas is introduced from the side surface direction of the substrate 11. Adopt the method of spraying.

First, after applying the same semiconductor solution 17a as in the first embodiment, before firing the semiconductor solution 17a, a gas is blown from the side surface direction of the substrate 11, so that the semiconductor solution 17a is formed in the formation region (hydrophobic region) of the semiconductor layer 47. In other words, the semiconductor solution 17a is made to have an inclination.
That is, by applying a gas from the side surface direction of the substrate 11 after applying the semiconductor solution 17a, the semiconductor solution on the substrate 11 is aggregated in the formation region of the semiconductor layer and has a distribution inclined to the semiconductor solution by the gas wind pressure. Make it. When the substrate 11 is heated and baked in this state, crystals are deposited in an orientation along the tilt direction of the semiconductor solution 17a, and the semiconductor layer 37 tilted with respect to the substrate 11 can be obtained.
In addition, the gas to spray is not specifically limited, Air, an inert gas, etc. can be illustrated. In addition, conditions such as a flow rate when spraying may be adjusted as appropriate so that the semiconductor solution 17a does not fall down from the substrate 11.

  Hereinafter, the effects of the present invention will be made clearer by examples. In addition, this invention is not limited to a following example, In the range which does not change the summary, it can change suitably and can implement.

(Example)
First, a gate electrode 52 made of molybdenum was formed on a plastic substrate by sputtering. The film thickness of the gate electrode 52 was 50 nm.
Next, an insulating film made of cycloolefin polymer (COP; manufactured by Nippon Zeon Co., Ltd.) was formed to a thickness of 200 nm by spin coating. The water contact angle on the surface of the insulating film was measured and found to be 70 °.
Next, a source electrode 54 made of gold and a drain electrode 55 made of gold were formed on the insulating film by vapor deposition / photolithography.

Next, a positive resist film was patterned on the substrate on which the source electrode 54 and the drain electrode 55 were formed so as to cover only the formation region of the coating-type semiconductor layer to be the channel region (active region) of the thin film transistor.
Next, plasma treatment using a fluorine-containing gas was performed as a fluorination treatment, and the exposed insulating film surface not covered with the positive resist film was fluorinated to form a hydrophobic region. In this example, CF ₄ gas was used, and plasma treatment was performed in a low output range of 25 W to 100 W and a processing time in the range of 10 seconds to 30 seconds. The water contact angle on the surface of the obtained hydrophobic region was measured and found to be 98 ° to 100 °. Moreover, when the depth of the etching groove | channel of the hydrophobic area | region formed by the fluorination process was measured, it was 2 nm or less.
Thereafter, the positive resist film was peeled off using an organic solvent.

Next, the coating type semiconductor layer 57 was formed by the patterning method described below.
First, a semiconductor solution is applied on the insulating film whose surface wettability and hydrophobicity are controlled by the fluorination treatment. As the semiconductor solution, a solution obtained by dissolving (low molecular organic semiconductor layer) in an organic solvent so as to have a concentration of 2% by weight was used. The coating amount of the semiconductor solution was 20-30 μl.
Next, a superhydrophobic (water contact angle 110 °) plastic substrate (patterning substrate) coated with a fluoropolymer (Cytop) on the surface of the semiconductor solution applied on the insulating film is pressed against the substrate. Then, the semiconductor solution was stretched over the entire substrate surface. Further, in this state, the substrate was placed on a heated hot plate, and the patterning substrate placed on the semiconductor solution was slid at a constant speed of 10 mm / second. As a result, the surface of the semiconductor solution is gradually exposed and fired and crystallized in order from the exposed surface, and the crystallized semiconductor solution is aggregated into the formation region of the semiconductor layer to form the coating type semiconductor layer 57. I was able to.

An optical micrograph of a thin film transistor element provided with the coating type semiconductor layer 57 manufactured using the patterning method described above is shown in FIG. As shown in FIG. 5, the semiconductor layer could be patterned and crystallized in a predetermined fine region.
FIG. 6 shows a graph of electrical characteristics (drain current (Id) -gate voltage (Vg) characteristics) of the thin film transistor element according to this example. Note that “1.E-x” in FIG. 6 means 1.0 × 10 ^−x . Further, the horizontal axis in FIG. 6 is the gate voltage Vg (V), and the vertical axis is the drain current Id (A).
In this example, since the semiconductor layer can be finely patterned, a low off current of 1.0 pA (1.0 × 10 ⁻¹² A) or less and a high on / off ratio can be realized.

10, 20, 20 ', 30, 40 ... Thin film transistor element 11 ... Substrate 12, 52 ... Gate electrode 13 ... Insulating film 14, 54 ... Source electrode 15, 55 ... Drain electrode 16 ... Hydrophobic region 17, 27, 27 ', 37, 47, 57 ... Coating type semiconductor layer (semiconductor layer)
17a: Semiconductor solution 18: Patterning substrate θ: Inclination angle G: Ground plane

Claims (14)

A method of manufacturing a thin film transistor manufactured on a substrate,
When forming a coating type semiconductor layer to be an active region on an insulating film,
Forming a hydrophobic region having a water contact angle of 80 ° to 110 ° by subjecting the insulating film having a water contact angle of 60 ° to 80 ° to fluorination treatment;
Applying a semiconductor solution in which a semiconductor material is dissolved in an organic solvent on the insulating film, followed by baking to pattern the active region and the inactive region in a self-organized manner;
In this order,
A method of manufacturing a thin film transistor element, characterized in that a difference in water contact angle between the insulating film and the hydrophobic region is in a range of 20 ° to 30 °.   2. The method of manufacturing a thin film transistor element according to claim 1, wherein the insulating film is a cycloolefin polymer or a cycloolefin derivative.   The method of manufacturing a thin film transistor element according to claim 1, wherein the semiconductor material is an organic semiconductor or an inorganic oxide semiconductor.   4. The method of manufacturing a thin film transistor element according to claim 1, wherein a concentration of the semiconductor material with respect to the semiconductor solution is 2% by weight or less.   The method for producing a thin film transistor element according to any one of claims 1 to 4, wherein the fluorination treatment is a plasma treatment using a fluorine-containing gas.   6. The method for manufacturing a thin film transistor element according to claim 1, wherein an etching depth by the fluorination treatment is limited to 2 nm or less.   The method for producing a thin film transistor element according to any one of claims 1 to 6, wherein a temperature of the baking is ½ or less of a boiling point of the semiconductor material.   Before baking the semiconductor solution applied on the insulating film, a patterning substrate having a hydrophobicity equal to or higher than the hydrophobic property of the hydrophobic region is disposed on the semiconductor solution. The method of manufacturing a thin film transistor element according to claim 1, wherein the thin film is stretched to a uniform thickness over the entire surface of the substrate.   9. The method of manufacturing a thin film transistor element according to claim 8, wherein a surface of the patterning substrate is coated with a fluororesin, and a water contact angle of the patterning substrate is 105 ° or more.   9. The method according to claim 8, wherein after the patterning substrate is disposed on the semiconductor solution, the substrate coated with the semiconductor solution is placed in the baking apparatus and the patterning substrate is slid in the horizontal direction. A method for producing the thin film transistor element according to claim 9.   The method for manufacturing a thin film transistor element according to any one of claims 8 to 10, wherein a speed at which the patterning substrate is slid is set to 100 mm / second or less.   Before firing the semiconductor solution coated on the insulating film, the substrate is tilted with respect to the horizontal direction so that the semiconductor solution is aggregated in a region other than the hydrophobic region, and the aggregated semiconductor solution is tilted. The method for producing a thin film transistor element according to claim 1, wherein:   Before firing the semiconductor solution applied on the insulating film, gas is blown from the side surface of the substrate to aggregate the semiconductor solution in a region other than the hydrophobic region, and the aggregated semiconductor solution has an inclination. The method for manufacturing a thin film transistor element according to claim 1, wherein: A method of patterning a coated semiconductor layer on an insulating film,
Forming a hydrophobic region having a water contact angle of 80 ° to 110 ° by subjecting the insulating film having a water contact angle of 60 ° to 80 ° to fluorination treatment;
A process of patterning the coating-type semiconductor layer in a self-organized manner by applying a semiconductor solution obtained by dissolving a semiconductor material in an organic solvent on the insulating film and then baking the semiconductor solution;
In this order,
The method of patterning a coated semiconductor layer, wherein a difference in water contact angle between the insulating film and the hydrophobic region is in a range of 20 ° to 30 °.