JP2014170964A - System and method to manufacture magnetic random access memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system and method to manufacture magnetic random access memory.SOLUTION: In a particular embodiment, a method of making a magnetic tunnel junction memory system includes forming a portion of a metal layer in an unbranched source line having a substantially rectilinear portion. The method also includes coupling the source line, at the substantially rectilinear portion, to a first transistor using a first via. The first transistor is configured to supply a first current received from the source line to a first magnetic tunnel junction device. The method includes coupling the source line to a second transistor using a second via, where the second transistor is configured to supply a second current received from the source line to a second magnetic tunnel junction device.

Description

  The present disclosure relates generally to the manufacture of magnetic random access memory (MRAM).

  Advances in technology have made computing devices smaller and more powerful. A variety of portable personal computing devices currently exist, including, for example, wireless computing devices such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight and easy to carry. More specifically, mobile wireless telephones such as mobile telephones and Internet Protocol (IP) telephones can transmit voice packets and data packets over a wireless network. In addition, many such wireless telephones include other types of devices built in. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Such wireless telephones can also process executable instructions, including software applications such as web browser applications that can be used to access the Internet. As such, these wireless telephones can include significant computing capabilities.

US Patent Application Publication No. 2002/057593 US Patent Application Publication No. 2004/119101 US Patent Application Publication No. 2007/114606 US Patent Application Publication No. 2006/198196

  Magnetic random access memory (MRAM) may be incorporated into systems where power savings are a consideration, such as embedded memory applications. Improvements in MRAM manufacturing that result in lower manufacturing costs help make MRAM a more practical replacement for other types of memory.

  In one particular embodiment, a method of making a magnetic tunnel junction (MTJ) memory system is disclosed. The method includes forming a portion of a metal layer in a source line having a substantially straight portion, and coupling the source line to the first transistor using a first via at the substantially straight portion. Including the step of. The first transistor is configured to supply a first current received from the source line to a first magnetic tunnel junction (MTJ) device. The method also includes coupling the source line to a second transistor using a second via, the second transistor passing a second current received from the source line to a second magnetic tunnel junction. It is configured to supply to a device (MTJ).

  In another particular embodiment, an apparatus is disclosed that includes a memory for storing data. The memory includes a first transistor including a first source terminal, a first magnetic tunnel junction (MTJ) device connected to the first transistor, and a first region that is conductive and substantially straight. Including source lines. The source line supplies a first current to the first transistor at a first source terminal. The source line is coupled from the first region to the first source terminal using the first via and supplies a second current to the second transistor.

  In another specific embodiment, a computer-readable tangible medium is disclosed, the computer-readable tangible medium forming a source line that includes a conductive material having a substantially straight region by a semiconductor manufacturing system. Includes possible instructions. The source line supplies current to the first memory cell and the second memory cell. The first memory cell includes a first transistor coupled to a source line using a first via, the first transistor passing a first current to a first magnetic tunnel junction (MTJ) device. Supply. The second memory cell includes a second transistor coupled to the source line using a second via. The second transistor supplies a second current to a second magnetic tunnel junction (MTJ) device.

  Improvements provided by the disclosed structure may include simplification of placement, simplification of three-dimensional topography, and reduced resistance of current carrying lines.

  One particular advantage gained by at least one of the disclosed embodiments is improved manufacturability of the MRAM due, at least in part, to a simple source line design. Another special advantage gained by at least one of the disclosed embodiments is reduced resistance of the connection lines, which can reduce power consumption.

  Other aspects, advantages and features of the present disclosure will be reviewed throughout this specification, including the following "Brief Description of the Drawings", "Modes for Carrying Out the Invention" and "Claims" section. It will become clear later.

FIG. 2 is a block diagram of one specific embodiment of an MRAM device. FIG. 2 is a top view of one particular embodiment of an MRAM device. 1 is a cross-sectional block diagram of one particular embodiment of an MRAM system. It is sectional drawing of the MRAM apparatus of FIG. 2 is a flow diagram of one particular embodiment for illustration of a method of making an MRAM device. 1 is a block diagram of a portable device including an MRAM system, according to one particular embodiment. FIG. 5 shows a specific illustrative embodiment of an electronic device manufacturing method 700.

  Referring to FIG. 1, a block diagram of one particular embodiment of a magnetic random access memory (MRAM) (or “memory”) device is disclosed, indicated generally at 100. Device 100 includes a first MRAM cell 102 and a second MRAM cell 104. To simplify the description of the MRAM device 100, only two cells are shown in the device 100, but it should be understood that the MRAM device includes more than two cells. The first MRAM cell 102 and the second MRAM cell 104 are substantially the same, and corresponding components are arranged at the mirror image positions of each other and on either side of the mirror image plane 101. The component parts of the first MRAM cell 102 will be described in detail. Each component portion of the first MRAM cell 102 can be found in the second MRAM cell 104.

  The first MRAM cell 102 includes a transistor 112 that includes a shared source 108, a channel region 113, and a drain 110 with the second MRAM cell 104. A first metal layer M1 is disposed above the transistor 112. The first metal layer can be separated into a plurality of portions that are insulated from each other. For example, the first portion 118 functions as a source contact shunt (source shunt) 106, ie, a conductor that couples two or more source contacts. The second portion 114 of M1 functions as a drain contact shunt (drain shunt) 114, ie, a conductor that couples two or more drain connectors. Source contact shunt 106 may be connected to source 108 by one or more source contacts 116. In the device 100 of FIG. 1, two contacts 116 are shown connecting the source 108 to the source contact shunt 106. By having two source contacts 116, it is possible to reduce the resistance between the source contact shunt 106 and the source 108 because the source contacts 116 are electrically in parallel.

  The source contact shunt 106 is electrically connected to the source line 120 by a conductive via 118. The source line 120 is disposed in a second metal layer M2 that is electrically insulated from the first metal layer M1. Source line 120 in M 2 can supply source current to source 108 via via 118, source contact shunt 106, and source contact 116. As shown in apparatus 100, source line 120 is substantially straight in shape. That is, the source line 120 has a substantially straight portion and is formed in M2, and the source line 120 is substantially perpendicular to the main axis 105 of the source contact shunt 106. The source line 120 is substantially unbranched, which means that there is essentially no branch extending from the main axis 121 of the source line 120. In one illustrative embodiment, the source line 120 has a rectangular cross section. Since the source line 120 has a substantially straight shape (straight line) and no branch, the productivity of the MRAM device 100 can be improved. This is because the production of a straight source line can be much simpler than the production of a source line containing branches.

  A drain contact shunt 114 is also formed in M 1 and is electrically isolated from the source contact shunt 106. In one illustrative embodiment, drain contact shunt 114 is electrically connected to drain 110 by two drain contacts 117. In another particular embodiment for illustration, there may be more than two drain contacts or fewer than two drain contacts. By having at least two drain contacts 117 functioning in parallel, the resistance between the drain contact shunt 114 and the drain is less than the resistance associated with one drain contact 117.

  The drain contact shunt 114 is electrically connected to a portion 122 of the M2 layer that is electrically isolated from the source line 120. Portion 122 is connected to lower contact 140 of magnetic tunnel junction (MTJ) 150 by electrical via 130. The lower contact 140 of the MTJ 150 is disposed in the metal layer M3. The other part of the M3 layer is electrically insulated from the M2 layer. Therefore, the electrical via 130 connects the portion 122 connected to the drain contact shunt 114 to the lower contact 140 of the MTJ 150. The upper contact 152 of the MTJ 150 is electrically connected to a portion 160 of the fourth metal layer M4, and the metal layer M4 is located above the M3 layer and insulated from the M3 layer.

  In one particular embodiment for illustration, the apparatus 100 is a processor (shown) for retrieving a portion of the data stored in the memory 100 and for supplying processed data to an output device (not shown). Not shown). In one illustrative embodiment, the apparatus 100 operates to perform wireless communication with a remote device (not shown). For example, the remote device is one of a mobile phone and a personal digital assistant. In one particular illustrative embodiment, the apparatus 100 comprises a set top box, music player, video player, entertainment unit, navigation device, communication device, personal digital assistant (PDA), fixed location data unit, and computer. The device 100 is included in devices selected from the group (not shown), and the device 100 is integrated into these devices.

  In operation, the source 108 is shared by the cells 102 and 104 to supply current to each of the first MRAM cell 102 and the second MRAM cell 104. Source 108 receives current from source line 120 located in M2 through electrical via 118 to source contact shunt 106 and source contact 116.

  The MTJ 150 in the first MRAM cell 102 is located off the main axis, i.e. off-center with respect to the transistor 113, thereby allowing additional metal lines in the higher layers such as M3 and M4 to be routed to the transistor 113. It becomes possible to arrange | position close to. For example, another portion of M2 (not shown) can be placed proximate to source line 120 and isolated from source line 120 to form an electrical path that can be used to convey information.

  FIG. 1 includes cross-section indicating lines 124 and 126. The cross section indicating line 124 indicates the direction of the vertical plane cross section including the indicating line 124. The cross-section indicating line 124 is placed in the forefront portion of FIG. The cross-section indicating line 126 indicates the orientation of the second cross-sectional plane parallel to the cross-sectional plane including the indicating line 126 and is located in the background portion of the apparatus 100. Each of the cross-section indicating lines 124 and 126 represents another cross-sectional plane that will be referenced in subsequent figures.

  FIG. 2 is a top view of one particular embodiment of an MRAM device, indicated generally at 200. The apparatus 200 shown in FIG. 2 is substantially the same apparatus as the apparatus 100 shown in FIG. The same numbered identifier of FIG. 2 as the numbered identifier of FIG. 1 refers to a common element. The device 200 includes a first MRAM cell 102 and a second MRAM cell 104 configured in a mirror image arrangement with each other. Within the MRAM cell 102, the transistor 112 includes a source 108, a drain 110, and a channel 113. Source contact shunt 106 is located above source 108 and is electrically connected to source 108 by one or more source contacts 116. A source line 120 that is substantially straight over a portion is located in the second metal layer M2 above the source contact shunt 116 and is connected to the source contact shunt 116 via an electrical via 118. The drain 110 is connected to the drain contact shunt 114 by one or more drain contacts 117.

  Parallel conductive lines 240 are located in the metal layer M3 above the metal layer M2. Parallel conductive line 240 is connected to a portion of source line 120 by a plurality of electrical vias 230 (vias 230 and 232 are shown in FIG. 2) and is parallel to source line 120 in the portion of source line 120. An electrical path that reduces resistance can be formed. A signal line 220 (not shown in FIG. 1) disposed in the metal layer M4 and insulated from other metal lines can be a path for sending electrical signals. The signal line 220 shown in FIG. 2 is not electrically connected to the MRAM cell 102 or the MRAM cell 104.

  The conductive portion 122 located in the M2 layer is connected to the drain contact shunt 114 by the conductive via 123. Portion 122 is electrically isolated from source line 120. The portion 122 is electrically connected to the lower contact 140 of the metal tunnel junction (MTJ) 150. The upper contact 152 of the MTJ 150 is electrically connected to a metal line 160 disposed in the M4 layer located above the M3 layer.

  In operation, the source line 120 supplies current to the MRAM cells 102 and 104 through the source contact shunt 106 to the common source 108, respectively. The advantages of the apparatus 200 include the location of the off-center MTJ 150, the use of straight source lines 120 and parallel conductive lines 240, the use of multiple source contacts and multiple drain contacts, and a portion of M2 used for unrelated applications. included. By placing the MTJ 150 off-center, a space for accommodating a portion of the M2 layer including the signal line 220 and the source line 120 is obtained. If the source line 120 has a linear shape, the manufacture of the mask for obtaining the shape of the source line is simplified, thereby simplifying the manufacture. The parallel conductive line 240 reduces the resistance of the source line 120. The plurality of source contacts 116 reduces the electrical resistance between the source 108 and the source line 120. The plurality of drain contacts 117 reduces the resistance between the drain 110 and the drain contact shunt 114. By electrically isolating a portion of the M2 layer, the M2 layer can be used for various functions.

  FIG. 3 is a cross-sectional block diagram of one particular embodiment of an MRAM system, indicated generally at 300. The system 300 includes a first subsystem 100 (cross-sectional indication line 124, Y1-Y1 'in FIG. 1) that is the apparatus 100 of FIG. Subsystem 100 is shown in FIG. 1 and includes a first MRAM cell 102 and a second MRAM cell 104. Subsystem 350 includes a third MRAM cell 302 and a fourth MRAM cell 304. The source line 120 arranged in the M2 layer has a substantially straight shape and is substantially unbranched. That is, the source line 120 has no branch extending from the main axis 121 of the source line 120. In one particular embodiment for illustration, the M2 layer is substantially flat, at a first distance 320 from the first transistor 112 in the first MRAM cell 102, and in the third MRAM cell 302. Located at a second distance 322 from the second transistor 312. In one particular embodiment for illustration, the first distance 320 and the second distance 322 are substantially the same. Source line 120 supplies subsystem 100 and subsystem 350 with source current via corresponding source contact shunts 106 and 306. Source contact shunts 106 and 306 provide source current to corresponding sources 108, 308 via one or more corresponding source contacts. Thus, source line 120 provides source current to MRAM cells 102 and 104 via common source 108 and source current to MRAM cells 302 and 304 via common source 308. A parallel conductive line 240 is connected to the source line 120 in parallel. Conductive line 240 is located in the M3 layer above the M2 layer and is connected in parallel with a portion of source line 120 by at least two vias including vias 230 and 232. The conductive line 240 serves to reduce the resistance of the source line 120. In operation, source line 120 is substantially unbranched and supplies source current to a plurality of MRAM cells. The plurality of source contacts in each of the subsystems 100 and 350 reduces the source contact resistance with the source line 120.

  4 is a cross-sectional view of the MRAM device 100 of FIG. The device 400 includes a first MRAM cell 102 and a second MRAM cell 104. The first MRAM cell 102 and the second MRAM cell 104 are in a mirror image orientation. The first MRAM cell 102 and the second MRAM cell 104 share a common source 108. The cross-sectional view shown in FIG. 4 is Y2-Y2 '(the cross-section indicating line 126 in FIG. 1).

  A drain 110 is connected to a drain contact shunt 114 located in the M1 metal layer. The M1 metal layer is located above the transistor 112. An electrical via 123 connects the drain contact shunt 114 to a portion 122 of the M2 metal layer proximate to the M1 metal layer. A via 130 connects a portion 122 of the M2 metal layer to a portion 140 of the M3 metal layer located above the M2 metal layer and connected to the lower contact of the magnetic tunnel junction (MTJ) 150. The top contact of MTJ 150 is connected to a portion 160 of the M4 metal layer. A portion 160 of the M4 metal layer can conduct current from each of the two MTJs 150 shown. Each metal layer portion can be isolated from the other metal layer portions by IMD oxides such as intermetal dielectric (IMD) oxide portions 420, 430, 440 and 450. Interlayer dielectric (ILD) oxide 410 can isolate drain contact 117 from the surrounding surface, and ILD oxide 410 can add structural support to device 400.

  Conductive portions 470 and 472 are formed from a portion of metal layer M5 and are electrically isolated from each other. Each of the conductive portions 470 and 472 can transmit a signal, and each conductive portion 470 and 472 is electrically isolated from the first MRAM cell 102 and the second MRAM cell 104.

  FIG. 5 is a flowchart of one particular embodiment for illustrating the method of making an MRAM device. At 502, a source line, such as source line 120 of FIGS. 1-3, having a substantially unbranched straight portion is formed in a portion of the metal layer. In one particular embodiment for illustration, the source line is fabricated by masking a portion of the second metal layer M2 and removing the exposed portion of M2 with an etching process. At 504, the source line is coupled to a first magnetic tunnel junction (MTJ) device using a first via to a first transistor that supplies a first current received from the source line. For example, as shown in FIGS. 1-2, the source line 120 is coupled to the first transistor 112 by a via 118 and supplies current to the MTJ device 150. In one illustrative embodiment, the conductive via is fabricated by etching a hole in the insulating layer and depositing metal along the sidewall of the hole to form a conductive bond between the conductive layers. .

  At 506, optionally, the source line is coupled to a conductive shunt in another metal layer using a first via, the conductive shunt being connected to the first source contact of the first transistor, and the first Coupled to the second source contact of the transistor. For example, FIGS. 1-2 show a source contact shunt 106 coupled with a source contact 116. At 508, the source line is coupled to the second transistor using a second electrical via to provide a second current to the second magnetic tunnel junction device. For example, FIG. 3 shows vias that couple source line 120 to MRAM cell 302. At 510, the source line is optionally connected in parallel with another conductive line using a third electrical via and a fourth electrical via. For example, FIGS. 2-3 show source line 120 coupled to parallel conductive line 240 using vias 230.

  In one illustrative embodiment, each of the above operations 502, 504, 506, 508, 510 is performed by a processor embedded in the electronic device. In another specific embodiment for illustration, some of the operations (eg, 502, 504, and 508) are performed by a processor embedded in the electronic device. The method ends at 512.

  Referring to FIG. 6, a block diagram of one illustrative embodiment of an electronic device, such as a communication device that utilizes an MRAM system, is depicted and is generally designated 600. The electronic device 600 includes a processor, such as a digital signal processor (DSP) 610. Electronic device 600 also includes a magnetic random access memory (MRAM) 664 coupled to DSP 610. In one illustrative example, MRAM 664 can be formed by any of FIGS. 1-5, or any combination thereof.

  FIG. 6 also shows a display controller 626 coupled to the digital signal processor 610 and the display 628. An encoder / decoder (CODEC) 634 may also be coupled to the digital signal processor 610. A speaker 636 and a microphone 638 can be coupled to the CODEC 634.

  FIG. 6 also illustrates that the wireless controller 640 can be coupled to the digital signal processor 610 and the wireless antenna 642. In one particular embodiment, MRAM 664, DSP 610, display controller 626, CODEC 634, and wireless controller 640 are included in a system-in-package device or system-on-chip device 622. In one particular embodiment, input device 630 and power supply 644 are coupled to system on chip device 622. Further, in one particular embodiment, display 628, input device 630, speaker 636, microphone 638, wireless antenna 642, and power source 644 are external to system on chip device 622, as shown in FIG. However, each of display 628, input device 630, speaker 636, microphone 638, wireless antenna 642, and power source 644 can be coupled to components of system-on-chip device 622, such as an interface or controller.

  The devices and functions disclosed above can be designed and configured in the form of computer files (eg, RTL, GDSII, GERBER, etc.) stored on computer readable media. Some or all of such files can be provided to manufacturers who manufacture devices based on such files. The resulting product includes a semiconductor wafer, which is then cut into semiconductor dies and packaged into semiconductor chips. The chip is then used in a device such as the device of FIG. 6 that uses MRAM.

  FIG. 7 is a diagram illustrating a specific illustrative embodiment of an electronic device manufacturing method 700. Physical device information 702 is received at manufacturing computer 700, such as at research computer 706. Physical device information 702 may include design information representing at least one physical characteristic of a semiconductor device, such as the MRAM device and system shown in FIGS. 1-5, or any combination thereof. For example, physical device information 702 can include physical parameters, material properties, and structural information input via user interface 704 coupled to research computer 706. Research computer 706 includes a processor 708, such as one or more processing cores, coupled to a computer readable medium such as memory 710. The memory 710 may store computer readable instructions that are executable by the processor 708 to convert the physical device information 702 to follow a certain file format and generate a library file 712.

  In one particular embodiment, the library file 712 includes at least one data file that includes converted design information. For example, the library file 712 includes a library of semiconductor devices including the MRAM 664 of FIG. 6, the MRAM apparatus and system of FIGS. 1-5, or any combination thereof, which is in conjunction with an electronic design automation (EDA) tool 720. Prepared for use.

  The library file 712 can be used with the EDA tool 720 in a design computer 714 that includes a processor 716 such as one or more processing cores coupled to a memory 718. The EDA tool 720 is stored in the memory 718 as processor-executable instructions so that the user of the design computer 714 can use the MRAM method, apparatus and system of FIGS. 1-5 of the library file 712, the electronic device of FIG. Combinations can be used to allow circuit design. For example, a user of the design computer 714 can input circuit design information 722 via a user interface 724 coupled to the design computer 714. The circuit design information 722 includes design information representing at least one physical characteristic of the semiconductor device such as the unbranched source line in FIGS. 1 to 5 and the unbranched source line in FIG. Can be included. To illustrate, circuit design characteristics include the identification of a particular circuit and its relationship to other elements in the circuit design, positioning information, feature size information, interconnect information, or other information that represents the physical characteristics of the semiconductor device. sell.

  The design computer 714 can be configured to convert design information including the circuit design information 722 to conform to a certain file format. To illustrate, this file formation can include a database binary file format representing planar geometry, text labels, and other information related to circuit placement, in a hierarchical format such as a graphic data system (GDSII) file format. The design computer 714 can be configured to generate a data file that includes converted design information, such as a GDSII file 726, which includes the unbranched source lines of FIGS. And information describing any of the methods in addition to other circuitry or information. To illustrate, the data file can include information corresponding to a system on chip (SOC), which includes the communication device of FIG. 6 and also includes additional electronic circuitry and components in the SOC.

  The GDSII file 726 is received at the manufacturing process 728 and the MRAM device and system including the unbranched source lines of FIGS. 1-3 can be manufactured according to the transformed information in the GDSII file 726. For example, the device manufacturing process includes providing a GDSII file 726 to the mask manufacturer 730 to create one or more masks, such as a mask to be used in a photolithography process, shown as a representative mask 732. be able to. The mask 732 can be used in the manufacturing process to produce one or more wafers 734 that can be tested and separated into dies, such as a representative die 736. Die 736 includes circuitry that includes one or more of the MRAM devices or systems of FIGS. 1-5, the electronic device of FIG. 6, or any combination thereof.

  The die 736 can be supplied to a packaging process 738 where it is incorporated into the representative package 740. For example, the package 740 can include a single die 736 or multiple dies, such as a system-in-package (SiP) configuration. Package 740 may be configured to comply with one or more standards or specifications, such as the Electronic Device Technology Joint Council (JEDEC) standard.

  Information about the package 740 can be distributed to various product designers by a part library stored in the computer 746. Computer 746 can include a processor 748, such as one or more processing cores, coupled to memory 750. The printed circuit board (PCB) tool is capable of processing PCB design information 742 that is stored in memory 750 as processor executable instructions and received via user interface 744 from a user of computer 746. The PCB design information 742 can include physical placement information on the circuit board of the packaged semiconductor device, which includes the MRAM apparatus and system of FIGS. 1-5, the electronic device of FIG. Or it corresponds to the package 740 including any combination thereof.

  Computer 746 converts PCB design information 742 to include data files such as GERBER file 752, physical placement information on the circuit board of the packaged semiconductor device, and placement of electrical connections such as traces and vias. This packaged semiconductor device that can be generated with data corresponds to a package 740 that includes either the MRAM apparatus and system of FIGS. 1-5, the communication device of FIG. 6, or any combination thereof. In another embodiment, the data file generated by the converted PCB design information can have a format other than the GERBER format.

  The GERBER file 752 can be used to create a PCB, such as a representative PCB 756, received in the board assembly process 754 and manufactured according to design information stored in the GERBER file 752. For example, the GERBER file 752 can be uploaded to one or more machines to perform various steps of the PCB production process. PCB 756 can be populated with electronic components including package 740 to form a representative printed circuit assembly (PCA) 758.

  PCA 758 can be received at product manufacturing process 760 and integrated into one or more electronic devices, such as first exemplary electronic device 762 and second exemplary electronic device 764. As a non-limiting example for illustration, the first representative electronic device 762 or the second representative electronic device 764, or both, are set-top boxes, music players, video players, entertainment units, navigation devices, communications It can be selected from the group consisting of devices, personal digital assistants (PDAs), fixed location data units, and computers. As another non-limiting example for illustration, one or more of electronic devices 762 and 764 may be a portable unit such as a mobile phone, a remote unit such as a handheld personal communication system (PCS) unit, or a personal digital assistant. A data unit, a global positioning system (GPS) enabled device, a navigation device, a fixed position data unit such as an instrument reader, or any other device that stores or retrieves data or computer instructions, or any combination thereof be able to. Although one or more of FIGS. 1-6 may illustrate remote units in accordance with the teachings of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Embodiments of the present disclosure can be suitably used in any device that includes an active integrated circuit including a memory and an on-chip circuit for testing and characterization.

  Accordingly, any of the MRAM devices and systems of FIGS. 1-6 can be manufactured, fabricated, and incorporated into an electronic device, as shown in the illustrative method 700. One or more aspects of the embodiments disclosed with respect to FIGS. 1-5 can be included in a library file 712, a GDSII file 726, a GERBER file 752, and the like at various processing stages, and even in a research computer 706 memory 710, memory 718 of design computer 714, memory 750 of computer 746, memory in one or more other computers or processors (not shown) used at various stages, such as board assembly process 754. One or more other physical embodiments, such as mask 732, die 736, package 740, PCA 758, other products (not shown) such as prototype circuits or devices, or the like It can also be incorporated into a combination. While various representative stages of production from physical device design to final product are depicted, in other embodiments, fewer stages may be used or additional stages may be included. is there. Similarly, method 700 can be performed by a single entity or by one or more entities that perform various stages of method 700.

  Those skilled in the art will understand that the various illustrative logic blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein are electronic hardware, computer, It will be further understood that it can be implemented as software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, configurations, modules, circuits, and steps have been described generally above with respect to these functions. Whether such a function is implemented as hardware or software depends on a specific application and design constraints imposed on the entire system. Those skilled in the art can implement the described functions in a variety of ways for each specific application, but such implementation decisions should be construed as departing from the scope of the present disclosure. is not.

  The method or algorithm steps described in connection with the embodiments disclosed herein may be implemented directly in hardware, in software modules executed by a processor, or in a combination of the two. . Software modules include random access memory (RAM), flash memory, read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), registers, hard disk, removable disk, compact disk read only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In alternative embodiments, the storage medium may be integral to the processor. These processors and storage media may be in an application specific integrated circuit (ASIC). The ASIC may be in a computing device or user terminal. In alternative embodiments, the processor and the storage medium may reside in a computing device or user terminal as separate components.

  The previous description of the disclosed embodiments is presented to enable any person skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the scope of the disclosure. can do. Accordingly, the present disclosure is not limited to the embodiments set forth herein, but provides the widest possible range consistent with the principles and novel features defined by the appended claims. It should be done.

100 Magnetic Random Access Memory (MRAM) Device 101 Mirror Image Surface 102 First MRAM Cell 104 Second MRAM Cell 105 Main Shaft of Source Contact Shunt 106 Source Contact Shunt 108 Source 110 Drain 112 Transistor 113 Channel Region 114 Drain Contact Shunt (Drain Shunt) )
116 Source contact 117 Drain contact 118 Electric via 120 Source line 121 Main axis of source line 122 Part of M2 metal layer 123 Electric via, conductive via 124 Cross section indicating line 126 Cross section indicating line 130 Via, electric via 140 Lower contact of MTJ 150 Magnetic tunnel Junction (MTJ)
152 MTJ top contact 160 Part of metal layer M4, metal line 200 MRAM device 220 signal line 230 via 232 via 240 parallel conductive line 302 third MRAM cell 304 fourth MRAM cell 306 source contact shunt 308 source 312 second Transistor 320 First Distance 322 Second Distance 350 Subsystem 410 Interlayer Dielectric (ILD) Oxide 420 Intermetal Dielectric (IMD) Oxide Part 430 Intermetal Dielectric (IMD) Oxide Part 440 Intermetal Dielectric (IMD) oxide portion 450 intermetal dielectric (IMD) oxide portion 470 conductive portion 472 conductive portion 600 electronic device 610 digital signal processor (DSP)
622 System on chip device 626 Display controller 628 Display 630 Input device 634 Encoder / decoder (CODEC)
636 Speaker 638 Microphone 640 Wireless controller 642 Wireless antenna 644 Power supply 664 Magnetic random access memory (MRAM)
M1 1st metal layer M2 2nd metal layer M3 metal layer M4 4th metal layer M5 metal layer

Claims (37)

Forming a portion of the metal layer in a source line having a substantially straight portion;
Coupling the source line to the first transistor using a first via at the substantially linear portion, wherein the first transistor receives a first current received from the source line; Configured to supply a first magnetic tunnel junction device;
Coupling the source line to a second transistor using a second via, wherein the second transistor receives a second current received from the source line in a second magnetic tunnel junction device; A step configured to supply to,
A method for fabricating a magnetic tunnel junction memory system, comprising:
A method wherein a portion of the source line is connected in parallel with a substantially straight portion of another conductive line by using a third via and a fourth via.   The method of claim 1, wherein the source line is substantially unbranched.   The method of claim 1, wherein the metal layer is substantially planar and is disposed at a first distance from the first transistor and at a second distance from the second transistor.   4. The method of claim 3, wherein the first distance and the second distance are substantially the same. The first via connects the source line to a shunt in another metal layer, the shunt comprising:
A first source contact coupled to a source terminal of the first transistor;
A second source contact coupled to the source terminal of the first transistor;
The method of claim 1, wherein   Forming the metal layer, electrically connecting the source line to the first transistor, and electrically connecting the source line to the second transistor are incorporated in an electronic device. The method of claim 1, controlled by a controlled processor. Forming a portion of the metal layer in a source line having a substantially straight portion;
A second step of coupling the source line to the first transistor using a first via at the substantially straight portion, wherein the first transistor receives from the source line; A second step, configured to supply a current to the first magnetic tunnel junction device;
A third step of coupling the source line to a second transistor using a second via, wherein the second transistor receives a second current received from the source line in a second magnetic field; A third step configured to supply a tunnel junction device;
A method comprising:
The first via connects the source line to a shunt in another metal layer, the shunt comprising:
A first source contact coupled to a source terminal of the first transistor;
A second source contact coupled to the source terminal of the first transistor;
Combined with
A method wherein a portion of the source line is connected in parallel with a substantially straight portion of another conductive line by using a third via and a fourth via.   The method of claim 7, wherein the first step, the second step, and the third step are performed by a processor embedded in an electronic device. A memory for storing data, the memory comprising:
A first transistor including a first source terminal;
A first magnetic tunnel junction (MTJ) device connected to the first transistor;
A source line that includes a first region that is conductive and substantially straight, the source line supplying a first current to the first transistor at the first source terminal; A source line coupled from the first region to the first source terminal using a first via, the source line supplying a second current to a second transistor;
A conductive line connected in parallel with at least a portion of the source line using a third via and a fourth via;
A device comprising a memory.   The apparatus of claim 9, wherein the source line is substantially unbranched.   The apparatus of claim 9, further comprising a processor that captures a portion of the data stored in the memory and provides the processed data to an output device.   The apparatus of claim 9, wherein the apparatus is operative to perform wireless communication with a remote station.   The apparatus of claim 12, wherein the remote station comprises one of a mobile phone, a personal digital assistant, and a set top box.   The apparatus of claim 9, wherein the source line is electrically connected to the second transistor using a second via.   The apparatus of claim 9, wherein the second transistor provides a portion of the second current to a second MTJ device.   The first via couples the source line to a shunt portion of a first metal layer coupled to the first source terminal, and the shunt portion is coupled to the first source terminal. The apparatus of claim 9, wherein the device is coupled to a first source contact and the shunt portion is coupled to a second source contact that is coupled to the first source terminal.   The third transistor using the first source terminal of the first transistor as a common source terminal, further comprising a third transistor for supplying a third current to a third MTJ device. 9. The apparatus according to 9.   The apparatus of claim 9, wherein the apparatus is incorporated into at least one semiconductor die.   A device selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communication device, personal digital assistant (PDA), fixed location data unit, and computer, in which the memory is embedded The apparatus of claim 9, further comprising: By semiconductor manufacturing system,
A source line including a conductive material having a substantially straight region is formed, and a second source line that is conductive is formed, and the second source line includes a third via and a fourth A computer-readable tangible medium comprising computer-executable instructions to be connected in parallel with at least a portion of the source line using
The source line supplies current to the first memory cell and the second memory cell;
The first memory cell includes a first transistor coupled to the source line using a first via, and the first transistor conducts a first current to a first magnetic tunnel junction (MTJ). To the device,
The second memory cell includes a second transistor coupled to the source line using a second via, the second transistor providing a second current to a second MTJ device; Computer-readable tangible medium.   21. The source line is formed in a first portion of a metal layer, and the first MTJ device is electrically connected to the first transistor by a second portion of the metal layer. The computer-readable tangible medium described.   21. The computer readable tangible medium of claim 20, wherein the first memory cell comprises a third transistor having a third transistor source terminal comprising a source terminal of the first transistor.   21. The first via directly connects the source line to an electrical shunt coupled to a first source contact of the first transistor and a second source contact of the first transistor. A computer-readable tangible medium described in 1. Means for forming a source line having a substantially straight portion;
Means for coupling the source line to a first transistor by using a first via, wherein the first transistor receives a first current received from the source line in a first magnetic tunnel junction; Means configured to supply the device;
Means for coupling the source line to a second transistor by using a second via, wherein the second transistor receives a second current received from the source line in a second magnetic tunnel junction; Means configured to supply the device;
An apparatus for fabricating a magnetic tunnel junction memory device comprising:
The first via directly connects the source line to an electrical shunt coupled to a first source contact of the first transistor and a second source contact of the first transistor; Wherein a part of the device is connected in parallel with a substantially straight part of another conductive line by using two vias.   25. The apparatus of claim 24, wherein the source line is substantially unbranched.   Means for coupling the source line to a third transistor using a third via, wherein the third transistor receives a third current received from the source line in a third magnetic tunnel junction device; 25. The apparatus of claim 24, wherein the third transistor shares a source terminal with the first transistor.   The apparatus of claim 24, wherein the apparatus is incorporated into at least one semiconductor die.   Selected from the group consisting of a set-top box, music player, video player, entertainment unit, navigation device, communication device, personal digital assistant (PDA), fixed location data unit, and computer, in which the magnetic tunnel junction memory device is The apparatus of claim 24, further comprising a device to be incorporated. Receiving design information representative of at least one physical characteristic of a semiconductor device, the semiconductor device including a memory for storing data, the memory comprising:
A first transistor including a first source terminal;
A first magnetic tunnel junction (MTJ) device coupled to the first transistor;
A source line comprising a first region that is conductive and substantially straight, wherein the source line supplies a first current to the first transistor at the first source terminal; and A source line coupling the first region to the first source terminal using a first via, the source line supplying a second current to a second transistor;
A conductive line connected in parallel with at least a portion of the source line by using a third via and a fourth via;
Preparing, steps;
Converting the design information to conform to a file format;
Generating a data file containing the converted design information, comprising:
The method wherein the first via directly connects the source line to an electrical shunt coupled to a first source contact of the first transistor and a second source contact of the first transistor.   30. The method of claim 29, wherein the file format is GDSII format. Receiving a data file containing design information corresponding to a semiconductor device;
Manufacturing the semiconductor device according to the design information, wherein the semiconductor device includes a memory for storing data, the memory comprising:
A first transistor including a first source terminal;
A first magnetic tunnel junction (MTJ) device coupled to the first transistor;
A source line that includes a first region that is conductive and substantially straight, the source line supplying a first current to the first transistor at the first source terminal; A source line that couples the first region to the first source terminal using a first via and the source line supplies a second current to a second transistor;
A conductive line connected in parallel with at least a portion of the source line by using a third via and a fourth via;
A step comprising:
A method comprising:
The method wherein the first via directly connects the source line to an electrical shunt coupled to a first source contact of the first transistor and a second source contact of the first transistor.   32. The method of claim 31, wherein the file format is GDSII format. Receiving design information including physical location information of a packaged semiconductor device on a circuit board, the packaged semiconductor device comprising:
A first transistor including a first source terminal;
A first magnetic tunnel junction (MTJ) device coupled to the first transistor;
A source line that includes a first region that is conductive and substantially straight, the source line supplying a first current to the first transistor at the first source terminal; A source line that couples the first region and the first source terminal using a first via, and the source line supplies a second current to a second transistor;
A conductive line connected in parallel with at least a portion of the source line by using a third via and a fourth via;
Comprising a semiconductor structure comprising:
Converting the design information to generate a data file;
A method comprising:
The method wherein the first via directly connects the source line to an electrical shunt coupled to a first source contact of the first transistor and a second source contact of the first transistor.   34. The method of claim 33, wherein the data file has a GERBER format. Receiving a data file containing design information, including physical location information of a packaged semiconductor device on a circuit board;
Manufacturing the circuit board according to the design information, wherein the packaged semiconductor device comprises:
A first transistor including a first source terminal;
A first magnetic tunnel junction (MTJ) device coupled to the first transistor;
A source line that includes a first region that is conductive and substantially straight, the source line supplying a first current to the first transistor at the first source terminal; A source line that couples the first region and the first source terminal using a first via, and the source line supplies a second current to a second transistor;
A conductive line connected in parallel with at least a portion of the source line by using a third via and a fourth via;
A step comprising:
A method comprising:
The method wherein the first via directly connects the source line to an electrical shunt coupled to a first source contact of the first transistor and a second source contact of the first transistor.   36. The method of claim 35, wherein the data file has a GERBER format.   Incorporating the circuit board into a device selected from the group consisting of a set-top box, music player, video player, entertainment unit, navigation device, communication device, personal digital assistant (PDA), fixed location data unit, and computer. 36. The method of claim 35, further comprising:

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