JP2004119897A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory wherein a power supply bounce is minimized and a readout margin of information is enhanced. <P>SOLUTION: The semiconductor memory has at least one cell array block (MB<00>) comprising a plurality of memory cells (MC<00>-MC<03>). The cell array block comprises word lines (WWL<0>, RWL<0>), a plurality of memory cells to be simultaneously selected by the word lines, a plurality of power supply lines (GND<0>-GND<3>) connected to one ends of the plurality of selected memory cells respectively, and a plurality of bit lines (BL<0>-BL<3>) connected to the other ends of the plurality of memory cells. According to this structure, the power supply bounce is minimized and the readout margin is enhanced in this semiconductor memory. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device having a configuration in which a current flows into a power supply line via a memory cell when reading stored data.
[0002]
[Prior art]
In recent years, as a memory device that can be replaced with a DRAM, an EEPROM, or the like, an MRAM configured using a magnetoresistive element having non-volatility, high-speed operation, high integration, and high reliability is expected, and its development is proceeding. (For example, see Non-Patent Documents 1 and 2).
[0003]
[Non-patent document 1]
ISSCC Proceedings TA7.2, pp128-129
[0004]
[Non-patent document 2]
ISSCC Proceedings TA7.3, pp130-131
As the magnetoresistive element, there are a GMR (Giant Magneto Resistive) element utilizing a magnetoresistance change due to a spin-polarized tunnel effect in a magnetic / insulator laminated structure, an MTJ (Magnetic Tunnel Junction) element, and the like. The MRAM using is promising.
[0005]
The MTJ element has a structure in which one ferromagnetic film sandwiches one insulating film, and a tunnel current is generated when the spin directions of the ferromagnetic films are parallel and antiparallel. It has the characteristic that the size of changes. When the spin directions are parallel, the resistance of the MTJ element is low because the tunnel current is large, and when the spin directions are antiparallel, the resistance of the MTJ element is low because the tunnel current is small. Get higher. In the MRAM, information is recorded as “0” data when the resistance value of the MTJ element is low, and as “1” data when the resistance value is high.
[0006]
FIG. 16 shows an equivalent circuit of one typical 1Tr-1 MTJ type memory cell of an MRAM using the MTJ element, and FIG. 17 shows an equivalent circuit of the memory cell array. Symbols in the figure are MB for a cell array block, MC for a memory cell, MTR for a memory cell transistor, GND for a ground electrode line, that is, a power supply line, BL for a bit line, WWL for a write word line, and RWL for a read word. Represents a line. <Nm> (nm is an integer) indicates <row column> in the memory cell.
[0007]
18 is a layout example of FIG. 17, and FIG. 19 is a cross-sectional structure diagram of a 1Tr-1MTJ type memory cell according to the related art. The symbols in the drawing mean that Gox is a gate insulating film, DL is a diffusion film, RWL is a read word line, MO is a first wiring layer, GND is a power supply line, M1 is a second wiring layer, and WWL is a write word. Line, CD is a contact from M0 to DL, V1 is a contact from M1 to M0, MTJ is a ferromagnetic tunnel junction element, MX is a wiring layer for MTJ connection, and CX is a contact from MX to M1.
[0008]
FIG. 20 is a circuit diagram in which GND between adjacent rows in the equivalent circuit of FIG. 17 is shared. FIG. 21 is a layout example of FIG.
[0009]
As shown in FIG. 17, FIG. 18, FIG. 19, FIG. 20, and FIG. 21, BL and WWL are wired in the orthogonal direction, and when writing information to a memory cell, a combined magnetic field is generated by applying a current to BL and WWL. And write the information. When reading information from a memory cell, RWL is activated, a current flows from BL to GND, and information is read by a sense amplifier connected to BL.
[0010]
However, the conventional power line wiring has the following problems.
[0011]
[Problems to be solved by the invention]
As shown in FIGS. 17 and 20, all of the conventional GNDs are wired in the same direction as RWL / WWL, and the memory cells are separated for each row. In such a configuration, currents from all the BLs in one memory cell array block flow into one GND wiring during a read operation, so that a large current flows through one GND wiring. There is a problem that a so-called power bounce occurs.
[0012]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device that minimizes power bounce on a power line and improves a read margin.
[0013]
[Means for Solving the Problems]
The semiconductor memory device of the present invention has at least one cell array block including a memory cell including a plurality of magneto-resistive elements, and the cell array block includes a word line and at least a read operation performed simultaneously by the word line. A plurality of selected memory cells, a plurality of power supply lines connected to one end of each of the selected plurality of memory cells, and a plurality of bit lines connected to the other end of each of the plurality of memory cells. It is characterized by having.
[0014]
With this configuration, it is possible to provide a semiconductor memory device that minimizes power bounce in a power line and improves a read margin.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
(1st Embodiment)
FIG. 1 shows a circuit configuration of the first embodiment of the present invention. This embodiment is a first equivalent circuit of a 1Tr-1MTJ type memory cell array. MB <00> and MB <10> are cell array blocks, respectively. One cell array block MB <00> includes four memory cells MC <00> to MC <03> and the other cell array block MB <10> also includes four memory cells MC <10> to MC <13>. Each of the memory cells MC <00> to MC <03> and MC <10> to MC <13> is one ferromagnetic tunnel element which is a magnetoresistive element, that is, MTJ elements MTJ <00> to MTJ <03>, MTJ. <10> to MTJ <13> and one memory cell transistor MTR <00> to MTR <03>, MTR <10> to MTR <13>.
[0017]
In the cell array blocks MB <00> and MB <10>, four bit lines BL <0> to BL <3> and four ground-side power supply lines GND <0> to GND <3> are commonly arranged. You. That is, the bit line BL <0> and the power supply line GND <0> are commonly arranged for the memory cells MC <00> and MC <10>. One end of each of the MTJ elements MTJ <00> and MTJ <10> is connected to the bit line BL <0>, and the other end is connected to the drain side of the memory cell transistors MTR <00> and MTR <10>, respectively. The sources of the transistors MTR <00> and MTR <10> are connected to the power supply line GND <0>, respectively. The remaining memory cells MC <01> to MC <03> and MC <11> to MC <13> are similarly connected.
[0018]
One write word line WWL <0> is commonly provided to the MTJ elements MTJ <00> to MTJ <03> in the cell array block MB <00>, and the memory cell transistors MTR <00> to MTR <03> are provided. Are commonly provided with one read word line RWL <0>. Similarly, one write word line WWL <1> is commonly provided for the MTJ elements MTJ <10> to MTJ <13> in the cell array block MB <10>, and the memory cell transistors MTR <10> to MTR are provided. One read word line RWL <1> is commonly provided for <13>.
[0019]
In the drawing, <nm> (nm is an integer) respectively corresponds to <row column> in each memory cell.
[0020]
For example, writing of information to the memory cell MC <00> shown in FIG. 1 is performed by the MTJ element MTJ by a combined magnetic field generated by applying current to the bit line BL <0> and the write word line WWL <0> simultaneously. This is performed by controlling the direction of spin of the free layer of <00>. That is, when a current flows through the bit line BL <0>, the bit line BL is transmitted not only to the MTJ <00> in the memory cell block MB <00> but also to the MTJ <10> in another memory cell block MB <10>. A magnetic field generated by a current flowing through <0> is applied. When a write current flows through WWL <0> in this state, a combined magnetic field with a magnetic field generated by this current acts only on MTJ element MTJ <00>, and thus selected memory cell MC <00>. Information is written only to At the time of writing this information, the memory cell transistor MTR <00> remains off, and no current flows through the power supply line GND <0>.
[0021]
Thereafter, when reading information, the memory cell transistors MTR <00> to MTR <03> are simultaneously turned on, for example, by activating the read word line RWL <0>. At this time, when the four bit lines BL <0> to BL <3> are activated at the same time, currents from bit lines BL <0> to BL <3> are applied to memory cell transistors MTR <00> to MTR, respectively. The current flows through the power supply lines GND <0> to GND <3> via <03>, and the current is detected by sense amplifiers (not shown) connected to the bit lines BL <0> to BL <3>, respectively. Information is read from MC <00> to MC <03>. In the other memory cell block MB <10>, the read word line RWL <1> is not activated, so that the power supply lines GND <0> to GND <3> are connected to the memory cells MC <10> to MC <13>. The read current does not flow at the same time.
[0022]
That is, in this embodiment, the power supply lines GND <0> to GND <3> are arranged in the same direction with the corresponding bit lines BL <0> to BL <3> in a one-to-one relationship. ing. By providing such power supply lines GND <0> to GND <3>, bit lines BL <0> to BL <3> can be changed from power supply lines GND <0> to GND <3> during information reading. The respective currents flow in only the cell array block MB <00>. For example, a structure in which only one current from one corresponding bit line BL <0> flows into one power supply line GND <0>. For this reason, the power supply bounce on the power supply line GND <0> can be minimized, and a reliable read operation can be realized without causing a malfunction in the subsequent sense amplifier. The same applies to other power supply lines GND <1> to GND <3>.
[0023]
With such an arrangement, even if each power line is provided corresponding to each bit line as in the first embodiment shown in FIG. Thus, it is possible to provide a semiconductor memory device that has good power bounce characteristics without deterioration and that can guarantee highly accurate information reading.
[0024]
FIG. 2 shows a first layout example of the MRAM according to the equivalent circuit shown in the first embodiment of FIG. FIG. 3 shows a cross-sectional structure of one memory cell constituting the MRAM as viewed in a direction indicated by an arrow by cutting along a line III-III 'in FIG. Hereinafter, the structure, operation, and effect of the present embodiment will be described in detail with reference to FIGS.
[0025]
FIG. 2 is a diagram showing a layout example of the four memory cells MC <00>, MC <01>, MC <10>, and MC <11> shown in FIG. FIG. 3 is a sectional structural view of a memory cell MC <00> in FIG.
[0026]
2 and 3, the source diffusion layer DL1 and the drain diffusion layer DL2 of the memory cell transistor MTR <00> are formed in the surface region of the silicon semiconductor substrate SUB, and the silicon semiconductor substrate SUB extends over these diffusion layers DL1 and DL2. A write word line RWL <0> as a gate electrode is formed on the surface via a gate oxide film Gox. Other memory cells MC <01>, MC <10>, and MC <11> are similarly formed.
[0027]
3, an interlayer insulating film 10 is deposited on silicon semiconductor substrate SUB so as to cover all memory cell transistors including memory cell transistor MTR <00>, and connected to diffusion layers DL1 and DL2 in interlayer insulating film 10. The contacts CD1 and CD2 are formed, and a power line GND <0> on the ground side and a first wiring layer M0 are formed on the surface of the interlayer insulating film 10 by, for example, copper embedded wiring. As shown in FIG. 2, the first wiring layer M0 protrudes into a space formed between a memory cell MC <00> including a memory cell transistor MTR <00> and an adjacent memory cell MC <10>. Is formed so as to extend from the contact CD2.
[0028]
An interlayer insulating film 20 is deposited on the interlayer insulating film 10, and the interlayer insulating film 20 is formed on the second wiring layer M0 via a via V1 connected to a tip end of the first wiring layer M0 protruding into the space. M1 is formed. At the same time that the second wiring layer M1 is formed, a write word line WWL <0> is formed at an overlapping position above the read word line RWL <0>.
[0029]
An interlayer insulating film 30 is deposited on the interlayer insulating film 20, and the interlayer insulating film 30 has a contact CX connected to the second wiring layer M1 above the via V1 and a third contact CX connected to the contact CX. The wiring layer MX is formed.
[0030]
An MTJ element MTJ <00> as a magnetoresistive element is formed on the third wiring layer MX at a position facing the write word line WWL <0>. In this state, an interlayer insulating film 40 is formed on interlayer insulating film 30, and a bit line BL <0> having a width completely covering MTJ element MTJ <00> is formed on the surface of interlayer insulating film 40. It is arranged in a direction orthogonal to write word line WWL <0>. In FIG. 3, the layer of the power supply line GND <0> drawn by a thin line continues as the same power supply line as the power supply line GND <0> drawn by a thick line, and extends from the front to the back of the drawing. As shown in FIG. 2, the power supply line GND <0> is arranged in parallel with the bit line BL <0>.
[0031]
In the layout shown in FIG. 2, memory cells MC <00> and MC arranged as elements in adjacent cell array blocks MB <00> and MB <10> along bit line BL <0> in FIG. The contact connected to the drain of the transistor is arranged by utilizing the space formed between <10>. That is, as described with reference to FIG. 3, the contact CX for connection between the drain of the memory cell transistor MTR <00> of the memory cell MC <00> and the MTJ element MTJ <00> is formed in this space. You. Similarly, as shown in FIG. 2, a contact CX for connection between the memory cell transistor MTR <10> of the memory cell MC <10> and the MTJ element MTJ <10> is formed using the same space.
[0032]
As described above, when the MTJ element is formed at a position directly above the gate electrode of each memory cell transistor, it is necessary to arrange a write word line using, for example, a metal wiring formed immediately below the MTJ element. There is. For this reason, the contact for connecting the MTJ element and the drain of the transistor is arranged at a position offset with respect to a line perpendicular to the substrate SUB connecting the transistor and the MTJ element. Therefore, as shown in FIG. 2, the space between the memory cells MC <00> and MC <10> adjacent to each other is used to connect the MTJ element to the drain of the memory cell transistor in each memory cell. The contact CX is formed.
[0033]
Further, in the example shown in FIG. 2, the gate width direction of the memory cell transistor MTR <00> is orthogonal to the longitudinal direction of the bit line BL <0>. On the other hand, the power supply line GND <0> provided corresponding to the bit line BL <0> is provided in the space between the two adjacent bit lines BL <0> and BL <1> in the same direction as the bit line BL <0>. Placed in Therefore, in order to connect the source region DL1 of the memory cell transistor MTR <00> shown in FIG. 3 to the power supply line GND <0>, a branch formed by branching from the bit line BL <0> into a T shape. The section BGND <00> is arranged.
For example, when writing information to each of the memory cells MC <00> to MC <03> in the cell array block MB <00>, a current corresponding to the information to be written to the bit lines BL <0> to BL <3> flows. At the same time, a current also flows through the write word line WWL <0>. For example, in the memory cell MC <00> shown in FIG. 3, the free layer of the MTJ element MTJ <00> is generated by a combined magnetic field generated by a current flowing through the bit line BL <0> and the write word line WWL <0>. Is regulated, and information is written to the memory cell MC <00>.
[0034]
Thereafter, when reading information, for example, a current flows through the read word line RWL <0> of the selected cell array block MB <00> to be activated, the memory cell transistor MTR <00> is turned on, and the bit is turned on. When the current from the line BL <0> is the MTJ element MTJ <00>, the wiring MX, the contact CX, the wiring M1, the via V1, the wiring M0, the drain contact CD2, the drain region DL2, the channel, the source region DL1, the source contact CD1, By sequentially energizing the branch part BGND <00> and the power supply line GND <0>, information is read by a sense amplifier (not shown) connected to the bit line BL <0>. At this time, the read current from the memory cell MC <00> flows into the power supply line GND <0> via the branching section BGND <00> dedicated to the memory cell MC <00>, and the read current from another memory cell MC <00>. Since no current flows, no power bounce occurs.
[0035]
In the layout shown in FIG. 2, the power supply lines GND <0> and GND <1> are arranged in the same direction as the bit lines BL <0> and BL <1>, respectively. By arranging such power supply lines, a current flowing from the bit line to the power supply line at the time of reading has a structure in which only one current flows from one bit line to one power supply line in a cell array block unit. . For this reason, the power bounce of the power supply line can be minimized, the possibility that a malfunction occurs in the sense amplifier is extremely reduced, and a large read margin can be taken, so that a reliable read operation is realized.
[0036]
In addition, by taking a symmetrical layout as shown by the arrangement of the contacts CX in the memory cells MC <00> and MC <10> in FIG. 2, the space between the memory cells is effectively used, and the layout area is reduced. Can be done.
[0037]
Although not shown, for example, in FIG. 3, the source diffusion layer DL1 which is a node connected to the power supply line GND <0> of the transistor MTR <00> of the memory cell MC <00> is connected to the memory cell MC in the adjacent cell array block. , It is possible to share one diffusion layer between the two transistors and further reduce the layout area of the memory cell. This is because the read word lines of two adjacent cell array blocks are not activated at the same time at the time of reading, and currents from two transistors do not simultaneously flow into the branch portion BGND <00> of the power supply line. Thus, such an arrangement becomes possible.
[0038]
FIG. 4 shows a second layout example in the embodiment of FIG. 4 is a diagram showing a layout example of a portion of four memory cells MC <00>, MC <01>, MC <10>, and MC <11> in FIG. 1 similarly to the layout of FIG. It is. 4, parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and the following description will be made by focusing only on differences in layout between the two.
[0039]
In the layout shown in FIG. 2, write word lines WWL <0>, WWL <1> and read word lines RWL <0>, RWL <1> are arranged above memory cell transistors so as to overlap each other. . On the other hand, in the layout of FIG. 4, the read word lines RWL <0>, RWL <1> are moved from the positions directly below the write word lines WWL <0>, WWL <1>, respectively, and the branch portions BRWL <00, respectively. >, BRWL <01>, BRWL <10>, and BRWL <11> are T-shaped.
[0040]
In this manner, the read word lines RWL <0> and RWL <1> are branched at the memory cell portion to form the T-time type, so that each memory cell transistor is arranged as shown in FIG. , The gate width direction of the transistor can be arranged in parallel with the power supply lines GND <0> and GND <1>.
[0041]
Therefore, the contact CX on the drain side connected via the first wiring layer M0 in FIG. 3 can be arranged near the transistor in the gate width direction as shown in FIG. In addition, the branch portions BGND <00> to BGND <11> shown in FIG. 2 are unnecessary, and the shapes of the power supply lines GND <0> and GND <1> are also straight lines. There is no need to draw out in the horizontal direction as in the sections BGND <00> to BGND <11>, and the pattern becomes simple, which is convenient in design and process. Further, since the branch part BGND <0> is eliminated, the length of the power supply line per memory cell is substantially shortened, and the resistance of the power supply lines GND <0> and GND <1> is further reduced. There is also. Further, by arranging the longitudinal direction of such a bit line and the gate width direction of the memory cell transistor so that the memory cell transistor formation region has a rectangular layout, the memory cell transistor can be formed in a direction orthogonal to the bit line. The area of the memory cell array can be reduced, and the chip area can be reduced.
[0042]
In the layout of FIG. 4 as well, power supply lines GND <0> and GND <1> are arranged in the same direction as bit lines BL <0> and BL <1>. By arranging such power supply lines GND <0> and GND <1>, at the time of reading, for example, current flows only from the bit line BL <0> to the power supply line GND <0>, and other bits The structure does not flow from the wire. For this reason, power bounce can be minimized, and a reliable read operation can be realized without a malfunction occurring in the sense amplifier ahead.
[0043]
FIG. 5 shows a third layout example in the first embodiment. This layout shows a layout example of the four memory cells MC <00>, MC <01>, MC <10>, and MC <11> shown in the first embodiment. In FIG. 5, portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and the following description will be made focusing only on the layout differences between the two.
[0044]
In this layout example, as shown in FIG. 5, in each of the memory cells MC <00> to MC <11>, the first wiring layer M0 is located almost directly above the drain contact CD2 connected to the drain region DL2 of the transistor. Is characterized in that three layers of a via V1, a second wiring layer M1, and a contact CX of the second wiring layer M1 and the third wiring layer MX are stacked.
[0045]
As described above, the three layers of the via V1, the second wiring layer M1, and the contact CX can be stacked almost directly above the drain contact CD2, as in the first layout example shown in FIG. This is because each memory cell transistor is rotated by 90 ° as compared with the layout example of FIG.
[0046]
That is, in the layout example shown in FIG. 2, the write word lines WWL <0> and WWL <1> are arranged so as to overlap with the drain contact CD2, and as shown in FIG. Since the use word lines WWL <0> and WWL <1> are simultaneously laminated in the process, the layout example shown in FIG. 5 cannot be taken. However, as shown in FIG. 5, each memory cell transistor is arranged such that the gate width direction is substantially the same as the bit lines BL <0> and BL <1> and the power supply lines GND <0> and GND <1>. 4, the drain contact CD2 can be formed so as not to overlap with the write word lines WWL <0> and WWL <1>, so that the via V1, the second wiring layer M1, and the contact The three layers of CX can be arranged almost directly above the non-overlapping drain contact CD2.
[0047]
By adopting such a rectangular layout, the area in the direction orthogonal to the horizontal bit lines can be further reduced, so that the memory cell array area can be reduced and the chip area can be further reduced. Further, as described above, since the second wiring layer M1 and the write word line WWL are simultaneously laminated in the same process, the pattern is simple, which is convenient in terms of design, process, and cost.
[0048]
FIG. 6 shows a fourth layout example in the first embodiment. FIG. 6 shows a layout example of four memory cells MC <00>, MC <01>, MC <10>, and MC <11> in FIG. 6, parts corresponding to those in FIG. 4 are denoted by the same reference numerals, and the following description will be made by focusing only on the layout differences between the two.
[0049]
As shown in FIG. 6, the other ends of BRWL <00>, BRWL <01>, BRWL <10>, and BRWL <11>, which are branch portions of the read word lines RWL <1> and RWL <3>, respectively. The connected read word lines RWL <0> and RWL <2> provided separately are arranged in substantially the same direction as the read word lines RWL <0> and RWL <1>. That is, it is characterized in that it is arranged in an H shape when viewed from the branch portions BRWL <00> to BRWL <11>.
[0050]
That is, in the memory cells MC <00> and MC <01>, reading is performed using two read word lines RWL <0> and RWL <1>. Similarly, the memory cells MC <10> and MC <11> are read using the read word lines RWL <2> and RWL <3>.
[0051]
For example, when reading the memory cell MC <00>, both read word lines RWL <0> and RWL <1> are activated, and the channels of the memory cell transistors of the memory cells MC <00> and MC <01> are changed. When turned on, a current flows through the bit line BL <0>, a current flows through the power supply line GND <0> through the above-described path, and reading is achieved by a sense amplifier (not shown) connected to the power supply line GND <0>.
[0052]
As described above, in each of the memory cells MC <00> to MC <11>, the read word lines RWL <0> to RWL <3> viewed from the branch portions BRWL <00> to BRWL <11> are H-shaped, By increasing the number of read word lines for each memory cell to two, a reliable read operation can be performed. Further, since the number of read word lines is doubled for each memory cell, the effective wiring resistance of each of the read word lines RWL <0> to RWL <3> is reduced, and the read word lines RWL <0> to RWL <3>.
[0053]
Further, the third layout example is different from the layout example in which one read word line RWL <0> and one read word line RWL <1> are read for each memory cell unit shown in FIGS. Reading is performed using two read word lines RWL <0>, RWL <1>, RWL <3>, and RWL <3> in units of memory cells. Therefore, the effective resistance of RWL <0> to RWL <3> is changed to the resistance value of the read word lines RWL <0> and RWL <1> in the layout examples shown in FIGS. The operation speed of the read word lines RWL <0> to RWL <3> in FIG. 6 is reduced by half compared with the operation speed of the read word lines RWL <0> and RWL <in FIG. 2, FIG. 4, and FIG. If the operation speed is set to be the same as 1>, it is possible to read at the same operation speed even if the scale of the memory cell array in the direction of the read word line RWL is doubled, so that the chip area and chip cost are reduced. Becomes possible.
[0054]
FIG. 7 shows a fifth layout example according to the first embodiment. FIG. 7 shows a layout example of four memory cells MC <00>, MC <01>, MC <10>, and MC <11> in FIG. In FIG. 7, portions corresponding to those in FIG. 6 are denoted by the same reference numerals, and the following description will be made focusing on only the layout differences.
[0055]
In the present layout example, as shown in FIG. 7, as compared to FIG. 6, for each of the memory cells MC <00> to MC <11>, the first wiring layer is located almost directly above the drain contact CD1 connected to the drain region DL1. It is characterized in that three layers of a via V1, a second wiring layer M1, and a contact CX of the second wiring layer M1 and the third wiring layer MX are stacked on M0.
[0056]
With such a layout, the layout area in the longitudinal direction of the bit lines BL <0> and BL <1> is further reduced while maintaining the effect of the reliable read operation and the like in the layout example of FIG. I can do it.
[0057]
(Second embodiment)
FIG. 8 shows a circuit configuration of the second embodiment of the present invention. This embodiment is also an example configured as a 1Tr-1MTJ type memory cell array. Each of memory cell blocks MB <00> and MB <10> is configured for four common bit lines BL <0> to BL <3>, and one cell array block MB <00> has four memories. The cells MC <00> to MC <03> are included, and the other cell array block MB <10> also includes four memory cells MC <10> to MC <13>.
[0058]
Each of the memory cells MC <00> to MC <03> and MC <10> to MC <13> has a ferromagnetic tunnel element, which is a magnetoresistive element, that is, an MTJ element MTJ <00> to MTJ <03>, MTJ <10>. To MJ <13> and memory cell transistors MTR <00> to MTR <03>, MTR <10> to MTR <13>. 8, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and the following description will be made by focusing only on differences between the two circuits.
[0059]
This embodiment is characterized in that one power supply line is arranged for two bit lines in memory cell block units. That is, as shown in FIG. 8, in the memory cell block MB <00>, the power supply line GND <0> is connected to the bit lines BL <0> and BL <1> in common with the memory cells MC <00> and MC <01>. The memory cells MC <02> and MC <03> are arranged in substantially the same direction via the node N <00>, and the power supply line GND <1> is shared by the bit lines BL <0> and BL <1>. Are arranged in almost the same direction via the node N <01>.
[0060]
Further, the node N <0> in FIG. 8 is connected to one end of the memory cell transistor MTR <00> of the memory cell MC <00> and one end of the memory cell transistor MTR <01> of the memory cell MC <01>. Similarly, the node N <01> is connected to one end of the memory cell transistors MTR <02> and MTR <03> of the memory cells MC <02> and MC <03>, respectively. The same applies to the memory cell block MB <10>.
[0061]
For example, consider a case where a current flows through the bit line BL <0> and the write word line WWL <0>, information is written to the memory cell MC <00>, and then information is read. In this read operation, when a current flows through the read word line RWL <0>, the memory cell transistors MTR <00> to MTR <03> of the memory cells MC <00> to MC <03> are turned on, and the bit line BL <0>>, A current flows from the magnetoresistive element MTJ <00> to the power supply line GND <0> via the node N <00> through the memory cell transistor MTR <00> connected in series. Although not shown in the figure, the reading is performed by the sense amplifier connected earlier. The same applies to other memory cells MC <10> to MC <13>.
[0062]
In the present embodiment, in units of memory cell blocks MB <00> and MB <01>, one bit line is provided for two bit lines BL <0> and BL <1> and one for BL <2> and BL <3>. Since the power supply lines GND <0> and GND <1> are arranged via the nodes <00> to N <11>, the bit lines BL <0> to BL <3>, the chip area can be reduced by reducing the cell array area in the vertical direction. Further, in the equivalent circuit of the conventional 1Tr-1MTJ type memory cell array shown in FIG. 17, for example, in the unit of the memory block MB <00>, the current from all the bit lines BL <0> to BL <3> is changed to the power supply line GND <0> only, and power bounce was a big problem. On the other hand, as described above, in the present embodiment, since one power supply line is arranged for two bit lines in memory cell block units, power supply bounce can be sufficiently reduced.
[0063]
FIG. 9 shows a first layout example according to the second embodiment. FIG. 9 shows a layout example of four memory cells MC <00>, MC <01>, MC <10>, and MC <11> in FIG. In FIG. 9, portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and the following description will be made focusing on only the layout differences between the two.
[0064]
As shown in FIG. 9, power supply line GND <0> is arranged in substantially the same direction as bit lines BL <0> and BL <1>, and memory cells MC <00> and MC <01 adjacent in the word line direction. >, MC <10> and MC <11> are characterized in that the source region CD1 and the power supply line GND <0> of each memory cell transistor are commonly connected. Therefore, in the equivalent circuit of FIG. 8, the sources of the transistors MTR <00> and MTR <01> are configured to be commonly connected at the node N <00>. However, as shown in the layout of FIG. Actually, the source region of one transistor MTR <00> is connected near one side end of power supply line GND <0>, and the source region of the other transistor MTR <01> is connected to power supply line GND <0>. The currents from these two transistors MTR <00> and MTR <01> do not concentrate on one point of the power supply line GND <0> because they are connected near the other side end. The same applies to the other nodes N <01>, N <10>, and N <11>.
[0065]
By taking such a layout example, as compared with the layouts shown in FIGS. 2 and 4 to 7 in the first embodiment, the layout is orthogonal to the longitudinal direction of the bit lines BL <0> and BL <1>. The layout area in the direction can be reduced, and the chip area can be reduced.
[0066]
In this layout example, the bit line and each memory cell formed in connection with the bit line are symmetrical with respect to the longitudinal center line of the power supply line GND <0>. Since the source region DL2 of each transistor can be connected in common to the line GND <0>, the transistors can be stacked in the same process, which is a layout example that is convenient in terms of design, process, cost, and the like.
[0067]
FIG. 10 shows a second layout example according to the second embodiment. FIG. 10 shows a layout example of four memory cells MC <00>, MC <01>, MC <10>, and MC <11> in FIG. In FIG. 10, portions corresponding to those in FIG. 5 are denoted by the same reference numerals, and the following description will be made focusing on only the differences in layout between the two.
[0068]
As shown in FIG. 10, power supply line GND <0> is arranged in substantially the same direction as bit lines BL <0> and BL <1>, and memory cells MC <00> and MC <01 adjacent in the word line direction. >, MC <10> and MC <11> that the source region CD1 of each memory cell transistor is commonly connected to the power supply line GND <0>, and that the drain contact CD2 connected to the drain region DL2 is substantially true. At an upper position, three layers of a via V1 stacked on the first wiring layer M0, a second wiring layer M1, and a contact CX of the second wiring layer M1 and the third wiring layer MX are stacked. It is.
[0069]
As described above, in each memory cell, the three layers of the via V1, the second wiring layer M1, and the contact CX are stacked almost immediately above the drain contact CD2, so that the bit line is compared with the layout of FIG. The layout area in the longitudinal direction of BL <0> and BL <1> can be further reduced. Also, in this layout example, similarly to FIG. 9, the source region DL <b> 1 is commonly connected to the power supply line GND <0> because it has a structure that is line-symmetric with respect to the power supply line GND <0>. This is a layout example that can be stacked in the same process, and is convenient in design, process, cost, and the like.
[0070]
FIG. 11 shows a third layout example according to the second embodiment. FIG. 11 shows a layout example of four memory cells MC <00>, MC <01>, MC <10>, and MC <11> in FIG. In FIG. 11, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and the following description will be made focusing on only the differences in layout between the two.
[0071]
As shown in FIG. 11, power supply line GND <0> is arranged in substantially the same direction as bit lines BL <0> and BL <1>, and memory cells MC <00> and MC <01 adjacent in the word line direction. >, MC <10> and MC <11> that the source region CD1 of each memory cell transistor is commonly connected to the power supply line GND <0>, and that the read word lines RWL <1> and RWL <3> Read word lines RWL <0> and RWL <2> connected to the other ends of BRWL <00>, BRWL <01>, BRWL <10>, and BRWL <11>, respectively, which are branch portions of The word lines RWL <0> and RWL <1> are arranged in substantially the same direction as the word lines RWL <0> and RWL <1>, and are arranged in an H shape when viewed from the branch portions BRWL <00> to BRWL <11>.
[0072]
As described above, in each of the memory cells MC <00> to MC <11>, the read word lines RWL <0> to RWL <3> viewed from the branch portions BRWL <00> to BRWL <11> are H-shaped, By increasing the number of read word lines for each memory cell to two, a reliable read operation can be performed. Further, by doubling the number of read word lines for each memory cell, the effective wiring resistance of each of the read word lines RWL <0> to RWL <3> is reduced, and RWL <0> to RWL < The operation speed of 3> can be improved.
[0073]
In addition, the layout example also has a structure that is line-symmetric with respect to the power supply line GND <0>, so that the source region DL1 can be commonly connected to the power supply line GND <0>. This is a layout example that can be laminated by a process and is convenient in design, process, cost, and the like.
[0074]
FIG. 12 shows a fourth layout example according to the second embodiment. FIG. 12 shows a layout example of four memory cells MC <00>, MC <01>, MC <10>, and MC <11> in FIG. 12, parts corresponding to those in FIG. 7 are denoted by the same reference numerals, and the following description will be made focusing on only the layout differences.
[0075]
As shown in FIG. 12, the other ends of BRWL <00>, BRWL <01>, BRWL <10>, and BRWL <11>, which are branch portions of the read word lines RWL <1> and RWL <3>, respectively. The connected other read word lines RWL <0>, RWL <2> are in substantially the same direction as the read word lines RWL <0>, RWL <1>, and branch portions BRWL <00> to BRWL <11. This is characterized in that they are arranged in an H-shape as viewed from above, and that three layers of a via V1, a second wiring layer M1, and a contact CX are stacked almost directly above the drain contact CD1.
[0076]
As described above, in each of the memory cells MC <00> to MC <11>, the read word lines RWL <0> to RWL <3> viewed from the branch portions BRWL <00> to BRWL <11> are H-shaped, By increasing the number of read word lines for each memory cell to two, a reliable read operation can be performed. Further, by doubling the number of read word lines for each memory cell, the effective wiring resistance of each of the read word lines RWL <0> to RWL <3> is reduced, and RWL <0> to RWL < The operation speed of 3> can be improved.
[0077]
In each memory cell, the three layers of the via V1, the second wiring layer M1, and the contact CX are stacked almost directly above one drain contact CD1, so that the bit size is smaller than that of the layout of FIG. The layout area in the longitudinal direction of the lines BL <0> and BL <1> can be reduced.
[0078]
(Third embodiment)
FIG. 13 shows a circuit configuration of the third embodiment of the present invention. This embodiment is an example configured as a 1Tr-1MTJ type memory cell array. In FIG. 13, one cell array block MB <00> includes four memory cells MC <00> to MC <03>, and the other cell array block MB <10> includes four memory cells MC <10>. > To MC <13>. Each of the memory cells MC <00> to MC <03> and MC <10> to MC <13> has one ferromagnetic tunnel element, which is a magnetoresistive element, that is, an MTJ element MTJ <00> to MTJ <03>, MTJ. <10> to MTJ <13> and one memory cell transistor MTR <00> to MTR <03>, and MTR <10> to MTR <13>.
[0079]
In FIG. 13, portions corresponding to those in FIG. 8 are denoted by the same reference numerals, and the following description will focus on only differences in the circuit configuration between the two.
[0080]
In this embodiment, new power supply lines GND <10> and GND <11> are added to the memory cell blocks MB <00> and MB <10> in substantially the same direction as the write and read word lines, respectively. It is characterized in that three power supply lines are arranged in each memory cell block for the bit lines BL <0> to BL <3>.
[0081]
That is, in the memory cell block MB <00> as shown in FIG. 13, one end of each of the memory cell transistors MTR <00> and MTR <01> of the memory cells MC <00> and MC <01> is a node N <00>, respectively. Power supply line GND <10> is connected via node N <02>, and power supply line GND <00> is connected to power supply line GND <10> via node N <01>. One end of each of the memory cell transistors MTR <02> and MTR <03> of the memory cells MC <02> and MC <03> is connected to a power supply line GND <10> via a node N <03> and a node N <05>, respectively. And the power supply line GND <01> is connected to the power supply line GND <10> via the node N <04>.
[0082]
Further, as shown in FIG. 13, the node N <00> is connected to one end of the memory cell transistor MTR <00> of the memory cell MC <00>, one end of the memory cell transistor MTR <01> of the memory cell MC <01>, The line GND <00> and the power line GND <10>. Node N <03> is one end of memory cell transistor MTR <02> of memory cell MC <02>, one end of memory cell transistor MTR <03> of memory cell MC <03>, power supply line GND <01>, and power supply line. GND <10>. The same applies to the memory cell block MB <10>.
[0083]
For example, when a current is applied to the bit line BL <0> and the write word line WWL <0> to write information into the memory cell MC <00> and then read the information, the read word line RWL <0> is used. , The memory cell transistors MTR <00> to MTR <03> of the memory cells MC <00> to MC <03> are turned on, a current flows to the bit line BL <0>, and the magnetoresistive element MTJ <00> flows through the memory cell transistors MTR <00> connected in series to the power supply lines GND <0> and GND <10> via the node N <00>, and is not shown in the figure. Is read by the sense amplifier connected earlier. The same applies to other memory cells MC <01> to MC <13>.
[0084]
In the present embodiment, in the unit of memory cell block MB <00>, three power supply lines GND <00 are provided for two bit lines BL <0> and BL <1>, and BL <2> and BL <3>. >, GND <01> and GND <11> are arranged via nodes N <00> and N <04>, so that bit lines BL <0> to BL <3> are connected to power supply line GND <00>. >, GND <01> can be further distributed to power supply line GND <10>. The same applies to the third power supply line GND <11> provided in the memory cell block MB <10>.
[0085]
As described above, in the present embodiment, three power lines are arranged for four bit lines in units of memory cell blocks, so that power bounce can be sufficiently reduced.
[0086]
(Fourth embodiment)
FIG. 14 shows a circuit configuration of the fourth embodiment of the present invention. This embodiment is configured as a 1Tr-1MTJ type memory cell array. FIG. 15 shows a layout example of the memory cell blocks MB <10> and MB <20>. One cell array block MB <10> includes four memory cells MC <10> to MC <13>, and the other cell array block MB <20> includes four memory cells MC <20> to MC <13. 23> is included. Each of the memory cells MC <10> to MC <13> and MC <20> to MC <23> is a single ferromagnetic tunnel element that is a magnetoresistive element, that is, an MTJ element MTJ <10> to MTJ <13>, MTJ. <20> to MTJ <23> and one memory cell transistor MTR <10> to MTR <13>, MTR <20> to MTR <23>. In FIG. 14, portions corresponding to those in FIG. 8 are denoted by the same reference numerals, and the following description will be made focusing only on differences in circuit configuration between the two.
[0087]
In the present embodiment, two power supply lines GND <10> and GND <11> provided corresponding to the cell array blocks MB <00> and MB <10> in the embodiment of FIG. Are used together. For this reason, it is important on the layout to arrange the source of the memory cell transistor of one cell array block MB <00> and the source of the memory cell transistor of the other cell array block MB <10> close to each other.
[0088]
That is, in FIG. 14, the word lines WWL <1>, WWL <2>, RWL <1>, and RWL <2> are further provided in the same direction for the two cell array blocks MB <10> and MB <20>. One end of each of memory cell transistors MTR <10> to MTR <23> adjacent along bit lines BL <0> to BL <3> and power supply line GND common to power supply lines GND <00> and GND <01>. The feature is that <11> is provided.
[0089]
That is, as shown in FIG. 14, in the memory cell block MB <10>, one end of the memory cell transistor MTR <10> of the memory cell MC <10> passes through the node N <10>, and the transistor in the memory cell MC <11>. One end of MTR <11> is connected to power supply line GND <11> via node N <12>, and power supply line GND <00> is connected to power supply line GND <11> via node N <11>. I have.
[0090]
In the memory cell MC <12>, one end of the memory cell transistor MTR <12> is connected to the power supply line GND <11> via the node N <13>, and in the memory cell MC <13>, via the node N <15>. And the power supply line GND <01> is connected to the power supply line GND <11> via the node N <14>. In the memory cell block MB <20>, the respective memory cell transistors are connected to the power supply line GND <11> via the same node, and are commonly connected to the power supply lines GND <00> and GND <01>. You.
[0091]
For example, when a current flows through the bit line BL <0> and the write word line WWL <1>, information is written into the memory cell MC <10>, and thereafter information is read, the read word line RWL <1 >, The memory cell transistors MTR <10> to MTR <13> of the memory cells MC <10> to MC <13> are turned on, for example, a current flows to the bit line BL <0> and the magnetoresistive element A current flows from the MTJ <10> to the power supply line GND <00> and the power supply line GND <11> via the node N <10> through the memory cell transistor MTR <10> connected in series. However, the information is read out by the sense amplifier connected earlier. The same applies to other memory cells MC <11> to MC <23>.
[0092]
In the present embodiment, in each memory cell block MB <10>, MB <20>, two bit lines BL <0> and BL <1>, and BL <2> and BL <3> are substantially used. 13, three power supply lines GND <00>, GND <01>, and GND <11> are arranged via nodes N <10> to N <15>, similar to the embodiment of FIG. Power bounce can be reduced, and the number of power lines in the longitudinal direction of the bit lines BL <0> to BL <3> is reduced, so that the cell array area can be further reduced.
[0093]
FIG. 15 shows a layout example according to the fourth embodiment of FIG. FIG. 15 shows four memory cells MC <10>, MC <11>, MC <20>, MC <21> and these memory cells MC <10> to MC <21> in FIG. This shows a layout example of two memory cells MC <00> and MC <01> that should follow in the same direction as bit lines BL <0> and BL <1>. In FIG. 15, portions corresponding to those in FIG. 2 are denoted by the same reference numerals, and the following description will be made focusing on only the layout differences.
[0094]
In the layout example shown in FIG. 15, memory cells MC <00> and MC <10 arranged as elements in adjacent cell array blocks MB <00> and MB <10> along bit line BL <0>. The contacts connected to the drains of the transistors of the respective memory cells are arranged by utilizing the space formed between <>. That is, as described with reference to FIG. 3, the contact CX for connection between the drain DL2 of the memory cell transistor MTR <00> of the memory cell MC <00> and the MTJ element MTJ <00> is formed in this space. Is done. Similarly, the same space is used to form contact CX for connection between memory cell transistor MTR <10> of memory cell MC <10> and MTJ element MTJ <10>, as shown in FIG. Same as in the example.
[0095]
However, in this layout example, the memory cells MC <10> and MC <20 adjacent to each other along the write word lines WWL <0> to WWL <2> and the read word lines RWL <0> to RWL <3>. >, A common power supply line GND <11> that is arranged in substantially the same direction as the word lines of the memory cells MC <11> and MC <21>.
[0096]
As described above, since power supply line GND <11> is shared by memory cells MC <10> to MC <21> adjacent to each other along the word line, layout in the longitudinal direction of bit lines BL <0> and BL <1> is performed. Area can be reduced. Further, since the source regions DL1 of the memory cells MC <10> to MC <21> can be commonly connected to the power supply line GND <11>, they can be stacked in the same process, and the design, process, cost, and the like can be reduced. This has the effect of being convenient.
[0097]
In each of the above embodiments, an example in which the MTJ element is used as the magnetoresistive element has been described. However, a similar effect can be obtained by using, for example, a GMR (Giant Magneto resistive) element as the magnetoresistive element.
[0098]
【The invention's effect】
As described in detail above, according to the present invention, it is possible to provide a semiconductor memory device that minimizes power bounce of a power line and improves a read margin.
[Brief description of the drawings]
FIG. 1 is a first equivalent circuit diagram of a 1Tr-1MTJ type memory cell array according to a first embodiment of the present invention.
FIG. 2 is a first layout example of the MRAM according to the first embodiment;
FIG. 3 is a cross-sectional view showing a cross-sectional structure of the memory cell of the MRAM taken along a line III-III ′ in FIG. 2 and viewed in a direction indicated by an arrow;
FIG. 4 is a second layout example according to the first embodiment;
FIG. 5 is a third layout example according to the first embodiment;
FIG. 6 is a fourth layout example according to the first embodiment;
FIG. 7 is a fifth layout example according to the first embodiment;
FIG. 8 is a second equivalent circuit diagram of the 1Tr-1MTJ type memory cell array according to the second embodiment of the present invention.
FIG. 9 is a first layout example according to the second embodiment;
FIG. 10 is a second layout example according to the second embodiment;
FIG. 11 is a third layout example according to the second embodiment;
FIG. 12 is a fourth layout example according to the second embodiment;
FIG. 13 is a third equivalent circuit diagram of the 1Tr-1MTJ type memory cell array according to the third embodiment of the present invention.
FIG. 14 is a fourth equivalent circuit diagram of the 1Tr-1MTJ type memory cell array according to the fourth embodiment of the present invention.
FIG. 15 is a layout example according to the fourth embodiment;
FIG. 16 is an equivalent circuit diagram of a conventional 1Tr-1MTJ memory cell.
FIG. 17 is a first equivalent circuit diagram of a conventional 1Tr-1MTJ type memory cell array.
FIG. 18 is a layout example relating to the equivalent circuit of FIG. 17;
FIG. 19 is a sectional structural view of a conventional 1Tr-1MTJ memory cell.
FIG. 20 is a second equivalent circuit diagram of a conventional 1Tr-1MTJ type memory cell array.
FIG. 21 is a layout example relating to the equivalent circuit of FIG. 20;
[Explanation of symbols]
MB <00>, MB <10>, MB <20> ... cell array block,
MC <00> to MC <23> ... memory cells,
MTJ <00> to MTJ <23>: ferromagnetic tunnel element,
MTR <00> to MTR <23>: memory cell transistors,
BL <0> to BL <3> ... bit lines,
WWL <0> to WWL <2> ... write word line,
RWL <0> to RWL <2> ... read word lines,
GND <0>, GND <1> ... power supply line.

Claims (19)

At least one cell array block including a memory cell including a plurality of magneto-resistive elements, wherein the cell array block includes:
A word line,
A plurality of memory cells simultaneously selected at least at the time of reading by the word line;
A plurality of power lines connected to one end of each of the selected plurality of memory cells;
A plurality of bit lines connected to respective other ends of the plurality of memory cells;
A semiconductor memory device comprising: 2. The semiconductor memory according to claim 1, wherein one end of each of the plurality of memory cells is connected to each of the plurality of power supply lines, and the other end is connected to each of the plurality of bit lines. apparatus. 2. The semiconductor memory device according to claim 1, wherein each of the plurality of power supply lines is commonly connected to two adjacent memory cells of the plurality of memory cells. 4. The semiconductor memory device according to claim 3, further comprising a common power supply line to which said plurality of power supply lines are connected in common. 5. The semiconductor memory device according to claim 4, wherein said common power supply lines are provided corresponding to said cell array blocks, respectively. 5. The semiconductor memory device according to claim 4, wherein said common power supply line is provided at a ratio of one to two cell array blocks adjacent to each other. A memory cell including a plurality of magneto-resistive elements formed on a semiconductor substrate to form at least one cell array block;
The cell array block comprises:
A word line,
A plurality of memory cells simultaneously selected at least at the time of reading by the word line;
A plurality of power lines each connected to one end of the selected plurality of memory cells;
A plurality of bit lines respectively connected to the other ends of the plurality of memory cells and arranged in parallel with the plurality of power supply lines,
A semiconductor memory device comprising: A memory cell including a plurality of magneto-resistive elements formed on a semiconductor substrate to form at least one cell array block;
A word line,
The plurality of memory cells simultaneously selected at least at the time of reading by the word line;
A plurality of power lines each connected to one end of the selected plurality of memory cells;
A plurality of bit lines respectively connected to the other end of the memory cell and arranged in parallel with the power supply line,
2. The semiconductor memory device according to claim 1, wherein said word lines are arranged substantially at right angles to said plurality of bit lines and said plurality of power supply lines. The memory cells are each
It comprises one magnetoresistive element and one select element connected in series to this magnetoresistive element, wherein the word lines include a write word line and a read word line,
The cell array block comprises:
A plurality of magneto-resistive elements,
A plurality of selection elements each connected in series to the plurality of magnetoresistance elements,
The write word line;
The read word line;
Multiple bit lines,
And a plurality of power lines,
The plurality of magneto-resistive elements are simultaneously selected by the read word line, one end of each of the plurality of magneto-resistive elements is connected to the bit line, and the other end is connected to one end of the select element. 9. The semiconductor memory device according to claim 7, wherein the plurality of power supply lines are simultaneously selected by a word line, and the plurality of power supply lines are respectively connected to the other ends of the plurality of selection elements. 10. The semiconductor memory device according to claim 9, wherein each of the plurality of power supply lines is commonly connected to two adjacent selection elements of the plurality of selection elements. 11. The semiconductor memory device according to claim 10, further comprising a common power supply line commonly connected to said plurality of power supply lines. 12. The semiconductor memory device according to claim 11, wherein said common power supply line is provided corresponding to said cell array block. 12. The semiconductor memory device according to claim 11, wherein one common power supply line is provided for two cell array blocks adjacent to each other. First and second memory cells including NMOS transistors arranged adjacent to each other along the bit line;
A first NMOS transistor included in the first memory cell has a first gate electrode used as the read word line, a first magnetoresistive element connected in series with the first NMOS transistor, and The write word line is disposed above the first gate electrode, and a first contact for connecting a drain region of the first NMOS transistor to the first magnetoresistive element is connected to the bit line. And a drain region of a second NMOS transistor included in the second memory cell in the space formed between the second memory cell and the second memory cell formed along the second memory cell. 10. The semiconductor memory device according to claim 9, further comprising a second contact for connecting to the magnetoresistive element. The memory cell includes an NMOS transistor, a source region of the NMOS transistor is arranged corresponding to one end of the bit line in a longitudinal direction, and the drain region and the contact are located at other positions in the longitudinal direction of the bit line. The power supply line is disposed corresponding to an end portion, and the power supply line is disposed at least partially overlapped with the bit line at one end portion in the bit line longitudinal direction, and branches in one direction along the source region / drain region. The semiconductor memory device according to claim 9, further comprising a first read word line drawn out and formed in a T-shape. A second read word line connected to the first read word line, drawn out in the other direction along the source region / drain region, and arranged in an H shape;
16. The semiconductor memory device according to claim 15, wherein: Further, a contact for connecting a drain region of an NMOS transistor included in the memory cell to the magnetoresistive element is disposed almost directly above the drain region.
17. The semiconductor memory device according to claim 15, wherein: Further, a common power supply line is provided, which shares a power supply line of the third memory cell and the fourth memory cell arranged adjacently along the read word line of the plurality of memory cells,
The source regions of the NMOS transistors included in the third memory cell and the fourth memory cell are arranged to face each other;
The common power supply line is commonly connected to the source region;
18. The semiconductor memory device according to claim 15, wherein: A first common power supply line commonly connected to power supply lines of the first memory cell and the second memory cell arranged adjacent to each other along the bit line;
A second common power supply line that shares the power supply line of the third memory cell and the fourth memory cell that are arranged adjacently along the read word line;
The first power supply line and the second power supply line are connected to each other;
Source regions of NMOS transistors included in the first memory cell and the second memory cell are arranged to face each other;
The second common power supply line is commonly connected to the respective source regions;
15. The semiconductor memory device according to claim 14, wherein:

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