JP2004119897A5

JP2004119897A5 -

Info

Publication number: JP2004119897A5
Application number: JP2002284447A
Authority: JP
Filing date: 2002-09-27
Publication date: 2005-09-29

Claims

Including a memory cell including a plurality of magnetoresistive elements formed on a semiconductor substrate so as to constitute at least one cell array block;
A word line,
A plurality of the memory cells that are simultaneously selected at the time of reading by the word line; and
A plurality of power lines respectively connected to one end of the selected plurality of memory cells;
A plurality of bit lines each connected to the other end of the memory cell and arranged in parallel with the power line;
2. The semiconductor memory device according to claim 1, wherein the word line is disposed substantially perpendicular to the plurality of bit lines and the plurality of power supply lines.

Each of the memory cells is
One magnetoresistive element and one select element connected in series to the magnetoresistive element, and the word line includes a write word line and a read word line;
The cell array block is:
A plurality of magnetoresistive elements;
A plurality of selection elements each connected in series to the plurality of magnetoresistive elements;
The write word line;
The read word line;
Multiple bit lines,
A plurality of power lines,
The plurality of magnetoresistive elements are simultaneously selected by the read word line, each one end is connected to the bit line, the other end is connected to one end of the selection element, and each of the plurality of selection elements is the read line. 2. The semiconductor memory device according to claim 1, wherein the plurality of power supply lines are simultaneously selected by a word line, and the plurality of power supply lines are respectively connected to the other ends of the plurality of selection elements.

3. The semiconductor memory device according to claim 2, wherein each of the plurality of power supply lines is connected in common to two selection elements adjacent to each other among the plurality of selection elements.

4. The semiconductor memory device according to claim 3, further comprising a common power supply line commonly connected to the plurality of power supply lines, wherein the common power supply line is provided corresponding to the cell array block. .

First and second memory cells including NMOS transistors arranged adjacent to each other along the bit line;
The first NMOS transistor included in the first memory cell has a first gate electrode used as the read word line, and a first magnetoresistive element connected in series with the first NMOS transistor; The write word line is disposed above the first gate electrode, and a first contact for connecting a drain region of the first NMOS transistor to the first magnetoresistive element is connected to the bit line. The drain region of the second NMOS transistor included in the second memory cell is disposed in the space formed between the second memory cell and the second memory cell formed along the second memory cell. 3. The semiconductor memory device according to claim 2, further comprising a second contact for connecting to the magnetoresistive element.