JP2014143258A - Surface-mounting type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a surface-mounting type semiconductor device capable of alleviating partial current concentration at reverse blocking, and of being miniaturized.SOLUTION: On one surface side of a single first conductivity type semiconductor substrate, a second conductivity type first semiconductor region having an opposite conductivity type to the first conductivity type is formed. Similarly, on one surface side of the single first conductivity type semiconductor substrate, a second conductivity type second semiconductor region is formed separately from the first semiconductor region. On the other surface side of the single first conductivity type semiconductor substrate, a low-resistive layer is formed to alleviate partial current concentration at reverse blocking.

Description

  The present invention relates to a surface-mount type semiconductor device in which two semiconductor elements are surface-mounted on a single semiconductor.

  A surface-mount type semiconductor device forms two diodes by PN junction of semiconductor elements, connects the two diodes in the reverse direction using a connection conductor, and uses a reverse drop to absorb a bidirectional varistor or surge absorber. It is used as an element. In this case, in the structure in which two diodes are connected using the connection conductor, not only the number of parts is large and the structure of the assembly jig is complicated, but also the assembly process including the solder process is increased. Therefore, there is a surface-mount type semiconductor device that is easy to manufacture and thin by forming two PN junctions on a single N-type semiconductor to form the same semiconductor element (see Patent Document 1).

  FIG. 5 is a structural diagram of a surface-mounting type semiconductor device in which two semiconductor elements are surface-mounted on a single semiconductor. Two P-layer semiconductor regions 12a and 12b are formed on a single N-layer semiconductor substrate 11 to form a semiconductor element having two PN junctions. Anode electrodes 13a and 13b are attached to the P layer semiconductor regions 12a and 12b, and the N layer semiconductor substrate 11 directly connects the PN junction with the P layer semiconductor region 12a and the PN junction with the P layer semiconductor region 12b. Therefore, the cathode electrode is omitted and is directly connected in the reverse direction. Thereby, the process of forming the cathode electrode and the process of connecting the cathode electrode can be omitted, and the assembly process is simplified.

  When a voltage higher than the breakdown voltage of the PN junction by the N layer semiconductor substrate 11 and the P layer semiconductor region 12b on the anode electrode 13b side is applied between the anode electrode 13a and the anode electrode 13b (at the time of surge absorption), As indicated by an arrow, a current I flows from the anode electrode 13a to the anode electrode 13b through the P layer semiconductor region 12a, the N layer semiconductor substrate 11, and the P layer semiconductor region 12b. As a result, the surface mount semiconductor device functions as a surge absorbing element.

Japanese Patent No. 3238825

  However, when the distance between the anode electrode 13a and the anode electrode 13b is shortened as shown in FIG. 6 in order to reduce the size of the surface mount semiconductor device shown in FIG. There is a problem that the current I concentrates on the end portion 12b1 of the P-layer semiconductor region 12b, causing destruction.

  That is, at the time of blocking in the reverse direction, current tends to concentrate at a short distance between the P-layer semiconductor region 12a and the P-layer semiconductor region 12b. There is a problem that the property becomes low.

  An object of the present invention is to provide a surface-mounting type semiconductor device that can alleviate partial current concentration when blocking in the reverse direction and that can be reduced in size.

  The surface mount type semiconductor device according to the invention of claim 1 is a second conductivity type formed on one surface side of a single first conductivity type semiconductor substrate and having a conductivity type opposite to the first conductivity type. A first semiconductor region; a second semiconductor region of a second conductivity type formed on one surface side of the single semiconductor substrate of the first conductivity type and spaced apart from the first semiconductor region; And a low resistance layer formed on the other surface side of the first conductive type semiconductor substrate.

  According to a second aspect of the present invention, there is provided a surface mount type semiconductor device according to the first aspect of the invention, wherein the low resistance layer has a higher impurity concentration and lower resistance than the semiconductor of the single first conductivity type semiconductor substrate. It is one conductivity type layer or conductor.

  According to a third aspect of the present invention, there is provided the surface mount type semiconductor device according to the first or second aspect of the invention, wherein the thickness of the low resistance layer is the second conductivity type when the low resistance layer is increased. An allowable current density range is defined based on the current density when the current density at the current concentration occurrence point of the first semiconductor region or the second conductivity type second semiconductor region converges, and the allowable current density range is satisfied. It is characterized by a thickness.

According to the first aspect of the present invention, since the low resistance layer is formed on the other surface side of the single semiconductor substrate of the first conductivity type, current can be dispersed in the low resistance layer when blocking in the reverse direction. Accordingly, the current density can be kept low and the local temperature rise can be restrained, so that the reliability of the apparatus can be improved. According to the invention of claim 2, in addition to the effect of the invention of claim 1, a low resistance Since the layer is a first conductivity type layer or conductor having a high impurity concentration and a low resistance, the current can be more dispersed. When metal is used as the conductor, heat dissipation is also improved.

  According to the invention of claim 3, in addition to the effect of the invention of claim 1 or 2, the thickness of the low resistance layer satisfies an allowable current density range determined based on the current density when the current density converges. Because of the thickness, the thickness of the low resistance layer does not become too thick, and current concentration can be suppressed.

The block diagram of Example 1 of the surface-mount type semiconductor device which concerns on embodiment of this invention. The block diagram of Example 2 of the surface-mount type semiconductor device which concerns on embodiment of this invention. The block diagram of Example 3 of the surface-mount type semiconductor device which concerns on embodiment of this invention. The graph which shows the relationship between the low resistance layer thickness in the surface mount-type semiconductor device which concerns on embodiment of this invention, and the current density in an electric current concentration generation location. FIG. 6 is a structural diagram illustrating an example of a conventional surface-mount semiconductor device. FIG. 6 is a structural diagram showing an example when a conventional surface mount semiconductor device is miniaturized.

  Embodiments of the present invention will be described below. In the following description, it is assumed that the first conductivity type semiconductor is N-type, the second conductivity type semiconductor is P-type, and the electrode is an anode electrode. Note that this may be reversed, that is, the first conductivity type semiconductor may be a P type, the second conductivity type semiconductor may be an N type, and the electrode may be a cathode electrode.

  FIG. 1 is a configuration diagram of Example 1 of a surface-mount semiconductor device according to an embodiment of the present invention. In the first embodiment, the second conductive type semiconductor regions 15a and 15b and the electrodes 16a and 16b in the single first conductive type semiconductor substrate 14 are formed compared to the conventional example shown in FIG. The low resistance layer 17 is provided on the opposite surface.

  In FIG. 1, a second conductive type first semiconductor region 15 a and a second conductive type second semiconductor region 15 b are formed on one surface of a single first conductive type semiconductor substrate 14. An electrode 16a is attached to the second conductivity type first semiconductor region 15a, and an electrode 16b is attached to the second conductivity type second semiconductor region 15b.

  For example, aluminum Al is used for the electrodes 16a and 16b, but nickel Ni, gold Au, silver Ag, or the like may be used as long as the metal can form the electrodes.

  On the other surface of the first conductivity type semiconductor substrate 14, a PN junction with the second conductivity type semiconductor region 15a and a PN junction with the second conductivity type semiconductor region 15b are provided. 14, and a low resistance layer 17. Thus, two semiconductor elements (diodes) having two PN junctions are formed. FIG. 1 shows a case where the low resistance layer 17 is formed of a conductor. A metal is used as the conductor. For example, aluminum Al is used, but nickel Ni, gold Au, silver Ag, or the like may be used.

  Here, when a voltage higher than the breakdown voltage of the PN junction is applied between the electrodes 16a and 16b, the current I is concentrated on the end 15a1 of the first semiconductor region 15a and the end 15b1 of the second semiconductor region 15b. However, in Example 1 of the embodiment of the present invention, since the low resistance layer 17 is formed on the other surface of the first conductivity type semiconductor substrate 14, current concentration can be suppressed.

  For example, when a voltage higher than the breakdown voltage of the PN junction is applied between the electrodes 16a and 16b in the direction from the first conductive type semiconductor substrate 14 to the second conductive type semiconductor region 15b, the first conductive type semiconductor A current I1 can be supplied to the substrate 14 and a current I2 can be supplied to the low resistance layer 17 in a divided manner. Thereby, when a conductor is used as the low resistance layer 17, the current I1 flowing through the first conductivity type semiconductor substrate 14 is reduced. Therefore, the current density at the end 15b1 of the second conductivity type second semiconductor region 15b can be kept low, and the surface mount semiconductor device can be downsized. Further, when a conductor is used as the low resistance layer 17, heat dissipation is also improved.

Next, FIG. 2 is a configuration diagram of Example 2 of the surface mount semiconductor device according to the embodiment of the present invention. The second embodiment is different from the first embodiment shown in FIG. 1 in that a low resistance first conductive type layer N ⁺ having a high impurity concentration is used instead of the conductor as the low resistance layer 17 and the first conductive type semiconductor substrate is used. 14 is obtained by the first conductivity type layer ^N-.

Also in this case, the current I3 can be shunted through the first conductivity type semiconductor substrate 14 and the current I4 can be shunted through the low resistance layer 17, and the current I3 flowing through the first conductivity type semiconductor substrate 14 is divided into the low resistance layer 17 Less than the current I4 flowing through the thick low resistance first conductivity type layer N ⁺ . Therefore, the current density at the end 15b1 of the second conductivity type second semiconductor region 15b can be kept low, and the surface mount semiconductor device can be downsized.

Next, FIG. 3 is a configuration diagram of Example 3 of the surface mount semiconductor device according to the embodiment of the present invention. The third embodiment is different from the first embodiment shown in FIG. 1 in that a low resistance first conductivity type layer N ⁺ 19 is provided in addition to the conductor 18 as the low resistance layer 17. is obtained by the first conductivity type layer ^N-.

Also in this case, the current I5 can be shunted through the first conductivity type semiconductor substrate 14 and the current I6 can be shunted through the low resistance layer 17. The current I5 flowing through the first conductivity type semiconductor substrate 14 is smaller than the current I6 flowing through the conductor 18 of the low resistance layer 17 and the low resistance first conductivity type layer N ⁺ 19. Therefore, the current density at the end 15b1 of the second conductivity type second semiconductor region 15b can be kept low, and the surface mount semiconductor device can be downsized.

  Next, the thickness of the low resistance layer 17 will be described. FIG. 4 is a graph showing an example of the relationship between the low resistance layer thickness D and the current density ratio J / J0 at the location where current concentration occurs in the surface mount semiconductor device according to the embodiment of the present invention.

  The relationship between the low resistance layer thickness D and the current density J at the current concentration occurrence point (for example, the end 15a1 of the first semiconductor region 15a or the end 15b1 of the second semiconductor region 15b) is as follows. Of the first conductivity type semiconductor substrate 14, the thickness and withstand capability of the first conductivity type semiconductor substrate 14, and the size of the second conductivity type semiconductor region.

  Therefore, when the thickness D of the low resistance layer is increased, the current density J at the current concentration portion converges to the current density J0 when D is ∞. Therefore, the ideal value of the current density ratio J / J0 at which the current density J is the smallest is “1.00” when D is ∞. The range of the low resistance layer thickness D is determined with reference to the current density J0 when the current density J converges. First, the current density Jb (current density ratio Jb / J0) is determined as the allowable upper limit value of the current density J. This current density Jb is determined to be equal to or less than a value obtained by subtracting a margin value from a current density at which no breakdown occurs at a current concentration occurrence location. The low resistance layer thickness at this time is determined to be Db or more from FIG. On the other hand, when the practical limit value of the low resistance layer thickness D is “1.00”, the value of D not exceeding this is determined to be Da or less. Thereby, the low resistance layer thickness D is determined not to be too thick and to be equal to or less than the current density at which no breakdown occurs at the location where current concentration occurs.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 11 ... N layer semiconductor substrate, 12 ... P layer semiconductor region, 13 ... Anode electrode, 14 ... First conductivity type semiconductor substrate, 15 ... Second conductivity type semiconductor region, 16 ... Electrode, 17 ... Low resistance layer, 18 ... conductor, 19 ... low resistance first conductivity type layer

Claims (3)

A first semiconductor region of a second conductivity type formed on one surface side of a single semiconductor substrate of a first conductivity type and having a conductivity type opposite to the first conductivity type;
A second conductivity type second semiconductor region formed on one surface side of the single first conductivity type semiconductor substrate and spaced apart from the first semiconductor region;
A surface mount type semiconductor device comprising: a low resistance layer formed on the other surface side of the single first conductivity type semiconductor substrate.   2. The surface-mounting type according to claim 1, wherein the low-resistance layer is a first-conductivity-type layer or conductor having a higher impurity concentration and lower resistance than a semiconductor of the single first-conductivity-type semiconductor substrate. Semiconductor device.   When the thickness of the low-resistance layer is increased, the thickness of the low-resistance layer is the same as that of the current concentration occurrence portion of the second conductive type first semiconductor region or the second conductive type second semiconductor region. 3. The surface-mount type semiconductor device according to claim 1, wherein an allowable current density range is determined with reference to a current density when the current density converges, and the thickness satisfies the allowable current density range.

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