JP2014107418A - Semiconductor device and manufacturing method of the same - Google Patents

Semiconductor device and manufacturing method of the same Download PDF

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JP2014107418A
JP2014107418A JP2012259502A JP2012259502A JP2014107418A JP 2014107418 A JP2014107418 A JP 2014107418A JP 2012259502 A JP2012259502 A JP 2012259502A JP 2012259502 A JP2012259502 A JP 2012259502A JP 2014107418 A JP2014107418 A JP 2014107418A
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bonding wire
semiconductor device
bonding
electrode pad
mold layer
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Tatsunori Kin
辰徳 金
Tetsuya Okawa
哲也 大川
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
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    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To manufacture a highly reliable semiconductor device in an easy bonding process.SOLUTION: A semiconductor device comprises: a mold layer 40 composed of a halogen-free resin material; electrode pads 12, 13 formed by an alloy consisting primarily of aluminum (Al) and containing copper (Cu); and a bonding wire 30 formed by an alloy consisting primarily of silver (Ag) and added with gold (Au) and palladium (Pd), in which it is preferable that an additive amount of Au is within a range of 5-20 wt.% and an additive amount of Pd is within a range of 3-15 wt.%.

Description

本発明は、モールド層中にボンディングワイヤが接続された構造を具備する半導体装置、及びその製造方法に関する。   The present invention relates to a semiconductor device having a structure in which a bonding wire is connected in a mold layer, and a manufacturing method thereof.

例えばＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）等の半導体素子（スイッチング素子）が形成されたパワー半導体チップが使用される際には、この半導体素子を長期間にわたり安全に、かつ高い信頼性をもって使用するために、半導体チップがモールド層中に封止された形態の半導体モジュール（半導体装置）とされる。この場合、半導体チップ上の電極パッドとリード端子となるリードフレームとがボンディングワイヤで接続され、このリードフレームがモールド層から突出する形態とされる。   For example, when a power semiconductor chip on which a semiconductor element (switching element) such as an IGBT (Insulated Gate Bipolar Transistor) is formed is used, in order to use the semiconductor element safely and with high reliability over a long period of time. A semiconductor module (semiconductor device) having a semiconductor chip sealed in a mold layer is obtained. In this case, the electrode pad on the semiconductor chip and the lead frame serving as the lead terminal are connected by a bonding wire, and the lead frame protrudes from the mold layer.

こうした半導体装置の具体的構成は、例えば特許文献１に記載されている。図１は、この半導体装置の断面図である。この半導体装置においては、半導体チップ１１がダイパッド２１（リードフレーム）にはんだ等（図示せず）によって接合されて搭載されており、ダイパッド２１の両側には、リード端子（リードフレーム）２２、２３が配される。ダイパッド２１、リード端子２２、２３は銅等からなる金属板で一体成型されて製造されて構成され、これらは製造工程の途中においては図示された範囲外で結合されている。   A specific configuration of such a semiconductor device is described in Patent Document 1, for example. FIG. 1 is a cross-sectional view of this semiconductor device. In this semiconductor device, a semiconductor chip 11 is mounted on a die pad 21 (lead frame) by solder or the like (not shown), and lead terminals (lead frames) 22 and 23 are provided on both sides of the die pad 21. Arranged. The die pad 21 and the lead terminals 22 and 23 are manufactured by being integrally molded with a metal plate made of copper or the like, and these are joined outside the illustrated range during the manufacturing process.

半導体チップ１１の上面には、電極パッド１２、１３が設けられ、これらは半導体チップ１１内に形成された半導体素子の電極端子と接続される。電極パッド１２はリード端子２２と、電極パッド１３はリード端子２３と、それぞれボンディングワイヤ３０で接続される。半導体チップ１１の上面における電極パッド１２、１３が形成された以外の箇所は、ポリイミド層１４で覆われている。ボンディングワイヤ３０の端部には略球状とされたイニシャルボール３１が形成され、このイニシャルボール３１が電極パッド１３等と直接接合される。   Electrode pads 12 and 13 are provided on the upper surface of the semiconductor chip 11, and these are connected to electrode terminals of semiconductor elements formed in the semiconductor chip 11. The electrode pad 12 is connected to the lead terminal 22, and the electrode pad 13 is connected to the lead terminal 23 by a bonding wire 30. The portions other than the electrode pads 12 and 13 formed on the upper surface of the semiconductor chip 11 are covered with the polyimide layer 14. An initial ball 31 having a substantially spherical shape is formed at the end of the bonding wire 30, and the initial ball 31 is directly bonded to the electrode pad 13 or the like.

図１の構造においては、半導体チップ１１（電極パッド１２、１３を含む）、ダイパッド２１、ボンディングワイヤ３０は、樹脂材料（封止樹脂）で構成されたモールド層４０中に封止され、このモールド層４０の左右において、リード端子２２、２３がそれぞれ突出し、この半導体装置のリードとして使用される。モールド層４０によって、この半導体装置の耐環境性（耐湿性等）、耐衝撃性等が確保され、かつ半導体素子の電極端子間の絶縁性も確保される。   In the structure of FIG. 1, the semiconductor chip 11 (including the electrode pads 12 and 13), the die pad 21 and the bonding wire 30 are sealed in a mold layer 40 made of a resin material (sealing resin). Lead terminals 22 and 23 protrude on the left and right sides of the layer 40, and are used as leads of the semiconductor device. The mold layer 40 ensures environment resistance (such as moisture resistance) and impact resistance of the semiconductor device, and also ensures insulation between the electrode terminals of the semiconductor element.

この半導体装置を製造する際には、まず、図１の構造においてモールド層４０のみが形成されていない形態の構造体を製造する。このためには、ダイパッド２１の上に半導体チップ１１を搭載してから、電極パッド１２、１３とリード端子２２、２３とをボンディングワイヤ３０で接合して、この構造体を製造する。その後、例えばトランスファーモールド等の方法を用いて、熱硬化製樹脂等でモールド層４０を形成する。その後、図１に示されるように、ダイパッド２１、リード端子２２、２３を分離することによって、半導体装置（半導体モジュール）が得られる。   When manufacturing this semiconductor device, first, a structure in which only the mold layer 40 is not formed in the structure of FIG. 1 is manufactured. For this purpose, after mounting the semiconductor chip 11 on the die pad 21, the electrode pads 12, 13 and the lead terminals 22, 23 are joined by the bonding wires 30 to manufacture this structure. Thereafter, the mold layer 40 is formed of a thermosetting resin or the like using a method such as transfer molding. Thereafter, as shown in FIG. 1, the die pad 21 and the lead terminals 22 and 23 are separated to obtain a semiconductor device (semiconductor module).

この構造の半導体装置の高温保管時における信頼性は、ボンディングワイヤ３０と電極パッド１２（１３）、リード端子２２、２３との間の接合特性に影響を受ける。ここで、リード端子２２、２３が厚い金属板で構成される一方で、電極パッド１２、１３は、半導体素子が形成された半導体チップ１１上に薄い絶縁層等を介して形成される。このため、ボンディングワイヤ３０を電極パッド１２、１３に接合する際の条件（印加圧力等）においては、ボンディングワイヤ３０をリード端子２２、２３に接合する際の条件と比べて、その許容範囲が狭くなる。このため、一般には、ボンディングワイヤ３０と電極パッド１２、１３との間の接合特性が信頼性に与える影響が大きくなる。   The reliability of the semiconductor device having this structure during high-temperature storage is affected by the bonding characteristics between the bonding wire 30, the electrode pad 12 (13), and the lead terminals 22 and 23. Here, while the lead terminals 22 and 23 are formed of a thick metal plate, the electrode pads 12 and 13 are formed on the semiconductor chip 11 on which the semiconductor element is formed via a thin insulating layer or the like. For this reason, the conditions for applying the bonding wire 30 to the electrode pads 12, 13 (applied pressure, etc.) are narrower than the conditions for bonding the bonding wire 30 to the lead terminals 22, 23. Become. For this reason, generally, the influence of the bonding characteristics between the bonding wire 30 and the electrode pads 12 and 13 on the reliability is increased.

図２にボンディングワイヤ３０と電極パッド１２（１３）との接合部近辺を拡大して示すように、接合直後においては、ボンディングワイヤ３０と電極パッド１２（１３）との間に、これらを構成する材料を主成分とした薄い合金層１５が形成される。ボンディングワイヤ３０（イニシャルボール３１）と電極パッド１２（１３）の間の接合特性は、この合金層１５によって大きく左右される。この合金層１５が形成されるために、ボンディングワイヤ３０と電極パッド１２（１３）とが接合される。   As shown in FIG. 2 in an enlarged manner near the joint between the bonding wire 30 and the electrode pad 12 (13), immediately after the bonding, these are formed between the bonding wire 30 and the electrode pad 12 (13). A thin alloy layer 15 mainly composed of the material is formed. The bonding characteristics between the bonding wire 30 (initial ball 31) and the electrode pad 12 (13) are greatly influenced by the alloy layer 15. In order to form this alloy layer 15, the bonding wire 30 and the electrode pad 12 (13) are joined.

しかしながら、特許文献１には、高温保管時において、この合金層１５が成長することによって、接合強度が低下する、抵抗が上昇する等の問題が発生することが記載されている。更に、モールド層４０中に含まれる物質（特に臭素等のハロゲン）がこの合金層１５を腐食させることによって、合金層１５中にボイドや高抵抗層を形成させることが、接合強度の低下や抵抗の上昇をもたらすことも記載されている。ボンディングワイヤ３０の材質としては、金（Ａｕ）や、これよりも安価である銅（Ｃｕ）を主成分としたものが用いられるが、こうした問題は、どちらの場合においても発生する。   However, Patent Document 1 describes that, when the alloy layer 15 grows during high-temperature storage, problems such as a decrease in bonding strength and an increase in resistance occur. Furthermore, a substance (particularly halogen such as bromine) contained in the mold layer 40 corrodes the alloy layer 15 to form voids or a high resistance layer in the alloy layer 15. It is also described that it leads to an increase in. As a material of the bonding wire 30, a material mainly composed of gold (Au) or copper (Cu) which is cheaper than this is used. However, such a problem occurs in either case.

こうした状況を考慮し、特許文献１には、モールド層４０を構成する材料をハロゲンフリーとし、かつ電極パッド１２、１３をアルミニウム（Ａｌ）を主成分とし銅（Ｃｕ）を含む合金で構成することが記載されている。また、ボンディングワイヤ３０を、Ｃｕを主成分とし燐（Ｐ）を含む合金で構成して、これらの電極パッド１２、１３、モールド層４０と組み合わせて使用することが特に好ましいことが記載されている。この場合には、合金層１５はＣｕとＡｌを主成分とした合金で構成され、かつその組成は均一ではなく、電極パッド１２（１３）側からボンディングワイヤ３０（イニシャルボール３１）側に向かってＡｌリッチからＣｕリッチとなる。こうした構成の合金層１５が形成されることにより、高温保管時における合金層１５の成長が抑制され、かつハロゲンの悪影響も低減されるために、特に高い信頼性が得られる。   In view of these circumstances, Patent Document 1 discloses that the material constituting the mold layer 40 is halogen-free, and the electrode pads 12 and 13 are made of an alloy containing aluminum (Al) as a main component and containing copper (Cu). Is described. Further, it is described that it is particularly preferable that the bonding wire 30 is made of an alloy containing Cu as a main component and containing phosphorus (P) and used in combination with these electrode pads 12 and 13 and the mold layer 40. . In this case, the alloy layer 15 is made of an alloy mainly composed of Cu and Al, and the composition thereof is not uniform. From the electrode pad 12 (13) side toward the bonding wire 30 (initial ball 31) side. Al rich to Cu rich. By forming the alloy layer 15 having such a configuration, the growth of the alloy layer 15 during high-temperature storage is suppressed and the adverse effect of halogen is reduced, so that particularly high reliability is obtained.

特開２００９−１７７１０４号公報JP 2009-177104 A

しかしながら、Ｃｕを主成分とするボンディングワイヤを電極パッドに接合する工程（ボンディング工程）は容易ではない。   However, the process of bonding a bonding wire containing Cu as a main component to the electrode pad (bonding process) is not easy.

例えば、ボンディングワイヤ３０を接続する際には、キャピラリと呼ばれる筒状の部品の中にボンディングワイヤ３０が通される。その後、ボンディングワイヤ３０の先端に高電圧を印加し、アーク放電による発熱によってその先端部を溶融させることによって、その先端部にイニシャルボール３１が形成される。このイニシャルボール３１が電極パッド１２（１３）等に直接接合されて、ボンディングワイヤ３０が接続される。この際、酸化しやすいＣｕを主成分とするボンディングワイヤ３０においては、イニシャルボール３１を形成するための雰囲気に要求される条件が厳しく、例えば還元剤となる水素を導入することが必須とされる。Ｃｕは非常に酸化しやすい材料であるため、イニシャルボール３１を形成する場合のみならず、ボンディングワイヤ３０を電極パッド１２（１３）に接合する際においても、Ｃｕの酸化を抑制する必要があるのは同様である。このため、ボンディング工程の雰囲気に水素を導入することが必須となる。周知のように、水素を含むガスは爆発性があるため、その取り扱いは容易ではなく、ボンディング工程を行うために必要となる設備が大規模となった。   For example, when the bonding wire 30 is connected, the bonding wire 30 is passed through a cylindrical part called a capillary. Thereafter, a high voltage is applied to the tip of the bonding wire 30 and the tip is melted by heat generated by arc discharge, whereby the initial ball 31 is formed at the tip. The initial ball 31 is directly bonded to the electrode pad 12 (13) or the like, and the bonding wire 30 is connected. At this time, in the bonding wire 30 whose main component is Cu which is easily oxidized, the conditions required for the atmosphere for forming the initial ball 31 are strict, and for example, it is essential to introduce hydrogen as a reducing agent. . Since Cu is a material that is very easily oxidized, it is necessary to suppress oxidation of Cu not only when forming the initial ball 31 but also when bonding the bonding wire 30 to the electrode pad 12 (13). Is the same. For this reason, it is essential to introduce hydrogen into the atmosphere of the bonding process. As is well known, since gas containing hydrogen is explosive, handling thereof is not easy, and facilities required for performing the bonding process have become large.

また、Ｃｕは非常に硬い材料であるため、イニシャルボール３１の変形が生じにくく、これを電極パッド１２（１３）等に接合するためには、高い圧力を印加する必要がある。一方で、半導体チップ１１上の電極パッド１２（１３）にこれを接合する際の圧力が高すぎた場合には、半導体チップ１１に形成された半導体素子に損傷を与えるおそれがある。このため、ボンディングワイヤ３０を電極パッド１２（１３）等に接合する際の印加圧力の許容範囲は狭く、その制御も難しかった。   Further, since Cu is a very hard material, the initial ball 31 is hardly deformed, and a high pressure needs to be applied to join it to the electrode pad 12 (13) or the like. On the other hand, if the pressure applied to the electrode pad 12 (13) on the semiconductor chip 11 is too high, the semiconductor element formed on the semiconductor chip 11 may be damaged. For this reason, the allowable range of the applied pressure when bonding the bonding wire 30 to the electrode pad 12 (13) or the like is narrow, and its control is difficult.

このため、信頼性の高い半導体装置を、容易なボンディング工程によって製造することは困難であった。   For this reason, it has been difficult to manufacture a highly reliable semiconductor device by an easy bonding process.

本発明は、かかる問題点に鑑みてなされたものであり、上記問題点を解決する発明を提供することを目的とする。   The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

本発明は、上記課題を解決すべく、以下に掲げる構成とした。
本発明の半導体装置は、半導体チップ上に形成された電極パッドにボンディングワイヤが接続された構造がモールド層中に封止された構成を具備する半導体装置であって、前記電極パッドは、アルミニウム（Ａｌ）を主成分とし、銅（Ｃｕ）を含む合金で形成され、前記ボンディングワイヤは、銀（Ａｇ）を主成分とし、金（Ａｕ）を５〜２０重量％の範囲、パラジウム（Ｐｄ）を３〜１５重量％含む合金で形成され、前記モールド層は、ハロゲン含有率が１０００ｐｐｍ未満の樹脂材料で構成されたことを特徴とする。
本発明の半導体装置の製造方法は、前記半導体装置の製造方法であって、不活性ガス雰囲気において、前記ボンディングワイヤを前記電極パッドに加圧して接合するボンディング工程を具備することを特徴とする。 In order to solve the above problems, the present invention has the following configurations.
The semiconductor device of the present invention is a semiconductor device having a structure in which a bonding wire is connected to an electrode pad formed on a semiconductor chip and sealed in a mold layer, and the electrode pad is made of aluminum ( The bonding wire is made of an alloy containing Al) as a main component and copper (Cu), and the bonding wire is mainly composed of silver (Ag), gold (Au) in the range of 5 to 20% by weight, and palladium (Pd). The mold layer is formed of a resin material having a halogen content of less than 1000 ppm.
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device, comprising a bonding step of pressing and bonding the bonding wire to the electrode pad in an inert gas atmosphere.

本発明は以上のように構成されているので、信頼性の高い半導体装置を、容易なボンディング工程によって製造することができる。   Since the present invention is configured as described above, a highly reliable semiconductor device can be manufactured by an easy bonding process.

本発明の実施の形態に係る半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置における、電極パッドとボンディングワイヤとの間の接合部分付近の構造を拡大して示す断面図である。It is sectional drawing which expands and shows the structure of the junction part between an electrode pad and a bonding wire in the semiconductor device which concerns on embodiment of this invention.

以下、本発明の実施の形態となる半導体装置について説明する。この半導体装置（半導体モジュール）の構成は、図１に示されたものと同様である。すなわち、電極パッド１２、１３をその上面に具備する半導体チップ１１が、モールド層４０中に封止されている。この際、ボンディングワイヤ３０及びボンディングワイヤ３０とその電極パッド１２、１３、リード端子２２、２３との接合部も、モールド層４０中に封止される。   Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. The configuration of this semiconductor device (semiconductor module) is the same as that shown in FIG. That is, the semiconductor chip 11 having the electrode pads 12 and 13 on its upper surface is sealed in the mold layer 40. At this time, the bonding wire 30 and bonding portions of the bonding wire 30 and the electrode pads 12 and 13 and the lead terminals 22 and 23 are also sealed in the mold layer 40.

ここで、モールド層４０は、特許文献１に記載の技術と同様に、ハロゲンフリーの樹脂材料で構成される。この樹脂材料としては、例えば、エポキシ樹脂等の熱硬化製樹脂等を用いることができる。これによって、図１の構成のモールド層４０を例えばトランスファーモールド法等によって容易に形成することができる。ここで、ハロゲンフリーとは、ハロゲン（Ｂｒ等）の濃度が１０００ｐｐｍ以下、更に好ましくは１００ｐｐｍ以下であることを意味する。   Here, the mold layer 40 is made of a halogen-free resin material as in the technique described in Patent Document 1. As this resin material, for example, a thermosetting resin such as an epoxy resin can be used. Accordingly, the mold layer 40 having the configuration shown in FIG. 1 can be easily formed by, for example, a transfer molding method. Here, halogen-free means that the concentration of halogen (Br, etc.) is 1000 ppm or less, more preferably 100 ppm or less.

電極パッド１２、１３も、特許文献１に記載の技術と同様に、アルミニウム（Ａｌ）を主成分とし、銅（Ｃｕ）を含む合金で形成される。ここで、Ａｌを主成分とするとは、Ａｌの含有量が５０％を越えることを意味する。この電極パッド１２、１３は、例えばスパッタリング等によって半導体チップ１１上に容易に形成することができる。   Similarly to the technique described in Patent Document 1, the electrode pads 12 and 13 are also formed of an alloy containing aluminum (Al) as a main component and copper (Cu). Here, “having Al as a main component” means that the content of Al exceeds 50%. The electrode pads 12 and 13 can be easily formed on the semiconductor chip 11 by, for example, sputtering.

一方、ボンディングワイヤ３０は、銀（Ａｇ）を主成分とし、金（Ａｕ）、パラジウム（Ｐｄ）が添加された合金で形成される。このうち、Ａｕの添加量は５〜２０重量％の範囲、Ｐｄの添加量は３〜１５重量％が好ましい。   On the other hand, the bonding wire 30 is formed of an alloy containing silver (Ag) as a main component and added with gold (Au) and palladium (Pd). Among these, the addition amount of Au is preferably in the range of 5 to 20% by weight, and the addition amount of Pd is preferably 3 to 15% by weight.

上記の組み合わせで図１の構成の半導体装置を製造した場合には、特許文献１に記載の技術と同様に、高温保管における高い信頼性が得られる。この理由について、以下に説明する。   When the semiconductor device having the configuration shown in FIG. 1 is manufactured by the above combination, high reliability in high-temperature storage can be obtained as in the technique described in Patent Document 1. The reason for this will be described below.

特許文献１に記載の技術においては、ボンディングワイヤ３０の主成分をＣｕ、電極パッド１２（１３）の主成分をＡｌとした場合において、ＣｕとＡｌを主成分とする合金層１５が形成される。この合金層１５における厚さ方向の組成分布を最適化することによって、高温保管時の信頼性を高めていた。   In the technique described in Patent Document 1, when the main component of the bonding wire 30 is Cu and the main component of the electrode pad 12 (13) is Al, the alloy layer 15 mainly composed of Cu and Al is formed. . By optimizing the composition distribution in the thickness direction in the alloy layer 15, the reliability at high temperature storage has been improved.

これに対して、Ａｇを主成分としたボンディングワイヤ３０を用いた場合においては、ＡｌとＡｇを主成分とする合金層１５が形成される。このため、高温保管時における、ＡｌとＡｇを主成分とする合金層１５の成長が抑制されることが好ましいことは明らかである。この点において、ＰｄとＡｌの反応速度が遅いので、Ｐｄは、高温保管時における合金層１５の成長を抑制する。また、ＡｌとＡｇを主成分とする合金層１５は、ＣｕとＡｌを主成分とする合金層１５よりも、ハロゲン（Ｂｒ等）による腐食の影響を受けにくい。ただし、ハロゲンは、ＡｌとＡｇを主成分とする合金層１５の高温保管時における成長を促進する。このため、ハロゲンフリーの樹脂材料で構成されたモールド層４０を用いることによって、特に合金層１５の成長が抑制される。   On the other hand, when the bonding wire 30 mainly composed of Ag is used, the alloy layer 15 mainly composed of Al and Ag is formed. For this reason, it is clear that it is preferable to suppress the growth of the alloy layer 15 mainly composed of Al and Ag during high-temperature storage. In this respect, since the reaction rate of Pd and Al is slow, Pd suppresses the growth of the alloy layer 15 during high temperature storage. Further, the alloy layer 15 mainly composed of Al and Ag is less susceptible to corrosion by halogen (Br or the like) than the alloy layer 15 mainly composed of Cu and Al. However, the halogen promotes the growth of the alloy layer 15 mainly composed of Al and Ag during high temperature storage. For this reason, the growth of the alloy layer 15 is particularly suppressed by using the mold layer 40 made of a halogen-free resin material.

また、ボンディングワイヤ３０にＡｕを添加することにより、樹脂中のハロゲンとの間の反応が抑制される。また、ボンディングワイヤ３０自身や、イニシャルボール３１の酸化が抑制される。   Further, by adding Au to the bonding wire 30, the reaction with the halogen in the resin is suppressed. Further, the oxidation of the bonding wire 30 itself and the initial ball 31 is suppressed.

ここで、Ｐｄの添加量が３重量％未満である場合には、高温保管時における合金層１５の成長が抑制される効果が小さくなる。Ｐｄの添加量が１５重量％を越える場合には、ボンディングワイヤ３０の電気抵抗が高くなる。また、Ａｕの添加量が５重量％未満である場合には、前記のハロゲンとの反応抑制や酸化に対する効果が小さくなる。Ａｕの添加量が２０重量％を越えた場合には、ボンディングワイヤ３０の製造コストが高くなるために好ましくない。   Here, when the addition amount of Pd is less than 3% by weight, the effect of suppressing the growth of the alloy layer 15 during high-temperature storage is reduced. When the amount of Pd added exceeds 15% by weight, the electrical resistance of the bonding wire 30 increases. Moreover, when the addition amount of Au is less than 5% by weight, the effect on the reaction suppression and oxidation with the halogen becomes small. When the added amount of Au exceeds 20% by weight, the manufacturing cost of the bonding wire 30 is increased, which is not preferable.

すなわち、上記の組成のボンディングワイヤ３０を用いることにより、特許文献１に記載の技術と同様に、高温保管時における合金層１５の成長、腐食が抑制されるため、半導体装置の高い信頼性が得られる。   That is, by using the bonding wire 30 having the above composition, the growth and corrosion of the alloy layer 15 during high-temperature storage is suppressed as in the technique described in Patent Document 1, so that high reliability of the semiconductor device is obtained. It is done.

また、Ａｇを主成分としたボンディングワイヤ３０を電極パッド１２（１３）に接合する際に、ＡｇはＣｕと比べて酸化しにくい材料であるため、その雰囲気に還元剤（例えば水素１０％）を含む必要はない。このため、水素を含まない不活性ガス（窒素等）を用いて容易かつ爆発の危険性がなく、安全にボンディング工程を行うことができる。   Further, when bonding the bonding wire 30 containing Ag as a main component to the electrode pad 12 (13), Ag is a material that is hard to oxidize compared to Cu, and therefore a reducing agent (for example, 10% hydrogen) is added to the atmosphere. It is not necessary to include. For this reason, the bonding process can be performed safely using an inert gas (nitrogen or the like) that does not contain hydrogen easily and without risk of explosion.

更に、ＡｇはＣｕと比べて軟らかい材料であるために、電極パッド１２（１３）への接合時に印加する圧力を、より低くすることができる。このため、接合時において半導体チップ１１に形成された半導体素子に損傷を与える可能性も低くなり、印加圧力の許容範囲が広くなる。以上により、上記のボンディングワイヤ３０を用いた場合には、ボンディング工程を容易に行うことができる。   Furthermore, since Ag is a softer material than Cu, the pressure applied at the time of bonding to the electrode pad 12 (13) can be further reduced. For this reason, the possibility of damaging the semiconductor element formed on the semiconductor chip 11 at the time of bonding is reduced, and the allowable range of the applied pressure is widened. As described above, when the bonding wire 30 is used, the bonding process can be easily performed.

具体的には、例えば、電極パッド１２（１３）を、Ａｌ：９９．５重量％、Ｃｕ：０．５重量％の合金（厚さ５μｍ）で構成し、ボンディングワイヤ３０を、重量％、Ａｕ：８．５重量％、Ｐｄ：３．５重量％、Ａｇ：残部、とした組成（３８μｍ径）とし、これらの間の接合（イニシャルボール形成を含む）を、２００℃、窒素雰囲気で行うことができる。この場合、１７５℃、１０００時間の高温保管後においても、劣化のない接合特性が得られる。   Specifically, for example, the electrode pad 12 (13) is made of an alloy (thickness 5 μm) of Al: 99.5 wt% and Cu: 0.5 wt%, and the bonding wire 30 is made of wt%, Au : 8.5% by weight, Pd: 3.5% by weight, Ag: balance, 38 μm diameter, and bonding between them (including initial ball formation) is performed at 200 ° C. in a nitrogen atmosphere. Can do. In this case, even after high temperature storage at 175 ° C. for 1000 hours, bonding characteristics without deterioration can be obtained.

更に、Ａｕを主成分とするボンディングワイヤを用いる場合と比べると、上記の組成のボンディングワイヤ３０は、より低コストであることも明らかである。   Furthermore, it is apparent that the bonding wire 30 having the above composition is lower in cost than the case of using a bonding wire mainly composed of Au.

１１ 半導体チップ
１２、１３ 電極パッド
１４ ポリイミド層
１５ 合金層
２１ ダイパッド（リードフレーム）
２２、２３ リード端子（リードフレーム）
３０ ボンディングワイヤ
３１ イニシャルボール（ボンディングワイヤ）
４０ モールド層 11 Semiconductor chip 12, 13 Electrode pad 14 Polyimide layer 15 Alloy layer 21 Die pad (lead frame)
22, 23 Lead terminal (lead frame)
30 Bonding wire 31 Initial ball (bonding wire)
40 Mold layer

Claims (2)

半導体チップ上に形成された電極パッドにボンディングワイヤが接続された構造がモールド層中に封止された構成を具備する半導体装置であって、
前記電極パッドは、アルミニウム（Ａｌ）を主成分とし、銅（Ｃｕ）を含む合金で形成され、
前記ボンディングワイヤは、銀（Ａｇ）を主成分とし、金（Ａｕ）を５〜２０重量％の範囲、パラジウム（Ｐｄ）を３〜１５重量％含む合金で形成され、
前記モールド層は、ハロゲン含有率が１０００ｐｐｍ未満の樹脂材料で構成されたことを特徴とする半導体装置。 A semiconductor device comprising a structure in which a bonding wire is connected to an electrode pad formed on a semiconductor chip and sealed in a mold layer,
The electrode pad is made of an alloy containing aluminum (Al) as a main component and copper (Cu),
The bonding wire is formed of an alloy containing silver (Ag) as a main component, gold (Au) in the range of 5 to 20% by weight, and palladium (Pd) in the range of 3 to 15% by weight,
The semiconductor device, wherein the mold layer is made of a resin material having a halogen content of less than 1000 ppm. 請求項１に記載の半導体装置の製造方法であって、
不活性ガス雰囲気において、前記ボンディングワイヤを前記電極パッドに加圧して接合するボンディング工程を具備することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, comprising: a bonding step of pressing and bonding the bonding wire to the electrode pad in an inert gas atmosphere.
JP2012259502A 2012-11-28 2012-11-28 Semiconductor device and manufacturing method of the same Pending JP2014107418A (en)

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CN109346590A (en) * 2018-11-20 2019-02-15 北京宇极芯光光电技术有限公司 A kind of full spectrum white-light LED device

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JP2006270075A (en) * 2005-02-22 2006-10-05 Nec Electronics Corp Semiconductor device
JP2012169374A (en) * 2011-02-10 2012-09-06 Tanaka Electronics Ind Co Ltd Ag-Au-Pd TERNARY ALLOY BASED BONDING WIRE

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Publication number Priority date Publication date Assignee Title
JP2006270075A (en) * 2005-02-22 2006-10-05 Nec Electronics Corp Semiconductor device
JP2012169374A (en) * 2011-02-10 2012-09-06 Tanaka Electronics Ind Co Ltd Ag-Au-Pd TERNARY ALLOY BASED BONDING WIRE

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109346590A (en) * 2018-11-20 2019-02-15 北京宇极芯光光电技术有限公司 A kind of full spectrum white-light LED device
CN109346590B (en) * 2018-11-20 2023-10-03 北京宇极芯光光电技术有限公司 Full spectrum white light LED device

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