JP2014082378A - Manufacturing method of reverse blocking mos semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a reverse blocking MOS semiconductor device which can reduce decrease in resistance of a semiconductor substrate, and suppresses decrease in on-state voltage, and reduce reverse leakage current and decrease in breakdown voltage even having high voltage of 1200 V and over.SOLUTION: The manufacturing method of a reverse blocking MOS semiconductor device comprises: a first step of forming an annular p-type isolation diffusion layer by ion implantation on an outer periphery of each region to be a device chip of an n-type semiconductor substrate by heat treatment at a diffusion temperature of 1280°C-1320°C for 300 hours-330 hours; and a second step of forming a MOS gate structure and a breakdown voltage structure, which become a semiconductor functional region on an inner periphery surrounded by the annular isolation diffusion layer. In the first step, when lowering the temperature after completion of the heat treatment at the diffusion temperature of 1280°C-1320°C for 300 hours-330 hours, a diffusion temperature-time program is executed for lowering the temperature to a temperature range of not less than 1000°C and not more than 1200°C and subsequently keeping the temperature within the temperature range for 25 hours and over.

Description

  The present invention relates to a method for manufacturing a reverse blocking MOS semiconductor device having a step of forming a deep impurity diffusion layer accompanied by high temperature and long time diffusion.

  In recent years, in a power conversion circuit for performing AC (alternating current) / AC conversion, AC / DC (direct current) conversion, DC / AC conversion, etc. using a semiconductor element, direct current smoothing composed of an electrolytic capacitor, a direct current reactor, etc. A matrix converter is known as a direct link type conversion circuit that can eliminate the need for a circuit. Since this matrix converter is used under an alternating voltage, a plurality of switching devices constituting the matrix converter require bidirectional switching devices capable of current control in the forward and reverse directions.

  Recently, from the viewpoint of circuit miniaturization, weight reduction, high efficiency, high speed response and low cost, the bidirectional switching device is replaced with two reverse blocking IGBTs as shown in the equivalent circuit diagram of FIG. An antiparallel connection configuration has attracted attention. Such a bidirectional switching device having a reverse-blocking IGBT with an anti-parallel connection has an advantage that a diode for blocking a reverse voltage can be eliminated. The reverse blocking IGBT is a device having a characteristic that the reverse breakdown voltage is set to a breakdown voltage comparable to the forward breakdown voltage and the breakdown voltage reliability is also improved. On the other hand, in a normal IGBT used in a conventional power conversion circuit, an effective reverse breakdown voltage is unnecessary as in a normal transistor or MOSFET that does not have a reverse breakdown voltage. An IGBT having a low performance and a low withstand voltage reliability was sufficient.

  FIG. 5 is a schematic cross-sectional view showing such a reverse blocking IGBT, which is described in Patent Document 1 below. This reverse blocking IGBT has an active region 110 in the center of the device chip, and has a structure having a p-type isolation diffusion layer 31 surrounding the outer side of the active region 110 with a breakdown voltage structure region 120 therebetween. Features. In order to form the p-type isolation / diffusion layer 31 only by thermal diffusion from one main surface of the n-type silicon substrate 1, the depth of the p-type isolation / diffusion layer 31 needs to be greater than the thickness of the substrate. So with high temperature long time thermal diffusion drive. The active region 110 of the reverse blocking IGBT shown in FIG. 5 includes an n-type drift layer 1, a p-type base region 2, an n-type emitter region 3, a gate insulating film 4, a gate electrode 5, an interlayer insulating film 6, an emitter electrode 9 and p. This is a region serving as a main current path of a vertical IGBT including the type collector layer 10 and the collector electrode 11. The p-type isolation diffusion layer 31 is a p-type region formed at a depth reaching the p-type collector layer 10 on the back surface side by thermal diffusion of boron from the surface of the n-type silicon substrate. By this p-type isolation diffusion layer 31, the end portion of the pn junction surface between the p-type collector layer 10 and the n-type drift layer 1, which is a reverse breakdown voltage junction, is exposed on the chip side end surface 12 that becomes a cut surface when chipping. Without being exposed to the surface 13 of the breakdown voltage structure region 120 protected by the insulating film, the reverse breakdown voltage reliability can be increased.

  4 (a) to 4 (d) are cross-sectional views of a manufacturing process showing a conventional impurity diffusion process in which the p-type isolation diffusion layer 104 according to such reverse blocking IGBT is formed by boron ion implantation and thermal diffusion in the order of steps. FIG. First, a thermal oxide film 101 having a thickness of about 0.8 μm to 2.5 μm is formed as a dopant mask on the surface side of a thick silicon semiconductor substrate 100 having a thickness of 600 μm or more (FIG. 4A). The oxide film 101 is patterned to form an opening 102 for introducing an impurity for forming an isolation diffusion layer (FIG. 4B). Next, boron which becomes an impurity is ion-implanted 103 from the opening 102 (FIG. 4C). The thermal oxide film 101 used as a dopant mask for selective diffusion of boron (for the p-type isolation diffusion layer) is removed. Heat treatment is performed at a high temperature (1300 ° C.) for a long time (100 hours to 200 hours) to form a p-type diffusion layer 104 having a depth of about 100 μm to 200 μm (FIG. 4D). This p-type diffusion layer 104 is used as a separation diffusion layer. Thereafter, an oxide film is formed again on the surface of the silicon semiconductor substrate 100 surrounded by the p-type diffusion layer 104, and a process (not shown) for forming a MOS gate structure and a necessary surface side functional region is performed. The silicon semiconductor substrate 100 is thinned by grinding and removing from the back surface of the silicon semiconductor substrate 100 until it reaches the bottom of the p-type diffusion layer 104 (FIG. 4D). A back surface structure composed of a p collector layer and a collector electrode (not shown) is formed on this back ground surface, and the silicon semiconductor substrate 100 is cut by a scribe line 105 located at the center of the diffusion layer 104. The reverse blocking IGBT formed into a chip by this cutting is the cross-sectional view of FIG.

  However, as shown in FIG. 5, in the reverse blocking IGBT in which the p-type isolation diffusion layer 31 is formed by ion implantation, as described above, a high-temperature long-time thermal diffusion drive is performed to form the deep p-type isolation diffusion layer 31. Is done. As a result, interstitial oxygen is introduced into the silicon substrate during this high-temperature and long-time thermal diffusion drive, and oxygen precipitates, an oxygen donor phenomenon, crystal defects, and the like are introduced. When these crystal defects are introduced, there is a high possibility that the leakage current becomes high at the pn junction in the silicon substrate and that the withstand voltage and reliability of the insulating film formed on the silicon substrate are greatly deteriorated.

  FIG. 7 is a current I-voltage V waveform characteristic diagram showing a reverse breakdown voltage waveform of the reverse blocking IGBT. When there are almost no crystal defects in the silicon substrate, a hard waveform with a sharp rise in current as shown in FIG. 7A is shown, but there are many crystal defects due to the aforementioned nitrogen precipitates and the like. Is included, a soft waveform in which the current rises gently as shown in FIG. When the reverse currents in the IV waveforms of (a) and (b) are compared at the standard breakdown voltage (dashed line) shown in FIG. 7, the soft waveform of (b) is the reverse of the hard waveform of (a). It can be seen that the direction current, that is, the reverse leakage current is large. A device having a reverse leakage current larger than a predetermined reference value has a reverse breakdown voltage failure.

  In addition, a gettering technique for the purpose of suppressing the influence of crystal defects caused by donor formation of oxygen introduced by a high-temperature long-time thermal diffusion drive in the reverse blocking IGBT as described above is known. For such gettering, high-temperature and long-time thermal diffusion drive conditions include heat treatment at 1300 ° C. for 100 hours or more, heat treatment at 1100 ° C. for 200 minutes, 1150 ° C. for 120 minutes, and 1000 ° C. for 30 minutes. (Patent Documents 2 and 3).

Japanese Patent Laying-Open No. 2006-80269 (FIG. 7) Japanese Patent No. 489825 (paragraph 0011) Japanese Patent No. 4995172 (paragraph 0010)

  However, the reverse blocking IGBT requires separation diffusion in which both main surfaces are connected by a diffusion layer having a conductivity type different from that of the substrate by impurity diffusion from one main surface of the silicon substrate as described above. . For example, in an n-type silicon substrate, the separation diffusion layer is p-type. In such separation diffusion, as the thickness of the silicon substrate increases, the time during which the silicon substrate is exposed to a high temperature is inevitably increased during the separation diffusion. And the reverse breakdown voltage tends to be smaller than the forward breakdown voltage. In particular, in the high breakdown voltage reverse blocking IGBT of 1200 V or higher, the reverse breakdown voltage tends to be difficult to extend. As a countermeasure, it is necessary to design in advance that the resistivity of the substrate is higher than usual and the thickness of the substrate is thicker than usual. However, since the resistivity of the substrate is higher than usual and the thickness of the substrate is increased, the diffusion time becomes longer and the semiconductor characteristics are deteriorated. The problem becomes difficult.

  As described above, according to the diffusion heat treatment conditions according to the inventions described in Patent Documents 2 and 3, even when a deep isolation diffusion layer necessary for a high breakdown voltage reverse blocking IGBT is formed, generation of crystal defects is suppressed to some extent. However, it has been found that it is still insufficient to prevent the resistivity of the silicon substrate (high resistance drift layer) from being lowered by the oxygen donor. In addition, since the decrease in resistivity of the silicon substrate (high resistance drift layer) decreases the forward breakdown voltage and reverse breakdown voltage of the reverse blocking IGBT, an expected decrease in resistivity is anticipated in advance when designing the element. Therefore, it is necessary to increase the resistivity of the input substrate and increase the substrate thickness accordingly. As a result, it is inevitable to increase the on-voltage of the device and deteriorate the trade-off relationship between the on-voltage and the turn-off voltage. In addition, due to the high oxygen concentration introduced with high temperature and long time diffusion, a large amount of oxygen precipitates are deposited in the silicon substrate, which increases the reverse leakage current and decreases the reverse breakdown voltage. It had a great influence. Therefore, when the thickness of the substrate is further increased, the diffusion time of the p-type separation diffusion layer is further increased, and the above-described problem is further deteriorated.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to reduce the resistance of the semiconductor substrate even when the withstand voltage is 1200 V or higher, and to reduce the on-voltage and reverse voltage. An object of the present invention is to provide a reverse blocking MOS semiconductor device manufacturing method capable of reducing leakage current and breakdown voltage reduction.

  In order to solve the above-described problems and achieve the object of the present invention, an annular p-type separation diffusion layer is formed by ion implantation at the outer peripheral portion of each device chip region of an n-type semiconductor substrate, with a diffusion temperature of 1280 ° C. A first step of forming by heat treatment at ˜1320 ° C. for 300 hours to 330 hours, and a second step of forming a MOS gate structure and a breakdown voltage structure as a semiconductor functional region in the inner periphery surrounded by the annular isolation diffusion layer In the reverse blocking MOS type semiconductor device manufacturing method, in the first step, the temperature is 1000 ° C. or more and 1200 ° C. or less when the temperature is lowered after the heat treatment of the diffusion temperature of 1280 ° C. to 1320 ° C. and 300 hours to 330 hours. A method of manufacturing a reverse blocking MOS semiconductor device having a diffusion temperature-time program in which a temperature is lowered to a range and then maintained at a temperature within the temperature range for 25 hours or more.

  In order to solve the above-described problems and achieve the object of the present invention, an annular p-type separation diffusion layer is formed by ion implantation at the outer peripheral portion of the region to be each device chip of the n-type semiconductor substrate. A first step of forming under a heat treatment condition of 1280 ° C. to 1320 ° C. for 300 hours to 330 hours; a second step of forming a MOS gate structure and a breakdown voltage structure as a semiconductor functional region in the inner periphery surrounded by the annular isolation diffusion layer In the manufacturing method of the reverse blocking MOS semiconductor device having the steps, in the first step, the heat treatment is performed at a diffusion temperature of 1280 ° C. to 1320 ° C. for 300 hours to 330 hours. A reverse-blocking MOS type semiconductor device having a diffusion temperature-time program in which a temperature is raised to a temperature range of 1200 ° C. or lower and held at a temperature within the temperature range for 25 hours or more. The production method. It is preferable that the temperature maintained within the temperature range of 1000 μm or more and 1200 μm or less for the 25 hours or more is a constant temperature. Moreover, it is also preferable that the thickness of the semiconductor substrate heat-treated in the first step is in the range of 100 μm to 200 μm. Furthermore, it is desirable that the forward withstand voltage and the reverse withstand voltage are 1200 V or more. Furthermore, a reverse blocking IGBT is desirable as the reverse blocking MOS semiconductor device.

  According to the present invention, there is provided a method for manufacturing a reverse blocking MOS semiconductor device in which the reduction in resistance of a semiconductor substrate is reduced even when the breakdown voltage is 1200 V or higher, and the ON voltage, reverse leakage current, and breakdown voltage drop are small. Can do.

It is a diffusion temperature-time program figure at the time of p-type isolation | separation diffusion layer formation concerning this invention. It is a diffusion temperature-time program figure at the time of the conventional p-type isolation | separation diffusion layer formation. It is an oxygen concentration profile figure which shows oxygen concentration distribution from the surface of the silicon substrate of this invention and the conventional reverse block IGBT. It is manufacturing process sectional drawing which shows the isolation | separation diffused layer formation method by the conventional ion implantation. It is sectional drawing of reverse prevention IGBT. It is an equivalent circuit diagram of a bidirectional switching device using a reverse blocking IGBT. It is a current I-voltage V waveform characteristic view showing a reverse breakdown voltage waveform of a reverse blocking IGBT. It is principal part sectional drawing which showed the manufacturing method of the reverse blocking IGBT concerning the Example of this invention in order of the process (the 1). It is principal part sectional drawing which showed the manufacturing method of reverse blocking IGBT concerning the Example of this invention in order of the process (the 2). It is principal part sectional drawing which showed the manufacturing method of reverse blocking IGBT concerning the Example of this invention in order of the process (the 3). It is principal part sectional drawing which showed the manufacturing method of reverse blocking IGBT concerning the Example of this invention in order of the process (the 4). It is principal part sectional drawing which showed the manufacturing method of reverse blocking IGBT concerning the Example of this invention in order of the process (the 5).

  Embodiments according to a method of manufacturing a reverse blocking MOS semiconductor device of the present invention will be described below in detail with reference to the drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is relatively high or low, respectively. In the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. It should be noted that the accompanying drawings described in the embodiments are not drawn to scale or dimensional ratios for the sake of easy understanding or understanding.

  In the following embodiments, a reverse blocking IGBT manufacturing method will be described as a method for manufacturing a reverse blocking MOS semiconductor device according to the present invention. However, the present invention is not limited to the manufacturing method of the reverse blocking IGBT.

An embodiment of a method for manufacturing a reverse blocking IGBT according to the present invention will be described in detail with a focus on its characteristic part.
FIG. 8 to FIG. 12 are cross-sectional views of relevant parts showing the reverse blocking IGBT manufacturing method according to the embodiment of the present invention in the order of steps. A method for manufacturing a reverse blocking IGBT having a breakdown voltage of 1200 V will be described. As shown in FIG. 8, an initial oxide film of about 0.8 μm to 2.5 μm is formed on the surface of the FZ silicon substrate 1 having a thickness of 600 μm or more and a specific resistance of 80 Ωcm. In the subsequent process, the initial oxide film is selectively etched in an annular pattern surrounding the outer periphery of the active region over the semiconductor functional region at the center of each device chip region in the silicon substrate 1 for separation and diffusion with a width of 170 μm. The opening 20 is formed. Next, as shown in FIG. 9, boron, which is a p-type impurity, is ion-implanted from the opening 20 using the initial oxide film as a mask. After the boron implantation, the initial oxide film used as the dopant mask is removed. Heat treatment is performed in an oxidizing atmosphere at a high temperature (1300 ° C.) for a long time (300 hours to 330 hours) to form a p-type diffusion layer having a depth of about 220 to 230 μm (FIG. 9). This p-type diffusion layer is used as the separation diffusion layer 31. The present invention is characterized by a temperature and time program for forming the separation diffusion layer 31. This temperature and time program will be described in detail later.

  Next, as shown in FIG. 10, after removing the oxide film formed on the substrate surface during the formation of the separation diffusion layer 31, the oxide film is reattached, and this oxide film and / or the deposited polysilicon film are used. A p base region 2, an n-type emitter region 3, a gate oxide film 4, a gate electrode 5, an interlayer insulating film 6, an emitter electrode 9 and the like having a predetermined pattern are formed by a method similar to that of a normal planar gate IGBT. Although not shown, a trench-type surface structure may be used. Furthermore, in order to increase the speed, electron beam irradiation or helium irradiation may be performed as a lifetime killer. Next, as shown in FIG. 11, the back surface is shaved so that the thickness of the FZ silicon substrate 1 is about 200 μm, and the p-type separation diffusion layer 31 is exposed on the shaving surface 21.

Next, as shown in FIG. 12, boron having a dose amount of 1 × 10 ¹³ cm ⁻² is ion-implanted into the back surface 20 and subjected to low-temperature annealing at about 350 ° C. for about 1 hour, thereby activating the peak concentration of boron. Is formed on the back side p-type collector layer 10 having a thickness of about 1 × 10 ¹⁷ cm ⁻³ and a thickness of about 1 μm. The p-type collector layer 10 on the back surface and the p-type isolation diffusion layer 31 are conductively connected. When the silicon substrate 1 is cut into device chips after the collector electrode 11 is formed, a reverse blocking IGBT as shown in FIG. 12 is completed.

  The separation diffusion layer forming method according to the present invention is different from the conventional reverse blocking IGBT formation diffusion layer forming method described with reference to FIG. 4 in the following points. About other processes, it can be made to be the same as that of the manufacturing method of the conventional reverse blocking IGBT. That is, in the reverse blocking IGBT manufacturing method according to the present invention, when the temperature of the step of forming the p-type separation diffusion layer by ion implantation is lowered after the end of the heat treatment at the diffusion temperature of 1280 ° C to 1320 ° C for 300 hours to 330 hours. In addition, the temperature is once lowered to a temperature range of 1000 ° C. or higher and 1200 ° C. or lower, and then a diffusion temperature-time program is maintained for 25 hours or longer at a temperature within the temperature range.

  Alternatively, when the temperature of the step of forming the p-type separation diffusion layer by ion implantation is increased in order to perform a heat treatment at a diffusion temperature of 1280 ° C. to 1320 ° C. for 300 hours to 330 hours, a temperature range of 1000 ° C. to 1200 ° C. A diffusion temperature-time program in which the temperature is temporarily maintained at a temperature within the above temperature range for 25 hours or longer and then heat treatment is performed at a desired diffusion temperature of 1280 ° C to 1320 ° C for 300 hours to 330 hours. Is different from the conventional point.

  Such a diffusion temperature-time program according to the present invention will be further described below. FIG. 1 is a diffusion temperature-time program diagram when forming a p-type isolation diffusion layer according to the present invention. FIG. 2 is a diffusion temperature-time program diagram when forming a conventional p-type isolation diffusion layer for comparison. In either case, the vertical axis represents the diffusion furnace temperature, and the horizontal axis represents the time schedule. However, neither the vertical axis interval nor the horizontal axis interval in FIGS. 1 and 2 shows an accurate proportional relationship with the diffusion furnace temperature and time, respectively. The left end of the figure is the start time of the program, that is, the furnace loading of the silicon substrate, and the right end is the end time, that is, the furnace starting of the silicon substrate.

After completing the ion implantation into the annular separation diffusion layer opening 20 formed in the outer peripheral portion of the surface in each reverse blocking IGBT chip pattern of the silicon substrate 1 in the process of FIG. 8, the process of FIG. enter. As specific processing conditions and work, boron (1.6 ₂ liters / minute) of oxygen (O ₂ ) gas and 4.6 liters / minute of argon (Ar) gas are flown as carrier gas in a diffusion furnace at 750 ° C. After completion of the ion implantation, the silicon substrate 1 is set and held for 60 minutes as shown in FIG. Thereafter, the furnace temperature of the diffusion furnace is increased at a heating rate of 1.0 ° C./min. When reaching 1250 ° C., the heating rate is decreased to 0.5 ° C./min and the furnace temperature is increased to 1300 ° C. The separation diffusion layer 31 having a diffusion depth of 200 μm or more is formed by holding at a furnace temperature of 1300 ° C. for 300 hours. After completion of the diffusion heat treatment at 1300 ° C., the furnace temperature is lowered to 1200 ° C. at a temperature lowering rate of 0.5 ° C./min. After reaching 1200 ° C., hold at 1200 ° C. for 25 hours. Thereafter, the furnace temperature is lowered to 1000 ° C. at a temperature lowering rate of 1.0 ° C./min. Further, the furnace temperature is lowered to 750 ° C. at a temperature lowering rate of 2.5 ° C./min, and held at 750 ° C. for 60 minutes. When 1 is taken out from the diffusion furnace, the state shown in FIG. 9 is obtained. The difference between the present invention and the conventional diffusion temperature-time program diagram of FIG. 1 and FIG. 2 is the presence or absence of a holding time at 1200 ° C.

  On the other hand, as described with reference to FIG. 10, the silicon substrate 1 taken out from the diffusion furnace is formed with the semiconductor functional region in the central active region surrounded by the isolation diffusion layer 31 and the breakdown voltage structure region around it. The After that, when the depth of the separation diffusion layer is about 220 μm, the remaining thickness of the substrate is cut to about 200 μm from the back surface of the silicon substrate 1 opposite to the ion implantation surface as shown in FIG. If a p-type collector layer and a collector electrode are formed on the back surface of the substrate as shown in FIG. 12, the reverse blocking IGBT according to the present invention can be obtained.

  As described above, in the reverse blocking IGBT with a withstand voltage of 1200 V according to the present invention, when forming the isolation diffusion layer 31, before and after the high-temperature long-time diffusion drive process consisting of 300 hours to 330 hours at 1300 ° C., 1000 ° C. It is characterized by having a process that is held in the temperature range of from 1 to 1200 ° C. for 25 hours.

  On the other hand, FIG. 3 is an oxygen concentration profile diagram in which the vertical axis represents the oxygen concentration and the horizontal axis represents the depth of the oxygen donor layer from the surface of the silicon substrate. FIG. 3 shows the oxygen concentration from the substrate surface in the case of having the same diffusion drive conditions as those for forming the separation diffusion layer 31 and the processing conditions with the holding time in the temperature range of 1000 ° C. to 1200 ° C. as parameters. Distribution is shown.

There are three types of holding time in the above-described temperature range of 1000 ° C. to 1200 ° C .: none, 15 hours, and 25 hours. Without the holding time, the oxygen concentration is constant at about 1.2 × 10 ¹⁸ / cm ⁻³ in a deep region after the depth of 50 μm from the surface, and 1.5 × 10 ¹⁷ / of the surface in the region shallower than 50 μm. The gradient is such that the oxygen concentration decreases toward a low oxygen concentration of cm ⁻³ . When the holding time is 15 hours, the oxygen concentration is constant at about 1.2 × 10 ¹⁸ / cm ⁻³ in a deep region after 100 μm, and in the region shallower than 100 μm, the slope is inclined toward the low oxygen concentration surface as described above. ing. When the holding time is 25 hours, the oxygen concentration is constant at about 1.2 × 10 ¹⁸ / cm ⁻³ in a deep region after 150 μm, and in the region shallower than 150 μm, the gradient is inclined toward the low oxygen concentration surface as described above. ing.

  FIG. 3 shows that when the holding time is 25 hours, the oxygen concentration is low in the region shallower than 150 μm from the surface, so that the influence of the resistance reduction of the n-type silicon substrate by the oxygen donor is reduced. When manufacturing a reverse blocking IGBT with a withstand voltage of 1200 V using a silicon substrate having a resistivity of 80 Ωcm, the depletion layer expands by about 170 μm, and about 150 μm of that, the oxygen concentration becomes low and the increase in the substrate concentration by the oxygen donor is suppressed. The As a result, the effect of lowering the resistance of the substrate is reduced, so that the effect on the breakdown voltage of the device is reduced. As described above, according to the embodiment described above, by suppressing the decrease in the substrate resistivity due to the oxygen donor, it is not necessary to design the silicon substrate with a high resistivity and a large thickness in advance. Can be reduced. In addition, even if the silicon substrate is subjected to a high-temperature long-time diffusion treatment in an oxygen atmosphere, the substrate surface is prevented from having a high oxygen concentration, so that no oxygen precipitation occurs on the substrate surface and a defect-free layer is obtained. Leakage current is reduced and the breakdown voltage is reduced. As a result, the yield rate is improved.

DESCRIPTION OF SYMBOLS 1 Silicon substrate, drift layer 2 p-type base region 3 n-type emitter region 4 Gate insulating film 5 Gate electrode 6 Interlayer insulating film 9 Emitter electrode 10 p-type collector layer 11 Collector electrode 12 Chip side end surface 13 Surface of breakdown voltage structure region 20 Opening 21 Cutting surface 31 Separation diffusion layer

Claims (6)

An annular second conductivity type separation diffusion layer is formed by ion implantation on the outer periphery of the region to be each device chip of the first conductivity type semiconductor substrate under a heat treatment condition of a diffusion temperature of 1280 ° C. to 1320 ° C. for 300 hours to 330 hours. In the manufacturing method of the reverse blocking MOS type semiconductor device, which has a first step, a second step of forming a MOS gate structure and a breakdown voltage structure serving as a semiconductor functional region in an inner periphery surrounded by the annular isolation diffusion layer. In the step, after the heat treatment at the diffusion temperature of 1280 to 1320 ° C. and 300 to 330 hours, the temperature is lowered to a temperature range of 1000 ° C. to 1200 ° C., and then the temperature within the temperature range. And a diffusion temperature-time program for holding for at least 25 hours. An annular second conductivity type separation diffusion layer is formed by ion implantation on the outer periphery of the region to be each device chip of the first conductivity type semiconductor substrate under a heat treatment condition of a diffusion temperature of 1280 ° C. to 1320 ° C. for 300 hours to 330 hours. In the manufacturing method of the reverse blocking MOS type semiconductor device, which has a first step, a second step of forming a MOS gate structure and a breakdown voltage structure serving as a semiconductor functional region in an inner periphery surrounded by the annular isolation diffusion layer. In the process, in order to perform the heat treatment at the diffusion temperature of 1280 to 1320 ° C. and 300 to 330 hours, the temperature is raised to a temperature range of 1000 ° C. to 1200 ° C. A method of manufacturing a reverse blocking MOS semiconductor device, comprising a diffusion temperature-time program for holding at a temperature within 25 hours or more. 3. The method of manufacturing a reverse blocking MOS semiconductor device according to claim 1, wherein the temperature maintained in the temperature range of 1000 ° C. or more and 1200 ° C. or less for the 25 hours or more is a constant temperature. 3. The method of manufacturing a reverse blocking MOS semiconductor device according to claim 1, wherein the thickness of the semiconductor substrate heat-treated in the first step is in the range of 100 [mu] m to 200 [mu] m. 3. The method of manufacturing a reverse blocking MOS semiconductor device according to claim 1, wherein a forward breakdown voltage and a reverse breakdown voltage are 1200 V or more. 2. The method of manufacturing a reverse blocking MOS semiconductor device according to claim 1, wherein the reverse blocking MOS semiconductor device is a reverse blocking IGBT.

Images