JP2014032673A - ダブルパターニング技術のための物理的決定性境界インターコネクト・フィーチャを生成するシステム及び方法 - Google Patents
ダブルパターニング技術のための物理的決定性境界インターコネクト・フィーチャを生成するシステム及び方法 Download PDFInfo
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- JP2014032673A JP2014032673A JP2013160071A JP2013160071A JP2014032673A JP 2014032673 A JP2014032673 A JP 2014032673A JP 2013160071 A JP2013160071 A JP 2013160071A JP 2013160071 A JP2013160071 A JP 2013160071A JP 2014032673 A JP2014032673 A JP 2014032673A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
【解決手段】一実施形態において、本システムは、(1)少なくとも1つのダブルパターニング・デザイン・ルールに基づいて、あるセルに対して決定性境界インターコネクト・フィーチャを生成するように構成された、決定性境界インターコネクト・フィーチャ生成器と、(2)上記決定性境界インターコネクト・フィーチャ生成器と関連付けられ、上記決定性境界インターコネクト・フィーチャ及び上記セルの他のフィーチャをそれらに対して配置するように構成されたセル配置ツール及びインターコネクト経路設定ツールとを具備している。
【選択図】図1
Description
Claims (10)
- ダブルパターニング技術のためのレイアウトを生成するシステムであって、
少なくとも1つのダブルパターニング・デザイン・ルールに基づいて、あるセルに対して決定性境界インターコネクト・フィーチャを生成するように構成された、決定性境界インターコネクト・フィーチャ生成器と、
前記決定性境界インターコネクト・フィーチャ生成器と関連付けられ、前記決定性境界インターコネクト・フィーチャ及び前記セルの他のフィーチャをそれらに対して配置するように構成されたセル配置ツール及びインターコネクト経路設定ツールと
を備えたシステム。 - 前記決定性境界インターコネクト・フィーチャ生成器は、決定性境界インターコネクト・フィーチャのファミリーを、同じ数量のインターコネクト層を使って生成するように更に構成される、請求項1に記載のシステム。
- 前記インターコネクト層は、ダブルパターニング層に限定される、請求項2に記載のシステム。
- 前記決定性境界インターコネクト・フィーチャは、集積回路の電力レールに接続されるように構成される、請求項1に記載のシステム。
- 前記決定性境界インターコネクト・フィーチャは、キャパシタで使用されるように構成される、請求項1に記載のシステム。
- 前記決定性境界インターコネクト・フィーチャは、側部セル決定性境界インターコネクト・フィーチャ及びU形状決定性境界インターコネクト・フィーチャのうちの一方であり、I/Oバッファ・セル及びI/Oサポートセルのうちの一方に対応する、請求項1に記載のシステム。
- 前記決定性境界インターコネクト・フィーチャは、フルリング決定性境界インターコネクト・フィーチャであり、コアブロック・セルに対応する、請求項1に記載のシステム。
- 前記決定性境界インターコネクトは、1つ又は複数の導電性材料で形成され、前記少なくとも1つのダブルパターニング・デザイン・ルールを使って画成されるとともにレイアウトされる物理的フィーチャである、請求項1に記載のシステム。
- ダブルパターニング技術のためのレイアウトを生成する方法であって、
少なくとも1つのダブルパターニング・デザイン・ルールに基づいて、あるセルに対して決定性境界インターコネクト・フィーチャを生成することと、
前記決定性境界インターコネクト・フィーチャ及び前記セルの他のフィーチャを、それらに対して配置することと
を含む方法。 - ミックスド・セル・ライブラリを使って回路を設計するとともに実装するためのプログラム命令を含むコンピュータ可読記録媒体であって、
コンピュータシステムの1つ又は複数のプロセッサによって前記プログラム命令が実行されると、前記1つ又は複数のプロセッサが、
少なくとも1つのダブルパターニング・デザイン・ルールに基づいて、あるセルに対して決定性境界インターコネクト・フィーチャを生成し、且つ
前記決定性境界インターコネクト・フィーチャ及び前記セルの他のフィーチャを、それらに対して配置する
コンピュータ可読記録媒体。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/564,159 US20140040847A1 (en) | 2012-08-01 | 2012-08-01 | System and method for generating physical deterministic boundary interconnect features for dual patterning technologies |
US13/564,159 | 2012-08-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014032673A true JP2014032673A (ja) | 2014-02-20 |
JP5694463B2 JP5694463B2 (ja) | 2015-04-01 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2013160071A Expired - Fee Related JP5694463B2 (ja) | 2012-08-01 | 2013-08-01 | ダブルパターニング技術のための物理的決定性境界インターコネクト・フィーチャを生成するシステム及び方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20140040847A1 (ja) |
EP (1) | EP2693351A1 (ja) |
JP (1) | JP5694463B2 (ja) |
KR (1) | KR101460448B1 (ja) |
CN (1) | CN103577634A (ja) |
TW (1) | TW201407397A (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140167815A1 (en) * | 2012-12-18 | 2014-06-19 | Broadcom Corporation | Area reconfigurable cells of a standard cell library |
US10296695B1 (en) | 2014-03-31 | 2019-05-21 | Cadence Design Systems, Inc. | Method, system, and computer program product for implementing track patterns for electronic circuit designs |
JP6373150B2 (ja) | 2014-06-16 | 2018-08-15 | 東京エレクトロン株式会社 | 基板処理システム及び基板処理方法 |
EP3200072B1 (en) * | 2015-03-24 | 2019-08-14 | Huawei Technologies Co., Ltd. | Method for updating terminal system, terminal and system |
US9659138B1 (en) | 2015-03-31 | 2017-05-23 | Cadence Design Systems, Inc. | Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques |
US9904756B1 (en) * | 2015-03-31 | 2018-02-27 | Cadence Design Systems, Inc. | Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs |
US9652579B1 (en) | 2015-03-31 | 2017-05-16 | Cadence Design Systems, Inc. | Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs |
EP3414642A4 (en) | 2016-02-08 | 2020-09-30 | Chaologix, Inc. | SIDE CHANNEL CONSCIOUS AUTOMATIC PLACE AND ROUTE |
US9996655B2 (en) | 2016-03-04 | 2018-06-12 | Sandisk Technologies Llc | Skeleton I/O generation for early ESD analysis |
KR102514044B1 (ko) * | 2016-03-22 | 2023-03-24 | 삼성전자주식회사 | 집적 회로 및 집적 회로의 설계 방법 |
US10572615B2 (en) * | 2017-04-28 | 2020-02-25 | Synopsys, Inc. | Placement and routing of cells using cell-level layout-dependent stress effects |
US10559558B2 (en) | 2017-09-29 | 2020-02-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pin modification for standard cells |
US10878165B2 (en) * | 2018-07-16 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for generating layout diagram including protruding pin cell regions and semiconductor device based on same |
US11449660B1 (en) * | 2020-03-10 | 2022-09-20 | Synopsys, Inc. | Method to perform secondary-PG aware buffering in IC design flow |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011164922A (ja) * | 2010-02-09 | 2011-08-25 | Renesas Electronics Corp | 半導体集積回路のレイアウト装置、及び半導体集積回路のレイアウト方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6898068B2 (en) * | 2003-09-24 | 2005-05-24 | Texas Instruments Incorporated | Dual mask capacitor for integrated circuits |
US7979829B2 (en) | 2007-02-20 | 2011-07-12 | Tela Innovations, Inc. | Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods |
US7888705B2 (en) | 2007-08-02 | 2011-02-15 | Tela Innovations, Inc. | Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same |
US8255837B2 (en) * | 2009-02-03 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for cell boundary isolation in double patterning design |
JP2010278189A (ja) | 2009-05-28 | 2010-12-09 | Renesas Electronics Corp | 半導体集積回路の設計方法及び設計システム |
US8219939B2 (en) * | 2009-11-12 | 2012-07-10 | Advanced Micro Devices, Inc. | Method of creating photolithographic masks for semiconductor device features with reduced design rule violations |
US8507957B2 (en) * | 2011-05-02 | 2013-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit layouts with power rails under bottom metal layer |
US8607172B2 (en) * | 2011-10-06 | 2013-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods of designing the same |
US10283437B2 (en) * | 2012-11-27 | 2019-05-07 | Advanced Micro Devices, Inc. | Metal density distribution for double pattern lithography |
-
2012
- 2012-08-01 US US13/564,159 patent/US20140040847A1/en not_active Abandoned
-
2013
- 2013-07-30 KR KR1020130090215A patent/KR101460448B1/ko not_active IP Right Cessation
- 2013-07-31 TW TW102127492A patent/TW201407397A/zh unknown
- 2013-08-01 JP JP2013160071A patent/JP5694463B2/ja not_active Expired - Fee Related
- 2013-08-01 CN CN201310494740.0A patent/CN103577634A/zh active Pending
- 2013-08-01 EP EP13178946.3A patent/EP2693351A1/en not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011164922A (ja) * | 2010-02-09 | 2011-08-25 | Renesas Electronics Corp | 半導体集積回路のレイアウト装置、及び半導体集積回路のレイアウト方法 |
Non-Patent Citations (1)
Title |
---|
JPN6014038124; Christopher Cork, et al.: 'Large-scale double-patterning compliant layouts for DP engine and design rule development.' Proc. of SPIE, [online] Vol.7275, 20090312, pp.72751K-1〜72751K-7, SPIE * |
Also Published As
Publication number | Publication date |
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CN103577634A (zh) | 2014-02-12 |
EP2693351A1 (en) | 2014-02-05 |
KR20140017438A (ko) | 2014-02-11 |
US20140040847A1 (en) | 2014-02-06 |
JP5694463B2 (ja) | 2015-04-01 |
TW201407397A (zh) | 2014-02-16 |
KR101460448B1 (ko) | 2014-11-10 |
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