JP2013528888A - 少なくとも1つのセキュアなメモリ領域と少なくとも1つの非セキュアなメモリ領域とを同時に提供するメモリモジュール - Google Patents
少なくとも1つのセキュアなメモリ領域と少なくとも1つの非セキュアなメモリ領域とを同時に提供するメモリモジュール Download PDFInfo
- Publication number
- JP2013528888A JP2013528888A JP2013506504A JP2013506504A JP2013528888A JP 2013528888 A JP2013528888 A JP 2013528888A JP 2013506504 A JP2013506504 A JP 2013506504A JP 2013506504 A JP2013506504 A JP 2013506504A JP 2013528888 A JP2013528888 A JP 2013528888A
- Authority
- JP
- Japan
- Prior art keywords
- memory module
- memory
- secure
- write
- microcontroller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 106
- 230000006870 function Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
- G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1056—Simplification
Abstract
【選択図】図2
Description
Claims (11)
- 少なくとも1つのセキュアなメモリ領域(163)と少なくとも1つの非セキュアなメモリ領域(133)とを同時に提供するメモリモジュール(230)であって、前記メモリモジュール(230)は、各前記メモリ領域(133、163)のための固有の書込み/読出し電子ユニット(132、162)と、複数の書込み/読出し電子ユニット(132、162)及び/又は複数のメモリ領域(133、163)のための少なくとも1つの共有のアナログ回路部(234)と、を備える、メモリモジュール(230)。
- 前記メモリモジュール(230)は、全ての書込み/読出し電子ユニット(132、162)及び/又は全てのメモリ領域(133、163)のための厳密に1つのアナログ回路部(234)を備える、請求項1に記載のメモリモジュール(230)。
- 前記アナログ回路部(234)は、前記書込み/読出し電子ユニット(132、162)及び/又は前記メモリ領域(133、163)に供給するための電圧供給回路を備える、請求項1又は2に記載のメモリモジュール(230)。
- 前記メモリモジュール(230)は、少なくとも2つの書込み/読出し電子ユニット(132、162)を接続するための少なくとも1つの共有のインタフェースユニット(231)を備える、請求項1〜3のいずれか1項に記載のメモリモジュール(230)。
- 前記メモリモジュール(230)は、全ての書込み/読出し電子ユニット(132、162)を接続するための厳密に1つのインタフェースユニット(231)を備える、請求項4に記載のメモリモジュール(230)。
- 前記メモリ領域(133、163)は、フラッシュメモリ領域として構成され、前記アナログ回路部(234)は、チャージポンプ及び/又は書込み/読出しアンプバンクを備える、請求項1〜5のいずれか1項に記載のメモリモジュール(230)。
- 請求項1〜6のいずれか1項に記載のメモリモジュール(230)を備えたマイクロコントローラ(200)。
- それぞれが前記メモリモジュール(230)と接続され、非セキュアなデータ又はセキュアなデータの書込み及び/又は読出しのために前記メモリモジュール(230)にアクセスする少なくとも1つの主CPU(110)及び少なくとも1つのセキュアなCPU(150)を備える、請求項7に記載のマイクロコントローラ(200)。
- 前記少なくとも1つの主CPU(110)及び前記少なくとも1つのセキュアなCPU(150)は、それぞれマイクロコントローラ内部のバス接続(120)を介して、前記メモリモジュール(230)の前記インタフェースユニット(231)と接続される、請求項8に記載のマイクロコントローラ(200)。
- 前記少なくとも1つのセキュアなCPU(150)は、追加的な識別接続(240)を介して、前記メモリモジュール(230)と追加的に接続される、請求項8又は9に記載のマイクロコントローラ(200)。
- 前記少なくとも1つのセキュアなCPU(150)は、前記識別接続(240)を介して、前記メモリモジュール(230)の前記インタフェースユニット(231)と接続される、請求項10に記載のマイクロコントローラ(200)。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102010028231A DE102010028231A1 (de) | 2010-04-27 | 2010-04-27 | Speichermodul zur gleichzeitigen Bereitstellung wenigstens eines sicheren und wenigstens eines unsicheren Speicherbereichs |
DE102010028231.6 | 2010-04-27 | ||
PCT/EP2010/065858 WO2011134541A1 (de) | 2010-04-27 | 2010-10-21 | Speichermodul zur gleichzeitigen bereitstellung wenigstens eines sicheren und wenigstens eines unsicheren speicherbereichs |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013528888A true JP2013528888A (ja) | 2013-07-11 |
JP5876473B2 JP5876473B2 (ja) | 2016-03-02 |
Family
ID=43640169
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013506504A Active JP5876473B2 (ja) | 2010-04-27 | 2010-10-21 | 少なくとも1つのセキュアなメモリ領域と少なくとも1つの非セキュアなメモリ領域とを同時に提供するメモリモジュール |
Country Status (7)
Country | Link |
---|---|
US (1) | US8976585B2 (ja) |
EP (2) | EP2564389B1 (ja) |
JP (1) | JP5876473B2 (ja) |
KR (1) | KR101789846B1 (ja) |
CN (1) | CN102844815B (ja) |
DE (1) | DE102010028231A1 (ja) |
WO (1) | WO2011134541A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102010063717A1 (de) | 2010-12-21 | 2012-06-21 | Bayerische Motoren Werke Aktiengesellschaft | Verfahren zum Verbinden mindestens zweier Bauteile gemäß dem Oberbegriff des Patentanspruches 1 |
CN103559460B (zh) * | 2013-11-06 | 2016-06-08 | 深圳国微技术有限公司 | 一种条件接收卡cam及数据处理方法 |
CN104778794B (zh) * | 2015-04-24 | 2017-06-20 | 华为技术有限公司 | 移动支付装置和方法 |
KR102429906B1 (ko) | 2015-10-13 | 2022-08-05 | 삼성전자주식회사 | 스토리지 장치, 상기 스토리지 장치와 통신하는 호스트 및 상기 스토리지 장치를 포함하는 전자 장치 |
FR3043228B1 (fr) * | 2015-11-03 | 2018-03-30 | Proton World International N.V. | Demarrage controle d'un circuit electronique |
CN107526693A (zh) * | 2017-08-11 | 2017-12-29 | 致象尔微电子科技(上海)有限公司 | 一种基于线性映射表的内存隔离方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001526819A (ja) * | 1997-03-31 | 2001-12-18 | アトメル・コーポレイション | プログラム読出/データ書込を同時に行なう能力を有する、結合されたプログラムおよびデータ不揮発性メモリ |
WO2002001368A2 (en) * | 2000-06-27 | 2002-01-03 | Intel Corporation | Embedded security device within a nonvolatile memory device |
JP2008310950A (ja) * | 2008-07-07 | 2008-12-25 | Renesas Technology Corp | 半導体処理装置及びicカード |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4744062A (en) * | 1985-04-23 | 1988-05-10 | Hitachi, Ltd. | Semiconductor integrated circuit with nonvolatile memory |
US5267218A (en) * | 1992-03-31 | 1993-11-30 | Intel Corporation | Nonvolatile memory card with a single power supply input |
US5293424A (en) * | 1992-10-14 | 1994-03-08 | Bull Hn Information Systems Inc. | Secure memory card |
US5491809A (en) * | 1993-01-05 | 1996-02-13 | Texas Instruments Incorporated | Smart erase algorithm with secure scheme for flash EPROMs |
KR970008188B1 (ko) * | 1993-04-08 | 1997-05-21 | 가부시끼가이샤 히다찌세이사꾸쇼 | 플래시메모리의 제어방법 및 그것을 사용한 정보처리장치 |
JPH0844628A (ja) * | 1994-08-03 | 1996-02-16 | Hitachi Ltd | 不揮発性メモリ、およびそれを用いたメモリカード、情報処理装置、ならびに不揮発性メモリのソフトウェアライトプロテクト制御方法 |
US5749088A (en) * | 1994-09-15 | 1998-05-05 | Intel Corporation | Memory card with erasure blocks and circuitry for selectively protecting the blocks from memory operations |
US6094724A (en) * | 1997-11-26 | 2000-07-25 | Atmel Corporation | Secure memory having anti-wire tapping |
US6122216A (en) * | 1998-12-09 | 2000-09-19 | Compaq Computer Corporation | Single package dual memory device |
US6510501B1 (en) * | 1999-05-11 | 2003-01-21 | National Semiconductor Corporation | Non-volatile memory read/write security protection feature selection through non-volatile memory bits |
EP1067557B1 (en) * | 1999-06-22 | 2005-02-02 | STMicroelectronics S.r.l. | Flash compatible EEPROM |
JP2002353960A (ja) * | 2001-05-30 | 2002-12-06 | Fujitsu Ltd | コード実行装置およびコード配布方法 |
KR100543442B1 (ko) * | 2002-09-06 | 2006-01-23 | 삼성전자주식회사 | 불 휘발성 반도체 메모리 장치의 메모리 블록들의 쓰기방지 영역을 설정하는 장치 |
JP4423206B2 (ja) * | 2002-11-18 | 2010-03-03 | エイアールエム リミテッド | 安全モードと非安全モードとを切り換えるプロセッサ |
JP2004265162A (ja) * | 2003-03-03 | 2004-09-24 | Renesas Technology Corp | 記憶装置およびアドレス管理方法 |
US7318171B2 (en) * | 2003-03-12 | 2008-01-08 | Intel Corporation | Policy-based response to system errors occurring during OS runtime |
KR100532442B1 (ko) * | 2003-06-17 | 2005-11-30 | 삼성전자주식회사 | 데이터 처리방법 및 데이터 처리장치 |
JP2005011151A (ja) * | 2003-06-20 | 2005-01-13 | Renesas Technology Corp | メモリカード |
JP4750719B2 (ja) * | 2004-11-26 | 2011-08-17 | パナソニック株式会社 | プロセッサ、セキュア処理システム |
US7412579B2 (en) * | 2004-12-30 | 2008-08-12 | O'connor Dennis M | Secure memory controller |
US8245000B2 (en) * | 2005-05-20 | 2012-08-14 | Stec, Inc. | System and method for managing security of a memory device |
WO2007004219A2 (en) * | 2005-07-04 | 2007-01-11 | Discretix Technologies Ltd. | System, device and method of verifying that a code is executed by a processor |
US20070150754A1 (en) * | 2005-12-22 | 2007-06-28 | Pauly Steven J | Secure software system and method for a printer |
US7765399B2 (en) * | 2006-02-22 | 2010-07-27 | Harris Corporation | Computer architecture for a handheld electronic device |
US8209550B2 (en) * | 2007-04-20 | 2012-06-26 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and apparatus for protecting SIMLock information in an electronic device |
US8738926B2 (en) * | 2008-01-10 | 2014-05-27 | Intel Mobile Communications GmbH | Data processing system, method for executing a cryptographic algorithm and method for preparing execution of a cryptographic algorithm |
JP2009289155A (ja) * | 2008-05-30 | 2009-12-10 | Panasonic Corp | 半導体記憶装置 |
US8370644B2 (en) * | 2008-05-30 | 2013-02-05 | Spansion Llc | Instant hardware erase for content reset and pseudo-random number generation |
JP4406463B2 (ja) | 2008-07-29 | 2010-01-27 | 東芝電子エンジニアリング株式会社 | カラーフィルタパネルの製造装置 |
US8910307B2 (en) * | 2012-05-10 | 2014-12-09 | Qualcomm Incorporated | Hardware enforced output security settings |
-
2010
- 2010-04-27 DE DE102010028231A patent/DE102010028231A1/de not_active Withdrawn
- 2010-10-21 US US13/642,922 patent/US8976585B2/en active Active
- 2010-10-21 WO PCT/EP2010/065858 patent/WO2011134541A1/de active Application Filing
- 2010-10-21 CN CN201080066463.8A patent/CN102844815B/zh active Active
- 2010-10-21 JP JP2013506504A patent/JP5876473B2/ja active Active
- 2010-10-21 KR KR1020127028010A patent/KR101789846B1/ko active IP Right Grant
- 2010-10-21 EP EP10774169.6A patent/EP2564389B1/de active Active
- 2010-10-21 EP EP13170311.8A patent/EP2637173B1/de active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001526819A (ja) * | 1997-03-31 | 2001-12-18 | アトメル・コーポレイション | プログラム読出/データ書込を同時に行なう能力を有する、結合されたプログラムおよびデータ不揮発性メモリ |
WO2002001368A2 (en) * | 2000-06-27 | 2002-01-03 | Intel Corporation | Embedded security device within a nonvolatile memory device |
JP2008310950A (ja) * | 2008-07-07 | 2008-12-25 | Renesas Technology Corp | 半導体処理装置及びicカード |
Also Published As
Publication number | Publication date |
---|---|
KR20130071425A (ko) | 2013-06-28 |
DE102010028231A1 (de) | 2011-10-27 |
EP2637173A3 (de) | 2017-08-23 |
WO2011134541A1 (de) | 2011-11-03 |
CN102844815A (zh) | 2012-12-26 |
EP2637173B1 (de) | 2020-12-09 |
EP2637173A2 (de) | 2013-09-11 |
JP5876473B2 (ja) | 2016-03-02 |
EP2564389A1 (de) | 2013-03-06 |
KR101789846B1 (ko) | 2017-10-25 |
EP2564389B1 (de) | 2015-06-17 |
US20130128664A1 (en) | 2013-05-23 |
US8976585B2 (en) | 2015-03-10 |
CN102844815B (zh) | 2015-11-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5876473B2 (ja) | 少なくとも1つのセキュアなメモリ領域と少なくとも1つの非セキュアなメモリ領域とを同時に提供するメモリモジュール | |
US8711628B2 (en) | Use of emerging non-volatile memory elements with flash memory | |
TWI391936B (zh) | 記憶體裝置架構以及操作 | |
US9361036B2 (en) | Correction of block errors for a system having non-volatile memory | |
TW200534280A (en) | Electronic memory with tri-level cell pair | |
CN109065096A (zh) | 具有错误校正逻辑的存储模块 | |
US11442666B2 (en) | Storage system and dual-write programming method with reverse order for secondary block | |
US9230692B2 (en) | Apparatuses and methods for mapping memory addresses to redundant memory | |
US9811477B2 (en) | Memory system and method for writing data to a block of an erased page | |
US20120159044A1 (en) | Non-volatile memory system with block protection function and block status control method | |
US11868635B2 (en) | Storage system with privacy-centric multi-partitions and method for use therewith | |
US10002265B2 (en) | Storage system and method for providing gray levels of read security | |
US9111649B2 (en) | Tamper resistant semiconductor device with access control | |
US20100165765A1 (en) | Protection register for a non-volatile memory | |
US9373377B2 (en) | Apparatuses, integrated circuits, and methods for testmode security systems | |
JP4467587B2 (ja) | プログラマブル論理デバイス | |
US9025355B2 (en) | Non-volatile memory device with clustered memory cells | |
US7499318B2 (en) | Nonvolatile semiconductor memory device having a management memory capable of suppressing bitline interference during a read operation | |
US7890721B2 (en) | Implementation of integrated status of a protection register word in a protection register array | |
US20090097301A1 (en) | Semiconductor storage apparatus and semiconductor integrated circuit incorporating the same | |
US7038932B1 (en) | High reliability area efficient non-volatile configuration data storage for ferroelectric memories | |
US20230359766A1 (en) | Data Storage Device and Method for Token Generation and Parameter Anonymization | |
RU2002101662A (ru) | Устройство защиты от несанкционированного доступа к информации, хранимой в персональной ЭВМ | |
JP2013077209A (ja) | プログラム、情報処理システム、情報処理装置、および情報処理方法 | |
KR20200067418A (ko) | 폐쇄 셀과 어드레스 디코더를 구비한 반도체 메모리 디바이스 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20131127 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140107 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140407 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140805 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20151111 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160121 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5876473 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |