JP2013514642A5 - - Google Patents

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JP2013514642A5
JP2013514642A5 JP2012543585A JP2012543585A JP2013514642A5 JP 2013514642 A5 JP2013514642 A5 JP 2013514642A5 JP 2012543585 A JP2012543585 A JP 2012543585A JP 2012543585 A JP2012543585 A JP 2012543585A JP 2013514642 A5 JP2013514642 A5 JP 2013514642A5
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semiconductor
sealing material
surface region
support
region
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JP5710638B2 (en
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Claims (15)

オプトエレクトロニクス素子において、
− 動作時に光を放射するかまたは受光するのに適した活性領域（３）を備えた少なくとも１つのオプトエレクトロニクス的に活性な無機半導体素子（１０）と、
− 少なくとも１つの表面領域（７）に、前記表面領域（７）を気密に覆う、原子間堆積によって被着したシーリング材料（６）とを有しており、
− ただし、前記表面領域（７）には、前記活性領域（３）の露出した側面が含まれている、
ことを特徴とする、オプトエレクトロニクス素子。 In optoelectronic devices,
At least one optoelectronically active inorganic semiconductor element (10) with an active region (3) suitable for emitting or receiving light during operation;
- at least one surface region (7), said covering the surface region (7) hermetically, and possess the adherend was the sealing material (6) by atomic deposition,
- However, in the surface region (7) includes a exposed side surface of the active region (3),
An optoelectronic device characterized by that. 請求項１に記載の素子において、
− 前記半導体素子（１０）は少なくとも１つの電気コンタクト層（４）を有しており、
− 前記シーリング材料（６）は、前記コンタクト層（４）または該コンタクト層（４）の部分領域を除いて前記半導体素子（１０）の露出したすべての表面を完全に覆う、
ことを特徴とする素子。 The device of claim 1, wherein
The semiconductor element (10) has at least one electrical contact layer (4);
The sealing material (6) completely covers all exposed surfaces of the semiconductor element (10) except for the contact layer (4) or a partial region of the contact layer (4);
An element characterized by that. 請求項１または２に記載の素子において、
− 前記半導体素子（１０）は、取り付け面（９）によって支持体（１１）に載置されている、
ことを特徴とする素子。 The element according to claim 1 or 2,
The semiconductor element (10) is mounted on a support (11) by means of a mounting surface (9),
An element characterized by that. 請求項３に記載の素子において、
− 前記シーリング材料（６）は前記半導体素子（１０）の露出したすべての表面を覆う、
ことを特徴とする素子。 The device according to claim 3, wherein
The sealing material (6) covers all exposed surfaces of the semiconductor element (10);
An element characterized by that. 請求項３または４に記載の素子において、
− 前記半導体素子（１０）は、少なくとも１つの電気コンタクト素子（２１）を介して前記支持体（１１）に電気接続されており、
− 前記シーリング材料（６）は当該電気コンタクト素子（２１）を覆っている
ことを特徴とする素子。 The element according to claim 3 or 4,
The semiconductor element (10) is electrically connected to the support (11) via at least one electrical contact element (21);
The element characterized in that the sealing material (6) covers the electrical contact element (21); 請求項３から５までのいずれか１項に記載の素子において、
− 前記シーリング材料（６）は、前記支持体（１１）の表面（１７）の少なくとも一部を覆っている、
ことを特徴とする素子。 The element according to any one of claims 3 to 5,
The sealing material (6) covers at least part of the surface (17) of the support (11);
An element characterized by that. 請求項６に記載の素子において、
− 前記シーリング材料（６）は、前記支持体（１１）の電気接続領域（２２）を除いて当該支持体（１１）および前記半導体素子（１０）の露出したすべての表面（７，１７）を完全に覆っている、
ことを特徴とする素子。 The device according to claim 6.
The sealing material (6) covers all exposed surfaces (7, 17) of the support (11) and the semiconductor element (10) except for the electrical connection region (22) of the support (11); Completely covering,
An element characterized by that. 請求項１から７までのいずれか１項に記載の素子において、
− 前記半導体素子（１０）および前記シーリング材料（６）は、少なくとも部分的にケーシング材料（２０）によって包囲されている、
ことを特徴とする素子。 In the element according to any one of claims 1 to 7,
The semiconductor element (10) and the sealing material (6) are at least partially surrounded by a casing material (20);
An element characterized by that. 請求項１から８までのいずれか１項に記載の素子において、
− 前記オプトエレクトロニクス素子は、複数の半導体素子（１０）を有しており、
− 前記シーリング材料（６）は、前記複数の半導体素子（１０）の各半導体素子の少なくとも１つの表面領域（７）にそれぞれ被着されている、
ことを特徴とする素子。 The element according to any one of claims 1 to 8,
The optoelectronic element comprises a plurality of semiconductor elements (10);
The sealing material (6) is deposited on at least one surface region (7) of each semiconductor element of the plurality of semiconductor elements (10),
An element characterized by that. 請求項１から９までのいずれか１項に記載の素子において、
− 前記半導体素子（１０）は、少なくとも１つの表面領域（７）に少なくとも１つのマイクロ開口部（１２）を有しており、
− 前記シーリング材料（６）によって当該マイクロ開口部（１２）がシーリングされる、
ことを特徴とする素子。 The element according to any one of claims 1 to 9,
The semiconductor element (10) has at least one micro-opening (12) in at least one surface region (7);
The micro-opening (12) is sealed by the sealing material (6);
An element characterized by that. 請求項１０に記載の素子において、
− 少なくとも１つのマイクロ開口部（１２）を有する前記表面領域（７）は、基板（１）の表面および／または半導体積層体（２）のエピタキシャル成長させた層の一部分である、
ことを特徴とする素子。 The device of claim 10, wherein
The surface region (7) with at least one micro-opening (12) is part of the surface of the substrate (1) and / or the epitaxially grown layer of the semiconductor stack (2);
An element characterized by that. 請求項１０または１１に記載の素子において、
− 前記半導体素子（１０）は、パッシベーション層（１３）および／または成長保護層（１４）を有しており、
− 少なくとも１つのマイクロ開口部（１２）を有する前記表面領域（７）は、前記パッシベーション層（１３）および／または前記成長保護層（１４）の表面の一部分である、
ことを特徴とする素子。 The element according to claim 10 or 11,
The semiconductor element (10) has a passivation layer (13) and / or a growth protection layer (14);
The surface region (7) with at least one micro-opening (12) is part of the surface of the passivation layer (13) and / or the growth protection layer (14);
An element characterized by that. 請求項１から１２までのいずれか１項に記載の素子において、
− 前記表面領域（７）は少なくとも部分的に影になっている、
ことを特徴とする素子。 The element according to any one of claims 1 to 12,
The surface region (7) is at least partially shaded;
An element characterized by that. 請求項１から１３までのいずれか１項に記載の、半導体素子（１０）を有するオプトエレクトロニクス素子を製造する方法において、
− 原子間堆積を用いて前記シーリング材料（６）を半導体層結合体（９０）に被着し、
− その後、当該半導体層結合体（９０）を複数の半導体素子（１０）に切り離す、
ことを特徴とする方法。 14. A method for producing an optoelectronic device comprising a semiconductor device (10) according to any one of claims 1-13.
-Applying said sealing material (6) to the semiconductor layer combination (90) using interatomic deposition;
-Thereafter, the semiconductor layer combination (90) is separated into a plurality of semiconductor elements (10),
A method characterized by that. 請求項１から１３までのいずれか１項に記載の、半導体素子（１０）を有するオプトエレクトロニクス素子を製造する方法において、
− 前記半導体素子（１０）を支持体（１１）に取り付け、
− その後、原子間堆積によって前記シーリング材料（６）をデポジットする、
ことを特徴とする方法。 14. A method for producing an optoelectronic device comprising a semiconductor device (10) according to any one of claims 1-13.
-Attaching said semiconductor element (10) to a support (11);
-Then depositing said sealing material (6) by interatomic deposition;
A method characterized by that.
JP2012543585A 2009-12-18 2010-11-30 Optoelectronic device and method of manufacturing optoelectronic device Active JP5710638B2 (en)

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DE102009058796.9 2009-12-18
DE102009058796A DE102009058796A1 (en) 2009-12-18 2009-12-18 Optoelectronic component and method for producing an optoelectronic component
PCT/EP2010/068548 WO2011073027A1 (en) 2009-12-18 2010-11-30 Optoelectronic component and method for producing an opto-electronic component

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JP (2) JP5710638B2 (en)
KR (1) KR20120114311A (en)
CN (1) CN102668140B (en)
DE (1) DE102009058796A1 (en)
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