JP2013232574A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which can inhibit stacking fault extension while suppressing decrease in effective cell area.SOLUTION: A silicon carbide semiconductor device comprises: a first conductivity type epitaxial layer 9 formed on a first conductivity type SiC substrate 8 having an off-angle; a plurality of second conductivity type well regions 10 which are formed on a surface of the epitaxial layer 9 and arranged at intervals; a first conductivity type source region 11 partially formed on a surface of each well region 10; a gate electrode 6 formed across on the well region 10 and on the epitaxial layer 9 via a gate insulation film 7; and a current limitation region 4 formed on the epitaxial layer 9 in a region sandwiched by the well regions 10 and along a step flow growth direction of the epitaxial layer 9.

Description

  The present invention relates to a semiconductor device using silicon carbide.

  Wide-gap semiconductor materials such as silicon carbide (SiC) have higher dielectric breakdown resistance than silicon (Si), and thus increase the impurity concentration of impurity regions formed in a semiconductor substrate as compared with a semiconductor substrate using Si. be able to. In the semiconductor substrate using SiC, since the impurity concentration in the impurity region can be increased, the electrical resistance of the semiconductor substrate can be reduced. This reduction in resistance can reduce loss in the switching operation of a power device using the semiconductor substrate.

  A semiconductor substrate using SiC has high thermal conductivity and excellent mechanical strength. Therefore, if a semiconductor substrate using SiC is used, it is expected that a small, low-loss and high-efficiency power device can be realized.

  From such a viewpoint, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) using an SiC substrate is manufactured.

  On the other hand, there is a well-known reliability problem that the forward voltage (Vf) shifts when a forward current continues to flow through a PIN diode structure using SiC as a semiconductor material.

  This is because, when minority carriers are injected into the PIN diode structure, they recombine with the majority carriers, and the recombination energy is expanded to stacking faults, which are surface defects, starting from basal plane dislocations existing in the SiC substrate. It is because it ends up. The stacking fault formed in this manner inhibits the flow of current in the PIN diode structure, so that the flowing current is reduced, the forward voltage is shifted, and reliability is deteriorated.

  It has been reported that this stacking fault starts from a basal plane dislocation and expands into a triangular shape or a wedge shape, and is orthogonal to the step flow growth direction (Non-Patent Document 1) which is the epitaxial growth direction. Extend longer in the direction you want.

  There is a report that such a forward voltage shift in the PIN diode structure also occurs in a MOSFET using a SiC substrate (Non-patent Document 2).

  This is because the MOSFET structure has a parasitic diode (body diode) between the source and drain, so that when a forward current flows through the body diode, the same deterioration as that of the PIN diode, that is, step flow growth in the epitaxial growth direction. This is because element characteristics (forward voltage) due to stacking faults extending in a direction perpendicular to the direction fluctuate and deteriorate reliability.

  Generally, a Schottky barrier diode having a low Vf is used as a freewheeling diode in a switching circuit. However, when a body diode of a SiC-MOSFET is used as a freewheeling diode, a MOSFET characteristic (forward voltage) shifts and reliability is improved. It becomes a big problem.

  With respect to this problem, Patent Document 1 discloses a structure that can suppress the expansion of stacking faults by embedding an insulating film in an epitaxial layer and separating the epitaxial layer into islands.

Japanese Patent No. 4100680

Semiconductor SiC technology and application (Nikkan Kogyo Shimbun) 35 IEEE ELECTRON DEVICE LETTERS Vol. No. 28 7, “A New Degradation Mechanism in High-Voltage SiC Power MOSFETs” JULY 2007

  However, the structure as in Patent Document 1 has a problem that the effective cell area is excessively reduced by the insulating film embedded in the epitaxial layer in a lattice shape, and the ON resistance of the device is increased.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a silicon carbide semiconductor device capable of suppressing the expansion of stacking faults while suppressing a decrease in effective cell area.

  A silicon carbide semiconductor device according to one embodiment of the present invention includes a first conductivity type silicon carbide semiconductor substrate having an off angle, a first conductivity type epitaxial layer formed on the silicon carbide semiconductor substrate, and the surface of the epitaxial layer. A plurality of well regions of a second conductivity type formed separately from each other, a source region of a first conductivity type partially formed on the surface of each well region, and a gate insulating film on the well region To a gate electrode formed on the epitaxial layer, a source electrode formed on the source region, a drain electrode formed on the back surface of the silicon carbide semiconductor substrate, and the well region in the epitaxial layer. And a current limiting region formed along the step flow growth direction of the epitaxial layer.

  According to the above aspect of the invention, the step flow growth of the epitaxial layer is provided by providing the current limiting region formed along the step flow growth direction of the epitaxial layer in the region sandwiched between the well regions in the epitaxial layer. Expansion of stacking faults in a direction perpendicular to the direction can be effectively suppressed. Therefore, fluctuations in element characteristics (forward voltage) caused by expansion of stacking faults can be suppressed. Further, the current limiting region can be easily formed, and the reduction of the effective cell area can be suppressed.

It is a top view which shows the silicon carbide semiconductor device regarding 1st Embodiment of this invention. It is sectional drawing which shows the silicon carbide semiconductor device regarding 1st Embodiment of this invention. It is sectional drawing which shows the silicon carbide semiconductor device regarding 2nd Embodiment of this invention. It is sectional drawing which shows the silicon carbide semiconductor device regarding 3rd Embodiment of this invention. It is a perspective view of the injection | pouring area | region regarding 3rd Embodiment of this invention. It is sectional drawing which shows the silicon carbide semiconductor device regarding 4th Embodiment of this invention. It is a perspective view of the injection | pouring area | region regarding 4th Embodiment of this invention. It is sectional drawing which shows the modification of the silicon carbide semiconductor device regarding 4th Embodiment of this invention. It is sectional drawing which shows the silicon carbide semiconductor device regarding 5th Embodiment of this invention. It is a general-view figure which shows the silicon carbide semiconductor device as a premise technique of this invention. It is sectional drawing which shows the silicon carbide semiconductor device as a premise technique of this invention. It is a figure which shows the layout of the silicon carbide semiconductor device as a premise technique of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  First, the configuration of a silicon carbide semiconductor device that is a prerequisite technology of the present invention will be described.

  FIG. 10 is an overview diagram showing a configuration of a silicon carbide semiconductor device as a prerequisite technology of the present invention.

  As shown in FIG. 10, the silicon carbide semiconductor device includes source pad 2 on first conductivity type SiC substrate 8 having an off angle, and gate pad formed by surrounding source pad 2 on SiC substrate 8. 1 is a MOSFET having 1. Although not shown, the back side of SiC substrate 8 is used as a drain terminal.

  FIG. 11 is a cross-sectional view showing a transistor array structure in which the source pad 2 shown in FIG. 10 is uniformly spread.

  As shown in FIG. 11, the transistor array structure has a first conductivity type epitaxial layer 9 (drift region) formed on the first conductivity type SiC substrate 8 having an off angle, and is separated from the surface of the epitaxial layer 9. The second conductivity type well region 10 is formed.

  A first conductivity type source region 11 is formed on the surface of each well region 10, and a second conductivity type well contact region for reducing contact resistance with a metal electrode (source electrode) is formed on the surface of the source region 11. 12 (high concentration) is partially formed in the central portion.

  In addition, the silicon carbide semiconductor device includes a gate insulating film 7 formed over (overlapping with) a source region 11 in each well region 10 and a source region 11 in another well region 10. A gate electrode 6 formed over the well region 10 and the other well region 10, an interlayer insulating film 5 formed covering the gate insulating film 7 and the gate electrode 6, and an interlayer insulating film 5 A source electrode 13 formed above and connected to the source region 11 in each contact hole is provided.

  An arrow 101 shown in FIG. 11 indicates the direction of current flowing through the body diode of the SiC-MOSFET. Current flows between a source that is an anode and a drain that is a cathode.

  FIG. 12 is a plan view of FIG. 11 as viewed from above, and shows an implantation region of a transistor cell. Unit transistor cells are evenly arranged and spread on the source pad.

  As shown in FIG. 12, the unit transistor cell is formed of a well region 10, a source region 11, and a well contact region 12. When viewed from above, the source region 11 surrounds the well contact region 12, and the source region 11 The region 10 is enclosed. Further, as shown in FIG. 12, the unit transistor cells are arranged spaced apart from each other on the surface of the epitaxial layer 9.

  Assuming the structure as described above, a silicon carbide semiconductor device capable of suppressing the extension of stacking faults in the direction orthogonal to the step flow growth direction of epitaxial layer 9 and also suppressing the decrease in effective cell area will be described below. The embodiment will be described.

<First Embodiment>
<Configuration>
FIG. 1 is a plan view showing a silicon carbide semiconductor device according to the first embodiment of the present invention. The same components as those in FIG. 10 are denoted by the same reference numerals, and detailed description thereof is omitted. A configuration different from that in FIG. 10 will be described below.

  The silicon carbide semiconductor device shown in FIG. 1 includes, in addition to the structure shown in FIG. 10, a current limiting region 4 formed along the illustrated step flow growth direction (the left-right direction in FIG. 1). The step flow growth direction shown in FIG. 1 is the step flow growth direction of the epitaxial layer 9. For example, in the case of a semiconductor substrate in which the (0001) plane of 4H type SiC having an off angle appears on the surface, The <11-20> direction, which is the step flow growth direction, is shown.

  Stacking fault extension is extended by the recombination energy of minority carriers and majority carriers (electron-hole pairs) when current flows through the PN diode structure. Therefore, the stacking fault expansion is suppressed by providing the current limiting region 4 which is a region that limits the flowing current value to a current value at which the stacking fault does not expand.

  FIG. 2 is a cross-sectional view showing the transistor array structure laid down on the source pad 2 shown in FIG. FIG. 2 is a view of the epitaxial layer 9 as viewed from the step flow growth direction. About the same structure as FIG. 11, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted. The configuration different from FIG. 11 will be described below.

  The silicon carbide semiconductor device shown in FIG. 2 includes a current limiting region 4 formed at a position sandwiched between the transistor cells. The current limiting region 4 includes an insulating layer 40 embedded in the epitaxial layer 9, and the current value is limited in this region.

  A gate insulating film 7 is formed above the region where the insulating layer 40 is formed, and an interlayer insulating film 5 is formed on the gate insulating film 7. The gate electrode 6 is not formed in the upper periphery of the insulating layer 40, that is, in the current limiting region 4.

  According to such a configuration, when the stacking fault due to the forward current stress expands in the direction perpendicular to the step flow growth direction, the progress of the stacking fault stops when the current limiting region 4 is reached, and the stacking fault further increases. Can be prevented from expanding.

  Thus, by forming the current limiting region 4 parallel to the step flow growth direction, it is possible to efficiently suppress the stacking fault from expanding in the direction orthogonal to the step flow growth direction. Therefore, the shift of the MOSFET characteristics (forward voltage) due to the expansion of stacking faults can be suppressed.

  In addition, it is possible to suppress a decrease in effective cell area and prevent an increase in the ON resistance of the device.

<Effect>
According to the embodiment of the present invention, a silicon carbide semiconductor device includes a first conductivity type SiC substrate 8 having an off angle, a first conductivity type epitaxial layer 9 formed on the SiC substrate 8, and an epitaxial layer 9. Via a plurality of second conductivity type well regions 10 formed on the surface and spaced apart from each other, a first conductivity type source region 11 partially formed on the surface of each well region 10, and the gate insulating film 7, Gate electrode 6 formed on well region 10 to epitaxial layer 9, source electrode 13 formed on source region 11, drain electrode formed on the back surface of SiC substrate 8, and well in epitaxial layer 9 The region sandwiched between the regions 10 includes a current limiting region 4 formed along the step flow growth direction of the epitaxial layer 9.

  According to such a silicon carbide semiconductor device, stacking faults in the direction perpendicular to the step flow growth direction of the epitaxial layer 9 are formed by forming the current limiting region 4 in parallel with the step flow growth direction of the epitaxial layer 9. Can be effectively suppressed. Therefore, fluctuations in element characteristics (forward voltage) caused by expansion of stacking faults can be suppressed.

  Further, by forming the current limiting region 4 in the step flow growth direction of the epitaxial layer 9, it is possible to suppress a reduction in effective cell area as compared with the case where the current limiting region is formed in a lattice shape, for example. Further, the off breakdown voltage of the device can be maintained.

  According to the embodiment relating to the present invention, the current limiting region 4 includes the insulating layer 40 embedded in the epitaxial layer 9.

  According to such a silicon carbide semiconductor device, the current flowing in current limiting region 4 can be more effectively limited.

Second Embodiment
<Configuration>
FIG. 3 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to this embodiment of the present invention. FIG. 3 is a view seen from the step flow growth direction of the epitaxial layer 9. The same components as those in FIG. 2 are denoted by the same reference numerals and detailed description thereof is omitted. The configuration different from FIG. 2 will be described below.

  The silicon carbide semiconductor device shown in FIG. 3 includes a current limiting region 4A formed at a position sandwiched between the transistor cells. The current limiting region 4A is a region including the epitaxial layer 9, the gate insulating film 7, and the interlayer insulating film 5 in a region where the gate electrode 6 is not formed. That is, the silicon carbide semiconductor device shown in FIG. 3 has a configuration in which insulating layer 40 in FIG. 2 is excluded.

  The current limiting region 4A includes an insulating region, and current flow is suppressed in the region. The current limiting region 4 </ b> A is formed along the step flow growth direction of the epitaxial layer 9.

  Here, the current limiting region 4 </ b> A may be configured by the epitaxial layer 9 and the interlayer insulating film 5. That is, the interlayer insulating film 5 may be directly formed on the epitaxial layer 9 in the current limiting region 4A.

<Effect>
According to the embodiment relating to the present invention, the current limiting region 4 </ b> A includes the gate insulating film 7 and the interlayer insulating film 5 as the insulating film formed on the epitaxial layer 9.

  According to such a silicon carbide semiconductor device, when the stacking fault due to the forward current stress expands in the direction perpendicular to the step flow growth direction, the progress of the stacking fault stops when it reaches the current limiting region 4A. As described above, expansion of the stacking fault can be suppressed.

<Third Embodiment>
<Configuration>
FIG. 4 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to this embodiment of the present invention. FIG. 4 is a view seen from the step flow growth direction of the epitaxial layer 9. About the same structure as FIG. 3, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted. A configuration different from FIG. 3 will be described below.

  The silicon carbide semiconductor device shown in FIG. 4 includes a current limiting region 4B formed at a position sandwiched between the transistor cells. The current limiting region 4B is a region including the epitaxial layer 9, the second conductivity type well region 10, the gate insulating film 7, and the interlayer insulating film 5 in a region where the gate electrode 6 is not formed.

  The current limiting region 4B includes an insulating region, and current flow is suppressed in the region. The current limiting region 4B is formed along the step flow growth direction of the epitaxial layer 9.

  Compared to the configuration shown in FIG. 3, the well region 10 is different in that the right and left ends of the surface of the epitaxial layer 9 in the current limiting region 4B are formed. In addition, the contact hole is formed in the portion where the source electrode 13 is in contact with the well region 10 formed in the left and right ends of the current limiting region 4B in the gate insulating film 7 and the interlayer insulating film 5 provided in the current limiting region 4B. Is different.

  Here, the current limiting region 4 </ b> B may be configured by the epitaxial layer 9, the well region 10, and the interlayer insulating film 5. That is, the interlayer insulating film 5 may be directly formed on the epitaxial layer 9 in the current limiting region 4B.

  FIG. 5 is a perspective view of FIG. 4 as viewed from above, and shows an implantation region of a transistor cell. As shown in FIG. 5, the current limiting region 4 </ b> B is formed along the step flow growth direction (e.g., <11-20> direction) of the epitaxial layer 9.

  As shown in FIG. 5, the unit transistor cells are arranged apart from each other, but are further separated by the current limiting region 4B.

<Effect>
According to the embodiment of the present invention, the current limiting region 4B includes the well region 10 in which the source region 11 is not formed on the surface thereof.

  According to such a silicon carbide semiconductor device, electric field relaxation in the current limiting region 4B can be performed by the well region 10, and expansion of stacking faults can be suppressed while improving the breakdown voltage.

<Fourth embodiment>
<Configuration>
FIG. 6 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to this embodiment of the present invention. FIG. 6 is a view seen from the step flow growth direction of the epitaxial layer 9. The same components as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted. The configuration different from FIG. 4 will be described below.

  The silicon carbide semiconductor device shown in FIG. 6 includes a current limiting region 4C formed at a position sandwiched between the transistor cells. The current limiting region 4C is a region realized by not injecting the source region 11 and the well contact region 12 in a part of the uniformly arranged transistor cells. That is, some transistor cells that are not implanted with the source region 11 and the well contact region 12 are arranged along the step flow growth direction of the epitaxial layer 9 while maintaining a uniform spacing in the transistor array structure.

  FIG. 7 is a perspective view of FIG. 6 as viewed from above, and shows an implantation region of a transistor cell. As shown in FIG. 7, the current limiting region 4 </ b> C is formed along the step flow growth direction (for example, <11-20> direction) of the epitaxial layer 9.

  The source region 11 and the well contact region 12 are not formed in the well region 10 in the current limiting region 4C. Further, the well regions 10 in these current limiting regions 4C are spaced apart from each other and arranged uniformly, as wells 10 outside the current limiting region 4C. In the case of this configuration, the well region 10 to be the current limiting region 4C and the well region 10 to be outside the current limiting region 4C can be formed in the same process, and the formation is easy.

  In normal operation, since the contact resistance between the well region 10 and the source electrode 13 is large, the flow of current in the current limiting region 4C is suppressed.

  The number of well regions 10 in the current limiting region 4C is not limited to the case shown in FIGS. 6 and 7 and may be as follows.

  FIG. 8 is a cross-sectional view showing a modification of the structure of the silicon carbide semiconductor device according to this embodiment.

  FIG. 8 is a view of the epitaxial layer 9 as viewed from the step flow growth direction. About the same structure as FIG. 6, the same code | symbol is attached | subjected and it abbreviate | omits about detailed description. A configuration different from that in FIG. 6 will be described below.

  The silicon carbide semiconductor device shown in FIG. 8 includes a current limiting region 4D formed at a position sandwiched between the transistor cells. The current limiting region 4D is a region that is realized by not implanting the source region 11 and the well contact region 12 for some of the uniformly arranged transistor cells. In contrast, the number of well regions 10 arranged in the direction orthogonal to the step flow growth direction is one. Even in this configuration, the well region 10 to be the current limiting region 4D and the well region 10 to be outside the current limiting region 4D can be formed in the same process, and the formation is easy.

<Effect>
According to the embodiment of the present invention, the well regions 10 provided in the current limiting region 4C and the current limiting region 4D are arranged at equal intervals together with the well regions 10 formed outside the current limiting region.

  According to such a silicon carbide semiconductor device, by maintaining a uniform arrangement interval of the transistor array structure, expansion of stacking faults can be suppressed while suppressing a decrease in breakdown voltage. Further, the well region 10 inside and outside the current limiting region can be formed in the same process, and the formation is easy.

<Fifth Embodiment>
<Configuration>
FIG. 9 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to this embodiment of the present invention. FIG. 9 is a view seen from the step flow growth direction of the epitaxial layer 9. About the same structure as FIG. 8, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted. A configuration different from that in FIG. 8 will be described below.

  The silicon carbide semiconductor device shown in FIG. 9 includes a current limiting region 4E formed at a position sandwiched between the transistor cells. The current limiting region 4E is a region realized by the well region 10A in which the source region 11 and the well contact region 12 are not implanted. Unlike the current limiting region 4D, the current limiting region 4E is a direction orthogonal to the step flow growth direction in the current limiting region 4E. The width of the well region 10A (left and right width in FIG. 9) is determined as follows.

  That is, the lateral width of the well region 10A is such that the current density at the interface 102 between the SiC substrate 8 and the epitaxial layer 9 under the current limiting region 4E is the current density at the interface 103 between the SiC substrate 8 and the epitaxial layer 9 under the transistor cell. It is adjusted to be 1/10 or less. Desirably, the current density at the interface 102 under the current limiting region 4E is adjusted to be 1/100 or less of the current density at the interface 103 under the transistor cell.

  The arrangement interval between the well region 10A and the well region 10 may be equal or different.

<Effect>
According to the embodiment of the present invention, the lateral width of the well region 10A provided in the current limiting region 4E in the direction orthogonal to the step flow growth direction is the interface between the SiC substrate 8 and the epitaxial layer 9 below the current limiting region 4E. Is adjusted to be 1/10 or less of the current density at the interface between the SiC substrate 8 and the epitaxial layer 9 under the well region 10 formed outside the current limiting region 4E.

  According to such a silicon carbide semiconductor device, the current density at the interface under the well region 10A is set to at least 1/10 or less of the current density at the interface under the well region 10 so that the current flowing in the current limiting region 4E is effective. Can be suppressed.

  If the current density under the current limiting region 4E is 1/10 or less of the current density under the transistor cell, the current value is limited sufficiently low in the current limiting region 4E. Large formation can be avoided.

  Furthermore, it is possible to suppress the stacking fault expansion while suppressing an increase in ON resistance, an increase in loss and the like of the device.

  In the embodiment of the present invention, the material of each component, material, conditions for implementation, and the like are also described, but these are examples and are not limited to those described.

  In the present invention, within the scope of the invention, the embodiments can be freely combined, arbitrary constituent elements of each embodiment can be modified, or arbitrary constituent elements can be omitted in each embodiment.

  1 gate pad, 2 source pad, 4, 4A, 4B, 4C, 4D, 4E current limiting region, 5 interlayer insulating film, 6 gate electrode, 7 gate insulating film, 8 SiC substrate, 9 epitaxial layer, 10, 10A well region , 11 source region, 12 well contact region, 13 source electrode, 40 insulating layer, 101 arrow, 102, 103 interface.

Claims (7)

A first conductivity type silicon carbide semiconductor substrate having an off angle;
An epitaxial layer of a first conductivity type formed on the silicon carbide semiconductor substrate;
A plurality of well regions of a second conductivity type formed on the epitaxial layer surface apart from each other;
A first conductivity type source region partially formed on the surface of each well region;
A gate electrode formed on the epitaxial layer from the well region via a gate insulating film;
A source electrode formed on the source region;
A drain electrode formed on the back surface of the silicon carbide semiconductor substrate;
In the region sandwiched between the well regions in the epitaxial layer, comprising a current limiting region formed along the step flow growth direction of the epitaxial layer,
Silicon carbide semiconductor device. The silicon carbide semiconductor substrate has a (0001) plane appearing on the substrate surface,
The current limiting region is formed along the <11-20> direction,
The silicon carbide semiconductor device according to claim 1. The current limiting region includes an insulating film formed on the epitaxial layer,
The silicon carbide semiconductor device according to claim 1 or 2. The current limiting region comprises an insulating layer embedded in the epitaxial layer,
The silicon carbide semiconductor device in any one of Claims 1-3. The current limiting region includes the well region in which the source region is not formed on the surface thereof,
The silicon carbide semiconductor device in any one of Claims 1-4. The well region provided in the current limiting region is arranged at regular intervals together with the well region formed outside the current limiting region,
The silicon carbide semiconductor device according to claim 5. The left-right width in the direction perpendicular to the step flow growth direction of the well region provided in the current limiting region,
The current density at the interface between the silicon carbide semiconductor substrate and the epitaxial layer under the current limiting region is at the interface between the silicon carbide semiconductor substrate and the epitaxial layer under the well region formed outside the current limiting region. It is adjusted to be 1/10 or less of the current density,
The silicon carbide semiconductor device according to claim 5 or 6.

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