JP2015002277A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device capable of suppressing characteristic shift by inhibiting stacking fault extension while suppressing high resistance of on-resistance in forward behavior.SOLUTION: On a surface part on one side in a thickness direction of a semiconductor substrate 21 having an off angle and made of silicon carbide, a drift layer 22 is formed which is made of a first conductivity type silicon carbide crystal. In the inside of the drift layer 22, a plurality of current limitation regions 10 are formed by a material having conductivity. The current limitation region 10 limits the current flowing through between a source electrode 26 and a drain electrode 28. Each current limitation region 10 is formed in a rectangular parallelepiped shape and arranged so as to have a longitudinal direction set to a direction perpendicular to an off direction of the drift layer 22.

Description

  The present invention relates to a silicon carbide semiconductor device.

  A wide gap semiconductor material such as silicon carbide has a higher dielectric breakdown resistance than silicon, so that it is possible to increase the impurity concentration of the substrate and reduce the resistance of the substrate as compared with the case of using a silicon material. By reducing the resistance of the substrate, loss in the switching operation of the power element can be reduced. In addition, wide gap semiconductor materials have higher thermal conductivity and superior mechanical strength compared to silicon, so they are expected as materials that can realize small, low-loss and high-efficiency power devices. Yes.

  However, in a silicon carbide semiconductor device using silicon carbide as a semiconductor material, there is a well-known reliability problem that the forward voltage shifts when a forward current continues to flow through the PN diode structure. This problem occurs as follows.

  When minority carriers are injected into the PN diode structure, the injected minority carriers recombine with the majority carriers. Due to the recombination energy generated at the time of recombination, defects existing in the silicon carbide substrate are expanded to stacking faults that are surface defects starting from basal plane dislocations. Since the stacking fault acts as a resistance and inhibits the flow of current, the flowing current decreases due to the stacking fault, causing the above-described forward voltage shift, and lowering the reliability.

  Examples of stacking faults have been reported to expand into a triangular shape (for example, see Non-Patent Document 1) or a wedge shape (for example, see Non-Patent Document 2) starting from a basal plane dislocation. It is easy to expand in the direction perpendicular to the step flow growth direction which is the epitaxial growth direction.

  There is a report that a forward voltage shift due to a stacking fault occurs in a similar manner even in a MOSFET using silicon carbide (hereinafter sometimes referred to as “silicon carbide MOSFET”) (for example, see Non-Patent Document 3). Since the MOSFET structure has a parasitic diode (hereinafter sometimes referred to as “body diode”) between the source and the drain, if a forward current flows through the body diode, the same deterioration as that of the PN diode is caused.

  As the freewheeling diode in the switching circuit, a Schottky barrier diode having a relatively low forward voltage is used. However, when the body diode of the silicon carbide MOSFET is used as the freewheeling diode, a MOSFET characteristic shift is caused and reliability is increased. It becomes a big problem on the top.

  A technique for solving this problem is disclosed in Patent Document 1, for example. In Patent Document 1, a lattice-shaped groove reaching the substrate is formed in the epitaxial layer in the device region, and the epitaxial layer is separated into islands by embedding an insulating film in the formed groove. A structure for suppressing expansion is disclosed.

  In addition, devices using silicon carbide have been developed for higher breakdown voltage, and the thickness of the epitaxial layer necessary for device operation has also increased. Since the epitaxial layer acts as a resistance component when energized, it is necessary to develop a structure capable of further reducing the resistance of the device itself, in addition to the aforementioned reliability problem.

Japanese Patent No. 4100680

Bin Chen, 6 others, “Electrical and Optical Properties of Stacking Faults in 4H-SiC Devices”, Journal of Electronic Materials (Journal of ELECTRONIC MATERIALS), 2010, Vol.39, No.6, p.684-687 S. Ha, 4 others, “Driving Force of Stacking-Fault Formation in SiC pin Diodes”, Physical Review Letters, 2004 Year, Volume 92, p.175504-1-175504-4 Anant Agarwal, “A New Degradation Mechanism in High-Voltage SiC Power MOSFETs”, IEEE ELECTRON DEVICE LETTERS, 2007 July, Vol. 28, No. 7, p. 587-589

  The technique disclosed in Patent Document 1 has a problem that a complicated process is required for embedding an insulating film, and it is difficult to accurately form a groove reaching the substrate in the process. In addition, the presence of the buried insulating film reduces the effective current-carrying area of the device region, and increases the on-resistance of the device.

  An object of the present invention is to provide a silicon carbide semiconductor device capable of suppressing expansion of stacking faults and suppressing a characteristic shift while suppressing an increase in on-resistance in a forward operation.

  A silicon carbide semiconductor device of the present invention has a semiconductor substrate made of silicon carbide having an off angle and a drift made of a silicon carbide crystal of a first conductivity type formed on a surface portion on one side in the thickness direction of the semiconductor substrate. A contact semiconductor region which is a second conductivity type semiconductor region formed on a part of a surface portion on one side in the thickness direction of the drift layer, and one side in the thickness direction of the drift layer in contact with the contact semiconductor region One side electrode provided on the surface portion of the semiconductor substrate, the other side electrode provided on the surface portion on the other side in the thickness direction of the semiconductor substrate, and the drift layer is formed of a conductive material, A plurality of current limiting regions that limit current flowing between the one side electrode and the other side electrode, and each of the current limiting regions is formed in a rectangular parallelepiped shape and is perpendicular to the off direction of the drift layer Direction It arrange | positions so that it may have a longitudinal direction.

  According to the silicon carbide semiconductor device of the present invention, the drift layer made of the first conductivity type silicon carbide crystal is formed on the surface portion on the one side in the thickness direction of the semiconductor substrate made of silicon carbide having an off angle. The A contact semiconductor region that is a semiconductor region of the second conductivity type is formed in a part of the surface portion on one side in the thickness direction of the drift layer. One side electrode is provided on the surface portion on one side in the thickness direction of the drift layer in contact with the contact semiconductor region. On the surface portion on the other side in the thickness direction of the semiconductor substrate, the other side electrode is provided.

  Inside the drift layer, a plurality of current limiting regions are formed of a conductive material. The current flowing between the one side electrode and the other side electrode is limited by the current limiting region. Each current limiting region is formed in a rectangular parallelepiped shape, and is arranged to have a longitudinal direction in a direction perpendicular to the off direction of the drift layer. Thus, the current limiting region is arranged in parallel to the surface on one side in the thickness direction of the silicon carbide crystal layers that are sequentially formed when the drift layer is formed. By disposing the current limiting region in this way, in the forward operation in which a forward current flows between the one side electrode and the other side electrode, the extension of stacking faults generated in the drift layer is suppressed, and the characteristic shift is suppressed. be able to. In addition, since the current limiting region is formed of a conductive material, it is possible to suppress an increase in on-resistance. Therefore, it is possible to realize a silicon carbide semiconductor device capable of suppressing an increase in stacking faults and suppressing a characteristic shift while suppressing an increase in on-resistance during forward operation.

1 is a plan view showing a configuration of a silicon carbide semiconductor device 1 according to a first embodiment of the present invention. It is sectional drawing which shows the structure of the silicon carbide semiconductor device 1 which is the 1st Embodiment of this invention. 3 is a perspective view showing how to extend stacking faults 14 in the drift layer 22. FIG. It is sectional drawing which shows the structure at the time of forming the current limiting area | region 10 with a 2nd conductivity type semiconductor. 5 is a graph showing an electric field distribution inside a drift layer 22 in the configuration shown in FIG. 4. It is sectional drawing which shows the structure of the current limiting area | region 10 in the 1st Embodiment of this invention. FIG. 6 is a cross-sectional view showing a configuration at a stage where the formation of the lower current limiting region 10 is completed. It is sectional drawing which shows the structure of the silicon carbide semiconductor device 2 which is the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the current limiting area | region 10 in the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the silicon carbide semiconductor device 3 which is the 3rd Embodiment of this invention. It is sectional drawing which shows the structure of the current limiting area | region 50 in the 3rd Embodiment of this invention.

<First Embodiment>
FIG. 1 is a plan view showing a configuration of a silicon carbide semiconductor device 1 according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a configuration of silicon carbide semiconductor device 1 according to the first embodiment of the present invention. 2 corresponds to a cross-sectional view taken along the section line AA of FIG. In FIG. 1, the description of the well region 23, the source region 24, the well contact region 25, the gate electrode 26, and the gate insulating film 27 shown in FIG. Silicon carbide semiconductor device 1 of the present embodiment is a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

  In the present embodiment, regarding the conductivity type of the impurity, the n-type is defined as “first conductivity type” and the p-type is defined as “second conductivity type”.

  Silicon carbide semiconductor device 1 includes current limiting region 10, source pad 11, gate wiring 12, gate pad 13, semiconductor substrate 21, drift layer 22, well region 23, source region 24, well contact region 25, gate electrode 26, and gate. An insulating film 27 and a drain electrode 28 are provided. The source pad 11 is electrically connected to the source region 24 through a contact hole (not shown). The source pad 11 corresponds to one side electrode. The well region 23 corresponds to a contact semiconductor region. The drain electrode 28 corresponds to the other side electrode.

  In the present embodiment, semiconductor substrate 21 is a semiconductor substrate (hereinafter sometimes referred to as a “silicon carbide substrate”) 21 made of silicon carbide of the first conductivity type, specifically, n-type. Silicon carbide substrate 21 has an off angle. Specifically, silicon carbide substrate 21 has an off angle of 1 ° to 12 °, and more preferably 4 ° to 8 ° with respect to the c-axis direction.

  Here, the “off angle” refers to the inclination angle of the Si surface having silicon (Si) atoms on the outermost surface with respect to the crystal axis direction in the silicon carbide (SiC) substrate 21. In the silicon carbide (SiC) substrate 21, it means that the Si surface is inclined with respect to the crystal axis direction. The off angle may not be limited to the above range. Silicon carbide substrate 21 only needs to have an off-angle, and the value of off-angle does not affect the effect of the present embodiment for any plane orientation.

  In the present embodiment, as an example, a silicon carbide semiconductor device using silicon carbide substrate 21 in which the (0001) plane Si plane is inclined at an off angle of 4 ° or more and 8 ° or less in the <11-20> direction. 1, a case where a silicon carbide MOSFET is manufactured will be described. Here, in the notation of the Miller index, “−” means a bar attached on the index immediately after that. For example, <11-20> indicates that a bar is added on “2”. In the Miller index notation, the Miller index surrounded by the symbol “<>” is a summary of equivalent directions, and the symbol “[]” is used to indicate a specific Miller index. Enclosed with

The drift layer 22 is provided on the surface portion on one side in the thickness direction of the semiconductor substrate 21. The drift layer 22 has first conductivity type, specifically, n-type conductivity. In the present embodiment, drift layer 22 is formed of an epitaxial crystal growth layer. The impurity concentration of the drift layer 22 is, for example, in the range of 1 × 10 ¹³ cm ^{−3 to} 1 × 10 ¹⁸ cm ⁻³ . The dimension in the thickness direction of drift layer 22 (hereinafter sometimes referred to as “thickness dimension”) is, for example, not less than 4 μm and not more than 200 μm. The impurity concentration and thickness dimension of the drift layer 22 are not limited to this.

  The current limiting region 10 is formed inside the drift layer 22. The current limiting region 10 is formed of a conductive material. In the present embodiment, current limiting region 10 is formed of a second conductivity type semiconductor material, specifically, p-type silicon carbide. The current limiting region 10 has a rectangular parallelepiped shape extending in a direction perpendicular to the thickness direction of the semiconductor substrate 21.

  In the present embodiment, a plurality of current limiting regions 10 are formed inside the drift layer 22. The plurality of current limiting regions 10 include two types of current limiting regions 10 having different distances from the surface on one side in the thickness direction of the drift layer 22. In the following description, when the two types of current limiting regions 10 are distinguished from each other, one of the two types of current limiting regions 10 that is closer to the semiconductor substrate 21 is referred to as a “lower current limiting region” and that is farther from the semiconductor substrate 21. Is referred to as the “upper current limiting region”. By providing the current limiting region 10, the bipolar current value can be reduced to a value that does not expand the stacking fault.

  As described above, the semiconductor substrate 21 in which the (0001) plane is inclined at an off angle of 4 ° or more and 8 ° or less in a direction perpendicular to the step flow growth direction that is the epitaxial growth direction, that is, the <11-20> direction. When silicon carbide MOSFET is produced as silicon carbide semiconductor device 1 using current, current limiting region 10 is formed such that its longitudinal direction is perpendicular to [11-20] direction. Here, the step flow growth direction refers to the direction of one-dimensional lateral growth from the atomic step. The step flow growth direction is the crystal growth direction and corresponds to the off direction of the drift layer 22.

  In FIG. 1, the [11-20] direction that is the off direction of the drift layer 22 is represented by an arrow B, and the longitudinal direction of the current limiting region 10 is represented by an arrow D. As shown in FIG. 1, current limiting region 10 is formed to have a longitudinal direction D in a direction perpendicular to off direction B in a plan view as viewed from one side in the thickness direction of silicon carbide semiconductor device 1.

  Silicon carbide semiconductor device 1 has a PN diode structure as a semiconductor switching element. In the forward operation of the semiconductor switching element, if a forward current continues to flow through the PN diode structure, a defect existing in the semiconductor substrate 21 may be expanded to the stacking fault 14 as shown in FIG.

  FIG. 3 is a perspective view showing how to extend the stacking fault 14 in the drift layer 22. In FIG. 3, the off angle is represented by the symbol “θ”, the [11-20] direction that is the off direction of the drift layer 22 is represented by arrow B, and the longitudinal direction of the current limiting region 10 is represented by arrow D. Further, the surface on one side in the thickness direction of the drift layer 22 is indicated by reference numeral “22a”, and the (0001) plane is indicated by reference numeral “32”.

  As shown in FIG. 3, the stacking fault 14 is expanded mainly by using a basal plane dislocation (abbreviation: BPD) 33 existing at the interface 31 between the semiconductor substrate 21 and the drift layer 22 as an expansion starting point C. , Extending in directions 34 and 35 perpendicular to the step flow growth direction.

  In the present embodiment, a current limiting region 10 is formed as shown in FIGS. Therefore, when the stacking fault 14 expands in a direction perpendicular to the step flow growth direction due to the forward current stress, the supply of recombination energy stops when the stacking fault 14 reaches the current limiting region 10, No further expansion.

  In this way, by disposing the current limiting region 10 so that its longitudinal direction is perpendicular to the step flow growth direction, expansion of the stacking fault 14 can be suppressed. As a result, a characteristic shift such as a forward voltage shift can be suppressed.

  As in the present embodiment, when the drift layer 22 is composed of the first conductivity type semiconductor, the current limiting region 10 may be composed of the second conductivity type semiconductor region. By configuring the current limiting region 10 with the second conductivity type semiconductor region, the electric field strength distribution inside the drift layer 22 can be controlled. In the present embodiment, since drift layer 22 is formed of an n-type semiconductor, current limiting region 10 may be formed of a p-type semiconductor region.

FIG. 4 is a cross-sectional view showing a configuration when the current limiting region 10 is formed of a second conductivity type semiconductor. In FIG. 4, a case where an n-type substrate is used as the silicon carbide substrate 21, the drift layer 22 is configured by an n-type semiconductor, and a p-type semiconductor region is used as the second conductivity type semiconductor region configuring the current limiting region 10. Show. The p-type semiconductor region constituting the current limiting region 10 is formed so that the concentration of the p-type impurity is higher than the concentration of the n-type impurity of the drift layer 22. Therefore, in FIG. 4, the conductivity of the current limiting region 10 is represented by “p ⁺ ”.

In FIG. 4, in order to facilitate understanding, description is omitted except for items necessary for explanation. In FIG. 4, the well region 23, the source region 24, and the well contact region 25 shown in FIG. 2 are collectively represented as a p ⁺ semiconductor region 30.

  FIG. 5 is a graph showing the electric field distribution inside the drift layer 22 in the configuration shown in FIG. The vertical axis in FIG. 5 indicates the electric field strength, and the horizontal axis indicates the depth from the surface of the drift layer 22.

  As can be seen from FIG. 5, by using the second conductivity type semiconductor region as the current limiting region 10, the slope of the change in the electric field strength with respect to the depth direction can be increased when an element with the same breakdown voltage is manufactured. it can. In other words, the impurity doping concentration during epitaxial growth can be increased. Therefore, in the present embodiment, it is possible to suppress the expansion of the stacking fault 14 and to suppress the increase in the on-resistance of the device, thereby realizing a low on-resistance.

  As described above, according to the present embodiment, when the stacking fault 14 expands in the direction perpendicular to the step flow growth direction due to the forward current stress, the recombination energy is reached when it reaches the current limiting region 10. The supply is stopped and the stacking fault 14 does not expand any more. The stacking fault 14 has an extension angle in the vertical direction in FIG. 2 determined by the off-angle of the semiconductor substrate 21. Therefore, it is preferable that the current limiting region 10 is disposed at a position where the extension of the stacking fault 14 can be stopped without omission. It is.

  A preferred configuration of the current limiting region 10 will be specifically described. FIG. 6 is a sectional view showing the configuration of the current limiting region 10 in the first embodiment of the present invention. FIG. 6 corresponds to a cross-sectional view taken along the section line AA of FIG. 1 described above. FIG. 6 is a simplified version of FIG. 2 described above, and is omitted except for information necessary for explanation in order to facilitate understanding.

  In FIG. 6, the off-angle of the semiconductor substrate 11 is represented by “α1”, the dimension in the width direction of the current limiting region 10 (hereinafter sometimes referred to as “width”) is represented by “w1”, and the height of the current limiting region 10 A dimension in the direction (hereinafter may be referred to as “height”) is represented by “h1”, and an interval between adjacent current limiting regions 10 (hereinafter also referred to as “restricted region spacing”) is represented by “w2”. Here, the width direction of the current limiting region 10 refers to one direction perpendicular to the thickness direction of the semiconductor substrate 21. Further, the height direction of the current limiting region 10 refers to one direction parallel to the thickness direction of the semiconductor substrate 21.

  The height h1 of the current limiting region 10 is preferably 0.2 μm or more and 4 μm or less, and more preferably 0.2 μm or more and 2 μm or less. In particular, as will be described later, when the current limiting region 10 is formed using buried epitaxial growth, the height h1 of the current limiting region 10 is preferably 0.2 μm or more and 4 μm or less as described above. More preferably, it is 2 μm or more and 2 μm or less.

  As shown in FIG. 3 described above, the stacking fault 14 extending from the basal plane transition 33 or the like existing at the interface 31 between the semiconductor substrate 21 and the drift layer 22 extends in the direction of the off angle θ. In the cross-sectional view of FIG. 6, the off angle θ is represented by “α1”, and the stacking fault 14 is represented by a thick line. Therefore, as shown in FIG. 6, in the cross-sectional configuration, the stacking fault 14 extends in the direction of the off angle α1.

The current limiting region 10 needs to be arranged at a location that prevents the stacking fault 14 from extending. Specifically, the current limiting region 10 is preferably configured such that the limiting region interval w2 and the height h1 satisfy the following formula (1).
tan α1 ≦ h1 / w2 (1)

The current limiting region 10 is more preferably configured such that the limiting region intervals w2 and h1 satisfy the following formula (1a).
tan α1 = h1 / w2 (1a)

  The ratio of the width w1 of the current limiting region 10 to the limiting region spacing w2, specifically, the ratio w1 / w2 of the width w1 of the current limiting region 10 to the limiting region spacing w2 is the above formula (1), more preferably the formula After satisfying (1a), the acceptor concentration of the second conductivity type semiconductor constituting the current limiting region 10 is configured to sufficiently compensate the donor concentration of the first conductivity type semiconductor constituting the surrounding drift layer 22. It is preferable. Specifically, the width w1 of the current limiting region 10 is preferably 1 μm or more and 5 μm or less, and the limiting region interval w2 is preferably 4 μm or more and 20 μm or less.

  Silicon carbide semiconductor device 1 of the present embodiment is manufactured as follows. First, a semiconductor substrate 21 made of silicon carbide of the first conductivity type, specifically, an n-type silicon carbide substrate is prepared. A first conductivity type drift layer 22 made of an epitaxial growth layer, specifically, a drift layer 22 made of n-type silicon carbide is formed on the surface portion on one side in the thickness direction of the semiconductor substrate 21. Drift layer 22 is formed by the following method, for example.

  FIG. 7 is a cross-sectional view showing a configuration at a stage where the formation of the lower current limiting region 10 is completed. A first conductivity type epitaxial growth layer (hereinafter sometimes referred to as a “lower epitaxial layer”) constituting the lower portion of the drift layer 22 on the surface portion on one side in the thickness direction of the semiconductor substrate 21, specifically an n-type lower portion Epitaxial layer 22A is epitaxially grown. The lower epitaxial layer 22A is grown to a position where the lower current limiting region 10 is formed. The thickness dimension of the lower epitaxial layer 22A is, for example, not less than 2 μm and not more than 100 μm.

  When the lower epitaxial layer 22A grows to a desired thickness dimension, the growth is interrupted there, and the semiconductor substrate 21 on which the lower epitaxial layer 22A is formed (hereinafter sometimes simply referred to as “substrate”) is once removed from the furnace.

  Next, an etching mask (not shown) such as a resist mask or an oxide film mask processed by photolithography is formed on the surface portion on one side in the thickness direction of the lower epitaxial layer 22A. The etching mask is formed so as to have an opening in a portion corresponding to the portion where the current limiting region 10 is formed.

  Using the formed etching mask, dry etching of the lower epitaxial layer 22A corresponding to the opening of the etching mask is performed, and a plurality of processed grooves 40 are formed on the surface portion on one side in the thickness direction of the lower epitaxial layer 22A. To do. Each processed groove 40 is formed to extend in one direction perpendicular to the thickness direction of the semiconductor substrate 21. The plurality of processed grooves 40 are formed side by side in a direction perpendicular to the extending direction of each processed groove 40 which is the one direction.

  Next, after a silicon oxide film is formed by thermally oxidizing the substrate, the formed silicon oxide film is removed with hydrofluoric acid. As a result, the surface-modified layer formed on the substrate is removed to obtain a clean surface. Thereafter, a second conductivity type epitaxial growth layer (hereinafter also referred to as “second conductivity type epitaxial layer”) is specifically formed on the surface portion on one side in the thickness direction of the lower epitaxial layer 22A in which the processed groove 40 is formed, specifically Grows a p-type epitaxial growth layer until the processing groove 44 is filled. This epitaxial growth may be referred to as “buried epitaxial growth” in the following description.

  Thereafter, chemical mechanical polishing (abbreviation: CMP) processing is performed on the second conductivity type epitaxial layer until the drift layer 22 whose growth has been interrupted, that is, the lower epitaxial layer 22A is exposed. As a result, the second conductivity type epitaxial layer remains in the processed groove 40 only. The second conductivity type epitaxial layer remaining in the processed groove 40 becomes the current limiting region 10, specifically, the lower current limiting region 10. In this way, the current limiting region 10 is formed.

As the impurity of the current limiting region 10, aluminum or boron is preferable. The current limiting region 10 may contain one of aluminum and boron, or may contain both. The impurity concentration of the current limiting region 10 exceeds the impurity concentration of the drift layer 22 and is set within a range of 1 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁹ cm ⁻³ .

  Next, a first conductivity type epitaxial growth layer (hereinafter referred to as an “internal epitaxial layer”) which becomes a part of the drift layer 22 on the surface portion on one side in the thickness direction of the lower epitaxial layer 22A where the lower current limiting region 10 is formed. Specifically, an n-type epitaxial growth layer is epitaxially grown. The internal epitaxial layer is grown by the same thickness dimension as that before the interruption of the growth of the lower epitaxial layer 22A, that is, by a thickness dimension of 2 μm or more and 100 μm or less.

  Next, in the same manner as when the lower current limiting region 10 is formed, the processing groove is formed in the internal epitaxial layer, the surface-modified layer is removed, the second conductivity type epitaxial layer is formed, and the CMP process is performed, so that the upper current limiting is performed. Region 10 is formed. Thereafter, a first conductivity type epitaxial growth layer, specifically, an n-type epitaxial growth layer constituting the upper portion of the drift layer 22 is grown until a desired thickness dimension is obtained. Thereby, the drift layer 22 is formed.

  Then, according to the design of the device structure, a normal MOSFET structure fabrication process is performed. Specifically, as shown in FIG. 2 described above, a second conductivity type, specifically, a p-type well region 23 is formed on a part of the surface portion on one side in the thickness direction of the drift layer 22 by ion implantation. Form. Further, a first conductivity type, specifically, an n-type source region 24 and a well contact region 25 are formed on a portion of the surface portion of one side in the thickness direction of the well region 23.

  Next, a gate insulating film 27 is formed of silicon dioxide or the like on the surface portion on one side in the thickness direction of the drift layer 22 in which the well region 23, the source region 24, and the well contact region 25 are formed. A gate electrode 26 is formed of aluminum or the like on the surface portion on one side in the thickness direction of the formed gate insulating film 27. Next, the drain electrode 28 is formed of aluminum or the like on the surface portion on the other side in the thickness direction of the semiconductor substrate 21. Thus, silicon carbide MOSFET is manufactured as silicon carbide semiconductor device 1.

  Silicon carbide semiconductor device 1 of the present embodiment may be manufactured as follows. First, in the same manner as shown in FIG. 7, the lower epitaxial layer 22A is grown on the surface portion on one side in the thickness direction of the semiconductor substrate 21 until the thickness becomes, for example, 2 μm or more and 100 μm or less. Is removed and once removed from the furnace.

  Next, a mask such as a resist mask or an oxide film mask processed by photolithography is formed on the epitaxial growth layer in which the growth is interrupted, that is, on the surface portion on one side in the thickness direction of the lower epitaxial layer 22A. Using the formed mask, impurity ions are implanted into a portion of the surface portion on one side in the thickness direction of the lower epitaxial layer 22A, specifically, the portion where the current limiting region 10 is to be formed, thereby limiting the current of the second conductivity type. Region 10, specifically, p-type current limiting region 10 is formed. The formed current limiting region 10 becomes the lower current limiting region 10.

At the time of ion implantation for forming the current limiting region 10, the semiconductor substrate 21 may not be actively heated, and may be heated at a temperature of 200 ° C. or higher and 800 ° C. or lower, for example. . Aluminum or boron is suitable as an impurity to be implanted into a portion to be the current limiting region 10 (hereinafter sometimes referred to as “implanted impurity”). The current limiting region 10 may contain one of aluminum and boron, or may contain both. The impurity concentration of the current limiting region 10 exceeds the impurity concentration of the drift layer 22 and is set within a range of 1 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁹ cm ⁻³ .

  Thereafter, heat treatment is performed in an inert gas atmosphere such as argon or nitrogen or in a vacuum at a temperature in the range of 1500 ° C. to 2200 ° C. for a time in the range of 0.5 minutes to 60 minutes. Thereby, the implanted impurities are electrically activated. This heat treatment is preferably performed in a state where the surface of the drift layer 22 or the surface of the drift layer 22 and the back surface of the semiconductor substrate 21 are covered with a film made of carbon. By doing so, it is possible to prevent the surface of the drift layer 22 from being roughened by etching with residual moisture and residual oxygen in the apparatus during the heat treatment.

  Next, similarly to the case shown in FIG. 7 described above, a silicon oxide film is formed by thermal oxidation and a silicon oxide film is removed by hydrofluoric acid, thereby removing the surface-modified layer and obtaining a clean surface. . Next, an epitaxial growth layer is further grown as an internal epitaxial layer on the surface portion on one side in the thickness direction of the lower epitaxial layer 22A where the lower current limiting region 10 is formed. The internal epitaxial layer is grown by the same thickness dimension as that before the interruption of the growth of the lower epitaxial layer 22A, that is, by a thickness dimension of 2 μm or more and 100 μm or less. Thereafter, a normal MOSFET structure fabrication process is performed according to the device structure design. Thereby, silicon carbide MOSFET is manufactured as silicon carbide semiconductor device 1.

  In the present embodiment, when a buried epitaxial growth method is used as a method for forming the current limiting region 10, a highly accurate design can be achieved as compared with the case where the current limiting region 10 is formed using ion implantation. When the buried epitaxial growth method is used, the current limiting region 10 is formed in the processing groove 40 processed by dry etching, and the height h1 of the current limiting region 10 is higher than that in the case of manufacturing using ion implantation. Can be increased. Therefore, the design margin can be increased.

  As described above, according to the present embodiment, a plurality of current limiting regions 10 are formed in the drift layer 22 from a conductive material. The current limiting region 10 limits the current flowing between the source electrode 26 and the drain electrode 28. Each current limiting region 10 is formed in a rectangular parallelepiped shape, and is arranged so as to have a longitudinal direction in a direction perpendicular to the step flow growth direction which is the off direction of drift layer 22. Thus, current limiting region 10 is formed with respect to the surface of one side in the thickness direction of the silicon carbide crystal layer that is sequentially formed when the drift layer is formed, that is, the growth layer that is sequentially formed during the epitaxial growth of drift layer 22. It will be arranged in parallel.

  By disposing the current limiting region 10 in this way, in the forward operation in which a forward current flows between the source electrode 26 and the drain electrode 28, the expansion of the stacking fault 14 generated in the drift layer 22 is suppressed, and the characteristic shift is performed. Can be suppressed. Further, since the current limiting region 10 is formed of a conductive material, it is possible to suppress an increase in on-resistance. Therefore, in forward operation, silicon carbide semiconductor device 1 capable of suppressing expansion of stacking fault 14 and suppressing characteristic shift while suppressing increase in on-resistance can be realized.

  Further, as described above, the current limiting region 10 is preferably configured such that the limiting region interval w2 and the height h1 satisfy the above-described formula (1). By configuring the current limiting region 10 in this way, all the expansion of the stacking faults 14 from the interface between the semiconductor substrate 21 and the drift layer 22 can be stopped at a place where the current can be stopped in the drift layer 22. Can be arranged. As a result, the forward voltage shift can be more reliably suppressed.

  In the present embodiment described above, as an example, the structure in which the growth of the drift layer 22 is interrupted twice and two current limiting regions are provided has been described. However, as shown in FIG. It is good also as a structure provided only for 3 layers or more. In any of the configurations, the expansion suppression of the stacking fault 14 such as the expansion suppression of the stacking fault 14 to the junction FET (hereinafter sometimes referred to as “JFET”) region can be realized as in the present embodiment. . Further, the configuration of the present embodiment can be applied to the semiconductor substrate 21 having any off-angle within a range not departing from the intention.

  In the present embodiment, the case where the first conductivity type is used as the conductivity type of the semiconductor substrate 21 has been described, but the second conductivity type may be used as the conductivity type of the semiconductor substrate 21.

<Second Embodiment>
FIG. 8 is a cross sectional view showing a configuration of silicon carbide semiconductor device 2 according to the second embodiment of the present invention. Since silicon carbide semiconductor device 2 of the present embodiment has a configuration similar to that of silicon carbide semiconductor device 1 of the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted. To do. FIG. 8 corresponds to a cross-sectional view taken along the section line AA shown in FIG.

  Silicon carbide semiconductor device 2 of the present embodiment has a configuration similar to that of silicon carbide semiconductor device 1 of the first embodiment except that current limiting region 10 has a different configuration. Silicon carbide semiconductor device 2 of the present embodiment is a silicon carbide MOSFET, similarly to silicon carbide semiconductor device 1 of the first embodiment.

  In the MOSFET, it is considered that the increase in on-resistance during forward operation due to the expansion of stacking faults is mainly caused by stacking faults extending to the JFET region. This is because the current concentrates in the JFET region when the forward current is supplied to the MOSFET.

  In the present embodiment, the current limiting region 10 is formed so as to selectively stop the stacking fault 14 extending from the interface between the semiconductor substrate 21 and the drift layer 22 to the JFET region. As a result, the reduction of the current conduction area in the epitaxial layer, that is, in the drift layer 22 due to the provision of the current limiting region 10 is minimized. Also, the drift layer 22 formed by forming the second conductivity type semiconductor region constituting the current limiting region 10 by narrowing the formation position of the current limiting region 10 to a place where the stacking fault 14 extending to the JFET region can be stopped. The damage to the is minimized.

  A preferred configuration of the current limiting region 10 in the present embodiment will be specifically described. FIG. 9 is a cross-sectional view showing the configuration of the current limiting region 10 in the second embodiment of the present invention. FIG. 9 corresponds to a cross-sectional view taken along the section line AA of FIG. FIG. 9 is a simplified version of FIG. 8 described above, and description is omitted except for information necessary for explanation in order to facilitate understanding. In the present embodiment, as shown in FIG. 8, two layers of current limiting regions 10 having different positions from the surface of the drift layer 22 are formed. However, in FIG. Only one current limiting region 10 of the layers is shown.

  In FIG. 9, the off angle of the semiconductor substrate 21 is represented by “α2”, the width of the current limiting region 10 is represented by “w1”, the height of the current limiting region 10 is represented by “h1”, and the adjacent current limiting regions are adjacent to each other. A limited area interval that is an interval between them is represented by “w2”.

  The height h1 of the current limiting region 10 is preferably 0.2 μm or more and 4 μm or less, and more preferably 0.2 μm or more and 2 μm or less. In particular, when the current limiting region 10 is formed by using the above-described buried epitaxial growth, the height h1 of the current limiting region 10 is preferably 0.2 μm or more and 4 μm or less as described above, and is 0.2 μm or more. More preferably, it is 2 μm or less.

  In FIG. 9, the cell pitch of the silicon carbide MOSFET 2 is represented by “a1”, the width of the JFET region 41 is represented by “b1”, and toward the paper surface of FIG. 9, from the upper end of the current limiting region 10 to the lower end of the JFET region 41. The width from the left end of the JFET region 41 to the left end of one current limiting region 10 is represented by “d1”.

  As shown in FIG. 9, the stacking fault 14 expanding from the basal plane transition existing at the interface between the semiconductor substrate 21 and the drift layer 22 extends in the direction defined by the off angle α2. A portion indicated by a broken line in the stacking fault 14 in FIG. 9 indicates a virtual extension line when the stacking fault 14 is expanded.

  The current limiting region 10 needs to be arranged at a location that prevents the stacking fault 14 from extending to the JFET region 41. Specifically, the current limiting region 10 has a width b1 of the JFET region 41, a width w1 of the current limiting region 10 and a height h1 of the current limiting region 10 satisfying the following expression (2a) and the current limiting The width c1 from the upper end of region 10 to the lower end of JFET region 41 and the width d1 from the left end of JFET region 41 to the left end of one current limiting region 10 satisfy the following expression (2b), and the cell pitch of silicon carbide MOSFET 2 It is preferable that a1 and the limited region interval w2 are configured to satisfy the following expression (2c).

tan α2 = h1 / (b1-w1) (2a)
d1 = c1 / tan α2 (2b)
a1 = w2 (2c)

  The current limiting region 10 satisfies the equations (2a) to (2c), and the acceptor concentration of the second conductivity type semiconductor constituting the current limiting region 10 is the first conductivity constituting the surrounding drift layer 22. It is preferable to be configured to sufficiently compensate the donor concentration of the type semiconductor. Specifically, the width w1 of the current limiting region 10 is preferably 1 μm or more and 5 μm or less, and the limiting region interval w2 is preferably 4 μm or more and 20 μm or less.

  Silicon carbide semiconductor device 2 of the present embodiment can be manufactured in the same manner as silicon carbide semiconductor device 1 of the first embodiment. Also in the present embodiment, when a buried epitaxial growth method is used as a method for forming the current limiting region 10, it is possible to design with higher accuracy than in the case of using ion implantation. When the buried epitaxial growth method is used, the current limiting region 10 is formed in the processing groove 40 processed by dry etching, and the height h1 of the current limiting region 10 is higher than that formed by ion implantation. Can be increased. Therefore, the design margin can be increased.

  As described above, according to the present embodiment, as in the first embodiment, in the forward operation, the increase of the on-resistance is suppressed and the expansion of the stacking fault 14 is suppressed, and the characteristics are reduced. Silicon carbide semiconductor device 2 capable of suppressing the shift can be realized.

  Further, as described above, the current limiting region 10 is preferably configured to satisfy the above-described formulas (2a) to (2c). By configuring the current limiting region 10 in this way, all of the stacking faults 14 extending from the interface between the semiconductor substrate 21 and the drift layer 22 to the JFET region 41 can be stopped in the drift layer 22. The current limiting region 50 can be arranged at the place. As a result, the forward voltage shift can be more reliably suppressed.

  In the present embodiment described above, as an example, the configuration in which the two-layer current limiting region 10 is provided as in the first embodiment has been described. However, as shown in FIG. Only a layer may be provided, or three or more layers may be provided. In any configuration, the extension of the stacking fault 14 to the JFET region 41 can be suppressed as in the present embodiment. The configuration of the present embodiment can also be applied to the semiconductor substrate 21 having other off-angles without departing from the intention.

<Third Embodiment>
FIG. 10 is a cross sectional view showing a configuration of silicon carbide semiconductor device 3 according to the third embodiment of the present invention. Since silicon carbide semiconductor device 3 of the present embodiment has a configuration similar to that of silicon carbide semiconductor device 1 of the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted. To do. 10 corresponds to a cross-sectional view taken along the section line AA shown in FIG.

  Silicon carbide semiconductor device 3 of the present embodiment has a configuration similar to that of silicon carbide semiconductor device 1 of the first embodiment except that current limiting region 50 has a different configuration. Silicon carbide semiconductor device 3 of the present embodiment is a silicon carbide MOSFET, similarly to silicon carbide semiconductor device 1 of the first embodiment.

  In the MOSFET, it is considered that the increase in on-resistance during forward operation due to the expansion of stacking faults is mainly caused by stacking faults extending to the JFET region. This is because the current concentrates in the JFET region when the forward current is supplied to the MOSFET.

  In the present embodiment, in order to suppress the extension of the stacking fault 14 from the interface between the semiconductor substrate 21 and the drift layer 22, the stacking fault 14 extends to the JFET region at the interface between the semiconductor substrate 21 and the drift layer 22. The current limiting region 50 is formed so as to include a basal plane transition or the like serving as a starting point. As a result, the expansion of the stacking fault 14 can be suppressed and the characteristic shift can be suppressed.

  The current limiting region 50 may be formed with the interface between the semiconductor substrate 21 and the drift layer 22 as a lower end, or may be formed so as to straddle the semiconductor substrate 21 and the drift layer 22.

  In the present embodiment, the current limiting region 50 is formed so as to selectively stop the stacking fault 14 extending from the interface between the semiconductor substrate 21 and the drift layer 22 to the JFET region. As a result, the reduction of the current carrying area in the epitaxial layer, that is, in the drift layer 22 due to the provision of the current limiting region 50 is minimized. Further, the drift layer 22 formed by forming the second conductivity type semiconductor region constituting the current limiting region 50 by narrowing the formation position of the current limiting region 50 to a place where the stacking fault 14 extending to the JFET region can be stopped. The damage to the is minimized.

  A preferred configuration of the current limiting region 50 in the present embodiment will be specifically described. FIG. 11 is a cross-sectional view showing the configuration of the current limiting region 50 in the third embodiment of the present invention. FIG. 11 corresponds to a cross-sectional view taken along the section line AA of FIG. FIG. 11 is a simplified version of FIG. 9 described above, and is omitted except for information necessary for explanation in order to facilitate understanding.

  In FIG. 11, the off angle of the semiconductor substrate 21 is represented by “α3”, the width of the current limiting region 50 is represented by “w11”, the height of the current limiting region 50 is represented by “h11”, and the adjacent current limiting regions 50 A restricted area interval which is an interval between each other is represented by “w12”.

  The height h11 of the current limiting region 50 is preferably 0.2 μm or more and 4 μm or less, and more preferably 0.2 μm or more and 2 μm or less. In particular, when the current limiting region 50 is formed using the above-described buried epitaxial growth, the height h11 of the current limiting region 50 is preferably 0.2 μm or more and 4 μm or less as described above, and is 0.2 μm or more. More preferably, it is 2 μm or less.

  In FIG. 11, the cell pitch of the silicon carbide MOSFET 3 is represented by “a12”, the width of the JFET region 41 is represented by “b11”, and from the top of the current limiting region 50 toward the bottom of the JFET region 41 toward the paper surface of FIG. The width from the left end of the JFET region 41 to the left end of one current limiting region 50 is represented by “d11”.

  As shown in FIG. 11, the stacking fault 14 expanding from the basal plane transition existing at the interface between the semiconductor substrate 21 and the drift layer 22 extends in the direction defined by the off angle α <b> 3. A portion indicated by a broken line in the stacking fault 14 in FIG. 11 indicates a virtual extension line when the stacking fault 14 is expanded.

  The current limiting region 50 needs to be disposed at a location that prevents the stacking fault 14 from extending to the JFET region 41. Specifically, in the current limiting region 50, the width b11 of the JFET region 41 and the width w11 of the current limiting region 50 satisfy the following expression (3a), and the lower end of the JFET region 41 extends from the upper end of the current limiting region 50. And the width d11 from the left end of the JFET region 41 to the left end of one current limiting region 50 satisfy the following expression (3b), and the cell pitch a11 and the limiting region interval w12 of the silicon carbide MOSFET 3 are: It is preferable to be configured to satisfy the following formula (3c).

b11 = w11 (3a)
d11 = c11 / tan α3 (3b)
a11 = w12 (3c)

  The height h11 of the current limiting region 50 can be set to an arbitrary value sufficient to suppress recombination of electrons and holes, and a range of 0.05 μm to 0.5 μm is preferable.

  The current limiting region 50 satisfies the above-described equations (3a) to (3c), and the acceptor concentration of the second conductivity type semiconductor constituting the current limiting region 50 is the first conductivity constituting the surrounding drift layer 22. It is preferable to be configured to sufficiently compensate the donor concentration of the type semiconductor. Specifically, the width w11 of the current limiting region 50 is preferably 1 μm or more and 5 μm or less, and the limiting region interval w12 is preferably 4 μm or more and 20 μm or less.

  Silicon carbide semiconductor device 3 of the present embodiment can be manufactured in the same manner as silicon carbide semiconductor device 1 of the first embodiment. Also in the present embodiment, when a buried epitaxial growth method is used as a method for forming the current limiting region 50, it is possible to design with higher accuracy than in the case of using ion implantation. In the case of using the buried epitaxial growth method, the current limiting region 50 is formed in the processed groove 40 processed by dry etching, and the height h11 of the current limiting region 50 is higher than that in the case of using ion implantation. Can be increased. Therefore, the design margin can be increased.

  As described above, according to the present embodiment, as in the first embodiment, in the forward operation, the increase of the on-resistance is suppressed and the expansion of the stacking fault 14 is suppressed, and the characteristics are reduced. Silicon carbide semiconductor device 3 capable of suppressing the shift can be realized.

  Further, as described above, the current limiting region 50 is preferably configured to satisfy the above-described formulas (3a) to (3c). By configuring the current limiting region 50 in this way, among the stacking faults 14 that extend from the interface between the semiconductor substrate 21 and the drift layer 22, the stacking fault 14 extends to the JFET region 41, but between the semiconductor substrate 21 and the drift layer 22. The current limiting region 50 can be arranged so as to include the expansion starting point at the interface. As a result, the forward voltage shift can be more reliably suppressed.

  In the present embodiment described above, as an example, as in the first embodiment, a configuration in which only one current limiting region 50 is provided near the interface between the semiconductor substrate 21 and the drift layer 22 has been described. The current limiting region 50 may be separately provided inside the drift layer 22 so that two layers are provided, or the number of layers of three or more layers may be provided. In any configuration, the extension of the stacking fault 14 to the JFET region 41 can be suppressed as in the present embodiment. The configuration of the present embodiment can also be applied to the semiconductor substrate 21 having other off-angles without departing from the intention.

  In each of the embodiments described above, current limiting regions 10 and 50 are configured by a second conductivity type semiconductor region formed of silicon carbide, specifically, a p-type semiconductor region. Thereby, the increase in the on-resistance of silicon carbide semiconductor devices 1 to 3 can be more reliably suppressed.

  The present invention can be freely combined with each embodiment within the scope of the invention. In addition, any component in each embodiment can be changed or omitted as appropriate. For example, silicon carbide semiconductor devices 1 to 3 according to the above-described embodiments are MOSFETs, but are not limited thereto.

  The configurations of silicon carbide semiconductor devices 1 to 3 according to the embodiments of the present invention include a PN diode, a PiN diode, an MPS (Merged PiN Schottky) diode, and an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor; abbreviated as IGBT). It is applicable to other devices that have a PN junction similar to a MOSFET and are concerned about expansion of stacking faults. By applying the configuration of each embodiment of the present invention, an effect similar to that of each embodiment can be obtained. For example, when applied to a PN diode, the contact region corresponds to a contact semiconductor region, the anode electrode corresponds to one side electrode, and the cathode electrode corresponds to the other side electrode.

  In each of the above-described embodiments, the case where the n-type is the “first conductivity type” and the p-type is the “second conductivity type” has been described with respect to the impurity conductivity type. Then, the p-type may be the “first conductivity type” and the n-type may be the “second conductivity type”.

1, 2, 3 Silicon carbide semiconductor device, 10, 50 Current limiting region, 11 source pad, 12 gate wiring, 13 gate pad, 14 stacking fault, 21 semiconductor substrate (silicon carbide substrate), 22 drift layer, 23 well region, 24 source region, 25 well contact region, 26 gate electrode, 27 gate insulating film, 28 drain electrode, 30 p ⁺ semiconductor region.

Claims (5)

A semiconductor substrate having an off angle and made of silicon carbide;
A drift layer made of a silicon carbide crystal of a first conductivity type formed on a surface portion on one side in the thickness direction of the semiconductor substrate;
A contact semiconductor region which is a semiconductor region of a second conductivity type formed in a part of the surface portion on one side in the thickness direction of the drift layer;
One side electrode provided on a surface portion on one side in the thickness direction of the drift layer in contact with the contact semiconductor region;
The other side electrode provided on the surface portion on the other side in the thickness direction of the semiconductor substrate;
A plurality of current limiting regions that are formed of a conductive material inside the drift layer and limit a current flowing between the one side electrode and the other side electrode,
Each said current limiting area | region is formed in a rectangular parallelepiped shape, and is arrange | positioned so that it may have a longitudinal direction in the direction perpendicular | vertical with respect to the off direction of the said drift layer. The material having conductivity is silicon carbide,
The silicon carbide semiconductor device according to claim 1, wherein the current limiting region is configured by a semiconductor region of a second conductivity type formed of the silicon carbide. When the off angle of the semiconductor substrate is α1, the limit region interval that is an interval between adjacent current limit regions is w2, and the height of each current limit region is h1, the current limit region is:
tan α1 ≦ h1 / w2 (1)
The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is configured to satisfy The off angle of the semiconductor substrate is α2, the width of the current limiting region is w1, the limiting region interval that is the interval between the adjacent current limiting regions is w2, and the height of each current limiting region is h1. The pitch between the contact semiconductor regions is a1, the interval between the contact semiconductor regions is b1, the interval between the contact semiconductor region and the current limiting region in the thickness direction is c1, and the pitch is viewed from the thickness direction. When the width of the region where the contact semiconductor region and the current limiting region overlap is defined as d1, the current limiting region is
tan α2 = h1 / (b1-w1) (2a)
d1 = c1 / tan α2 (2b)
a1 = w2 (2c)
The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is configured to satisfy The off-angle of the semiconductor substrate is α3, the width of the current limiting region is w11, the limiting region interval which is the interval between the adjacent current limiting regions is w12, the pitch of the contact semiconductor region is a11, The distance between the contact semiconductor regions is b11, the distance between the contact semiconductor region and the current limiting region in the thickness direction is c11, and the contact semiconductor region and the current limiting region overlap when viewed from the thickness direction. When the width of the region is d11, the current limiting region is
b11 = w11 (3a)
d11 = c11 / tan α3 (3b)
a11 = w12 (3c)
The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is configured to satisfy

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