JP5463725B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device using silicon carbide (SiC) as a semiconductor material and a method for manufacturing the same.

  Conventionally, a silicon carbide semiconductor material has a larger band gap than a silicon semiconductor material, so that it is known that a breakdown electric field strength is higher than that of a silicon semiconductor material. Here, the on-resistance is a resistance in a conductive state and is inversely proportional to the cube of the dielectric breakdown electric field strength. For this reason, for example, in a widely used silicon carbide semiconductor called 4H type, the on-resistance can be suppressed to 1/100 of that of a silicon semiconductor. Moreover, since a silicon carbide semiconductor has a large thermal conductivity, heat dissipation is easy. For these reasons, a next-generation low-loss power semiconductor device manufactured using a silicon carbide semiconductor is expected.

  In recent years, as the quality of silicon carbide wafers (semiconductor substrates) using silicon carbide semiconductor materials improves and the diameter increases, the metal oxide semiconductor field effect type greatly exceeds the characteristics of silicon semiconductor devices using silicon semiconductor materials. The development of transistors (MOSFETs), bipolar transistors, junction field effect transistors (JFETs), and the like is active. In particular, since the MOSFET is a voltage-driven element, the gate driving circuit can be suppressed at a low cost. Further, since the MOSFET is a majority carrier element having only electrons or holes and does not accumulate carriers in the conductive element, it does not require time for sweeping out the carriers out of the element at the time of turn-off. Therefore, for example, high-speed switching is possible as compared with a bipolar element in which both electrons and holes contribute to conduction.

Note that in this specification, a semiconductor having n or p means that electrons and holes are majority carriers, respectively. Further, “ ⁺ ” or “ ⁻ ” attached to n or p, such as n ⁺ or n ^−, is relatively higher or lower than the impurity concentration of the semiconductor to which they are not attached. Represents that.

FIG. 11 is a cross-sectional view showing a cross-sectional structure of a conventional general vertical MOSFET (DIMOSFET). As shown in FIG. 11, in the DIMOSFET, an n ⁻ type drift layer 22 is provided on an n ⁺ type drain layer 21, and a p type base layer is selectively formed on the surface layer of the n ⁻ type drift layer 22. 23 is provided. That is, the n ⁻ type drift layer 22 is sandwiched between the p type base layers 23 in the vicinity of the surface on the front surface side. An n ⁺ type source region 24 is provided on the surface layer of the p type base layer 23 apart from the n ⁻ type drift layer 22. Further, a gate electrode 27 is formed on the p − type base layer 23 between the n ⁻ type drift layer 22 and the n ⁺ type source region 24 and the n ⁻ type drift layer 22 via a gate oxide film 26. Is provided. Further, a source / base electrode 28 is provided on the front surface side, and a drain electrode 29 is provided on the back surface side.

In the DIMOSFET shown in FIG. 11, an accumulation layer resistance is generated when electrons move in the vicinity of the interface with the gate oxide film 26 in the n ⁻ -type drift layer 22. In addition, when current flows from the vicinity of the interface with the gate oxide film 26 in the n ⁻ type drift layer 22 toward the drain on the back surface side, the n ⁻ type drift layer 22 is sandwiched between the p type base layers 23. In addition, JFET resistance is likely to occur.

  In order to prevent the above-described accumulation layer resistance and JFET resistance from occurring, a MOSFET (UMOSFET) having a trench gate structure has been proposed. FIG. 12 is a sectional view showing a sectional structure of a conventional general UMOSFET. The UMOSFET is a MOSFET having a trench gate whose side wall is perpendicular to the main surface. FIG. 12 shows a cross-sectional structure of one cell pitch of UMOSFET.

As shown in FIG. 12, when manufacturing a UMOSFET, an n ⁻ type drift layer having a relatively high resistivity is formed on an n ⁺ type silicon carbide substrate having a relatively low resistivity to be an n ⁺ type drain layer 31. 32 and p-type base layer 33 are formed in this order by epitaxial SiC growth. Then, ion implantation is performed from the surface of the p-type base layer 33 to form the n ⁺ -type source region 34. A gate trench 35 that reaches the n ⁻ -type drift layer 32 is formed on such a silicon carbide wafer, and a gate electrode 37 is formed inside the gate trench 35 via a gate oxide film 36. Furthermore, the source / base electrode 38 is formed on the front surface side of the silicon carbide wafer 30 and the drain electrode 39 is formed on the back surface side, thereby completing the UMOSFET.

In the UMOSFET shown in FIG. 12, when the source / base electrode 38 is set to the ground potential in the off state and a sufficiently large negative bias is applied to the gate electrode 37, no current flows. The reason is that in the vicinity of the interface between the gate oxide film 36 and the region sandwiched between the n ⁺ -type source region 34 and the n ⁻ -type drift layer 32 of the p-type base layer 33, a hole-induced accumulation state occurs. This is because the path of electrons that are conductive carriers is blocked. Further, when a positive high voltage is applied to the drain electrode 39, the junction between the p-type base layer 33 and the n ⁻ -type drift layer 32 is in a reverse bias state, so that the depletion layer is in the p-type base layer 33 and the n ⁻ -type drift. The high voltage is maintained with the current spreading low and spreading into the layer 32.

Further, when a sufficiently large positive bias is applied to the gate electrode 37 in the on state, the region sandwiched between the n ⁺ type source region 34 and the n ⁻ type drift layer 32 of the p type base layer 33, the gate oxide film In the vicinity of the interface with 36, an inversion state in which electrons are induced occurs. Then, an inversion layer (not shown) in contact with the gate oxide film 36 of the source / base electrode 38, the n ⁺ -type source region 34, and the p-type base region 33, the n ⁻ -type drift layer 32, the n ⁺ -type drain layer 31, and the drain electrode Carriers flow in the order of 39.

  As described above, when the cell pitch is reduced in the DIMOSFET shown in FIG. 11, the JFET resistance appears from a predetermined cell pitch distance and the on-resistance increases, whereas in the UMOSFET shown in FIG. 12, the cell pitch is reduced. The on-resistance decreases monotonously. In particular, in a MOSFET having a withstand voltage of about 3 kV or less, since the MOS channel resistance cannot be ignored, the cell pitch must be reduced by miniaturization, and in this case, the UMOSFET is more suitable.

Here, as a method for reducing the size of the UMOSFET, for example, a source for widening the area where the source electrode is in contact with the n ⁺ -type source region and the p-type base region so as to intersect with the gate trench for embedding the gate electrode. A method of forming a trench has been proposed (see, for example, Patent Document 1 and Patent Document 2 below).

  FIG. 13 is a cross-sectional view of a main part showing the structure of a conventional UMOSFET and an explanatory diagram showing an electric field strength distribution. The electric field strength distribution is such that the vertical axis is aligned with the substrate thickness direction and the horizontal axis is the off-state electric field strength for the pn junction portion 41 and the MOS structure portion 42 indicated by the dashed frame, corresponding to the cross-sectional view of the main part. Represents.

As shown in FIG. 13, the electric field strength applied to the gate oxide film 36 (SiO ₂ film) at the bottom of the gate trench 35 becomes very large. The reason is that the relative dielectric constant of silicon carbide (for example, 9.7 in the case of 4H—SiC) and the relative dielectric constant of SiO ₂ (for example, 3.8) are different. Although not shown, the electric field strength applied to the oxide film at the corner of the gate trench 35 is further increased due to electric field concentration.

As shown in FIG. 13, in the UMOSFET, the peak of the electric field strength at the pn junction 41 between the p-type base region 33 and the n ⁻ -type drift layer 32 is the breakdown electric field strength of silicon carbide (for example, about 2 MV / cm), the gate oxide film 36 at the bottom of the gate trench 35 first reaches the dielectric breakdown electric field strength (for example, about 10 MV / cm) of the oxide film, causing dielectric breakdown at a voltage lower than the theoretical breakdown voltage. There is a problem that it ends up.

  Here, when a silicon semiconductor is used, the breakdown electric field strength of silicon is about 0.2 MV / cm, which is two orders of magnitude lower than the breakdown electric field strength of the oxide film (for example, about 10 MV / cm). , The dielectric breakdown first occurs at the pn junction 41. However, when silicon carbide (for example, 4H) is used, the breakdown electric field strength of silicon carbide is relatively large as 2 MV / cm, which is different by one digit from the breakdown electric field strength of the oxide film (for example, about 10 MV / cm). Therefore, the possibility that dielectric breakdown will occur first in the oxide film is higher than that in the silicon semiconductor.

As a method for solving such a problem, there is a method of forming a p ⁺ layer (electric field relaxation layer) at the bottom of the gate trench 35 (see, for example, Non-Patent Document 1). FIG. 14 is a cross-sectional view of a main part showing another structure of a conventional UMOSFET and an explanatory diagram showing an electric field strength distribution. As shown in FIG. 14, for example, when fabricating a UMOSFET, after forming the gate trench 35, ion implantation of aluminum (Al) or boron (B) is performed on the entire surface of the device, and the impurity concentration is 1 × 10 only at the bottom of the gate trench 35. A p ⁺ layer (electric field relaxation layer) 43 having a thickness of about ¹⁸ cm ⁻³ and a thickness of about 0.5 μm is formed.

  Therefore, in the UMOSFET described in Non-Patent Document 1, as shown in the electric field strength distribution in the cross section cut from the front surface side to the back surface side of the silicon carbide substrate of FIG. The electric field is absorbed by the electric field relaxation layer 43 at the bottom of the gate trench 35. For this reason, an electric field is not applied to the gate oxide film 36 at the bottom of the gate trench 35 and the dielectric breakdown of the gate oxide film 36 can be prevented, so that the breakdown voltage of the element is improved.

Japanese Patent No. 3647676 JP 2003-303967 A

Tan (J. Tan), two others, "High-Voltage Accumulation-Layer UMOSFET's in 4H-SiC", Eye Triple E Electron Device Letters ( IEEE ELECTRON DEVICE LETTERS), December 1998, Vol. 19, No. 12, p. 487-489

  However, in the above-described technique, ion implantation for forming the p-type base layer 33 is performed after forming the gate trench 35, thereby causing damage to the side wall of the gate trench 35 due to ion implantation. Accordingly, there is a problem that the state of the interface between the p-type base layer 33 and the gate oxide film 36 formed in the subsequent process becomes poor, and the MOS channel resistance increases.

Further, the JFET generated when the n ⁻ type drift layer 32 in contact with the lower end of the side wall of the gate trench 35 is sandwiched between the p ⁺ layer (electric field relaxation layer) 43 and the p type base layer 33 formed at the bottom of the gate trench 35. In order to reduce the resistance, it is conceivable to form an n-type current diffusion layer having a resistance lower than that of the n ⁻ -type drift layer 32 in a region in contact with the lower end of the side wall of the gate trench 35. Here, there is an optimum value for the impurity concentration and film thickness of the n-type current diffusion layer, and when the impurity concentration is lower than the optimum value or the film thickness is thin, there is a problem that JFET resistance occurs. Further, when the impurity concentration is higher than the optimum value or the film thickness is thick, the JFET resistance can be suppressed, but there is a problem that the withstand voltage at the time of reverse bias is lowered. The n-type current diffusion layer is formed by epitaxial growth, but there is a problem that it is difficult to control the impurity concentration and film thickness of the n-type current diffusion layer, and the yield decreases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing the same that can improve the withstand voltage and reduce the on-resistance in order to eliminate the above-described problems caused by the prior art.

In order to solve the above-described problems and achieve the object, a silicon carbide semiconductor device according to a first aspect of the present invention includes a first conductivity type provided on a front surface side of a first conductivity type silicon carbide semiconductor substrate. A drift layer; a first trench having a planar shape in a stripe shape; provided so as not to reach the first conductivity type silicon carbide semiconductor substrate from a surface of the first conductivity type drift layer; and the first trench. A second conductivity type base layer provided on the entire surface of the first conductivity type drift layer, a first conductivity type source layer provided on the entire surface of the second conductivity type base layer, and a planar shape intersecting the first trench a stripe-shaped such that, reached in the first conductivity type drift layer through the second conductive type base layer from the surface of the first conductivity type source layer, the bottom does not reach the bottom position of the first trench To form like Ri, a second trench that exposes the first conductive type source layer and the second conductivity type base layer on the side wall, inside the second trench, and a gate electrode embedded through the gate oxide film, the first A source electrode provided in contact with the one-conductivity-type source layer; an insulating film provided between the gate electrode and the source electrode; and a drain provided on the back side of the first-conductivity-type silicon carbide semiconductor substrate And an electrode.

  According to a second aspect of the present invention, the silicon carbide semiconductor device according to the first aspect of the present invention is provided on the surface layer of the first conductivity type drift layer so as to cover the bottom of the side wall of the first trench. The semiconductor device further includes a first conductivity type impurity layer having an impurity concentration higher than that of the first conductivity type drift layer.

According to a third aspect of the present invention, there is provided a method for manufacturing a silicon carbide semiconductor device comprising: a step of laminating a first conductivity type drift layer on the entire front surface side of a first conductivity type silicon carbide semiconductor substrate; Forming a first trench in a stripe shape so as not to reach the first conductivity type silicon carbide semiconductor substrate from the surface of the first conductivity type drift layer; and after forming the first trench, the first conductivity A step of laminating a second conductivity type base layer over the entire surface of the drift layer, a step of laminating a first conductivity type source layer over the entire surface of the second conductivity type base layer, and a planar shape intersecting the first trench. a stripe shape as the first from the surface of the conductive source layer through the second conductive type base layer reached on the first conductive type drift layer, so that the bottom does not reach the bottom position of the first trench To form into Ri, burying and forming a second trench that exposes the first conductive type source layer and the second conductivity type base layer on the side wall, inside the second trench, the gate electrode via a gate oxide film A step of forming an insulating film so as to cover the gate electrode, a step of forming a source electrode so as to be in contact with the first conductive type source layer, and a drain on the back side of the first conductive type silicon carbide semiconductor substrate. Forming an electrode.

According to a fourth aspect of the present invention, there is provided a method for manufacturing a silicon carbide semiconductor device, comprising: laminating a first conductivity type drift layer on the entire front surface side of a first conductivity type silicon carbide semiconductor substrate; A step of forming a first conductivity type impurity layer having an impurity concentration higher than that of the first conductivity type drift layer on the entire surface of the conductivity type drift layer, and a planar shape in a stripe shape, from the surface of the first conductivity type impurity layer; Forming a first trench so as not to reach the first conductivity type drift layer; and forming a second conductivity type base layer on the entire surface of the first conductivity type impurity layer after forming the first trench. A step of laminating the first conductivity type source layer on the entire surface of the second conductivity type base layer, and a stripe shape in which the planar shape intersects the first trench, from the surface of the first conductivity type source layer. The second conductivity type base layer It reached the first conductivity type drift layer through, by which the bottom portion is formed so as not to reach to the bottom position of the first trench, said first conductivity type source layer and the second conductivity type base layer on the side walls Forming a second trench to be exposed ; embedding a gate electrode in the second trench through a gate oxide film; forming an insulating film so as to cover the gate electrode; A step of forming a source electrode so as to be in contact with the conductive type source layer; and a step of forming a drain electrode on the back side of the first conductive type silicon carbide semiconductor substrate.

  According to the first or third aspect of the invention described above, since the second conductive type base layer and the first conductive type source layer are formed by epitaxial growth, the side wall of the second trench is not damaged by ion implantation. That is, the interface between the gate oxide film formed on the side wall of the second trench and the second conductivity type base layer is improved. For this reason, channel mobility improves and channel density improves.

  According to the invention of claim 2 or 4, the first conductivity type impurity layer having an impurity concentration higher than that of the first conductivity type drift layer is provided at the bottom of the side wall of the second trench. For this reason, the JFET resistance generated at the bottom of the side wall of the second trench can be reduced.

  According to the silicon carbide semiconductor device and the method for manufacturing the same according to the present invention, it is possible to improve the withstand voltage and reduce the on-resistance.

1 is a perspective sectional view showing a sectional structure of a semiconductor device according to a first embodiment; FIG. 6 is a perspective cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a perspective cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a perspective cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. 1 is a perspective sectional view showing a structure of a semiconductor device of Example 1. FIG. 6 is an explanatory diagram showing a relationship between on-resistance and a cell pitch of a first trench in Example 1 and Comparative Example 1. FIG. FIG. 6 is a perspective sectional view showing a sectional structure of a semiconductor device according to a second embodiment; 6 is a perspective cross-sectional view illustrating a structure of a semiconductor device of Example 2. FIG. FIG. 10 is an explanatory diagram showing the relationship between on-resistance and the cell pitch of the first trench in Example 2 and Comparative Example 2. FIG. 6 is a characteristic diagram showing a relationship between on-resistance and withstand voltage in Example 1, Example 2, Comparative Example 1, and Comparative Example 2. It is sectional drawing shown about the cross-section of the conventional common vertical MOSFET (DIMOSFET). It is sectional drawing which shows the cross-section of the conventional general UMOSFET. It is principal part sectional drawing which shows the structure of the conventional UMOSFET, and explanatory drawing which shows electric field strength distribution. It is principal part sectional drawing which shows the other structure of the conventional UMOSFET, and explanatory drawing which shows electric field strength distribution.

  Exemplary embodiments of a silicon carbide semiconductor device and a method for manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings. Note that, in the description of each embodiment and all the attached drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
First, the semiconductor device according to the first embodiment will be described. FIG. 1 is a perspective sectional view showing a sectional structure of the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment is manufactured using an epitaxial wafer. In the epitaxial wafer, an n-type buffer layer 2 and an n ⁻ -type drift layer 3 are laminated in this order on an n ⁺ -type 4H—SiC substrate 1.

The epitaxial wafer is provided with the first trench 4 so as to be perpendicular to the first main surface and have a planar shape in a stripe shape. A p-type base layer 5 and an n ⁺ -type source layer 6 are laminated in this order on the entire surface of the epitaxial wafer having the first trench 4. Therefore, the p-type base layer 5 and the n ⁺ -type source layer 6 are embedded in the first trench 4.

Further, the planar shape of the epitaxial wafer on which the p-type base layer 5 and the n ⁺ -type source layer 6 are stacked is perpendicular to the first main surface side, and the planar shape is striped. A gate trench (second trench) 7 is provided so as to cross 4. A gate electrode 9 is provided in the second trench 7 via a gate oxide film 8. A contact hole 16 reaching the p-type base layer 5 is selectively provided in the n ⁺ -type source layer 6 sandwiched between the first trenches 4 and the second trenches 7.

The interlayer insulating film 10 is provided so as to cover the gate electrode 9. Source electrode 11 is provided on interlayer insulating film 10 and n ⁺ -type source layer 6. Therefore, the source electrode 11 is electrically connected to the p-type base layer 5 through the contact hole 16. The drain electrode 12 is provided on the entire surface of the second main surface of the epitaxial wafer. Further, a metal 13 such as aluminum is sequentially laminated on the source electrode 11.

Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 2 to 4 are perspective sectional views sequentially illustrating the method for manufacturing the semiconductor device according to the first embodiment. First, as shown in FIG. 2, an n ⁺ -type 4H—SiC substrate 1 having a thickness of, for example, about 400 μm and an impurity concentration of, for example, 1 × 10 ¹⁸ cm ⁻³ is prepared. The n ⁺ -type 4H—SiC substrate 1 is a (0001) Si plane or a (000-1) C plane whose main surface has an off angle of 8 degrees in the <11-20> direction, for example.

The n ⁺ -type 4H—SiC substrate 1 has an n-type buffer layer 2 having a film thickness of, for example, 1 μm and an impurity concentration of, for example, 1 × 10 ¹⁷ cm ⁻³ , and a film thickness of, for example, 1 μm. An n ⁻ type drift layer 3 having a thickness of 9 × 10 ¹⁵ cm ⁻³ is formed in this order by epitaxial growth. Thereby, an epitaxial wafer is generated.

  Next, for example, by RIE (Reactive Ion Etching), the first trench 4 having a width of, for example, about 5 μm from the first main surface side of the epitaxial wafer so as to be perpendicular to the first main surface and have a planar shape in a stripe shape. Form. The first trench 4 is formed so that the side wall is in a direction parallel to, for example, the <11-20> direction.

Next, as shown in FIG. 3, the impurity concentration is, for example, 2 × 10 ¹⁷ cm ⁻³ and the film thickness is, for example, 2 μm over the entire first main surface side of the epitaxial wafer in which the first trench 4 is formed. A p-type base layer 5 is laminated, and an n ⁺ -type source layer 6 having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ and a film thickness of 2 μm, for example, is laminated on the p-type base layer 5. As a result, the p-type base layer 5 and the n ⁺ -type source layer 6 are buried in the first trench 4, and the surface on the first main surface side of the epitaxial wafer becomes flat.

In FIG. 3, the first trench 4 has a structure embedded with the p-type base layer 5 and the n ⁺ -type source layer 6. However, the present invention is not limited to this, and a void is formed in the n ⁺ -type source layer 6. May be formed. Further, the surface on the first main surface side of the epitaxial wafer may not be flat.

Next, as shown in FIG. 4, from the first main surface side of the epitaxial wafer on which the p-type base layer 5 and the n ⁺ -type source layer 6 are stacked, the planar shape is a stripe shape perpendicular to the first main surface, A second trench 7 having a width of, for example, about 1 μm is formed so as to intersect the first trench 4 on the surface of the first main surface. The second trench 7 is formed so that the side wall is in a direction parallel to, for example, the <1-100> direction. Note that the width of the second trench 7 is not limited to 1 μm, and it is better that the second trench 7 is miniaturized.

  Then, a gate oxide film 8, a gate electrode 9, an interlayer insulating film 10, a source electrode 11, a drain electrode 12, and a metal 13 are sequentially formed so as to form a normal trench gate type MOSFET, and the semiconductor device shown in FIG. Is completed.

Example 1
Next, the structure and characteristics of one cell of the semiconductor device according to the first embodiment (semiconductor device of Example 1) are verified. FIG. 5 is a perspective cross-sectional view illustrating the structure of the semiconductor device according to the first embodiment. FIG. 6 is an explanatory diagram showing the relationship between the on-resistance and the cell pitch of the first trench in Example 1 and Comparative Example 1. In FIG. 6, the vertical axis represents the on-resistance, and the horizontal axis represents the cell pitch L _TR4 of the first trench 4.

In the first embodiment, for example, the channel length L _CH shown in FIG. 5 is 2 μm, the cell pitch L _TR7 between the second trenches ₇ is 24 μm, the width L _NS of the buried portion of the source is 1 μm, and the width L of the second trench 7 _TR71 is 6 μm, the source depth D _NS is 2 μm, and the depth D _TR4 of the first trench 4 is 10 μm. In addition, the channel mobility when an electric field strength of 3 MV / cm is applied to the gate oxide film 8 is 40 cm ² / Vs.

In FIG. 6, Comparative Example 1 is a conventional semiconductor device in which a p ⁺ layer 43 is formed by ion implantation at the bottom of the gate trench 35 shown in FIG. In the semiconductor device of Comparative Example 1, the channel length L _CH , the cell pitch L _TR7 between the gate trenches 35, the width L _NS of the buried portion of the source, the width of the gate trench 35, and the source depth D _NS are the same as in Example 1. It is. In the semiconductor device of Comparative Example 1, the side wall of the gate trench 35 is damaged by ion implantation, and the channel mobility when an electric field strength of 3 MV / cm is applied to the gate oxide film 36 is 20 cm ² / Vs.

Here, if the cell pitch L _TR4 of the first trench 4 is relatively small, the MOS channel density is increased and the channel resistance is decreased, but the JFET resistance is increased. Further, when the cell pitch L _TR4 of the first trench 4 is relatively large, the JFET resistance decreases, but the channel resistance increases because the MOS channel density decreases.

As shown in FIG. 6, in Comparative Example 1, the on-resistance is 12.9 mΩcm ² without depending on the cell pitch L _TR4 of the first trench 4. In contrast, in Example 1, the on-resistance decreases as the cell pitch L _TR4 of the first trench 4 increases, and the on-resistance becomes 6.1 mΩcm ² when the cell pitch L _TR4 of the first trench 4 is 18 μm. The value of was shown.

Although illustration is omitted, in the first embodiment, when the cell pitch L _TR4 of the first trench 4 is increased, the electric field strength in the gate oxide film 8 increases and reaches the dielectric breakdown electric field strength. When the thickness of the gate oxide film 8 is 50 nm, the allowable electric field strength that can be applied to the gate oxide film 8 is 3 MV / cm, and the source electrode 11 and the gate electrode 9 are grounded, the drain electrode 12 When a positive bias is applied to the gate oxide film 8, the gate oxide film 8 does not reach the breakdown field strength until the cell pitch L _TR4 of the first trench 4 is about 19 μm. Therefore, if the cell pitch L _TR4 of the first trench 4 is smaller than 19 μm, the on-resistance of Example 1 is smaller than the on-resistance of Comparative Example 1.

  Furthermore, when the dimensions of each part of the cell are made smaller than the dimensions described above and the mobility is improved, the on-resistance decreases in both Example 1 and Comparative Example 1. However, when further miniaturization is performed, the on-resistance of Example 1 and Comparative Example 1 becomes the same, and the on-resistance of Comparative Example 1 becomes smaller than the on-resistance of Example 1.

Specifically, as shown in FIG. 5, the impurity concentration of the drift layer is 9 × 10 ¹⁵ cm ⁻³ , the depth D _TR4 of the first trench 4 is 10 μm, and the electric field strength of 3 MV / cm is applied to the gate oxide film 8. The channel pitch L _TR7 between the second trenches 7 (35) and the width L _TR71 of the second trenches 7 (35) are miniaturized while the channel mobility when applied is 40 cm ² / Vs. In this case, the cell pitch L _TR7 between second trenches 7 (35) 7 [mu] m, when the width L _TR71 of the second trench 7 (35) is the cell pitch L _TR4 of 1.75μm and the first trench 4 to about 19 .mu.m, performed The on-resistance of Example 1 is 4.3 mΩcm ² , which is approximately the same as the on-resistance (4.5 mΩcm ² ) of Comparative Example 1. Accordingly, the second trench 7 (35) cell pitch L _TR7 between the 7μm or more, if the width L _TR71 of the second trench 7 (35) is 1.75μm or more, the on-resistance of Example 1 is Comparative Example 1 On Less than resistance.

According to the first embodiment, since the p-type base layer 5 and the n ⁺ -type source layer 6 exposed on the side wall of the second trench 7 are formed by epitaxial growth, the side wall of the second trench 7 is damaged by ion implantation. Absent. Therefore, the interface between the gate oxide film 8 formed on the side wall of the second trench 7 and the p-type base layer 5 becomes good, the channel mobility is improved, and the channel density is increased. For this reason, the on-resistance can be reduced while maintaining the withstand voltage. As described above, the characteristic indicating the relationship between the withstand voltage and the on-resistance can be made extremely close to the 4H-SiC unipolar limit.

(Embodiment 2)
Next, a semiconductor device according to the second embodiment will be described. FIG. 7 is a perspective sectional view showing a sectional structure of the semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment, n ^- n on the type drift layer 3 ^- impurity concentration than -type drift layer 3 is high n ⁺ -type layer 17 is fabricated by using the laminated epitaxial wafer. The n ⁺ -type layer 17 is, for example, shallower than the first trench 4 and deeper than the second trench 7 from the first main surface side. Other configurations are the same as those in the first embodiment, and thus description thereof is omitted.

Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. In the semiconductor device according to the second embodiment, first, similarly to the semiconductor device according to the first embodiment, the film thickness is, for example, 1 μm and the impurity concentration is, for example, 1 × 10 ¹⁷ on the n ⁺ -type 4H—SiC substrate 1. cm ^-3 and the n-type buffer layer 2 is a film thickness of, for example, 1 [mu] m, n is the impurity concentration of, for example 9 × 10 ¹⁵ cm ^{-3 -} -type drift layer 3 is formed by epitaxial growth in this order. Further, an n ⁺ type layer 17 having an impurity concentration of, for example, 1 × 10 ¹⁷ cm ⁻³ is deposited on the n ⁻ type drift layer 3. Thereby, an epitaxial wafer is generated.

Next, for example, by RIE, the width is, for example, about 5 μm from the first main surface side of the epitaxial wafer on which the n ⁺ -type layer 17 is deposited so that the planar shape is a stripe shape perpendicular to the first main surface. A first trench 4 is formed. Since the subsequent processing is the same as that of the first embodiment, description thereof is omitted.

(Example 2)
Next, the structure and characteristics of one cell (semiconductor device of Example 2) of the semiconductor device according to the second embodiment will be verified. FIG. 8 is a perspective sectional view showing the structure of the semiconductor device according to the second embodiment. FIG. 9 is an explanatory diagram showing the relationship between the on-resistance and the cell pitch of the first trench in Example 2 and Comparative Example 2. In FIG. 9, the vertical axis represents on-resistance, and the horizontal axis represents the cell pitch L _TR4 of the first trench 4.

In Example 2, the dimensions of each part are set so that the on-resistance of Example 1 is smaller than the on-resistance of Comparative Example 1 and the difference between the on-resistance of Example 1 and Comparative Example 1 is the smallest. . That is, in the semiconductor device of Example 2, the channel length L _CH shown in FIG. 8 is 2 μm, the cell pitch L _TR7 between the second trenches ₇ is 7 μm, the width L _NS of the buried portion of the source is 1 μm, width L _TR71 is 1.75 [mu] m, the source depth D _NS is 2 [mu] m, the depth D _TR4 of the first trench 4 is 10 [mu] m. In addition, the channel mobility when an electric field strength of 3 MV / cm is applied to the gate oxide film 8 is 40 cm ² / Vs.

In FIG. 8, Comparative Example 2 has the same structure and the same channel mobility as Comparative Example 1, and includes channel length L _CH , cell pitch L _TR7 between gate trenches 35, and width L _NS of the buried portion of the source. The width of the gate trench 35 and the source depth D _NS are the same as in the second embodiment.

As shown in FIG. 9, the on-resistance in the comparative example 2 does not depend on the cell pitch L _TR4 of the first trench 4, but the on-resistance in the example 2 depends on the cell pitch L _TR4 of the first trench 4. In the second embodiment, the gate oxide film 8 does not reach the dielectric breakdown electric field strength until the cell pitch L _TR4 of the first trench 4 is about 10 μm. Therefore, the minimum value of the on-resistance of Example 2 was 3.3 mΩcm ² , which was lower than that of Example 1. This is because the JFET resistance can be almost ignored in the n ⁺ type layer 17 portion.

Furthermore, the dimensions of each part of the cell are made finer than the dimensions described above, and the mobility is improved. That is, the cell pitch L _TR7 between the second trenches 7 (35) and the width L _TR71 of the second trench 7 (35) are miniaturized while the depth D _TR4 of the first trench 4 is set to 10 μm. In this case, the cell pitch L _TR7 between second trenches 7 (35) is 4.5 [mu] m, when the width L _TR71 of the second trench 7 (35) is the cell pitch L _TR4 of 1.13μm and the first trench 4 to about 10μm The on-resistance of Example 2 is 3.1 mΩcm ² , which is approximately the same as the on-resistance of Comparative Example 2 (3.2 mΩcm ² ). Accordingly, the second trench 7 (35) cell pitch L _TR7 between the 4.5μm or more, if the width L _TR71 of the second trench 7 (35) is 1.13μm or more, compared on-resistance of Example 2 Example 2 It becomes smaller than the on-resistance.

  FIG. 10 is a characteristic diagram showing the relationship between the on-resistance and the withstand voltage in Example 1, Example 2, Comparative Example 1, and Comparative Example 2. As shown in FIG. 10, with the configuration of the second embodiment, the relationship between the on-resistance and the withstand voltage can be made closer to the unipolar limit of 4H—SiC.

According to the second embodiment, since the n ⁺ type layer 17 having an impurity concentration higher than that of the n ⁻ type drift layer 3 is formed at the bottom of the side wall of the second trench 7, the JFET resistance can be suppressed. Therefore, the on-resistance can be reduced as compared with the first embodiment while maintaining the withstand voltage.

  In the present embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is not limited to this. For example, the second conductivity type may be p-type and the first conductivity type may be n-type.

  As described above, the silicon carbide semiconductor device according to the present invention is useful for silicon carbide semiconductor devices such as MOSFETs and IGBTs having a trench gate structure, and is particularly suitable for MOS power silicon carbide semiconductor devices.

1 n ⁺ type 4H—SiC substrate 2 n type buffer layer 3 n ⁻ type drift layer 4 first trench 5 p type base layer 6 n ⁺ type source layer 7 second trench 8 gate oxide film 9 gate electrode 10 interlayer insulating film 11 Source electrode 12 Drain electrode 13 Metal 16 Contact hole

Claims (4)

A first conductivity type drift layer provided on the front surface side of the first conductivity type silicon carbide semiconductor substrate;
A first trench having a planar shape in stripes and provided so as not to reach the first conductivity type silicon carbide semiconductor substrate from the surface of the first conductivity type drift layer;
A second conductivity type base layer provided on the entire surface of the first conductivity type drift layer having the first trench;
A first conductivity type source layer provided on the entire surface of the second conductivity type base layer;
A stripe shape as a plane shape intersecting the first trench, reached on the first conductive type drift layer from the surface of the first conductivity type source layer through the second conductive type base layer, a bottom said A second trench that exposes the second conductivity type base layer and the first conductivity type source layer on a sidewall by forming the first trench so as not to reach a bottom position ;
A gate electrode embedded in the second trench through a gate oxide film;
A source electrode provided in contact with the first conductivity type source layer;
An insulating film provided between the gate electrode and the source electrode;
A drain electrode provided on the back side of the first conductivity type silicon carbide semiconductor substrate;
A silicon carbide semiconductor device comprising:   The surface layer of the first conductivity type drift layer is further provided with a first conductivity type impurity layer having an impurity concentration higher than that of the first conductivity type drift layer provided to cover the bottom of the sidewall of the first trench. The silicon carbide semiconductor device according to claim 1. Laminating a first conductivity type drift layer over the entire front surface side of the first conductivity type silicon carbide semiconductor substrate;
Forming a first trench so that the planar shape is striped and does not reach the first conductivity type silicon carbide semiconductor substrate from the surface of the first conductivity type drift layer;
Laminating a second conductivity type base layer on the entire surface of the first conductivity type drift layer after forming the first trench;
Laminating a first conductivity type source layer on the entire surface of the second conductivity type base layer;
A stripe shape as a plane shape intersecting the first trench, reached on the first conductive type drift layer from the surface of the first conductivity type source layer through the second conductive type base layer, a bottom said Forming a second trench that exposes the second conductivity type base layer and the first conductivity type source layer on a sidewall by forming the first trench so as not to reach a bottom position ;
Burying a gate electrode in the second trench through a gate oxide film;
Forming an insulating film so as to cover the gate electrode;
Forming a source electrode in contact with the first conductivity type source layer;
Forming a drain electrode on the back side of the first conductivity type silicon carbide semiconductor substrate;
The manufacturing method of the silicon carbide semiconductor device characterized by the above-mentioned. Laminating a first conductivity type drift layer over the entire front surface side of the first conductivity type silicon carbide semiconductor substrate;
Forming a first conductivity type impurity layer having an impurity concentration higher than that of the first conductivity type drift layer on the entire surface of the first conductivity type drift layer;
Forming a first trench so that the planar shape is a stripe shape and does not reach the first conductivity type drift layer from the surface of the first conductivity type impurity layer;
Forming a second conductive type base layer on the entire surface of the first conductive type impurity layer after forming the first trench;
Laminating a first conductivity type source layer on the entire surface of the second conductivity type base layer;
A stripe shape as a plane shape intersecting the first trench, reached on the first conductive type drift layer from the surface of the first conductivity type source layer through the second conductive type base layer, a bottom said Forming a second trench that exposes the second conductivity type base layer and the first conductivity type source layer on a sidewall by forming the first trench so as not to reach a bottom position ;
Burying a gate electrode in the second trench through a gate oxide film;
Forming an insulating film so as to cover the gate electrode;
Forming a source electrode in contact with the first conductivity type source layer;
Forming a drain electrode on the back side of the first conductivity type silicon carbide semiconductor substrate;
The manufacturing method of the silicon carbide semiconductor device characterized by the above-mentioned.

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