JP2014225589A - Semiconductor device and operation method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of low loss and high reliability, and provide an operation method of the same.SOLUTION: In a wide gap semiconductor device, a vertical MOSFET part, a vertical BJT part and a lateral IGBT part are incorporated in a cell, and a MOS gate electrode and a base electrode are arranged to drive the lateral IGBT part in addition to the vertical BJT part independent of the vertical MOSFET part. An increase in current-carrying area in the cell caused by activation of the vertical BJT part in addition to the vertical MOSFET part and activation of the lateral IGBT part cause conductivity modulation based on implantation of a minority carrier to reduce internal resistance of the cell thereby to achieve low loss. In addition, by activating the vertical MOSFET part first and flowing a current by a majority carrier and raising a temperature to 50°C and over and subsequently activating the vertical BJT part and the lateral IGBT part and flowing a current by both of the majority carrier and the minority carrier thereby to inhibit an influence of deterioration in an ON-state voltage due to stacking fault and achieve high reliability.

Description

  The present invention relates to a semiconductor device, and more particularly to a high-performance wide gap semiconductor device and an operation method thereof.

At present, Si insulated gate bipolar transistors (hereinafter referred to as Si-IGBT) exclusively made of silicon (hereinafter referred to as Si) are used for high voltage and high power and medium power applications, while SiMOS field effect transistors (hereinafter referred to as Si--) are used for small power applications. MOSFET) is widely used as a main semiconductor device in various fields of application. However, in recent years, wide gap semiconductor materials such as silicon carbide (hereinafter referred to as SiC) have attracted attention as semiconductor materials suitable for high voltage applications. For example, SiC has an excellent characteristic that the dielectric breakdown electric field strength is about 10 times higher than that of Si. When a semiconductor switching device is configured, a high reverse voltage blocking characteristic and a significantly low on-resistance can be realized. (For example, Non-Patent Document 1). Therefore, it is expected that the power loss can be greatly reduced and can contribute greatly to energy saving.
For this reason, development of wide-gap semiconductor switching devices using SiC, gallium nitride, diamond, etc. has been actively promoted. In particular, with regard to SiC, a medium-voltage SiC-MOSFET of 0.5 kV to 3 kV class (Non-patent Document 2). 10kV class high voltage SiC-MOSFET (Non-patent Document 3) and the like have been developed, and their excellent characteristics are disclosed, and are attracting attention as the next major power semiconductor device replacing Si-IGBT.

For example, Conventional Example 1 (Non-Patent Document 2) shown in FIG. 5 uses a 4-layer hexagonal SiC (hereinafter referred to as 4H-SiC) and is a SiC-MOSFET having a withstand voltage of 700 V and a low on-resistance of 2.7 mΩcm ^2. Has been achieved. In addition, in Conventional Example 2 (Non-Patent Document 3) shown in FIG. 6, a low on-resistance of 111 mΩcm ² is achieved by using 4H—SiC and a SiC-MOSFET having a withstand voltage of 10 kV.
These are all low values of 1/100 or less of theoretical values of on-resistance of Si-MOSFETs having the same breakdown voltage, and elements having the same breakdown voltage compared to the ideal value of Si-IGBT, which is the mainstream power semiconductor element at present. The on-resistance is as low as 1/10 or less. Further, the switching speed is also higher than that of the Si-IGBT, and the same high speed as that of the Si-MOSFET is maintained. As a result, a significant reduction in loss can be realized as compared with these Si semiconductor devices.

Yoshitaka Sugawara, Journal of the Institute of Electrical Engineers of Japan, Vol. 125, No. 1, pp. 25-28, 2005 S.Harada, 5 others, Low On Resistance in Inversion Channel IEMOSFET Home 7 4H-SiC C Face Substrate (Row on-resistance in inversion channel 4H-SiC C-face sub, Proceedings of the Eights International Symposium on Power Semiconductor Devices and ICs (June 2006, Proceedings of the 18th International Symposium on Power Semiconductor Devices & ICs), p. 125-128 Sei-Hyung Ryu, 5 others, 10kV 5A 4H-SiC Power DMOSFET (10kV, 5A, 4H-SiC Power DMOSFET), Proceedings of the Aethins International Symposium on Power Semiconductors and ICs 18th International Symposium on Power Semiconductor Devices & ICs), June 2006, p. 265-268

  By the way, although the disclosed SiC-MOSFETs of Conventional Examples 1 and 2 have achieved a low on-resistance of 1/100 or less of Si-MOSFET, a low on-resistance is more preferable from the viewpoint of energy saving. In a large current application, since the energization current is remarkably large, the power consumption of the semiconductor device is increased. Therefore, a significant reduction in loss by reducing the on-resistance is desired. In the on-resistance of the SiC-MOSFET, various internal resistances, that is, the resistance of the MOS channel portion, the resistance of the channel portion of the parasitic junction FET (hereinafter referred to as parasitic JFET), and the resistance of the drift layer occupy the main proportions. In the medium voltage semiconductor device, the ratio of the former two is particularly large, and in the high voltage semiconductor device, the ratio of the latter two is particularly large. Reducing the internal resistance and reducing the loss of the semiconductor device is an important first problem to be solved.

The MOSFET incorporates a pn junction diode composed of a body region and a drift layer electrically in antiparallel. In power converters such as inverters composed of MOSFETs, there is a trend to use this built-in pn junction diode as a flywheeling diode in order to reduce the size and cost of the apparatus.

This built-in pn junction diode is a bipolar semiconductor device in which both majority carriers and minority carriers are involved as carriers for carrying current. Wide gap semiconductors still have lower crystal quality than Si and a large amount of various defects. Of these defects, stacking faults are unique to wide gap semiconductors, where when the injected minority carriers collide with the lattice points of the crystal, the atoms of the lattice points are moved by the collision energy, which increases the size of the stacking faults. There is a nature of. This stacking fault traps and recombines minority carriers and disappears without contributing much to energization. This causes an increase in the internal resistance of the built-in pn junction diode and an increase in leakage current when the diode is reverse biased. Invite. When the built-in pn junction diode is reverse-biased, the SiC-MOSFET is forward-biased, so this increase in leakage current is a major obstacle. In addition, in the case of such a wide gap semiconductor device, stacking faults increase more and more while the device is operating and energized, and as a result, the internal resistance increases and the leakage current also increases. It will be damaged. In some cases, it can be damaged or destroyed. The realization of high reliability of such a wide gap semiconductor device that also uses a built-in bipolar semiconductor element is a second problem to be solved.

An object of the present invention is to solve the above-described problems of the prior art and to provide a low-loss wide-gap semiconductor device with lower on-resistance. The present invention also provides a semiconductor device capable of suppressing the loss of reliability of a wide gap semiconductor device due to deterioration of a bipolar semiconductor element such as a built-in pn junction diode and achieving high reliability, and its An object is to provide a method of operation.

In the following, in order to facilitate understanding, the layers and regions that each semiconductor layer and semiconductor region are functionally correspond to are partially described in parentheses.

In order to solve the above-described problems and achieve the object of the present invention, a wide gap semiconductor device according to the present invention includes:
A wide gap semiconductor device built in a cell,
A first semiconductor layer (SiC substrate) of a first conductivity type;
The first conductivity type second semiconductor layer (drift layer) and the first conductivity type second semiconductor layer (drift layer) provided on the front surface of the first conductivity type first semiconductor layer (SiC substrate). Two first semiconductor regions of the second conductivity type selectively provided on the front surface;
A first conductivity type third semiconductor region (source region) selectively provided on the front surface of one second conductivity type first semiconductor region (body region), and selectively in contact with this region First conductivity selectively provided on the front surface of the provided second conductivity type second semiconductor region (contact region) and the other second conductivity type first semiconductor region (body region / base region). Type fourth semiconductor region (emitter region), a second conductivity type third semiconductor region (base contact region) selectively provided isolated from this region, and the first conductivity type third semiconductor region ( A first main electrode (source electrode / emitter electrode) in contact with the source region), the second conductivity type second semiconductor region (contact region), and the first conductivity type fourth semiconductor region (emitter region);
A surface of the first conductive type second semiconductor region portion (channel region of the parasitic JFET) sandwiched between the two second conductive type first semiconductor regions (body region and body region / base region); A second conductivity type first semiconductor region portion (a channel region of the first MOSFET) sandwiched between a first conductivity type third semiconductor region (source region) and the first conductivity type second semiconductor layer (drift layer). ) And a first semiconductor region portion of the second conductivity type (second region) sandwiched between the fourth semiconductor region (emitter region) of the first conductivity type and the second semiconductor layer (drift layer) of the first conductivity type. A third semiconductor region (source region) of the first conductivity type and a fourth semiconductor region (emitter region of the first conductivity type) on both surfaces of the MOSFET channel region) with an insulating film (gate insulating film) interposed therebetween. ) To extend over First control electrode that is a (MOS gate electrode),
A second control electrode (base electrode) in contact with the surface of the second conductivity type third semiconductor region; and a second main electrode (drain electrode / collector electrode) in contact with the back surface of the first conductivity type first semiconductor layer. And a semiconductor device comprising
The first main electrode, the first conductive type third semiconductor region, the second conductive type second semiconductor region, the second conductive type first semiconductor region, and the first conductive type second semiconductor region. A first vertical MOSFET portion is constituted by the first semiconductor region of the first conductivity type, the second main electrode, and the first control electrode,
The first main electrode, the first conductive type fourth semiconductor region, the second conductive type first semiconductor region, the first conductive type second semiconductor region, and the first conductive type first semiconductor region. The second main electrode and the first control electrode constitute a second vertical MOSFET section. The first main electrode, the first conductive type fourth semiconductor region, and the second conductive type second 3 semiconductor regions, the first conductivity type first semiconductor region, the first conductivity type second semiconductor region, the first conductivity type first semiconductor region, the second main electrode, and the second control electrode. To form a vertical bipolar junction transistor (hereinafter referred to as BJT) portion, the second control electrode, the second conductive type third semiconductor region, the other second conductive type first semiconductor region, One conductivity type second semiconductor region, the one second conductivity type first semiconductor region, and the first conductivity type The third semiconductor region of said first main electrode, characterized in that it constitutes a lateral IGBT portion between the first control electrode.

The semiconductor device according to the present invention is the above-described invention,
The first conductivity type first semiconductor region portion and the first conductivity type sandwiched between the first conductivity type third semiconductor region (source region) and the first conductivity type second semiconductor layer (drift layer). Second conductivity type formed by epitaxial growth in the second conductivity type first semiconductor region portion sandwiched between the fourth semiconductor region (emitter region) and the first conductivity type second semiconductor layer (drift layer). Second conductivity type fourth semiconductor region (channel region of the first MOSFET) having a lower impurity concentration than the first type semiconductor region (body region) and second conductivity type fifth semiconductor region (of the second MOSFET) Channel region),
Near the surface of the second semiconductor region portion of the first conductivity type (the channel region of the parasitic JFET) sandwiched between the two first semiconductor regions (body regions) of the second second conductivity type, the first conductivity type The impurity concentration is higher than that of the second semiconductor layer (drift layer), and the second conductivity type fourth semiconductor region (channel region of the first MOSFET) and the second conductivity type fifth semiconductor region (of the second MOSFET). A fifth semiconductor region of the first conductivity type that is thicker than the channel region) is provided.

The semiconductor device according to the present invention is the above-described invention,
The insulating film (gate insulating film), the second semiconductor region portion of the first conductivity type (channel region of the parasitic JFET) sandwiched between the two second semiconductor regions of the first conductivity type (body region), and the The first conductivity type first semiconductor region portion sandwiched between the first conductivity type third semiconductor region (source region) and the first conductivity type second semiconductor layer (drift layer) and the first conductivity type Between the fourth semiconductor region (emitter region) and the surface of the second conductivity type first semiconductor region portion sandwiched between the first conductivity type second semiconductor layer (drift layer),
A sixth semiconductor region of second conductivity type (storage type MOS channel region) is interposed, and both ends of the third semiconductor region (source region) of the first conductivity type and fourth semiconductor region of the first conductivity type (emitter region). It is provided so that it may extend above.

According to these above-described inventions, it is possible to provide a low-loss semiconductor device with a lower on-resistance and lower power consumption when energized as described below.

In the wide gap semiconductor device according to the present invention, a forward bias voltage is applied between the driving state, that is, the first main electrode (source electrode / emitter electrode) and the second main electrode (drain electrode / collector electrode). When a control voltage equal to or higher than the threshold voltage is applied between one control electrode (MOS gate electrode) and the first main electrode, it is turned on and an on-current flows. This is because the first vertical MOSFET portion and the second vertical MOSFET portion in the cell are driven. At this time, the potentials of the second control electrode (base electrode) and the first main electrode (source electrode / emitter electrode) are the same as in the known vertical MOSFET. As described above, in the current path through which the on-current of the vertical MOSFET flows, the various internal resistances described above, that is, the resistance of the MOS channel portion and the parasitic JFET channel portion, the resistance of the drift layer, etc. And limits the on-current that flows in the same manner as a known MOSFET. In particular, since the potential of the second control electrode (base electrode) and the first main electrode (source electrode / emitter electrode) are the same, the potential of the source region connected to the first main electrode and the MOS potential The channel portion and the parasitic JFET channel portion have a slight voltage drop but are relatively close potentials, and the potentials of the base region and body region connected to the second control electrode (base electrode) are also relatively close potentials. . As a result, a depletion layer is formed at the junction between the MOS channel portion and the parasitic JFET channel portion and the base region / body region by a built-in voltage corresponding to the band gap. Therefore, since the channel is narrowed by the width of the depletion layer, each channel resistance is increased.

  In the wide gap semiconductor device according to the present invention, the second control electrode (base electrode) and the first main electrode (source electrode / emitter electrode) of the vertical BJT portion when the vertical MOSFET portion is on. A voltage in the forward bias direction can be applied between them. The voltage in the forward bias direction is a voltage having a polarity that becomes a forward bias when a voltage applied to a junction constituted by the emitter region and the base region of the vertical bipolar junction transistor portion exceeds a predetermined voltage. As a result, for example, the width of the depletion layer at the junction between the channel of the parasitic JFET and the base region / body region can be narrowed according to the voltage in the forward bias direction to widen the channel. As a result, by increasing the voltage in the forward bias direction of the second control electrode (base electrode), the on-resistance can be further lowered and the power consumption during energization can be reduced.

  In the wide gap semiconductor device according to the present invention, the voltage in the forward bias direction between the second control electrode (base electrode) and the first main electrode (source electrode / emitter electrode) of the vertical BJT portion is further increased. Thus, the voltage of the emitter junction formed by the emitter region connected to the first main electrode and the base region connected to the second control electrode can be increased. If this voltage is made higher than the built-in voltage of the wide gap semiconductor constituting the semiconductor device (for example, about 2.7 V or more in the case of SiC), carriers are injected from the emitter to the base, and the base current flows, and the vertical BJT Department turns on. As a result, a large collector current obtained by amplifying the base current by the current amplification factor of the vertical BJT portion can also flow in the drain region under the base region / body region.

When only the vertical MOSFET portion is on, the drift region under the base region / body region is a region in which no current flows, so that a current can flow in an unutilized region, and the wide gap semiconductor device The overall on-resistance can be greatly reduced. Since the current amplification factor can be easily increased to 50 to 200, the on-resistance reduction effect of the semiconductor device is extremely remarkable. Further, by increasing the voltage in the forward bias direction, the base current can be increased, so that the collector current can be further increased, and the on-resistance of the wide gap semiconductor device can be further greatly reduced.

By reducing the impurity concentration of the base region and body region within a range where the withstand voltage can be maintained and taking injection efficiency improvement measures such as suppressing the injection of carriers from the base to the emitter, the on-resistance can be further reduced. Power consumption during energization can be further reduced.
In addition, a measure for suppressing carrier surface recombination on the surface of the wide gap semiconductor in the isolation region between the emitter and the base contact is also effective in further reducing the on-resistance. As a measure for suppressing the carrier surface recombination, for example, when an SiC crystal is used as a wide gap semiconductor, it is formed by plasma CVD (Chemical Vapor Deposition) as a passivation film on the surface of the isolation region, and is nitrided in NO (Mononitriding Nitrogen) gas. An SiO ₂ film may be used.

In the wide gap semiconductor device according to the present invention, by further increasing the voltage in the forward bias direction between the second control electrode (base electrode) and the first main electrode (source electrode / emitter electrode), a lateral IGBT unit is formed. Can be turned on. As a result, minority carriers can be injected from the base region / body region functioning as the collector of the lateral IGBT portion into the channel region and the drain region of the parasitic junction FET. As a result, conductivity modulation can be caused in these channel region and drain region, and the resistance of these regions can be reduced. As a result, the on-resistance of the wide gap semiconductor device can be further reduced, and the power consumption during energization can be further reduced. On-resistance can be further reduced by taking measures to increase the lifetime of minority carriers in the channel region and drain region of the parasitic junction FET. For example, when the channel region or drift layer of the parasitic junction FET is an n-type SiC crystal, carbon vacancies in the crystal are reduced by implanting carbon atoms at 1 × 10 ¹⁷ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ . It is effective to use a drift layer. Conventionally, the lifetime of minority carriers of 1 μs or less can be extended to 2 to 10 μs or more, and the on-resistance of the wide gap semiconductor device can be further reduced.

The semiconductor device according to the present invention is the above-described invention,
The width of the fourth semiconductor region (emitter region) of the first conductivity type is larger than the width of the third semiconductor region (source region) of the first conductivity type.
Furthermore, the crystal orientation of the side surface of the fourth semiconductor region (emitter region) of the first conductivity type is {1-100}.

As the width of the emitter region of the vertical BJT portion becomes narrower, the current amplification factor becomes lower. This is understood as follows. The bottom surface of the emitter region is a surface where carriers are injected into the base, and the side surface of the emitter region is a surface where carriers recombine without contributing to the current amplification factor. When the width of the emitter region is narrowed, the area of the side surface of the emitter region is relatively larger than the area of the bottom surface in contact with the base region. In general, a wide-gap semiconductor device has a higher interface trap density and interface order density at the side surface than at the bottom junction, so that the surface recombination at the side with a larger area is larger and the current amplification factor is lower. Is.
On the other hand, since the side surface of the vertical MOSFET portion is in contact with the MOS channel region, the larger the side surface through which carriers flow, the better the efficiency and the smaller the source region width in terms of reducing the occupied area in the cell.
Therefore, the on-resistance of the wide gap semiconductor device can be further lowered by making the width of the emitter region in the cell of the vertical BJT portion larger than the width of the source region.

Also, in the wide gap semiconductor device, the interface order density varies depending on the crystal orientation. In 4H-SIC, when the crystal orientation is {1-100}, the total number of interfacial order densities is small compared to other crystal orientations. Therefore, by setting the crystal orientation of the side surface of the emitter region of the vertical SiC-BJT portion to {1-100}, the surface recombination at the side surface can be reduced and the current amplification factor can be increased, and the wide gap semiconductor device can be turned on. Resistance can be lowered.

  As described above, the wide gap semiconductor device according to the present invention effectively solves the first problem and realizes a low-loss wide gap semiconductor device with lower on-resistance and hence lower power consumption when energized. it can

In order to solve the above-described problems and achieve the object of the present invention, a wide gap semiconductor device according to the present invention includes:
At least the fourth semiconductor region (emitter region) of the first conductivity type is formed of a wide gap semiconductor having a wider energy gap.

  When the voltage in the forward bias direction between the second control electrode (base electrode) and the first main electrode (source electrode / emitter electrode) of the vertical BJT section is made higher than the built-in voltage of the emitter junction, When carriers of one polarity (for example, electrons in the case of an npn transistor) are injected, carriers of the other polarity (for example, holes in the case of an npn transistor) are also injected from the base to the emitter. Among these, the former carrier injection contributes to the improvement of the current amplification factor in connection with the transistor operation, and the latter carrier injection does not contribute.

If the energy gap of the wide gap semiconductor constituting the fourth semiconductor region (emitter region) of the first conductivity type is made wider than the energy gap of the wide gap semiconductor constituting the base region to form the heterojunction, Due to the difference in the gap, carrier injection from the emitter to the base contributing to the improvement of the current amplification factor can be promoted, but carrier injection from the base to the emitter which does not contribute can be suppressed. As a result, the injection efficiency of the vertical BJT portion (the ratio of the electron current to the base current in the case of an npn transistor) can be further increased, so that the current amplification factor can be further increased. As a result, when the vertical BJT portion is turned on, the on-resistance of the wide gap semiconductor device can be further reduced, and the power consumption during energization can be further reduced.

Further, by using the heterojunction described above, the impurity concentration in the base region can be increased while maintaining the efficiency of injection from the emitter to the base at the same level as in the case of a normal junction. As a result, since the base resistance can be reduced, the maximum operating frequency can be increased, and punch-through in the base region can be suppressed, so that a high breakdown voltage can be achieved.
As described above, the first problem is more effectively solved by the wide gap semiconductor device according to the present invention, and a low-loss wide gap semiconductor device with lower ON resistance and lower power consumption when energized is realized. it can

In order to solve the above-described problems and achieve the object of the present invention, a wide gap semiconductor device according to the present invention includes:
As described above, the vertical MOSFET section, the vertical BJT section, and the horizontal IGBT section are built in, and the vertical BJT section and the horizontal IGBT section can be operated independently of the vertical MOSFET section.
Therefore, in the wide gap semiconductor device according to the present invention, first, the vertical MOSFET portion is operated to flow a current due to majority carriers, then the vertical BJT portion is operated to flow a current due to both minority carriers and majority carriers, Further, the lateral IGBT unit is also operated, and it is possible to superimpose currents from both minority carriers and majority carriers. As a result, the following operation method according to the present invention can be applied, and a highly reliable semiconductor device can be realized.

In order to solve the above-described problems and achieve the object of the present invention, an operation method of a wide gap semiconductor device according to the present invention includes:
In the wide gap semiconductor device having the above-described configuration, at least when operating, the vertical MOSFET portion built in the wide gap semiconductor device is operated to flow a forward current due to majority carriers, and this current causes the wide gap semiconductor device to be 50 ° C. or higher. The internal bipolar semiconductor element portion is operated after the temperature is raised to.

In the wide gap semiconductor device having the above-described configuration, at least when operating, the first vertical MOSFET portion and the second vertical MOFET portion are operated to pass a forward current due to majority carriers, and this current causes the wide gap to be widened. After raising the temperature of the gap semiconductor device to 50 ° C. or more, a part or all of the vertical bipolar junction transistor part, the lateral IGBT part, and the built-in pn junction diode used as a flywheeling diode are operated. To do.

In the wide gap semiconductor device, when minority carriers are injected and energized as described above, stacking faults increase and on-voltage degradation occurs. When the wide gap semiconductor device is applied to, for example, an inverter device and the built-in pn junction diode of the vertical MOSFET portion of the wide gap semiconductor device is used as a flywheeling diode, the on-voltage degradation occurs in the built-in pn junction diode as described above. Will occur. In the wide gap semiconductor device, when a base current is applied during operation of the vertical BJT portion, minority carrier injection from the emitter to the base and minority carrier injection from the base to the emitter occur. For this reason, stacking faults are enlarged in each of the emitter region and the base / body region, and on-voltage degradation occurs.
During operation of the lateral IGBT portion, minority carriers are injected from the base region / body region functioning as an emitter into the channel region and the drain region of the parasitic junction FET. For this reason, stacking faults expand in each of the channel region and the drain region of the parasitic junction FET, and on-voltage degradation occurs.

These on-voltage degradations continue to be promoted when the wide gap semiconductor device continues to operate, and reliability is greatly impaired.
In particular, when a wide gap semiconductor device is operated and energized at a temperature of 40 ° C. or lower, the low-temperature low temperature causes a large number of minority carrier annihilation due to stacking faults, resulting in an increase in on-voltage. Become. As a result, when the expansion of stacking faults is promoted, the device may be damaged by excessively rapid heat generation. When re-operation at 40 ° C. or lower is repeated, the degree of heat generation is increased due to the expanded stacking faults, and the device may be destroyed.

In the operation method of the wide gap semiconductor device according to the present invention, at least when operating the wide gap semiconductor device, first, the vertical MOFET portion built in the wide gap semiconductor device is operated to flow a forward current due to majority carriers. After the temperature of the wide gap semiconductor device is raised to 50 ° C. or higher, the built-in vertical BJT unit is operated. For example, only the first vertical MOFET portion and the second vertical MOFET portion are operated to pass a forward current due to majority carriers, and the wide gap semiconductor device is heated to 50 ° C. or more by this current. Thereafter, one or all of the vertical BJT portion, the horizontal IGBT portion, and the built-in pn junction diode are operated. As a result, even if stacking faults already exist and continue to increase prior to operation, the above-described temperature rise can suppress the minority carrier disappearance phenomenon of stacking faults, thereby reducing the on-voltage degradation of the wide gap semiconductor device after operation. Damage to the semiconductor device due to excessive rapid heat generation can be suppressed. The higher the temperature rise during re-operation, the greater the effect of accelerating on-voltage degradation and suppressing breakdown. For example, in the case of SiC, the higher the temperature is in the range of 50 ° C. to 250 ° C., the greater the effect of suppressing the minority carrier annihilation phenomenon of the stacking faults, and the deterioration of the on-voltage can be suppressed. Above 250 ° C., operation can be resumed at substantially the same on-voltage as the initial on-voltage of the wide gap semiconductor device before the on-voltage degradation occurs.

Thus, the second problem can be effectively solved by the operation method of the present invention, and a wide-gap semiconductor device having high reliability and a driving method thereof can be realized.

As described above, according to the present invention, a voltage can be applied to the second control electrode of the wide gap semiconductor device, and the built-in bipolar element section can be operated, the on-resistance can be further lowered, and therefore the power consumption during energization is further reduced. it can. In addition, according to the present invention, the wide gap semiconductor device can be operated after the temperature is raised by energization of majority carriers, and it is possible to suppress deterioration of the reliability of the wide gap semiconductor device due to the expansion of stacking faults. Reliability can be achieved.

Cell sectional view of the semiconductor device according to the first embodiment. Cell sectional view of the semiconductor device according to the second embodiment. Cell sectional view of a semiconductor device according to the third exemplary embodiment. Cell sectional view of a semiconductor device according to the fourth exemplary embodiment. FIG. 6 is a cell cross-sectional view of a medium voltage SiC-MOSFET of Conventional Example 1. The cell sectional view of the high voltage SiC-MOSFET of the conventional example 2.

Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n or p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. In the drawings, the numbers and arrows indicating the layers and regions have the same basic function. In principle, the numbers and arrows are representative of each layer and the region, and the others are omitted. In the case of having other functions together, the former number is distinguished by a and the latter number by b. Since the SiC semiconductor has less impurity diffusion in the direction perpendicular to the depth direction than the Si semiconductor, each semiconductor region is shown in a rectangular shape in each drawing.

Embodiment 1

  FIG. 1 is a cell cross-sectional view schematically showing the wide gap semiconductor device according to the first embodiment. The width and thickness of each region are not necessarily shown in proportion to the actual dimensions. This semiconductor device is a wide-gap semiconductor device 100 having a design withstand voltage of 2 kV and made of, for example, a vertical SiC-MOSFET portion, a vertical SiC-BJT portion, and a horizontal SiC-IGBT portion, which is manufactured using a 4H-SiC substrate. . FIG. 1 shows only one cell portion in the active region of the semiconductor device 100. The wide gap semiconductor device 100 includes a breakdown voltage structure (not shown) so as to surround the active region, for example. The active region is a region through which a current flows when the semiconductor device is turned on and incorporates a plurality of cells. The breakdown voltage structure portion is a structure portion that relaxes the electric field strength on the surface of the semiconductor device and realizes a desired breakdown voltage.

The chip size of the wide gap semiconductor device 100 is 6.3 mm × 6.3 mm, the active region is 5.6 mm × 5.6 mm, and the width of the breakdown voltage structure part surrounding the active region is 0.35 mm. The semiconductor device cell in the active region is striped. The cell width may be 14 μm using a design rule that sets the minimum pattern width to 1.0 micrometer (hereinafter referred to as μm).

First, the configuration of the wide gap semiconductor device 100 will be described with reference to FIG.
An n ⁺ substrate 102 is provided in contact with the collector electrode 101 of the wide gap semiconductor device 100. An n ⁻ drift layer (first semiconductor layer) 103 is formed on the front surface of the n ⁺ substrate 102. The impurity concentration and thickness of the n ⁻ drift layer 103 may be, for example, 6 × 10 ¹⁵ cm ⁻³ and 16 μm. Alternatively, a drift layer in which carbon atoms are implanted at 7 × 10 ¹⁸ atoms / cm ³ in order to increase the lifetime of minority carriers may be used.

On the surface of the n ⁻ drift layer 103, p body regions (first semiconductor regions) 104a and 104b are selectively provided. The impurity concentration and thickness of these p body regions may be, for example, 1 × 10 ¹⁸ cm ⁻³ and 0.3 μm, respectively. The p body regions 104a and 104b are layers formed by, for example, aluminum ion implantation. The thickness of the n ⁻ drift layer 103 between the p body regions 104a and 104b and the n ⁺ substrate 102 is about 15.7 μm.

On the surface layers of p body regions 104a and 104b, n ⁺ source regions (second semiconductor regions) 105a and 105b, p ⁻ channel regions 106a and 106b, and p + contact region 107 are selectively provided. One end of n ⁺ source region 105 a is in contact with p ⁻ channel region 106 a, and the other end is in contact with p + contact region 107.

The impurity concentration and thickness of the p ^- channel regions 106a and 106b may be 5 × 10 ¹⁵ cm ⁻³ and 0.3 μm, respectively. The channel width may be 1.0 μm.
The impurity concentration and thickness of the n ⁺ source regions 105a and 105b may be, for example, 1 × 10 ¹⁹ cm ⁻³ and 0.3 μm, respectively. The impurity concentration and thickness of the p + contact region 107 may be, for example, 1 × 10 ¹⁹ cm ⁻³ and 0.4 μm. The width of the n ⁺ source region 105a may be 2.5 μm, for example.

An n ⁻ region 108 is provided between p ⁻ channel regions 106 a and 106 b and between p body regions 104 a and 104 b. The n ⁻ region 108 is formed of a double nitrogen ion implantation layer, and the impurity concentration is, for example, 1 × 10 ¹⁷ cm ⁻³ when the thickness is 0.2 μm from the surface, and 2 from 0.2 μm to the drift layer 103. It may be × 10 ¹⁶ cm ^-3 . Further, in order to increase the lifetime of minority carriers, an n ⁻ region in which carbon atoms are implanted at 8 × 10 ¹⁸ atoms / cm ³ may be used.

A gate electrode (control electrode) 111 is provided on the surface of p ⁻ channel regions 106a and 106b and the surface of n ⁻ region 108 via a gate insulating film 110, and both ends thereof are on n ⁺ source regions 105a and 105b, respectively. It is extended. The thickness of the gate insulating layer 110 may be about 650 angstroms. The source electrode (input electrode) 113 is in contact with the n ⁺ source regions 105 a and 105 b and is also in contact with the p ⁺ contact region 107. The source electrode 113 is insulated from the gate electrode 111 by the interlayer insulating film 112.

The n ⁺ source regions 105a and 105b, the p ⁻ channel regions 106a and 106b, the n ⁻ region 108, the n ⁻ drift layer 103, and the n ⁺ substrate 102 constitute a vertical SiC-MOSFET portion.

Further, the n ⁺ source region / emitter region 105b, the p body region / base region 104b, and the n ⁻ drift layer 103 constitute a vertical SiC-BJT portion, each of which includes an n ⁺ emitter, a p base, and an n ⁻ collector. Also works. The base electrode 114 is in contact with the p ⁺ base contact region 109 and is connected to the p base 104b through this.
The n ⁺ source / emitter region 105b is made wider than the n ⁺ source region 105a to 3.5 μm in order to keep the cell width to the minimum without departing from the design rule and to increase the current amplification factor. Good.

Further, the interfacial order density is high on the side surface of the emitter region and is different depending on the crystal orientation of 4H—SiC. In the case of 4H-SIC, when the crystal orientation is {1-100}, the total number of interface order density is small compared to other crystal orientations, so that the current amplification factor can be increased. As a result, the on-resistance of the wide gap semiconductor device can be increased. Can be lower. Therefore, in this embodiment, the crystal orientation of the side surface of the emitter region is set to {1-100}.

The impurity concentration and thickness of the p ⁺ base contact region 109 may be, for example, 1 × 10 ¹⁹ cm ⁻³ and 0.1 μm.
In addition, the source electrode 113 that also functions as an emitter electrode and the base electrode 114 are insulated by an insulating region 115.
The p body region / base region 104b, the n ⁻ region 108 (and the n ⁻ drift layer 103), the p ⁻ channel region 106a (and the p body region 104a), and the n ⁺ source region 105a constitute a lateral SiC-IGBT. Each of them functions as a p collector, an n base, a p base, and an n emitter.

  Next, a manufacturing method of the wide gap semiconductor device 100 will be described with a focus on the main manufacturing flow focusing on the cell portion shown in FIG. Most of the photo-etching process and annealing process are omitted. In addition, the description of the flow of manufacturing the breakdown voltage structure not shown and the protective film of the semiconductor device is omitted.

First, an n drift layer 103 having a thickness of 16 μm is formed by epitaxial growth on an off-angle 4H-SiCn ⁺ substrate having a thickness of 30 μm. Then, carbon ion implantation and activation annealing may be performed on at least the entire surface of the n drift layer 103 in the active region to increase the minority carrier lifetime. Further, p body regions 104a and 104b having a thickness of 0.3 μm are selectively formed by ion implantation of aluminum, and a p ⁻ layer having a thickness of 0.3 μm which finally becomes a p ⁻ channel region is formed by epitaxial growth. .

Then, n ⁺ source regions 105a and 105b having a thickness of 0.3 μm are selectively formed by ion implantation of nitrogen, and ap ⁺ contact regions 107 and 109 having a thickness of 0.4 μm are further formed by ion implantation of aluminum. Next, the n ⁻ region 108 is formed by double ion implantation of nitrogen.

Next, a gate oxide film 110 is formed, a polycrystalline Si gate electrode 111 is formed, and photo-etching is performed so as to have a predetermined width. Next, the gate oxide film on the p ⁻ layer epitaxial growth layer opposite to the p ⁻ channel region 106b of the n ⁺ emitter 105b is removed by etching, and then SiC recess etching is performed to a depth of 0.3 μm. As a result, a p ⁺ base contact region 109 having a thickness of 0.1 μm is formed. The recess etching may be performed so that the crystal orientation of the exposed surface of the n ⁺ emitter 105b is {1-100}.
Next, surface treatment is performed to suppress carrier surface recombination on the surface exposed to the recess etching portion, and an interlayer insulating film 112 is formed on the entire surface of the cell.
The formation and photoetching of the gate oxide film 110 and the polycrystalline Si gate electrode 111 are performed after the SiC recess etching and the surface treatment for suppressing carrier surface recombination, and then the interlayer insulating film 112 is formed. Also good.

Next, the interlayer insulating film 112 and the gate oxide film 110 at the portions where the n ⁺ source regions 105a and 105b, the p ⁺ contact region 107 and the electrode 113 are in contact, and the portion where the p ⁺ base contact region 109 and the base electrode 114 are in contact are removed. Then, an electrode film is formed. At this time, a well-known electrode forming method is applied so that a good ohmic contact can be realized at each contacting portion. Next, the electrode film is subjected to photo-etching to form the source electrode 113 and the base electrode 114, and further, the collector electrode 101 is formed by a known method, and the cell portion of FIG. 1 is manufactured.

Next, characteristics of the wide gap semiconductor device 100 according to the present embodiment will be described.
The wide gap semiconductor device 100 is obtained by performing die bonding and wire bonding using a TO-type high voltage package by a known technique, and further completely covering the chip and the wire with a protective high heat resistance resin (nanotech resin). After finishing the semiconductor device, it is used for the operation test.

When a forward voltage is applied between the source / emitter electrode 113 and the drain / collector electrode 101 in a state where the source / emitter electrode 113 and the base electrode 114 are at the same potential and no voltage is applied to the MOS gate electrode 111, a leakage current flows. Shows a good forward blocking characteristic, and the breakdown voltage at room temperature, that is, the voltage indicating avalanche breakdown is about 2.3 kV. Moreover, the leakage current before avalanche breakdown is 3 × 10 ⁻³ A / cm ² or less at room temperature and 5 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.

A forward voltage Vsd is applied between the drain / collector electrode 101 and the source / emitter electrode 113 while the source / emitter electrode 113 and the base electrode 114 are electrically connected to have the same potential, and the MOS gate electrode 111 has a threshold value. When a MOS gate voltage higher than the voltage is applied, an on-current flows. When the forward voltage Vsd is 5 V and the MOS gate voltage is 18 V, the on-current density Jsd is as good as 221 A / cm ² . In this state, only two vertical MOSFET sections in the cell are operating.

Next, a base voltage Vbe is applied between the base electrode 114 and the source / emitter electrode 113 so that the potential of the base electrode 114 becomes high. In this case, Jsd further increases as Vbe increases. For example, when Vsd is 5V, JSD the Vbe is 1.0V is JSD In 240A ^/ cm 2, Vbe is 2.0V is JSD In 264A ^/ cm 2, Vbe is 2.5V is 282A / cm ^2. As Vbe increases, Jsd increases. As described above, this is because the depletion layer at the junction between the MOS inversion channel and the channel of the parasitic JFET and the p-channel regions 106a and 106b, and between the channel of the parasitic JFET and the base region / body regions 104a and 104b. It is considered that the on-resistance decreases because the width of the channel is increased by narrowing the width in accordance with the increase of Vbe.

Furthermore, JSD if Vbe is 3.0V surged was 329A / cm ^2, Jsd the Vbe is JSD at 4.0V is 406A ^/ cm 2, Vbe is 5V further increased to 475A / cm ^2. As described above, when Vbe is about 2.7 V or more, carriers are injected from the emitter 105b to the base, the base current flows, and the vertical SiC-BJT portion is turned on. As a result, the drift below the base region / body region 104b occurs. It is considered that a large collector current obtained by amplifying the base current by the current amplification factor of the vertical SiC-BJT portion flows in the region 103. Making the width of the emitter region larger than the width of the source region and setting the crystal orientation of the side surface of the emitter region to {1-100} also contributes to increasing the current amplification factor.
When Vbe is 4.0 V or more, as described above, minority carriers are present in the channel region and the drift region 103 of the parasitic junction FET from the base region / body region 104b that functions as a collector with the lateral IGBT portion turned on. It is considered that holes are injected and conductivity modulation occurs in these channel regions and drift regions, so that the resistance of these regions is reduced and Jsd is further increased. Increasing the lifetime of minority carriers by carbon implantation contributes to further promoting conductivity modulation and further increasing Jsd.

The above consideration can also be supported by analyzing the carrier distribution at each Vbe by a two-dimensional simulation of the structure of the present embodiment.

In the wide gap semiconductor device according to the present embodiment, after the on / off pulse test in which Jsd 150 A / cm ² is repeatedly applied with a pulse width of 500 μs is performed for 10 hours, the wide gap semiconductor device is cooled to 40 ° C. or less and then turned on / off again. When the test for 10 hours is repeated 25 times, the on-voltage degradation is observed, and a wide gap semiconductor device is generated in which the on-voltage is about 5V at Jsd150A / cm ² but increases to 12V or more. In this case, an on-voltage deterioration of 7V occurs. When the on / off pulse test is performed 50 times, a semiconductor device that is damaged at the start of the on / off pulse test occurs at a certain frequency. Further, when the wide gap semiconductor device of the present embodiment is used to form an inverter and a pn junction diode built in the vertical MOFET portion is used as a flywheeling diode, the above Jsd is 150 A / cm ² . When the operation test is performed 50 times in total for 10 hours, a semiconductor device that is damaged at the start of the operation test occurs at a certain frequency.

When these wide-gap semiconductor devices are applied with the operation method according to the present invention, the deterioration of the on-voltage at Jsd150A / cm ² after 25 times can be suppressed to 3V or less. In addition, a semiconductor device that is damaged at the start of the on / off pulse test does not occur even in the 50 on / off pulse tests.
That is, when the wide gap semiconductor device of the present embodiment is operated by the operation method of the present embodiment, first, the base electrode 114 is set to the same potential as the main electrode 113 and the MOS gate voltage is set to 12V and built in the wide gap semiconductor device. The forward MOSFET current is caused to flow by operating the vertical MOSFET section. After the temperature of the wide gap semiconductor device is raised to about 80 ° C. by this current, a voltage is applied to the base electrode 114 and Vbe is set to about 5 V to operate the built-in vertical SiC-BJT unit and the like. As a result, even if stacking faults already exist and continue to increase prior to operation, the above-described temperature rise can suppress the minority carrier disappearance phenomenon of stacking faults. Thus, damage to the semiconductor device due to excessive rapid heat generation can be suppressed.

In addition, when the operation method according to the present invention is applied, an inverter is configured using the wide gap semiconductor device of the present embodiment, and an operation test is started in the middle even if an operation test is performed for 10 hours and 50 times for a total of 500 hours. No semiconductor device was occasionally damaged.
It should be noted that the higher the temperature rise temperature at the time of reactivation, the greater the effect of accelerating on-voltage degradation and suppressing damage as the temperature rises.

As described above, according to the semiconductor device according to the first embodiment, the base voltage can be independently increased, so that the vertical BJT part and the lateral IGBT can be driven, and only the vertical MOSFET part is turned on. A current can also flow through the drift region under the base region / body region that is not utilized, or conductivity modulation can be caused. When compared with the same breakdown voltage, the on-current density at the same forward voltage Vsd is A semiconductor device that can be significantly increased and has low on-resistance and low power consumption can be realized.
Further, according to the semiconductor device and the operation method thereof according to the first embodiment, the vertical SiC-BJT unit and the horizontal SiC- are operated after the MOSFET unit is operated with a relatively low current before operation and the temperature is increased with majority carrier current. The IGBT part and the built-in pn junction diode part for the flywheeling diode can be driven, so that the adverse effect of the on-voltage degradation peculiar to the bipolar semiconductor element part constituted by the wide gap can be suppressed, and the high reliability wide A gap semiconductor device and its operation method can be realized.

Embodiment 2

FIG. 2 is a cell cross-sectional view schematically showing the wide gap semiconductor device according to the second embodiment. Compared to the semiconductor device of the first embodiment, the first vertical SiC-MOSFET part is also used as the vertical SiC-BJT part, and the first vertical SiC- A base IGBT 207a and 207b and emitters 205a and 205b are newly provided in that a lateral IGBT portion having the base region / body region 204a of the MOSFET portion as a collector and the n + emitter 205b of the vertical SiC-BJT portion as an emitter is further provided. Except for the fact that the isolation regions 216a and 216b between them are in the shape of trench grooves, the other structures are substantially the same.
In addition, the manufacturing process includes a process of forming a trench groove by known dry etching to form the isolation regions 216a and 216b, and then filling with an insulator such as SiO ₂ . It is almost the same except that a part of the source electrode of the vertical SiC-MOSFET portion is separated using a known photoetching technique to form a new base electrode 214a.

Next, characteristics of the wide gap semiconductor device according to the second embodiment will be described.
When a forward voltage is applied between the source / emitter electrode 213 and the drain / collector electrode 201 in a state where the source / emitter electrode 213 and the base electrodes 214a and 214b are at the same potential and no MOS gate voltage is applied, a leakage current flows. The forward blocking characteristic is shown, and the breakdown voltage at room temperature, that is, the voltage indicating avalanche breakdown is about 2.2 kV. Moreover, the leakage current before avalanche breakdown is as good as 3.2 × 10 ⁻³ A / cm ² or less at room temperature and 5.4 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.

The source / emitter electrode 213 and the base electrode 214 are electrically connected to have the same potential, a forward voltage Vsd is applied between the drain / collector electrode 201 and the source / emitter electrode 213, and a MOS having a threshold voltage or higher is applied to the gate electrode 211. An on-current flows when a gate voltage is applied. When the forward voltage Vsd is 5 V and the MOS gate voltage is 18 V, the on-current density Jsd is as good as 204 A / cm ² . In this state, only two vertical MOSFET sections in the cell are operating.

Next, a base voltage Vbe is applied between the base electrodes 214a and 214b and the source / emitter electrode 213 so that the potential of the base electrode becomes high. When Vsd is 5V, MOS gate voltage of 18V, Vbe in the 1.0 V JSD is 224A ^/ cm 2, the Vbe is 2.0 V JSD is 244A ^/ cm 2, Vbe is JSD at 2.5V is 260A / cm ² It is. As Vbe increases, Jsd increases. As described above, this is because the depletion layer at the junction between the MOS inversion channel and the channel of the parasitic JFET and the p-channel regions 206a and 206b, and between the channel of the parasitic JFET and the base region / body regions 204a and 204b. It is considered that the on-resistance decreases because the width of the channel is increased by narrowing the width in accordance with the increase of Vbe.

Further, when Vbe becomes 3 V, Jsd is 461 A / cm ² , and increases rapidly. When Vbe is 4 V, Jsd increases to 548 A / cm ² , and when Vbe is 5 V, Jsd further increases to 618 A / cm ² . As described above, when Vbe is about 2.7 V or more, carriers are injected from the emitter regions 205a and 205b into the base region / body regions 204a and 204b, the base current flows, and the vertical SiC-BJT portion is turned on. It is considered that a large collector current obtained by amplifying the base current by the current amplification factor of the vertical SiC-BJT portion flows in the drift region 203 below the base region / body regions 204a and 204b. The fact that the width of the emitter region is made larger than the width of the source region and the crystal orientation of the side surface of the emitter region is set to {1-100} to increase the current amplification factor also contributes to a significant increase in Jsd.
Further, when Vbe is 4 V or more, the lateral IGBT portion is turned on as described above, and the minority carriers from the base region / body regions 204a and 204b functioning as collectors to the channel region of the parasitic junction FET and the drift region 203 are positive. It is considered that holes are injected and conductivity modulation occurs in these channel regions and drift regions, so that the resistance of these regions is reduced and Jsd is further increased. Increasing the lifetime of minority carriers by carbon implantation contributes to further promoting conductivity modulation and further increasing Jsd.

As described above, in the case of the second embodiment, the vertical SiC-BJT portion and the horizontal IGBT portion in the cell are doubled as compared with the first embodiment. In addition, Jsd can be further greatly increased and the on-resistance can be further greatly reduced by effectively utilizing current so that almost the entire drift layer including the drift layer under the first vertical SiC-MOSFET portion flows. A wide gap semiconductor device with low power consumption can be realized.

In the wide gap semiconductor device according to the present embodiment, if an operation test is performed for 10 hours and 50 times for a total of 500 hours with the above-described pulse current of Jsd150 A / cm ² and a pulse width of 500 μs, the semiconductor device is damaged at the start of an intermediate operation test. Occurs at a certain frequency.
Also, in the operation test of 25 hours for 10 hours and 250 hours in total, the on-voltage at Jsd150A / cm ² was about 5V before the start of the first test was over 12V, and the wide gap with on-voltage degradation reaching 7V Semiconductor devices were also generated.

However, when the operation method according to the present invention is applied to these wide gap semiconductor devices, the ON voltage at the above Jsd150A / cm ² is 6 V or less after the operation test of 25 hours for 10 hours and 25 hours in total. The deterioration could be suppressed to 1V or less. In addition, even if the operation test was performed 50 times for 10 hours and a total of 500 hours, no semiconductor device was damaged at the start of the intermediate operation test.

As described above, according to the semiconductor device according to the second embodiment, a highly reliable wide-gap semiconductor device and its operation method can be realized, and the vertical BJT section as compared with the semiconductor device according to the first embodiment. And the lateral IGBT portion can be doubled, so that the on-current density at the same forward voltage Vsd can be further greatly increased, and a wide-gap semiconductor device with lower on-resistance and lower power consumption can be realized.

Embodiment 3

FIG. 3 is a cell cross-sectional view schematically showing a wide gap semiconductor device having a design withstand voltage of 4.5 kV according to the third embodiment.
In the wide gap semiconductor device 300, an n ⁺ 4H—SiC substrate 302 is provided in contact with the collector electrode 301. An n ⁻ drift layer 303 made of 4H—SiC is formed on the front surface of the n ⁺ 4H—SiC substrate 302. The impurity concentration and thickness of the n ⁻ drift layer 303 may be 1 × 10 ¹⁵ cm ⁻³ and 46 μm, for example. Alternatively, a drift layer in which carbon atoms are implanted at ³ × 10 ¹⁹ atoms / cm ³ in order to increase the lifetime of minority carriers may be used.

On the front surface of the n ⁻ drift layer 303, p body regions 304a and 304b made of 4H—SiC are selectively provided. The thickness of p body regions 304a and 304b may be 0.3 μm. In this case, the thickness of n ⁻ drift layer 303 between p body regions 304a and 304b and n ⁺ substrate 302 is about 45.7 μm. . A p + contact region 309 is selectively provided in the p body region 304b.

On the front surface of the p body region, an n ⁺ source region 305 a, an n ⁺ source region / emitter region 305 b, p ⁻ channel regions 306 a and 306 b, a p + contact region 307, and an n ⁻ drift layer 303 front surface An n ⁻ region 308 is selectively provided on the surface, and these are all made of AlGaN. One end of n ⁺ source regions 305a and 305b is in contact with p ⁻ channel regions 306a and 306b, respectively, and the other end of n ⁺ source region 305a is in contact with p + contact region 307. Each p ⁻ channel region 306 a and 306 b is in contact with n ⁻ region 308.

The impurity concentration and thickness of the p ^- channel regions 306a and 306b may be 5 × 10 ¹⁵ cm ⁻³ and 0.3 μm, respectively. The channel width may be 1.0 μm.
The impurity concentration and thickness of the n ⁺ source regions 305a and 305b may be, for example, 1 × 10 ¹⁹ cm ⁻³ and 0.3 μm, respectively. The impurity concentration and thickness of the p + contact region 307 may be, for example, 1 × 10 ¹⁹ cm ⁻³ and 0.3 μm. The impurity concentration and thickness of the n ⁻ region 308 may be 8 × 10 ¹⁶ cm ⁻³ and 0.3 μm, and the width may be 4 μm. The horizontal widths of the other regions (n ⁺ source region, p ⁻ channel region, p + contact region) are the same as those in the first embodiment.

A gate electrode (control electrode) 311 is provided on the front surface of the p ⁻ channel regions 306a and 306b and the front surface of the n ⁻ region 308 via a gate insulating film 310, and both ends thereof are n ⁺ source. It extends over regions 305a and 305b. The thickness of the gate insulating film 310 may be about 650 angstroms. The source electrode (input electrode) 313 is in contact with the n ⁺ source regions 305 a and 305 b and also in contact with the p ⁺ contact region 307. The source electrode 313 is insulated from the gate electrode 311 by the interlayer insulating film 312.

The n ⁺ source regions 305a and 305b, the p ⁻ channel regions 306a and 306b, the n ⁻ region 308, the n ⁻ drift layer 303, and the n ⁺ substrate 302 constitute a vertical MOSFET portion.
Further, the n ⁺ source region 305b, the p body region 304b, and the n ⁻ drift layer 303 constitute a vertical BJT portion, and each also functions as an n ⁺ emitter, a p base, and an n ⁻ collector. The base electrode 314 is in contact with the p ⁺ base contact region 309 and is connected to the p base region 304b through this. The impurity concentration and thickness of the p ⁺ base contact region 309 may be, for example, 1 × 10 ¹⁹ cm ⁻³ and 0.1 μm.
The source / emitter electrode 313 and the base electrode 314 are insulated by an insulating region 315. Further, the p body region 304b, the n ⁻ region 308 and the n ⁻ drift layer 303, the p ⁻ channel region 306a and the p body region 304a, and the n ⁺ source region 305a constitute a lateral IGBT portion, and each includes a p collector, Functions as n-base, p-base, and n-emitter.

The AlGaN layer is used to increase the emitter injection efficiency of the vertical BJT part and increase the current amplification factor. That is, the junction between the AlGaN emitter region and the SiC base region is made a heterojunction, and the injection of holes from the SiC base region having a small energy gap to the AlGaN emitter region having a large energy gap is suppressed to occupy the base current. The injection efficiency is increased by increasing the ratio of the electron current.
In order to suppress the injection of holes from the base region to the emitter region and increase the injection efficiency, the larger the energy gap of AlGaN, the better. The energy gap of AlGaN can be changed by the composition ratio of Ga and Al, and can be increased as the ratio of Ai is increased. However, if the ratio of Ai is excessively increased, the interstitial disparity with the SiC crystal increases, the crystal quality of the junction deteriorates, and recombination of carriers at the junction increases, so that the injection efficiency decreases. . The ratio of Ga to Al is preferably between 95% to 5% and 65% to 35%, and in this embodiment is 80% to 20%. In order to suppress the adverse effect caused by the interstitial gap between the crystals in the AlGaN region and the SiC region, a buffer layer (not shown) has a small crystal interstitial gap with SiC, such as a thin GaN layer, between the two regions. Or the like is used.

Moreover, since the emitter injection efficiency can be increased by using a heterojunction as described above, even if the impurity concentration in the base region is increased to some extent, the injection efficiency can be higher than in the case of a normal junction. As a result, since the base resistance can be reduced to some extent, the maximum operating frequency can be increased, and punch-through in the base region can be suppressed, so that a high breakdown voltage can be achieved. Therefore, in the present embodiment, the impurity concentration of p body regions 304a and 304b is increased to 3 × 10 ¹⁸ cm ⁻³ .

In the manufacturing process of the wide gap semiconductor device 300, the n drift layer 303 is epitaxially grown and the p body regions 304a and 304b are selectively formed by ion implantation of aluminum in the manufacturing process of the first embodiment. the p ^- thickness 0.3μm to be a channel region ^p - points forming an AlGaN layer epitaxial growth (including epitaxial growth of the buffer layer), in forming the main electrode 313 and base electrode 314, the electrode 313 and the n This is substantially the same except that a well-known AlGaN ohmic contact film is interposed in each region in order to improve electrical connection between the p-type AlGaN region and the p-type AlGaN region. In the p ⁻ AlGaN layer, an n ⁺ source 305a, an n ⁺ emitter / source 305b, an n ⁻ region 308, and a p ⁺ contact region 307 are formed by selective ion implantation as in the manufacturing process of the first embodiment. .

Next, characteristics of the wide gap semiconductor device 300 according to the third embodiment will be described.
When a forward voltage is applied between the source / emitter electrode 314 and the drain / collector electrode 301 in a state where no MOS gate voltage is applied, a leakage current flows, but a good forward blocking characteristic is exhibited, and a breakdown voltage at room temperature, ie, avalanche breakdown Was about 5.1 kV. The leakage current before avalanche breakdown was as good as 2 × 10 ⁻³ A / cm ² or less at room temperature and 7 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.

A gate voltage higher than the threshold voltage is applied to the gate electrode 311, then a forward voltage Vsd is applied between the drain / collector electrode 301 and the source / emitter electrode 313, and a gate voltage 20 V higher than the threshold voltage is applied to the gate electrode 211. When applied, an on-current flows. The on-current density Jsd at a forward voltage Vsd of 5 V is 74 A / cm ^2, which is good for a 4.5 kV class device. In this state, only two vertical MOSFET sections in the cell are operating.

Next, a base voltage Vbe is applied between the base electrode 314 and the source / emitter electrode 313 so that the potential of the base electrode 314 becomes high. When Vsd is 5V, JSD the Vbe is 1.0V is JSD In 81A ^/ cm 2, Vbe is 2.0V is JSD In 88A ^/ cm 2, Vbe is 2.5V is 94A / cm ^2. As Vbe increases, Jsd increases. As described above, this is because the width of the depletion layer at the junction between the MOS inversion channel and the channel of the parasitic JFET and the p ^- channel regions 306a and 306b, and the junction between the channel of the parasitic JFET and the base region / body regions 304a and 304b. It is considered that the on-resistance is reduced because the width of the channel is increased by narrowing the width of the depletion layer according to the increase of Vbe.

Further, when Vbe reaches 3.0 V, Jsd increases rapidly to 208 A / cm ^{2. When} Vbe is 4.0 V, Jsd increases to 257 A / cm ² , and when Vbe reaches 5.0 V, Jsd further increases to 301 A / cm ² . As described above, when Vbe is about 2.7 V or more, carriers are injected from the emitter regions 305a and 305b into the base region / body regions 304a and 304b, the base current flows, and the vertical BJT portion is turned on. It is considered that a large collector current obtained by amplifying the base current by the current amplification factor of the vertical BJT portion flows in the drift region 303 below the region / body regions 304a and 304b. Making the width of the emitter region larger than the width of the source region also contributes to increasing the current amplification factor.
Also, when Vbe is 4.0 V or more, as described above, holes, which are minority carriers, are injected into the drift region 303 and diffused from the base region / body region 304b that functions as a collector when the lateral IGBT portion is turned on. It is considered that the conductivity of the drift region and the n region 308 is modulated and the resistance of these regions is reduced. Increasing the minority carrier lifetime by carbon implantation also contributes to further promoting conductivity modulation.

As described above, in the case of the third embodiment, the Jsd can be further greatly increased and significantly reduced by making the emitter junction of the vertical BJT portion in the cell a heterojunction as compared with the first embodiment. A wide gap semiconductor device with low on-resistance and low power consumption has been realized.
In addition, since the emitter junction is a heterojunction, the impurity concentration in the base region can be increased as described above, and a high breakdown voltage of 4.5 kV class can be easily achieved, as compared with the case where the emitter junction is formed by a normal junction. A maximum operating frequency of 350 kHz or higher was achieved.

In the wide gap semiconductor device according to the present embodiment, if an operation test is performed for 10 hours and 50 times for a total of 500 hours with the above-described pulse current of Jsd150 A / cm ² and a pulse width of 500 μs, the semiconductor device is damaged at the start of an intermediate operation test. Occurs at a certain frequency.
In addition, even in the operation test of 25 hours for 10 hours and 250 hours in total, the on-voltage at Jsd100A / cm ² was about 5V before the start of the first test was 15V or more, and the on-voltage degradation was wide as 10V. Semiconductor devices were also generated.

However, when the operation method according to the present invention is applied to these wide gap semiconductor devices, the on-state voltage at the above Jsd100 A / cm ² is 6.5 V or less after the operation test of 25 times for 10 hours and 25 hours in total. The on-voltage degradation could be suppressed to 1.5V or less. In addition, even if the operation test was performed 50 times for 10 hours and a total of 500 hours, no semiconductor device was damaged at the start of the intermediate operation test.

As described above, according to the semiconductor device according to the third embodiment, a highly reliable wide gap semiconductor device and its operation method can be realized, and an emitter junction can be provided as compared with the semiconductor device according to the first embodiment. By using a heterojunction, the current amplification factor of the vertical BJT portion can be increased, and a wide-gap semiconductor device with lower power consumption and lower power consumption can be realized.

Embodiment 4

FIG. 4 is a cell cross-sectional view schematically showing a wide gap semiconductor device having a design withstand voltage of 10 kV according to the fourth embodiment.
An n ⁺ 4H—SiC substrate 402 is provided in contact with the collector electrode 401 of the wide gap semiconductor device 400. An n ⁻ drift layer 403 made of 4H—SiC is formed on the front surface of the n ⁺ 4H—SiC substrate 402. The impurity concentration and thickness of the n ⁻ drift layer 403 may be, for example, 6 × 10 ¹⁴ cm ⁻³ and 120 μm. Alternatively, a drift layer in which carbon atoms are implanted at 2 × 10 ²⁰ atoms / cm ³ in order to increase the lifetime of minority carriers may be used.

P body regions 404 a and 404 b are selectively provided on the surface of n ⁻ drift layer 403. The impurity concentration and thickness of these p body regions may be, for example, 8 × 10 ¹⁷ cm ⁻³ and 0.6 μm, respectively. The p body regions 404a and 404b are layers formed by, for example, aluminum ion implantation.

On the front surface layer of p body regions 404a and 404b, n ⁺ source regions 405a and 405b and a p + contact region 407 are selectively provided.

The impurity concentration and thickness of the n ⁺ source regions 405a and 405b may be, for example, 1 × 10 ¹⁹ cm ⁻³ and 0.3 μm, respectively. In this case, the thicknesses of the p body regions 404a and 404b between the n ⁺ source regions 405a and 405b and the n ⁻ drift layer 403 are 0.3 μm.
The impurity concentration and thickness of the p ^{+ contact} region 407 may be, for example, 1 × 10 ¹⁹ cm ⁻³ and 0.4 μm. The horizontal widths of the n ⁺ source region 405a and the p + contact region 407 may be, for example, 2.5 μm and 1 μm, respectively. The interval between the n ⁺ source regions 405a and 405b and the n ⁻ drift layer 403 may be 1 μm. The interval between p body regions 404a and 404b may be 5 μm.

On the front surfaces of p body regions 404a and 404b and n ⁻ drift layer 403 between n ⁺ source regions 405a and 405b, an n ⁻ channel region 406 is provided, and both ends thereof are n ⁺ source region 405a and It extends over 405b. The impurity concentration and thickness of the n ⁻ channel region 406 may be 2 × 10 ¹⁵ cm ⁻³ and 0.3 μm, respectively. A gate electrode 411 is provided on the n ⁻ channel region 406 with a gate insulating film 410 interposed therebetween.
The thickness of the gate insulating film 410 may be about 650 angstroms. The source / emitter electrode 413 is in contact with the n ⁺ source regions 405 a and 405 b and also in contact with the p ⁺ contact region 407. The source / emitter electrode 413 is insulated from the gate electrode 411 and the interlayer insulating film 412.

The n ⁺ source regions 405 a and 405 b, the n ⁻ channel region 406, the n ⁻ drift layer 403, and the n ⁺ substrate 402 constitute an accumulation type vertical SiC-MOSFET portion. Therefore, when the vertical SiC-MOSFET portion is in the OFF state, it is important that the n ⁻ channel region 406 under the gate electrode 411 and over the p body regions 404a and 404b is completely depleted and pinched off.

Further, the n ⁺ source region 405b, the p body region 404b, and the n ⁻ drift layer 403 constitute a vertical SiC-BJT portion, and each also functions as an n ⁺ emitter, a p base, and an n ⁻ collector. The base electrode 414 is in contact with the p ⁺ base contact region 409 and is connected to the p base 404b through this. The impurity concentration and thickness of the p ⁺ base contact region 409 may be, for example, 1 × 10 ¹⁹ cm ⁻³ and 0.1 μm.
In addition, the source electrode 413 and the base electrode 414 that also function as an emitter electrode are insulated by an insulating region 415.
The p body region 404b, the n ⁻ drift layer 403, the p body region 404a, and the n ⁺ source region 405a constitute a lateral SiC-IGBT, and each functions as a p collector, n base, p base, and n emitter. To do.

Next, characteristics of the semiconductor device according to the fourth embodiment will be described.
When the forward blocking characteristic is measured under the same conditions as in the first embodiment, the breakdown voltage at room temperature, that is, the voltage indicating avalanche breakdown is about 10.7 kV. The leakage current before avalanche breakdown is as good as 4.5 × 10 ⁻³ A / cm ² or less at room temperature and 7 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.

The source / emitter electrode 413 and the base electrode 414 are electrically connected to have the same potential, a forward voltage Vsd is applied between the drain / collector electrode 411 and the source / emitter electrode 413, and a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 411. When 20V is applied, an on-current flows. When the forward voltage Vsd is 5 V, the on-current density Jsd is 35 A / cm ² , which is favorable as a 10 kV class high voltage semiconductor device. In this state, only the two vertical SiC-MOSFET sections in the cell are operating.

In this state, a base voltage Vbe is applied between the base electrode 414 and the source / emitter electrode 413 so that the potential of the base electrode 414 becomes high. When Vsd is 5 V, Jsd is 39 A / cm ² when Vbe is 1.0 V, Jsd is 42 A / cm ² when Vbe is 2.0 V, and Jsd is 45 A / cm ² when Vbe is 2.5 V. Jsd increases as Vbe increases. As described above, the width of the channel is increased by narrowing the width of the depletion layer at the junction between the MOS accumulation channel and the channel of the parasitic JFET and the base region / body regions 404a and 404b according to the increase of Vbe. Therefore, it is considered that the on-resistance is reduced.

Further, when Vbe reaches 3.0 V, Jsd increases to 52 A / cm ^{2. When} Vbe is 4.0 V, Jsd increases to 64 A / cm ² , and when Vbe is 5 V, Jsd further increases to 74 A / cm ² . As described above, when Vbe is about 2.7 V or more, carriers are injected from the emitter regions 405a and 405b into the base region / body regions 404a and 404b, the base current flows, and the vertical SiC-BJT part is turned on. It is considered that a large collector current obtained by amplifying the base current by the current amplification factor of the vertical BJT flows in the drift region 403 below the base region / body regions 404a and 404b. When Vbe is 4.0 V or more, as described above, the lateral SiC-IGBT portion is turned on and the base region / body regions 404a and 404b functioning as collectors are transferred to the channel region and the drift region 403 of the parasitic junction FET. It is considered that minority carrier holes are injected and conductivity modulation occurs in these channel regions and drift regions, so that the resistance of these regions decreases.

In addition, the fourth embodiment can significantly reduce the on-resistance as described above, and can greatly reduce the variation in channel width as compared with the first embodiment. This is because the storage MOSFET structure of this embodiment can accurately align the photoetching process of the n ⁺ source region 405a (and 405b) with respect to the p body region 404a (and 404b). As a result of reducing the variation in the accumulation channel width, the channel is shortened due to the variation, and therefore, it is possible to prevent the leakage current from increasing or the breakdown voltage from being lowered.

In the wide gap semiconductor device according to the present embodiment, if an operation test is performed for 10 hours and 50 times for a total of 500 hours with a pulse current of Jsd 50 A / cm ² and a pulse width of 500 μs similar to the above, it is damaged at the start of an intermediate operation test. Semiconductor devices occur at a certain frequency.
Also, in the operation test of 25 hours for 10 hours and 250 hours in total, the on-voltage at Jsd50A / cm ² was about 5V before the start of the first test was 14V or more, and the on-voltage degradation was 9V. Semiconductor devices were also generated.

However, when the operation method according to the present invention is applied to these wide gap semiconductor devices, the on-voltage at the above Jsd50 A / cm ² is 6 V or less after the operation test of 25 times for 10 hours and a total of 250 hours. The deterioration could be suppressed to 1V or less. In addition, even if the operation test was performed 50 times for 10 hours and a total of 500 hours, no semiconductor device was damaged at the start of the intermediate operation test.
In addition, when the operation method according to the present invention is applied, an inverter is configured using the wide gap semiconductor device of the present embodiment, and an operation test is started in the middle even if an operation test is performed for 10 hours and 50 times for a total of 500 hours. No semiconductor device was occasionally damaged.

As described above, according to the semiconductor device according to the fourth embodiment, as in the semiconductor device according to the first embodiment, a wide-gap semiconductor device with low on-resistance and low power consumption and high reliability, and its In addition to realizing the operation method, it is possible to realize a wide-gap semiconductor device in which variation in channel width can be reduced as compared with the semiconductor device according to the first embodiment, and leakage current is increased and breakdown voltage is reduced.

Although the present invention has been described based on the first to fourth embodiments, the present invention is not limited to these, and it is obvious to those skilled in the art that various modifications can be easily made. For example, various shapes such as a mesh shape can be adopted in addition to the stripe shape that also refers to the cell shape. In addition, although the n-type wide gap semiconductor device has been described, it is obvious that it can be similarly applied to p-type wide gap semiconductor devices having different polarities. Furthermore, it is obvious to those skilled in the art that the vertical MOSFET portion can be modified and applied to other MOSFET structures such as a simple DMOSFET structure or a trench gate type MOSFET structure. Also, the SiC semiconductor device has been mentioned, but it can be applied to wide gap semiconductor devices using other wide gap semiconductors such as GaN and diamond, and other heterojunctions such as heterojunction type BJT parts composed of GaN and AlGaN. The present invention can be applied to a wide gap semiconductor device using a type BJT section.

The present invention can be widely used in inverters and power converters of various voltage classes for consumer and industrial use, and can greatly reduce low power consumption and improve reliability. In particular, a significant reduction in low power consumption not only contributes to energy savings, but in the case of inverters and power converters with the same output, it is possible to reduce the size of the device that cools the required semiconductor devices, which can also contribute to resource savings. .
In particular, it has a large use impact in various applications where it is necessary to output a large amount of electric power instantly and respond to special situations during steady operation. For example, an inverter of a mobile device such as an electric car, a train or an electric ship is configured with the wide gap semiconductor device of the present invention, and during normal operation, it operates only with the MOSFET part and enjoys low power consumption, while avoiding a collision. In such a special case, the base voltage is increased to drive the bipolar element portion to produce a large output for a short time. In this case, it is possible to suppress an increase in switching loss caused by residual carriers at the time of off and a decrease in reliability caused by stacking faults due to the bipolar operation at the time of high output.

101, 201, 301, 401: Drain and collector electrodes 102, 202, 302, 402: n ⁺ 4H—SiC substrates 103, 203, 303, 403: n ⁻ drift layers 104a, 204a, 304a, 404a: p body regions 104b, 204b, 304b, 404b: p body region / base regions 105a, 205a, 305a, 405a: n ⁺ source regions 105b, 205b, 305b, 405b: n ⁺ source region / emitter regions 106a, 206a, 306a, 406a: p ^- channel region 106b, 206b, 306b, 406b: p - channel region 107,207a, 207b, 307,407: ^{p +} contact region 108, 208, 308: n ^- region
109, 309, 409: base contact regions 110, 210, 310, 410: gate insulating films 111, 211, 311, 411: gate electrodes 112, 212, 312, 412: interlayer insulating films 113, 213, 313, 413: sources Electrode and emitter electrodes 114, 214a, 214b, 314, 414: base electrodes 115, 215a, 215b, 315, 415: insulating regions 216a, 216b: insulating isolation regions

Claims (8)

A wide gap semiconductor device built in the cell
A first conductivity type first semiconductor layer; a first conductivity type second semiconductor layer provided on a front surface of the first conductivity type first semiconductor layer; and a first conductivity type second semiconductor layer. Two first semiconductor regions of the second conductivity type selectively provided on the front surface;
A first conductivity type third semiconductor region selectively provided on the front surface of one second conductivity type first semiconductor region, and a second conductivity type selectively provided in contact with the region. A first conductive type fourth semiconductor region selectively provided on the front surface of the second semiconductor region and the other second conductive type first semiconductor region, and selectively provided separately from this region; And a first main electrode in contact with the third semiconductor region of the second conductivity type, the third semiconductor region of the first conductivity type, the second semiconductor region of the second conductivity type, and the fourth semiconductor region of the first conductivity type. When,
A surface of the second semiconductor region of the first conductivity type sandwiched between the two first semiconductor regions of the second conductivity type, a third semiconductor region of the first conductivity type, and a second of the first conductivity type. The surface of the second conductive type first semiconductor region sandwiched between the semiconductor layers and the second conductive layer sandwiched between the first conductive type fourth semiconductor region and the first conductive type second semiconductor layer. Provided on the surface of the first semiconductor region portion of the conductive type so that both ends thereof extend on the third semiconductor region of the first conductive type and the fourth semiconductor region of the first conductive type via an insulating film. A first control electrode formed;
A semiconductor device comprising: a second control electrode in contact with a surface of the second conductive type third semiconductor region; and a second main electrode in contact with a back surface of the first conductive type first semiconductor layer;
The first main electrode; the first conductive type third semiconductor region; the second conductive type second semiconductor region; the one second conductive type first semiconductor region; the first conductive type second semiconductor region. The semiconductor region, the first conductive type first semiconductor region, the second main electrode, and the first control electrode constitute a first vertical MOSFET portion,
The first main electrode, the first conductive type fourth semiconductor region, the other second conductive type first semiconductor region, the first conductive type second semiconductor region, and the first conductive type first semiconductor region. The semiconductor region, the second main electrode, and the first control electrode constitute a second vertical MOSFET section. The first main electrode, the first conductivity type fourth semiconductor region, and the second conductivity type The third semiconductor region, the second semiconductor layer of the second conductivity type, the second semiconductor region of the first conductivity type, the first semiconductor region of the first conductivity type, the second main electrode, the second main electrode, A vertical bipolar junction transistor portion is configured with two control electrodes, the second control electrode, the second conductive type third semiconductor region, the other second conductive type first semiconductor region, and the first conductive type. Type second semiconductor region, said one second conductivity type first semiconductor region, said first conductivity type third semiconductor region Conductor region, a wide-gap semiconductor device characterized in that it constitutes a lateral IGBT portion between the first main electrode, the first control electrode. The wide gap semiconductor device according to claim 1,
The one second conductive type first semiconductor region portion and the first conductive type fourth semiconductor sandwiched between the first conductive type third semiconductor region and the first conductive type second semiconductor layer. Lower than the first semiconductor region of the second conductivity type formed by epitaxial growth in the second semiconductor layer portion of the other second conductivity type sandwiched between the region and the second semiconductor layer of the first conductivity type. A second conductivity type fourth semiconductor region and a second conductivity type fifth semiconductor region having an impurity concentration are provided;
In the vicinity of the surface of the first conductive type second semiconductor region sandwiched between the two second conductive type first semiconductor regions, the impurity concentration is higher than that of the first conductive type second semiconductor region and A wide-gap semiconductor device, wherein a fifth semiconductor region of a first conductivity type that is thicker than the fourth semiconductor region of the second conductivity type and a fifth semiconductor region of a second conductivity type is provided.

The wide gap semiconductor device according to claim 1,
The insulating film, the second semiconductor region portion of the first conductivity type sandwiched between the two first semiconductor regions of the second conductivity type, the third semiconductor region of the first conductivity type, and the first conductivity type The second conductivity type first semiconductor region portion sandwiched between the second semiconductor layers and the second conductivity type sandwiched between the first conductivity type fourth semiconductor region and the first conductivity type second semiconductor layer. Between the surface of the first semiconductor region portion of
A sixth semiconductor region of the second conductivity type is interposed, and both ends are provided to extend on the third semiconductor region of the first conductivity type and the fourth semiconductor region of the first conductivity type. Wide gap semiconductor device. In the wide gap semiconductor device according to claims 1 to 3,
A wide gap semiconductor device, wherein a width of the fourth semiconductor region of the first conductivity type is larger than a width of the third semiconductor region of the first conductivity type. In the wide gap semiconductor device according to claims 1 to 3,
A wide gap semiconductor device, wherein a crystal orientation of a side surface of the fourth semiconductor region of the first conductivity type is {1-100}. In the wide gap semiconductor device according to claim 1 and claim 2,
At least the fourth semiconductor region of the first conductivity type is formed of a wide gap semiconductor having a wider energy gap.   At least when operating, the unipolar semiconductor element incorporated in the wide gap semiconductor device is operated to pass a forward current due to majority carriers, the temperature of the wide gap semiconductor device is raised to 50 ° C. or more by this current, and then the built-in bipolar semiconductor The operation method of the wide gap semiconductor device according to claim 1, wherein the element portion is operated. 8. The method of operating a semiconductor device according to claim 7, wherein a pn junction diode used as a flywheeling diode is included in the bipolar semiconductor element portion incorporated in the wide gap semiconductor device.