JP2013222753A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which an occurrence frequency of a defective post electrode is low.SOLUTION: A semiconductor device comprises: wiring 109 provided on a semiconductor substrate; and a columnar post electrode 213 having a bottom connected to the wiring 109, a crown on the opposite side to the bottom, and a lateral face which links the bottom and the crown. The post electrode 213 includes a first post electrode 213a formed by plate processing and a second post electrode 213b formed on the first post electrode by plate processing. On the lateral face of the post electrode 213, an outer circumference protrusion 240 which is longer in a circumferential direction at a height higher than a bonding position 230 of the first post electrode 213a and the second post electrode 213b is formed.

Description

  The present invention relates to a semiconductor device, and more particularly to a post electrode thereof.

  In recent years, with the downsizing of electronic devices such as mobile phones and digital cameras, there is a strong demand for reducing the size of semiconductor devices mounted on electronic devices. In particular, the wafer level chip size package (WL-CSP) can reduce the package size to the chip size, and a WL-CSP in which components are mounted in a sealing resin is also being studied.

For example, Patent Document 1 (Japanese Patent Laid-Open No. 2002-299996) discloses a process of forming a post electrode in which copper (Cu) layers are stacked in two stages, and a process of mounting a capacitor portion as a component in a sealing resin. A method for manufacturing a semiconductor device is disclosed. However, in the formation of the post electrode of Patent Document 1, as shown in the flowchart of FIG.
(A) As a step for forming the first Cu layer, a first resist film is formed on the conductive film on the semiconductor wafer (Step S101), and holes are formed by exposure and development (Steps S102 and S103). ), Formation of the first Cu layer by plating (step S104), removal of the first resist film (step S105), temporary sealing of the first Cu layer (step S106), first Cu layer CMP processing (step S107) is performed on the layer and the temporary sealing layer,
(B) As a step for forming the second Cu layer, a second resist film is formed (Step S108), a hole is formed by exposure and development (Steps S109 and S110), and a second layer is formed by plating. Formation of Cu layer (step S111), removal of second resist film (step S112), temporary sealing of second Cu layer (step S113), CMP treatment for second Cu layer and temporary sealing layer (Step S114)
(C) As steps for mounting components, removal of temporary sealing (step S115), formation of a capacitor portion (step S116), sealing with an insulating layer (step S117), CMP processing for the capacitor portion and the insulating layer (step) S118), forming electrodes and solder bumps (step S119).

  Patent Document 2 (Japanese Patent Laid-Open No. 2004-172163) discloses a structure in which an upper post electrode is stacked on a lower post electrode.

JP 2002-299596 A JP 2004-172163 A

  In the semiconductor device described in Patent Document 1, the boundary position between the first temporary sealing layer and the second resist film coincides with the bonding position between the first and second Cu layers. An annular raised portion extending in the circumferential direction on the side surface of the Cu post electrode composed of the first and second Cu layers at the boundary position between the first temporary sealing layer and the second resist film Is easily formed.

  In the semiconductor device described in Patent Document 2, the peripheral length of the second layer post electrode is shorter than the peripheral length of the first layer post electrode. A step (step shape) is formed at the same position as the post electrode joining position.

  As in Patent Documents 1 and 2, when a raised portion or a step of the post electrode is formed at the same position as the bonding position of the Cu layer (post electrode) having a relatively low mechanical strength, the inside generated due to the warp of the substrate or the like There is a problem that the frequency of occurrence of defects in which the post electrode is pulled out or broken due to the stress acting on the raised portion or the stepped portion.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with a low occurrence frequency of defective post electrodes.

  A semiconductor device according to the present invention includes a wiring provided on a semiconductor substrate, a bottom connected to the wiring, a top opposite to the bottom, and a columnar post electrode having a side surface connecting the bottom and the top. And the post electrode includes a first post electrode formed by plating, and a second post electrode formed on the first post electrode by plating, and the post electrode An outer peripheral projection that is long in the circumferential direction is formed on the side surface at a position higher than the joining position of the first post electrode and the second post electrode.

  According to the present invention, it is possible to reduce the occurrence frequency of defective products of post electrodes of a semiconductor device.

It is a flowchart which shows the formation method of the post electrode of a prior art example. It is a flowchart which shows the manufacturing method of the semiconductor device of a comparative example. (A)-(i) is a schematic sectional drawing (the 1) which shows the process of the manufacturing method of the semiconductor device of a comparative example. (A)-(d) is a schematic sectional drawing (the 2) which shows the process of the manufacturing method of the semiconductor device of a comparative example. It is a schematic sectional drawing which shows the semiconductor device of a comparative example. 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention. (A)-(e) is a schematic sectional drawing (the 1) which shows the process of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. (A)-(d) is a schematic sectional drawing (the 2) which shows the process of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. (A)-(c) is a schematic sectional drawing (the 3) which shows the process of the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. (A) is a figure which shows the aspect-ratio of a comparative example, (b) and (c) are figures which show the aspect-ratio in Embodiment 1. FIG. (A) is a figure which shows the plating process in a comparative example, (b) And (c) is a figure which shows the plating process in Embodiment 1. FIG. It is a figure which shows the problem of a comparative example. 3 is a schematic cross-sectional view showing a post electrode of the semiconductor device according to the first embodiment. FIG. It is a principal part enlarged view of FIG. It is a flowchart which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. (A)-(d) is a schematic sectional drawing (the 1) which shows the process of the manufacturing method of the semiconductor device which concerns on Embodiment 2. FIG. (A)-(d) is a schematic sectional drawing (the 2) which shows the process of the manufacturing method of the semiconductor device which concerns on Embodiment 2. FIG. (A) And (b) is a schematic sectional drawing (the 3) which shows the process of the manufacturing method of the semiconductor device which concerns on Embodiment 2. FIG. FIG. 10 is a plan view schematically showing slits formed in the method for manufacturing a semiconductor device according to the second embodiment. 10 is a flowchart showing a method for manufacturing a semiconductor device according to a modification of the second embodiment. (A)-(e) is a schematic sectional drawing (the 1) which shows the process of the manufacturing method of the semiconductor device which concerns on the modification of Embodiment 2. FIG. (A)-(d) is a schematic sectional drawing (the 2) which shows the process of the manufacturing method of the semiconductor device which concerns on the modification of Embodiment 2, (e) is another example of (d). . (A)-(d) is a schematic sectional drawing (the 3) which shows the process of the manufacturing method of the semiconductor device which concerns on the modification of Embodiment 2. FIG. It is a side view which shows roughly the curvature of the semiconductor wafer which may arise when two sheets of dry films are piled up and affixed on a semiconductor wafer. It is a side view which shows roughly the dry film peeling which may occur when two dry films are piled up and affixed on a semiconductor wafer. It is a side view which shows roughly the surplus Cu formed in a peeling part at a plating process, when dry film peeling arises. (A) is a figure which shows a normal plating process, (b) is a figure which shows the problem which a dry film piece blocks a hole.

  First, a comparative example used for describing the embodiment will be described, and subsequently, Embodiments 1 and 2 will be described. In the comparative example and the first and second embodiments, in WL-CSP, when a component is mounted on a rewiring and the component is sealed with a mold resin (sealing resin), the mold resin is penetrated in the thickness direction. The post electrode thus formed and a method for forming the same

<< 1 >> Comparative Example FIG. 2 is a flowchart showing a method of manufacturing a semiconductor device of a comparative example. FIGS. 3A to 3I are schematic cross-sectional views (part 1) illustrating steps of a method for manufacturing a semiconductor device of a comparative example, and FIGS. 4A to 4D are diagrams of the semiconductor device of the comparative example. FIG. 4 is a schematic cross-sectional view (No. 2) showing a step of the manufacturing method, and FIG. 4D shows a step following FIG. FIG. 5 is a schematic cross-sectional view showing a semiconductor device of a comparative example. Hereinafter, a method for manufacturing a semiconductor device of a comparative example will be described with reference to the drawings.

  FIG. 3A shows a semiconductor wafer in a state where a wafer process is completed by performing a diffusion process or the like. In FIG. 3A, a wiring 102 and an interlayer insulating film 103 are formed on a semiconductor wafer 101, and a via (VIA) 104 connected to the wiring 102 is formed in the interlayer insulating film 103. And a passivation film 106 that covers the interlayer insulating film 103 is formed.

  Next, as illustrated in FIG. 3B, a lower insulating film 107 is formed, and an opening is formed in the lower insulating film 107 in accordance with the opening of the passivation film 106.

  Next, as shown in FIG. 3C, an UBM (Under Barrier Metal) film 108 is formed on the entire surface of the wafer. Further, using a photoresist technique, a resist film (not shown) is formed on the entire surface of the wafer, a rewiring pattern portion is opened, and rewiring 109 is formed only on the opening portion of the resist film using electroplating. Thereafter, the resist film is removed by ashing.

  Next, as shown in FIG. 3D, a first-layer photoresist dry film 110 is attached to the entire surface of the wafer on which the rewiring 109 is formed (step S201 in FIG. 2), and A second-layer photoresist dry film 111 is pasted on the first-layer photoresist dry film 110 (step S202 in FIG. 2). In the following description, the photoresist dry film is also simply referred to as “dry film”. Moreover, the thickness of the dry film is, for example, 120 μm.

  Next, as shown in FIG. 3E, exposure and development are performed on the desired rewiring 109 using a lithography technique, and the first dry film 110 and the second dry film 111 are thickened. An opening (hole) 112 penetrating in the vertical direction is formed (steps S203 and S204 in FIG. 2).

  Next, as shown in FIG. 3F, post electrodes (columnar electrodes) 113 made of Cu are formed in the openings 112 by plating (electroplating). In FIG. 3, the post electrode 113 is formed only in the opening 112 of the dry film (step S205 in FIG. 2).

  Next, as shown in FIG. 3G, the second and first dry films 111 and 110 are removed by chemical treatment, and the UBM film 108 is partially removed using the rewiring 109 as a blocking film (see FIG. 3G). Step S206 in FIG.

  Next, as shown in FIG. 3H, the component 114 is mounted on the rewiring 109 (step S207 in FIG. 2). The component 114 is an electronic component such as a light emitting element or a light receiving element, and there is no limitation on the type and quantity thereof.

  Thereafter, as shown in FIGS. 3I and 4A, the entire surface of the wafer is sealed with the mold resin 115 (step S208 in FIG. 2).

  Next, as shown in FIG. 4B, in the Si wafer 120 that has been sealed with the mold resin 115, the mold resin 115 is ground by CMP to expose the post electrode 113 (step S209 in FIG. 2). ). At this time, the post electrode 113 is formed so that the top of the post electrode 113 is positioned higher than the top of the component 114. It is possible to increase the height of the post electrode 113 by increasing the number of dry films.

  Thereafter, as shown in FIG. 4C, the solder paste 117 is printed on the post electrode 113 using the solder mask 116 as a mask, and a reflow process is performed after the solder mask is removed as shown in FIG. 4D. Then, a hemispherical solder terminal 118 is formed (step S210 in FIG. 2).

  Through the above steps, in the WL-CSP, the component is mounted on the rewiring, and the semiconductor device shown in FIG. 5 in which the component is sealed with the mold resin is completed.

<< 2 >> Embodiment 1
<< 2-1 >> Manufacturing Method of First Embodiment FIG. 6 is a flowchart showing a manufacturing method of a semiconductor device according to the first embodiment. FIGS. 7A to 7E are schematic cross-sectional views (part 1) illustrating steps of the method of manufacturing a semiconductor device according to the first embodiment, and FIGS. FIGS. 9A to 9C are schematic cross-sectional views illustrating the steps of the semiconductor device manufacturing method according to the first embodiment, and FIGS. 9A to 9C are schematic cross-sectional views illustrating the steps of the semiconductor device manufacturing method according to the first embodiment; FIGS. It is a figure (the 3). FIG. 8A shows a process following FIG. 7E, and FIG. 9A shows a process following FIG. 8D. 10 (a) to 10 (c) are schematic cross-sectional views showing the aspect ratio, and FIGS. 11 (a) to 11 (c) show plating steps in the structures of FIGS. 10 (a) to 10 (c). FIG.

  FIG. 7A shows the semiconductor wafer in a state where the diffusion process or the like is performed and the wafer process is completed. In FIG. 7A, a wiring 102 and an interlayer insulating film 103 are formed on a semiconductor wafer 101, and a via (VIA) 104 connected to the wiring 102 is formed in the interlayer insulating film 103. And a passivation film 106 that covers the interlayer insulating film 103 is formed.

  Next, as illustrated in FIG. 7B, a lower insulating film 107 is formed, and an opening is formed in the lower insulating film 107 in alignment with the opening of the passivation film 106.

  Next, as shown in FIG. 7C, the UBM film 108 is formed on the entire surface of the wafer. Further, using a photoresist technique, a resist film (not shown) is formed on the entire surface of the wafer, a rewiring pattern portion is opened, and rewiring 109 is formed only on the opening portion of the resist film using electroplating. Thereafter, the resist film is removed by ashing.

  Next, as shown in FIG. 7D, the first dry film 210 is attached to the entire surface of the wafer on which the rewiring 109 is formed (step S1 in FIG. 6).

  Next, as shown in FIG. 7E, an opening (hole) 212a penetrating through the first dry film 210 in the thickness direction is formed on the desired rewiring 109 using a lithography technique ( Steps S2 and S3) in FIG.

  Next, as shown in FIG. 8A, a post electrode 213a is formed by plating (electroplating) (step S4 in FIG. 6). The post electrode 213a is usually a copper (Cu) electrode, but may be another metal electrode (eg, gold, palladium, etc.). At this time, the post electrode 213a is formed only in the opening 212a of the first dry film 210. Further, as shown in FIG. 8A, the post electrode 213a is formed so that the upper surface of the post electrode 213a is lower than the upper surface 210a of the first dry film 210.

  Next, as shown in FIG. 8B, a second-layer dry film 211 is attached to the entire surface of the wafer (step S5 in FIG. 6).

  Next, as shown in FIG. 8C, the second dry film 211 is penetrated in the thickness direction over the opening (hole) 212 a of the first dry film 210 using a lithography technique. An opening (hole) 212b is formed (steps S6 and S7 in FIG. 6).

  Next, as shown in FIG. 8D, a second post electrode 213b is formed on the first post electrode by plating (electrolytic plating) (step S8 in FIG. 6). The post electrode 213b is usually a copper (Cu) electrode, but may be another metal electrode (eg, gold, palladium, etc.). At this time, the post electrode 213b is formed only in the opening 212b of the second dry film 211. The post electrode 213b is desirably formed higher than the upper surface of the second dry film 211. When many post electrodes 213b are formed on a semiconductor wafer, the plating speed may be different between the central portion and the peripheral portion of the semiconductor wafer. It is formed to be higher. A combination of the post electrodes 213a and 213b is referred to as a post electrode 213.

  However, when three or more layers of dry films are used, the upper surface of the second layer post electrode 213b is formed lower than the upper surface of the second layer dry film, like the first layer post electrode 213a. .

  Next, as shown in FIG. 9A, the second and first dry films 211 and 210 are removed by a chemical treatment (step S9 in FIG. 6), and the UBM film 108 with the rewiring 109 as a blocking film. Is partially removed.

  Next, as shown in FIG. 9B, the component 214 is mounted on the rewiring 109 (step S10 in FIG. 6). The component 214 is a light emitting element, a light receiving element, or a chip or packaged electronic component such as an oscillation element or a sensor, and the type and quantity thereof are not limited.

  Thereafter, as shown in FIG. 9C, the entire wafer surface is sealed with a mold resin 215 (step S11 in FIG. 6). Thereafter, the same processes as in FIGS. 3A to 3D are performed (steps S12 and S13 in FIG. 6). Through the above steps, in WL-CSP, a semiconductor device in which a component is mounted on a rewiring and the component is sealed with a mold resin is completed.

<< 2-2 >> Effect of Embodiment 1 FIG. 10A shows the aspect ratio (opening depth / opening width) of the hole of the comparative example, and FIGS. 10B and 10C show the implementation. The aspect ratio of the hole in form 1 is shown. In the first embodiment, the first dry film 210 is used as a plating process mask for forming the post electrode, and the post electrode 213a is formed. Then, the post electrode 213b is used as the second dry film 211 as a mask. By forming, the post electrode 213 having a high height is formed. Thus, by dividing the post electrode forming process into two, the aspect ratio of the dry film in the post electrode plating process can be reduced as compared with the comparative example shown in FIG.

  As shown in FIG. 11A, in the case of a hole having a high aspect ratio, when a Cup type plating apparatus having no deaeration mechanism is used in the plating process, it is very difficult to remove bubbles remaining in the opening. It is difficult to. Bubbles remaining in the openings of the dry films 110 and 111 become an obstruction factor for Cu plating, and post electrode plating in a state of embracing the bubbles is formed inside the post electrode 113 as shown in FIG. It will have a cavity. The cavity inside the post electrode 113 significantly reduces the strength and reliability of the post electrode 113, causing post electrode breakage in the process or product failure in the market.

  On the other hand, according to the manufacturing method of the first embodiment, as shown in FIGS. 11B and 11C, an inexpensive apparatus such as an apparatus having no deaeration mechanism or a Cup-type plating apparatus is used. However, since air bubbles easily escape from the opening, the post electrode (213 in FIG. 9C) having a height higher than that of the component 214 to be mounted can be formed in the post electrode 213 without a problem of a cavity. It becomes possible.

  In addition, by making the height of the upper portion of the post electrode 213a using the first layer dry film 210 as a mask lower than the upper surface of the first layer dry film, adhesion at the time of attaching the second layer dry film 211 is improved. It becomes possible to suppress the jump-out of the post electrode 213a that causes the decrease.

  Further, the development of the first dry film 210 tends to widen the pattern top. Thereby, a protrusion is generated at the interface between the first dry film 210 and the second dry film 211, and this protrusion has an effect of preventing the post electrode from coming off from the mold resin.

  As described above, according to the first embodiment, the post film plating process and the post electrode plating process are divided into two steps to form a high post electrode, so that even if an inexpensive apparatus is used, the post electrode is formed inside the post electrode. The height of the post electrode necessary for component mounting can be ensured without generating a cavity.

  FIG. 13 is a schematic cross-sectional view showing the post electrode 213 of the semiconductor device according to the first embodiment. FIG. 14 is an enlarged perspective view of the main part A of FIG. As shown in FIG. 13, a wiring 109 provided on a semiconductor substrate, a bottom connected to the wiring 109, a top opposite to the bottom, and a columnar post electrode 213 having a side surface connecting the bottom and the top. And have. In the first embodiment, the joint (joining position) 230 between the post electrode 213a and the post electrode 213b is the interface between the first dry film 210 and the second dry film 211 (this interface position is shown in FIG. As shown in the drawing, the ring-shaped outer circumferential protrusion (step) 240 is formed in the circumferential direction. By doing so, it is possible to prevent a decrease in adhesion that occurs when the second-layer dry film 211 is attached, and a post electrode level difference that occurs at the interface between the first-layer dry film and the second-layer dry film. Therefore, it is possible to suppress the post electrode from coming off from the mold resin.

  Further, the post electrode structure shown in FIGS. 13 and 14 is formed by using a third layer photoresist (not shown) on the second layer photoresist 211 and the second layer post electrode and the third layer. It is desirable to adopt the same when forming the post electrode of the eye.

<< 3 >> Embodiment 2
<< 3-1 >> Manufacturing Method of Second Embodiment FIG. 15 is a flowchart showing a method of manufacturing a semiconductor device according to the second embodiment. FIGS. 16A to 16D are schematic cross-sectional views (part 1) illustrating the steps of the method for manufacturing the semiconductor device according to the second embodiment, and FIGS. FIGS. 18A and 18B are schematic cross-sectional views illustrating the steps of the semiconductor device manufacturing method according to the second embodiment. FIGS. 18A and 18B are schematic cross-sectional views illustrating the steps of the semiconductor device manufacturing method according to the second embodiment. It is a figure (the 3). FIG. 17 (a) shows a process following FIG. 16 (d), and FIG. 18 (a) shows a process following FIG. 17 (d). Further, in FIGS. 16A to 16D, FIGS. 17A to 17D, and FIGS. 18A and 18B, the left diagram shows the region of the central portion (other than the outer peripheral portion) of the wafer. The right side shows an area close to the outer periphery of the wafer. FIG. 19 is a plan view schematically showing a slit formation example.

  FIG. 16A is formed by a process similar to the process of FIGS. 7A to 7C in the first embodiment.

  Next, as shown in FIG. 16B, a first-layer dry film 310 is attached to the entire surface of the wafer on which the rewiring 109 is formed.

  Next, as shown in FIG. 16C, an opening (hole) 312 a that penetrates the first dry film 310 in the thickness direction is formed on the desired rewiring 109 using the lithography technique. (Step S2 and Step S3 in FIG. 15).

  Next, as shown in FIG. 16D, the post electrode 313a is formed by plating (electrolytic plating) (step S4 in FIG. 15). At this time, the post electrode 313a is formed only in the opening 312a of the first dry film 310 (step S4 in FIG. 15). Further, the post electrode 313a is formed such that its upper surface is lower than the upper surface 310a of the first dry film 310.

  Next, as shown in FIG. 17A, a second-layer dry film 311 is attached to the entire surface of the wafer (step S5 in FIG. 15).

  Next, as shown in FIG. 17B, the second dry film 311 is penetrated in the thickness direction on the opening (hole) 312a of the first dry film 310 using a lithography technique. The opening (hole) 312b to be formed is formed, and the slit 320 which is a long groove is formed in the second dry film 311 (steps S21 and S22 in FIG. 15). For example, as shown in FIG. 19, the slits 320 may be formed in a lattice shape so as to surround one or more predetermined number of post electrodes. The purpose of forming the slit 320 is to make it difficult to cause a problem of internal stress (wafer warpage, etc.) caused by shrinkage of the dry film when the dry film is laminated and pasted on the semiconductor wafer. Therefore, the arrangement of the slits 320 is not limited to the example of FIG.

  Next, as shown in FIG. 17C, the second layer post electrode 313b is formed on the first layer post electrode 313a by using electroplating (step S8 in FIG. 15). At this time, the post electrode 313 b is formed in the opening of the second dry film 311. Further, the post electrode 313b is preferably formed such that the upper surface thereof is higher than the upper surface of the second dry film 311.

  Next, as shown in FIG. 17 (d), the second and first dry films 311 and 310 are removed by chemical treatment (step S9 in FIG. 15), and the UBM film 108 is formed using the rewiring 109 as a blocking film. Remove.

  Next, as shown in FIG. 18A, the component 314 is mounted on the rewiring 109 (step S10 in FIG. 15).

  Thereafter, as shown in FIG. 18B, the entire wafer surface is sealed with a mold resin 315 (step S11 in FIG. 15). Thereafter, the same processes as in FIGS. 3A to 3D are performed (steps S12 and S13 in FIG. 15). Through the above steps, in WL-CSP, a semiconductor device in which a component is mounted on a rewiring and the component is sealed with a mold resin is completed.

<< 3-2 >> Manufacturing Method of Modification of Second Embodiment FIG. 20 is a flowchart showing a manufacturing method of a semiconductor device according to a modification of the second embodiment. FIGS. 21A to 21E are schematic cross-sectional views (part 1) illustrating steps of a method for manufacturing a semiconductor device according to a modification of the second embodiment. FIGS. 22A to 22E are FIG. 23 is a schematic cross-sectional view (part 2) illustrating a process of the method for manufacturing a semiconductor device according to the modification of the second embodiment, and FIGS. 23A to 23D are semiconductor devices according to the modification of the second embodiment; It is a schematic sectional drawing (the 3) which shows the process of this manufacturing method. FIG. 22 (a) shows a process following FIG. 21 (e), and FIG. 23 (a) shows a process following FIG. 22 (d). Further, in FIGS. 21A to 21E, 22A to 22E, and 23A to 23D, the left diagram shows the region of the central portion (other than the outer peripheral portion) of the wafer. The right side shows an area close to the outer periphery of the wafer.

  FIG. 21A is formed by a process similar to the process of FIGS. 7A to 7C in the first embodiment.

  Next, as shown in FIG. 21B, a first dry film 410 is attached to the entire surface of the wafer on which the rewiring 109 is formed (step S1 in FIG. 20).

  Next, as shown in FIG. 21 (c), an opening (hole) 412a penetrating the first dry film 410 in the thickness direction is formed on the desired rewiring 109 using a lithography technique. A slit 57, which is a long groove, is formed in the first dry film 410, and a resist removal portion on the outer periphery of the wafer is formed (steps S31 and S32 in FIG. 20).

  Next, as shown in FIG. 21 (d), a resist 421 is applied to the entire surface of the wafer, and as shown in FIG. 21 (e), the resist 421 in the opening 412a for forming the post electrode is patterned and opened. (Step S33 in FIG. 20).

  Next, as shown in FIG. 22A, the post electrode 413a is formed by using electroplating. At this time, the post electrode 413a is formed only in the opening of the first dry film 410 (step S4 in FIG. 20).

  Next, as shown in FIG. 22B, the resist 421 at the outer periphery of the wafer is removed, and as shown in FIG. 22C, the second dry film is formed on the first dry film 410. 411 is pasted (step S5 in FIG. 20). At this time, in the outer peripheral portion of the wafer, it is also attached to the region (on the UBM film) where the first dry film 410 is removed.

  Next, as shown in FIG. 22D, the second dry film 411 is formed on the opening (hole) 412a and the slit 420 of the first dry film 410 by using a lithography technique. An opening (hole) 412b penetrating in the direction is formed (steps S34 and S35 in FIG. 20). At this time, instead of FIG. 22 (d), as shown in FIG. 22 (e), the second layer is used only on the opening (hole) 412a of the first dry film 410 by using a lithography technique. You may form the opening part (hole) 412b which penetrates the dry film 411 in the thickness direction.

  Next, as shown in FIG. 23A, the second layer post electrode 413b is formed on the first layer post electrode 413a by using electroplating (step S8 in FIG. 20). At this time, the post electrode 413b is formed in the opening 412b of the second dry film 411. The post electrode 413b is desirably formed higher than the upper surface of the second dry film 411.

  Next, as shown in FIG. 23B, the second and first dry films 411 and 410 are removed by chemical treatment, and the UBM film 108 is removed using the rewiring 109 as a blocking film (in FIG. 20). Step S9).

  Next, as shown in FIG. 23C, the component 414 is mounted on the rewiring 109 (step S10 in FIG. 20).

  Thereafter, as shown in FIG. 23D, the entire surface of the wafer is sealed with a mold resin 415 (step S11 in FIG. 20). Thereafter, the same processes as in FIGS. 3A to 3D are performed (steps S12 and S13 in FIG. 20). Through the above steps, in WL-CSP, a semiconductor device in which a component is mounted on a rewiring and the component is sealed with a mold resin is completed.

<< 3-3 >> Effects of Embodiment 2 FIG. 24 is a side view schematically showing warpage of a semiconductor wafer that may occur when two dry films are stacked and attached on a semiconductor wafer. FIG. 25 is a side view schematically showing dry film peeling that may occur when two dry films are stacked and pasted on a semiconductor wafer. FIG. 26 is a side view schematically showing excess Cu formed in the peeling portion in the plating step when dry film peeling occurs. FIG. 27A is a diagram illustrating a normal plating process, and FIG. 27B is a diagram illustrating a problem that a dry film piece blocks a hole.

  For example, as shown in FIG. 3D, when a high post electrode that enables component mounting is formed with thick dry films 110 and 111, internal stress generated in the laminated dry films 110 and 111 becomes large. This stress causes the wafer to warp. Further, the internal stress concentrates on the end portions (near the wafer edge) of the dry films 110 and 111, and causes the peeling of the dry films 110 and 111 near the wafer edge (near the outer peripheral portion) (FIG. 25). When the dry films 110 and 111 are peeled off, the dry film pieces generated during the peeling are mixed in the plating solution, and the dry film pieces close the openings as shown in FIG. As a cause of growth and an excessive post electrode (for example, Cu electrode) grows at a portion where the dry films 110 and 111 are peeled off, a process after the post electrode is formed by plating is shown in FIG. As described above, the wafer may be cracked starting from the excess Cu. Further, the internal stress generated in the thick dry films 110 and 111 causes the wafer to warp, causing a vacuum adsorption error or the like in the apparatus after the dry film is pasted, which may cause a problem in the process flow.

  Therefore, in the second embodiment, by performing post electrode plating with two layers of dry film, the stress of the dry film concentrated at one location on the outer periphery of the wafer is increased in the second layer on the outer periphery of the wafer. By removing the dry film, it is possible to disperse stress concentration points. Here, the outer peripheral portion of the wafer is covered with the first dry film, and it is possible to suppress the growth of excessive post electrodes generated on the outer periphery of the wafer. In addition, by forming lattice-like slits in the second dry film, it is possible to disperse the stress generated in the dry film and suppress the amount of warpage of the entire wafer. The effect of preventing warping by the slit is effective when the total film thickness of the first dry film 310 and the second dry film 311 is 100 μm or more, particularly 150 μm or more.

  Further, when the wafer outer peripheral portion of the first layer dry film is removed, the second layer dry film adheres to the wafer outer peripheral UBM film 108 and covers the end surface of the first layer dry film. In addition, it is possible to suppress the penetration of the plating solution generated at the dry film interface.

  As described above, according to the second embodiment, by removing the dry film on the outer peripheral portion of the wafer, peeling of the dry film caused by stress concentration is prevented, and mixing of the dry film pieces into the plating solution, excess post Wafer cracking due to electrode growth can be suppressed. Further, by forming slits of the second dry film in a lattice shape, it is possible to suppress the warpage of the wafer caused by the stress of the dry film and to prevent problems caused by the process flow.

  101 semiconductor wafer, 102 wiring, 103 interlayer insulating film, 104 via (VIA), 105 wiring, 106 passivation film, 107 lower insulating film, 108 UBM film, 109 rewiring, 120 substrate on which post electrode is formed, 110, 210 , 310, 410 First-layer photoresist dry film (first-layer dry film), 210a, 310a, 410a Upper surface of first-layer dry film, 111, 211, 311, 411 Second-layer photoresist dry film (Second layer dry film), 112 opening (hole), 113, 213, 313, 413 post electrode, 114, 214, 314, 414 parts, 115, 215, 315, 415 mold resin, 118 solder terminal, 212a 312a 412a First layer dry film opening (hole), 212b, 312b, 412b Second layer dry film opening (hole), 213a, 313a, 413a First layer post electrode, 213b, 313b, 413b 2 Layer post electrode 230 joint of post electrode 240 outer peripheral protrusion generated at interface position of dry film 320, 420, 422 slit, 421 resist.

Claims (6)

Wiring provided on the semiconductor substrate;
A columnar post electrode having a bottom connected to the wiring, a top opposite to the bottom, and a side surface connecting the bottom and the top;
The post electrode includes a first post electrode formed by plating, and a second post electrode formed on the first post electrode by plating,
An outer peripheral projection that is long in the circumferential direction is formed on the side surface of the post electrode at a position higher than the joining position of the first post electrode and the second post electrode. apparatus.   The semiconductor device according to claim 1, wherein a length of the second post electrode is longer than a length of the first post electrode.   The semiconductor device according to claim 1, wherein the post electrode further includes a third post electrode formed on the second post electrode by plating. A mold resin covering the side surface of the post electrode;
The semiconductor device according to claim 1, further comprising: a solder terminal provided on the top of the post electrode. 5. The semiconductor device according to claim 1, further comprising an electronic component mounted on a wiring on which the columnar electrode is not formed among the wirings provided on the semiconductor substrate. 6. . 6. The semiconductor device according to claim 5, wherein a height of the electronic component is higher than a length of the first post electrode.

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