JP2011035353A - Semiconductor apparatus and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently suppress ion migration between wirings even if a distance between adjacent wirings is remarkably reduced due to a fine pitch of the wirings in a re-wiring layer of a semiconductor apparatus. <P>SOLUTION: The semiconductor apparatus has a semiconductor substrate 11 in which a semiconductor device and an electrode 11c are formed on one main surface 11a, an interlayer dielectric 12 formed on the one main layer 11a, a plurality of resin patterns 13 made of polyimide along each of wiring patterns on the interlayer dielectric 12, re-wiring layers 14 formed on the resin patterns 13, respectively, and a sealing insulating layer 15 for sealing the upper part of the re-wiring layers 14. Side surfaces 13a of the resin patterns 13 are formed to be uneven at the cross section vertical to a longitudinal direction of the wiring patterns. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a rewiring layer and a method for manufacturing the same.

  In recent years, a package structure called a CSP (chip scale package or chip size package) is rapidly spreading as a semiconductor package. This package structure generally employs a so-called BGA (ball grid array) technique in which electrodes are arranged in a planar shape on a planar surface of the package. Therefore, it is possible to mount the semiconductor chip on the electronic circuit board with a smaller area than before, which can greatly contribute to the reduction in size and weight of the electronic device.

  However, as the semiconductor device is further miniaturized, it is necessary to miniaturize the wiring routed as the rewiring layer. As a result, it is considered that the possibility of an electrical short circuit between the wirings is increased. Therefore, it can be said that preventing an electrical short circuit between wirings is important in providing a highly reliable semiconductor device.

  In order to reduce the size of a semiconductor device, it is necessary to reduce the pitch of wiring, and the distance between adjacent wirings is extremely close. As a result, it is expected that ion migration occurs between the wirings, and the possibility of causing an electrical short circuit is increased.

  Patent Document 1 describes a semiconductor device in which a plurality of conductive parts formed so as not to be electrically connected to each other are formed on a plurality of resin parts arranged at intervals. Yes. According to this semiconductor device, the distance between the two adjacent conductive portions is increased, and a short circuit caused by migration is unlikely to occur.

  Patent Document 2 discloses a semiconductor device in which a plurality of conductive portions formed so as not to be electrically connected to each other are separately surrounded by a plurality of resin walls formed so as to partition a certain region. Are listed. According to this semiconductor device, since the resin wall is formed so as to surround the conductive portion, an electrical short caused by migration is unlikely to occur.

JP 2006-313832 A JP 2006-332108 A

In the case of Patent Document 1, since the resin portion is formed wider than the conductive portion and the side surface of the resin portion becomes a gentle slope, the width of the resin portion prevents a narrow pitch.
Also, in the case of Patent Document 2, since the resin wall is formed so as to surround the conductive portion, the resin wall around the conductive portion prevents the pitch from being narrowed.
Furthermore, in the case of Patent Document 1, since the side surface of the resin portion becomes a gentle slope, the distance of the member surface between two adjacent conductive portions is not increased for the height of the resin portion, and migration is not performed. The suppression effect is reduced.

  The present invention has been made in view of the above circumstances, and effectively suppresses ion migration between wirings even if the distance between adjacent wirings is extremely close by narrowing the wirings in the rewiring layer of the semiconductor device. It is an object of the present invention to provide a semiconductor device that can be used and a manufacturing method thereof.

  In order to solve the above problems, the present invention provides a semiconductor substrate in which a semiconductor device and an electrode are provided on one main surface, an interlayer insulating layer formed on one main surface of the semiconductor substrate, and the interlayer insulation A resin pattern portion made of polyimide formed along individual wiring patterns on the layer, a rewiring layer formed on each of the resin pattern portions, and a seal for sealing the top of the rewiring layer An insulating layer is provided, and the side surface of the resin pattern portion is uneven in a cross section perpendicular to the longitudinal direction of the wiring pattern.

  The present invention also includes a step of forming an interlayer insulating layer on the one main surface of the semiconductor substrate having a semiconductor device and an electrode provided on one main surface, and forming a resin pattern portion on the interlayer insulating layer. Forming a resin layer, forming a rewiring layer on the resin pattern portion forming resin layer along each wiring pattern, using the rewiring layer as an etching mask, Etching the resin layer for forming a resin pattern part using an etchant mainly composed of potassium oxide so that the resin layer for forming a resin pattern part is a plurality of resin pattern parts formed along each wiring pattern. And a step of making the side surface of the resin pattern portion uneven in a cross section perpendicular to the longitudinal direction of the wiring pattern, and a step of forming a sealing insulating layer for sealing the rewiring layer. To provide a method of manufacturing a semiconductor device according to claim Rukoto.

  According to the present invention, since the side surface of the resin pattern portion is uneven in the cross section perpendicular to the longitudinal direction of the wiring pattern, even if the wiring is narrowed, the interlayer insulating layer and the sealing insulating layer The distance between wirings along the interface is increased, and ion migration can be effectively suppressed.

(A) is sectional drawing which shows the 1st form example of the semiconductor device of this invention, (b) is sectional drawing which follows the AA line of (a), (c) is the elements on larger scale of the B section of (b). It is. It is sectional drawing which shows an example of the semiconductor substrate which has an interlayer insulation layer and the resin layer for resin pattern part formation. (A) is sectional drawing which shows an example in the state in which the rewiring layer was formed on the interlayer insulation layer of FIG. 2, (b) is sectional drawing which follows the CC line of (a). (A) is sectional drawing which shows an example of the state by which the resin pattern part formation resin layer of FIG. 3 was etched and the resin pattern part was formed, (b) is sectional drawing which follows the DD line | wire of (a), (C) is the elements on larger scale of the E section of (b). It is a microscope picture which shows an example of the state of the side surface after etching a polyimide layer. It is sectional drawing of the direction perpendicular | vertical to the wiring of the semiconductor device of a prior art example.

The present invention will be described below based on preferred embodiments with reference to the drawings.
FIG. 1 shows an example of a semiconductor device according to the present invention.
As shown in FIG. 1A, the schematic configuration of the semiconductor device 10 of the present embodiment includes a semiconductor substrate 11 in which a semiconductor device (not shown) and an electrode 11c are provided on one main surface 11a, and a semiconductor substrate 11 An interlayer insulating layer 12 formed on one main surface 11a, a resin pattern portion 13 made of polyimide formed on the interlayer insulating layer 12 along each wiring pattern, and an upper surface of the resin pattern portion 13. And a plurality of rewiring layers 14 formed on each of them, and a sealing insulating layer 15 that seals the top of the rewiring layer 14.

The semiconductor device 10 according to the present embodiment is characterized in that the side surface 13a of the resin pattern portion 13 has an uneven shape as shown in FIG. The uneven shape in the present invention is a shape in which unevenness appears on a cross section perpendicular to the wiring. For example, the concave portions and / or convex portions constituting the concave and convex shapes such as a stripe shape or a pie dough shape may be continuous entirely or locally along the longitudinal direction of the wiring.
As a result, as shown in FIG. 1B, the distance between the wirings along the interface between the interlayer insulating layer 12 and the sealing insulating layer 15 is increased even at a location where the plurality of rewiring layers 14 are close to each other, and ion migration is performed. Can be effectively suppressed.

  On the other hand, for example, in the case of the structure shown in FIG. 6, since a plurality of rewiring layers 14 are provided on the interlayer insulating layer 12, wiring along the interface between the interlayer insulating layer 12 and the sealing insulating layer 15 is provided. The inter-distance is equal to the linear distance (interval) indicated by the symbol d. For this reason, when the distance d is shortened by narrowing the pitch, ion migration occurs and there is a possibility of an electrical short circuit.

  The resin pattern portion 13 is made of polyimide. As polyimide, in addition to non-thermoplastic polyimide resins such as Kapton Apical and Upilex (both trade names), thermosetting materials such as bismaleide resins and polyamideimide resins, and heat such as auram (trade names) It includes a composite material in which plastic polyimide and a combination of these are laminated.

As a method of making the side surface 13a of the resin pattern portion 13 uneven, wet etching using an etchant containing potassium hydroxide as a main component can be mentioned. For example, the method of immersing in the high concentration potassium hydroxide (KOH) aqueous solution which added the organic solvent and the organic amine by the density | concentration 10-40% heated at about 60-80 degreeC is employable. Due to the hot strong alkaline solution, the side surface of the polyimide layer becomes a rough surface having irregularities similar to the fractured surface of the puff pastry reflecting the layered molecular structure of the polyimide (schematic diagram in FIG. 4 (c) and photograph in FIG. 5). See).
By adjusting the liquid temperature and alkali concentration, the etching progress rate and finished roughness can be adjusted. A similar effect can be obtained by using sodium hydroxide (NaOH) instead of potassium hydroxide (KOH).

The resin pattern portion 13 has a long ion migration path along its side surface 13a. As shown in FIG. 1B, the path is elongated when the distance between the resin pattern portions 13 adjacent to each other in the cross section in the direction perpendicular to the longitudinal direction of the wiring is longer than the distance between the wirings. The width of the portion 13 is preferably smaller than the wiring width w. When the width of the resin pattern portion 13 is not clear due to the uneven shape or inclination of the resin pattern portion 13, the entire resin pattern portion 13 is positioned below the rewiring layer 14 (that is, the side surface 13 a of the resin pattern portion 13. Is preferably located on the inner side of the side surface of the rewiring layer 14).
Although it depends on the wiring width w, it is preferable that the side etching when the rewiring layer 14 is used as an etching mask is 1 μm or more. Further, when the side etching width is 25% or less of the wiring width w, the width of the resin pattern portion 13 is more than half of the wiring width w, and the viewpoint of stability for supporting the rewiring layer 14 on the resin pattern portion 13 is obtained. Therefore, it is preferable.
The side surface 13a of the resin pattern portion 13 may be substantially vertical or inclined. When the side surface 13a is inclined, the width of the resin pattern portion 13 may be increased or the width may be decreased as it approaches the rewiring layer 14.
The interval between the adjacent convex portions (or the interval between the concave portions) in the cross section perpendicular to the longitudinal direction of the wiring pattern is not particularly limited, but is preferably about 1 to 2 μm. In this case, the thickness (height) of the resin pattern portion 13 is preferably 3 μm or more so that the side surface 13a of the resin pattern portion 13 includes at least one concave portion and one convex portion.
It is preferable that a plurality of convex portions and / or a plurality of concave portions exist within the range of the thickness (height) of the resin pattern portion 13.

Hereinafter, a preferable configuration of the semiconductor device 10 according to the present embodiment will be described in more detail.
The semiconductor substrate 11 has main surfaces 11a and 11b on the front and back sides, respectively. On one main surface 11a (upper surface in FIG. 1A), a semiconductor device such as an integrated circuit (not shown) and its electrode 11c are provided. In order to protect the integrated circuit, a passivation film (not shown) such as an oxide film or a nitride film is provided.
The semiconductor substrate 11 in the semiconductor device 10 of the present embodiment is composed of a semiconductor wafer such as a silicon (Si) wafer or a semiconductor chip obtained by dicing the wafer. The electrode 11c is made of, for example, an Al pad.

  The interlayer insulating layer 12 and the sealing insulating layer 15 may be an insulating layer made of resin or an insulating layer other than resin. In order to suppress signal delay due to inter-wiring capacitance, an insulating film having a low relative dielectric constant k (so-called low-k insulating film) is preferable. As a low-k insulating film, an organic film such as a SiOC film, a SiOCH film, a methylsilsesquioxane film, a benzocyclobutene film, an inorganic film such as a hydroxysilsesquioxane film, or a porous film of these films The thing which was done is mentioned. Further, the insulating film is not limited to the low-k insulating film, and other conventionally known insulating materials can be used.

  The rewiring layer 14 is made of a conductor (such as various metals or alloys) such as Cu, Al, Ni, Ag, Pb, Sn, Au, Co, Cr, Ti, or TiW, and has a thickness of, for example, 0.1 ˜20 μm. The formation method of the rewiring layer 14 is not specifically limited, For example, sputtering method, a vapor deposition method, a plating method etc., or the combination of these 2 or more methods is mentioned. Further, the rewiring layer 14 may be a single conductor layer or a laminate of multiple conductor layers. Further, a photolithography technique is preferably used for patterning the rewiring layer 14.

Each wiring pattern by the rewiring layer 14 is not particularly limited. For example, as shown in FIG. 1, one end portion 14a of the rewiring layer 14 is electrically connected to the electrode 11c of the semiconductor substrate 11, and the rewiring layer 14 The other end portion 14c may be a land portion 14d for mounting an external terminal 16 such as a solder bump, and an intermediate portion thereof may be a wiring portion 14b having a width w.
Since one end portion 14a of the redistribution layer 14 is electrically connected to the electrode 11c of the semiconductor substrate 11, the interlayer insulating layer 12 is provided with an opening 12a corresponding to at least a part of the region of the electrode 11c.
Further, in order to expose the external terminal 16, the sealing insulating layer 15 is provided with an opening 15a corresponding to at least a part of the land portion 14d.

  The external terminal 16 can be used for mounting a semiconductor chip formed of the semiconductor device 10 on an electronic circuit board such as a printed circuit board. Examples of the external terminal 16 include terminals formed on resin protrusions (not shown) in addition to the solder bumps shown in FIG. Examples of the solder bump forming method include a printing method, a plating method, a metal jet method, and a ball mounting method. For example, in the printing method, a solder paste can be printed and melted by a reflow process to form solder bumps. As the solder, a eutectic type or a lead-free type can be suitably used.

The semiconductor device 10 of this embodiment can be manufactured by the method shown in FIGS.
First, as shown in FIG. 2, an interlayer insulating layer 12 having an opening 12a is formed on one main surface 11a of a semiconductor substrate 11 so that at least a part of the electrode 11c is exposed.
A resin pattern portion forming resin layer 17 for forming the resin pattern portion 13 is formed on the interlayer insulating layer 12.

  Examples of the method for forming the interlayer insulating layer 12 include a spin coating method (spin coating method), a printing method, and a laminating method. The opening 12a can be formed by, for example, a method of forming a film of an insulator (resin or the like) constituting the interlayer insulating layer 12 on the entire surface and then patterning the film using a photolithography technique.

In the case of this embodiment, the resin pattern portion 13 is formed by etching using a part of the resin pattern portion forming resin layer 17 and using the rewiring layer 14 as an etching mask. That is, the resin pattern portion 13 is made of the same material as the resin pattern portion forming resin layer 17.
In order to prevent the resin pattern portion forming resin layer 17 from covering the electrode 11c, it is preferable to protect the resin pattern portion forming resin layer 17 from being formed in the opening 12a with a resist or the like. The thickness of the resin layer 17 for forming the resin pattern portion corresponds to the thickness (height) of the resin pattern portion 13 described above and is not particularly limited, but is preferably 3 μm or more, for example.

Next, as shown in FIG. 3A, one end 14a is electrically connected to the electrode 11c in the opening 12a from the inside of the opening 12a of the interlayer insulating layer 12 to the resin layer 17 for resin pattern portion formation, The rewiring layer 14 having the land portion 14d provided on the other end portion 14c is formed.
Although the formation method of the rewiring layer 14 is not specifically limited, For example, the following method is mentioned. First, a seed layer that is a thin conductive film is formed inside the opening 12a of the interlayer insulating layer 12 and on the resin layer 17 for resin pattern portion formation. A plating resist is formed on the seed layer, and a place where the rewiring layer 14 is formed is opened by exposure and development. Next, Cu or the like is deposited to a desired film thickness by electrolytic plating, and after removing the plating resist, the electrolytic plating layer is used as an etching mask, and an extra seed layer (outside the place where the rewiring layer 14 is formed). The existing part) is removed by etching.
As a result, as shown in FIG. 3B, the resin pattern portion forming resin layer 17 is placed between the one end portion 14a formed in the opening 12a and the other end portion 14c serving as the land portion 14d. A plurality of wiring portions 14b are formed to extend.

Next, as shown in FIG. 4A, the resin layer for forming a resin pattern portion 17 is etched. Etching is preferably wet etching using an etchant mainly composed of strong alkali such as potassium hydroxide or sodium hydroxide.
By etching the polyimide with strong alkali using the rewiring layer 14 as an etching mask, a plurality of resin pattern portions 13 are formed along each wiring pattern as shown in FIG. 4B. Further, as shown in FIG. 4C, the side surface 13a of the resin pattern portion 13 is uneven in a cross section perpendicular to the longitudinal direction of the wiring pattern.

  Next, the sealing insulating layer 15 is formed on the interlayer insulating layer 12 and the rewiring layer 14 using a fluid insulating material as a raw material. Further, before the sealing insulating layer 15 is cured, a pattern is formed by exposure and development so that at least a part of the land portion 14d is exposed, thereby forming the opening 15a. Further, by forming external terminals 16 such as solder bumps in the opening 15a, the semiconductor device 10 shown in FIG. 1 is completed. According to the semiconductor device 10 manufactured as described above, it is possible to mount the semiconductor chips on the electronic circuit board with a small area by BGA (ball grid array) technology.

  The present invention can be used for various semiconductor devices having a rewiring layer.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... Semiconductor substrate, 11a ... One main surface, 11b ... The other main surface, 11c ... Electrode, 12 ... Interlayer insulation layer (1st insulation layer), 13 ... Resin pattern part, 13a ... Resin pattern Sides of parts, 14 ... redistribution layer, 15 ... sealing insulating layer (second insulating layer), 16 ... external terminal, 17 ... resin layer forming resin layer.

Claims (2)

A semiconductor substrate provided with semiconductor devices and electrodes on one main surface;
An interlayer insulating layer formed on one main surface of the semiconductor substrate;
A resin pattern portion made of polyimide formed on the interlayer insulating layer along each wiring pattern, and
A rewiring layer formed on each of the resin pattern portions;
A sealing insulating layer that seals over the rewiring layer;
2. A semiconductor device according to claim 1, wherein the side surface of the resin pattern portion has an uneven shape in a cross section perpendicular to the longitudinal direction of the wiring pattern. Forming an interlayer insulating layer on the one main surface of the semiconductor substrate provided with a semiconductor device and an electrode on one main surface;
Forming a resin layer for forming a resin pattern part on the interlayer insulating layer;
A rewiring layer forming step of forming a rewiring layer along each wiring pattern on the resin pattern portion forming resin layer;
Using the rewiring layer as an etching mask and using an etching solution mainly composed of potassium hydroxide, the resin pattern portion forming resin layer is formed into a plurality of resin pattern portions formed along individual wiring patterns. Etching the resin layer for forming the resin pattern part, and making the side surface of the resin pattern part uneven in a cross section perpendicular to the longitudinal direction of the wiring pattern;
Forming a sealing insulating layer for sealing over the rewiring layer;
A method for manufacturing a semiconductor device, comprising: