JP2013196652A - Control device and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable accesses to a plurality of storage parts in parallel with simple processing.SOLUTION: A control device includes: a ROM 102; a first RAM 115 to a third RAM 131; a first CPU 110 for designating an address, and outputting a signal corresponding to the designated address and a prescribed bit value of the designated address; and a select signal generation part 114 for generating a select signal for selecting one or more memories among the ROM 102 and the first RAM 115 to the third RAM 131 in accordance with the signal and the prescribed bit value outputted from the first CPU 110 and outputting the select signal to the one or more memories. The first CPU 110 accesses the one or more memories selected by the select signal in parallel.

Description

  The present invention relates to a control device and an image forming apparatus.

  Conventionally, in a controller equipped with a plurality of processors and a RAM (Random Access Memory) paired with each of the plurality of processors, a predetermined processor writes data in parallel to the plurality of RAMs, and each of the plurality of processors is paired with each other. A technique for reading data from a RAM to be used is known (for example, see Patent Document 1).

  In the above-described prior art, a simultaneous selection control signal is used in addition to an address in order to enable selection of a plurality of RAMs as write targets. However, output control of the simultaneous selection control signal must be performed on the CPU side. , Processing becomes complicated.

  SUMMARY An advantage of some aspects of the invention is that it provides a control device and an image forming apparatus that can access a plurality of storage units in parallel with simple processing.

  In order to solve the above-described problems and achieve the object, a control device according to one aspect of the present invention specifies a plurality of storage units, an address, a signal corresponding to the specified address, and a predetermined bit of the specified address Generating a selection signal for selecting one or more storage units of the plurality of storage units according to the signal output from the processing unit and the predetermined bit value, A selection signal generation unit that outputs to the one or more storage units, and the processing unit accesses the one or more storage units selected by the selection signal in parallel.

  An image forming apparatus according to another aspect of the present invention includes the control device.

  According to the present invention, it is possible to access a plurality of storage units in parallel by simple processing.

FIG. 1 is a block diagram illustrating an example of the configuration of the control device of the present embodiment. FIG. 2 is a diagram illustrating an example of an address space allocation table according to the present embodiment. FIG. 3 is a diagram illustrating an example of a logical configuration of the select signal generation unit of the present embodiment. FIG. 4 is a diagram illustrating an example of the relationship between INPUT and OUTPUT of the select signal generation unit of the present embodiment. FIG. 5 is an explanatory diagram of an example of a control program writing method according to the first modification. FIG. 6 is a block diagram illustrating an example of the configuration of the control device according to the second modification. FIG. 7 is a schematic diagram illustrating an example of an overall configuration of a system including the control device according to the embodiment and each modification. FIG. 8 is a schematic diagram illustrating an example of a configuration related to image formation and transfer of the multifunction peripheral according to the embodiment and each modification. FIG. 9 is a block diagram illustrating an example of a hardware configuration of the multifunction peripheral according to the embodiment and each modification.

  Hereinafter, embodiments of a control device and an image forming apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram illustrating an example of the configuration of the control device 100 of the present embodiment. As illustrated in FIG. 1, the control device 100 includes a ROM (Read Only Memory) 102, a first CPU (Central Processing Unit) 110, a select signal generation unit 114, a first RAM (Random Access Memory) 115, and a second CPU 120. A second RAM 121, a third CPU 130, and a third RAM 131.

  The ROM 102 (an example of a storage unit) is a nonvolatile storage device and stores a control program. The first RAM 115 (an example of a storage unit), the second RAM 121 (an example of a storage unit), and the third RAM 131 (an example of a storage unit) are volatile storage devices, and a control program stored in the ROM 102 is downloaded.

  The first CPU 110 (an example of a processing unit), the second CPU 120 (an example of a processing unit), and the third CPU 130 (an example of a processing unit) execute control programs downloaded to a pair of the first RAM 115, the second RAM 121, and the third RAM 131, respectively. It works. That is, in the example shown in FIG. 1, the first CPU 110, the second CPU 120, and the third CPU 130 are each configured to be independently operable within a range surrounded by a broken line.

  Each CPU and RAM pair has the same performance, and the same processing is executed in any pair, but in this embodiment, the first CPU 110 is a master, and the second CPU 120 and the third CPU 130 are slaves. Is described as an example.

  For this reason, in this embodiment, as shown in FIG. 1, the ROM 102 and the select signal generation unit 114 are arranged within a broken line including the first CPU 110. Each CPU is connected in parallel (bus connection) to the ROM 102, the first RAM 115, the second RAM 121, and the third RAM 131 by a transmission path (data bus DB, address bus AB, etc.). Each CPU accesses these memories via a transmission path, and reads and writes data (including programs).

  In the following, description will be given mainly assuming that the first CPU 110 reads a control program from the ROM 102 and writes (downloads) the read control program to the first RAM 115 to the third RAM 131 in parallel.

  The first CPU 110 includes a core 111 and a decoder 112.

  The core 111 is a core part of the first CPU 110 and executes arithmetic processing and the like. The core 111 accesses an access target memory (in the example shown in FIG. 1, at least one of the ROM 102, the first RAM 115, the second RAM 121, and the third RAM 131). Is designated to the decoder 112. In this embodiment, the address is 32 bits, but is not limited to this.

  FIG. 2 is a diagram illustrating an example of an address space allocation table according to the present embodiment. In the assignment table shown in FIG. 2, a chip select (hereinafter sometimes referred to as CS) name, an address, Block_Size, and a select device are associated with each other. In the present embodiment, the first CPU 110 accesses two or more RAMs in parallel among the first RAM 115, the second RAM 121, and the third RAM 131. For this reason, in the assignment table shown in FIG. 2, combinations of RAMs (first RAM to third RAM, second RAM to third RAM) are also assigned to the select device. In the present embodiment, the first CPU 110 holds the assignment table shown in FIG. In the example illustrated in FIG. 2, the first RAM and the third RAM are not assigned, but a free address (for example, the address 0x2230_0000 to 0x223F_FFFF) may be assigned to the first RAM and the third RAM. .

  For example, when the memory (select device) to be accessed is the ROM 102, the core 111 refers to the allocation table illustrated in FIG. 2 and designates the address 0x2200 — 0000 to 0x220F_FFFF to the decoder 112. Further, for example, when the memory (select device) to be accessed is the first RAM 115 to the third RAM 131, the core 111 refers to the allocation table illustrated in FIG. 2 and designates the address 0x2220 — 0000 to 0x222F_FFFF to the decoder 112.

  The decoder 112 outputs a signal corresponding to the address designated from the core 111 and a predetermined bit value of the designated address to the select signal generation unit 114. In the present embodiment, the decoder 112 outputs the CS1 signal, the CS2 signal, and the CS3 signal to the select signal generation unit 114 via the ports as signals corresponding to the address specified from the core 111.

  In this embodiment, as shown in FIG. 2, the CS1 signal is a CS signal associated with the address 0x2200 — 0000-0x23FF_FFFF, and the CS2 signal is a CS signal associated with the address 0x2400 — 0000-0x25FF_FFFF, The CS3 signal is a CS signal associated with addresses 0x2600 — 0000 to 0x27FF_FFFF.

  In addition, the decoder 112 uses the 20th and 21st bit values of the address, that is, the address signal of the 20th bit of the address (hereinafter referred to as the A (20) signal) as the predetermined bit value of the address designated by the core 111. ) And the 21st bit address signal (hereinafter referred to as A (21) signal) are output to the select signal generator 114 via the address bus AB.

  For example, when the address 0x2200 — 0000 to 0x220F_FFFF is designated from the core 111, the decoder 112 refers to the assignment table shown in FIG. 2 and asserts the CS1 signal and negates the CS2 signal and the CS3 signal. In addition, the decoder 112 outputs the value “0” of the 20th bit and the value “0” of the 21st bit of the addresses 0x2220 — 0000 to 0x222F_FFFF to the select signal generation unit 114.

  Further, for example, when the address 0x2220 — 0000 to 0x222F_FFFF is designated from the core 111, the decoder 112 refers to the assignment table shown in FIG. 2 and asserts the CS1 signal and negates the CS2 signal and the CS3 signal. The decoder 112 outputs the 20th bit value “0” and the 21st bit value “1” of the addresses 0x2220 — 0000 to 0x222F_FFFF to the select signal generation unit 114.

  In this embodiment, when the CS signal is asserted, the output of the CS signal is Low (hereinafter referred to as L), and when the CS signal is negated, the output of the CS signal is High (hereinafter referred to as H). Shall be. Further, when the bit value is “0”, the output of the address signal of the bit is L, and when the bit value is “1”, the output of the address signal of the bit is H.

  The select signal generation unit 114 generates a select signal for selecting one or more memories of the ROM 102, the first RAM 115, the second RAM 121, and the third RAM 131 according to the signal output from the decoder 112 and a predetermined bit value. Output to one or more memories.

  In the present embodiment, the CS1 signal to the CS3 signal, the A (20) signal, and the A (21) signal are input from the decoder 112 to the select signal generation unit 114. The select signal generator 114 generates at least one of a CS4 signal for selecting the ROM 102, a CS5 signal for selecting the first RAM 115, a CS6 signal for selecting the second RAM 121, and a CS7 signal for selecting the third RAM 131 as the select signal. And output to the corresponding memory through the port.

  Thus, the select signal generation unit 114 is used to increase the number of CS signals. For example, it is assumed that the memory to be accessed is selected using the CS signal generated by the decoder 112 without using the select signal generation unit 114. In this case, since there are three CS signals CS1 to CS3 output from the decoder 112, only three memories to be accessed can be selected.

  On the other hand, the select signal generation unit 114 receives the CS1 signal to the CS3 signal and outputs a CS signal. Here, since the CS signal has two patterns (Low, High), the select signal generation unit 114 outputs four CS signals (CS4 signal to CS7 signal) by inputting the CS1 signal to CS3 signal. can do.

  In the present embodiment, as described above, the first CPU 110 accesses two or more RAMs in parallel among the first RAM 115, the second RAM 121, and the third RAM 131, so that the select signal generation unit 114 receives the CS4 signal to the CS7 signal. It is necessary to assert two or more CS signals.

  Therefore, the select signal generator 114 further receives the A (20) signal and the A (21) signal and outputs a CS signal. Here, since the address signal has two patterns (Low, High), the select signal generator 114 receives the CS1 to CS3 signals, the A (20) signal, and the A (21) signal as inputs. Two or more CS signals among the CS4 signal to the CS7 signal can be asserted.

  For example, the select signal generation unit 114 receives the CS1 signal “L”, the CS2 signal “H”, the CS3 signal “H”, the A (20) signal “L”, and the A (21) signal “L” from the decoder 112. When input, the CS4 signal is asserted and the CS5 to CS7 signals are negated. That is, the select signal generation unit 114 outputs the CS4 signal “L” to the ROM 102, the CS5 signal “H” to the first RAM 115, the CS6 signal “H” to the second RAM 121, and the CS7 signal “H”. Output to the third RAM 131.

  As a result, the first CPU 110 can access the ROM 102 and read the control program from the ROM 102.

  Further, for example, the select signal generation unit 114 receives the CS1 signal “L”, the CS2 signal “H”, the CS3 signal “H”, the A (20) signal “L”, and the A (21) signal “H” from the decoder 112. Is input, the CS4 signal is negated and the CS5 to CS7 signals are asserted. That is, the select signal generation unit 114 outputs the CS4 signal “H” to the ROM 102, the CS5 signal “L” to the first RAM 115, the CS6 signal “L” to the second RAM 121, and the CS7 signal “L”. Output to the third RAM 131.

  Accordingly, the first CPU 110 can access the first RAM 115 to the third RAM 131 in parallel, and can write the control program read from the ROM 102 in parallel to the first RAM 115 to the third RAM 131. As a result, the first CPU 110, the second CPU 120, and the third CPU 130 read out and execute the control programs downloaded to the first RAM 115, the second RAM 121, and the third RAM 131, respectively, to independently perform operations according to the control programs. And execute.

  FIG. 3 is a diagram illustrating an example of a logical configuration of the select signal generation unit 114 of the present embodiment, and FIG. 4 is a diagram illustrating an example of a relationship between INPUT and OUTPUT of the select signal generation unit 114 of the present embodiment. is there.

  In the present embodiment, the select signal generation unit 114 is realized by a combination of a NOT gate, a NAND gate, and a NOR gate as shown in FIG. 3, but the circuit configuration (logical configuration) of the select signal generation unit 114 Is not limited to this. The select signal generator 114 may have any circuit configuration as long as the relationship between INPUT and OUTPUT shown in FIG. 4 is established.

  In the circuit configuration shown in FIG. 3, the circuit configuration of the region 142 is for outputting four CS signals (CS4 signal to CS7 signal), and the circuit configuration of the region 141 is 2 out of the CS4 signal to CS7 signal. This is for asserting the above CS signal.

  As described above, in the present embodiment, the select signal generation unit generates a CS signal for selecting one or more memories according to an address designated by the CPU and a predetermined bit value of the address, and the one or more select signals are generated. Output to memory. In particular, in this embodiment, since the CS signal is generated using a predetermined bit value of the address in addition to the address, the simultaneous selection control signal as in the prior art is unnecessary, and output control of the simultaneous selection control signal is performed. There is no need to do it. Therefore, according to the present embodiment, the CPU can select one or more memories simply by specifying an address, and can access a plurality of memories in parallel with a simple process. As a result, according to the present embodiment, for example, the control program can be written (downloaded) in parallel to one or more selected memories, and the writing time of the control program can be shortened.

  If a simultaneous selection control signal is used as in the prior art, a port for the simultaneous selection control signal must be secured. This port is not an essential port for the processing of the control device, and the number of usable ports. Will be limited. On the other hand, in the present embodiment, since the predetermined bit value of the address is output via the address bus, it is not necessary to secure a separate port. For this reason, according to this embodiment, it is possible to prevent the control device from becoming too large and costly due to the exhaustion of ports and the increase in the number of usable ports. The CS signal port is an essential port for the processing of the control device 100, and does not limit the number of usable ports.

(Modification)
In addition, this invention is not limited to said each embodiment, A various deformation | transformation is possible.

(Modification 1)
In the above embodiment, the example in which the same control program is written (downloaded) in parallel to the first RAM 115 to the third RAM 131 has been described. However, the control program to be written may be different in some memories. In the above-described embodiment, it is assumed that each CPU and RAM pair has equivalent performance, and equivalent processing is executed in any pair. It is also assumed that the CPU control programs are different.

  In this case, the first CPU 110 writes the same control program to one or more memories selected by the CS signal by the select signal generation unit 114 in parallel, and then selects the memory to which the difference control program is written as the select signal generation unit. 114 may be selected by the CS signal, and the selected memory may be overwritten on the selected memory.

  FIG. 5 is an explanatory diagram of an example of a writing method when the control program to be written is different. In the example shown in FIG. 5, programs 1-1, 1-2, and 2-2 are stored in the ROM 102 (FROM), and the programs 1-1, 1-1 are stored in the first RAM 115 (first SRAM) and the third RAM 131 (third SRAM). 1-2 is downloaded and the programs 1-1 and 2-2 are downloaded to the second RAM 121 (second SRAM).

  In this case, first, the first CPU 110 reads the programs 1-1 and 1-2 from the ROM 102, and writes (downloads) the read programs 1-1 and 1-2 in parallel in the first RAM 115 to the third RAM 131. Note that the method of selecting the first RAM 115 to the third RAM 131 is as described in the above embodiment.

  Subsequently, the first CPU 110 reads the program 2-2 from the ROM 102, and writes (downloads) the read program 2-2 into the second RAM 121. In this case, the first CPU 110 (core 111) may specify the address 0x2400_0000 to 0x240F_FFFF (specifically, the address 0x2400_9000 to 0x2400_FFFF of the overwrite portion).

  Thereby, even when different control programs are written (downloaded) into a plurality of memories, the time for writing the control program can be shortened.

(Modification 2)
In the above-described embodiment, the ROM is a single ROM 102 prepared for the first CPU 110, but a plurality of ROMs may be prepared and used as a pair for each CPU. For example, as shown in FIG. 6, a first ROM 202 that is a pair of first CPUs 110, a second ROM 222 that is a pair of second CPUs 120, and a third ROM 232 that is a pair of third CPUs 130 are prepared in the control device 200. The first ROM 202, the second ROM 222, the third ROM 232, the first RAM 115, the second RAM 121, and the third RAM 131 may be connected in parallel.

  In this case, the select signal generation unit 114 further generates a CS4 signal for selecting the first ROM 202, a CS8 signal for selecting the second ROM 222, and a CS9 signal for selecting the third ROM 232 as select signals, and sends them to the corresponding memory via the port. Output.

  In this way, the first CPU 110 can write (download) the control program stored in the first ROM 202 not only in the first RAM 115 to the third RAM 131 but also in the second ROM 222 to the third ROM 232 in parallel. As a result, even if the control device 200 is restarted, the control program can be left in the second ROM 222 to the third ROM 232, and can be used for backup, mirroring, and the like.

(Modification 3)
In the above embodiment, the example in which the first CPU 110 reads the control program from the ROM 102 and writes (downloads) it in the first RAM 115 to the third RAM 131 in parallel has been described. However, the control program to be written is external to the control device 100. To the first CPU 110.

(Modification 4)
In the above embodiment, the case where there are three pairs of CPU and RAM has been described as an example, but the number of pairs may be any number. In this case, the number of CPUs serving as slaves increases.

(Modification 5)
In the above-described embodiment, an example in which the first CPU 110 writes (downloads) a control program in parallel to a plurality of RAMs has been described. However, data may be written in parallel to the registers of each CPU.

(Modification 6)
In the above embodiment, an example in which the first CPU 110 to the third CPU 130 are separate CPUs has been described. However, a plurality of cores included in a single CPU may be used.

(Image forming device)
As an example of an image forming apparatus including the control device according to the embodiment and each modification, a multifunction peripheral (MFP) including the control device according to the embodiment and each modification will be described. A multifunction peripheral is a device having at least two functions among a printing function, a copying function, a scanner function, and a facsimile function. However, the image forming apparatus is not limited to this, and may be a printing apparatus, a copying apparatus, a scanner apparatus, a facsimile apparatus, or the like.

  FIG. 7 is a schematic diagram illustrating an example of an overall configuration of a system 1 including the control device according to the embodiment and each modification. As shown in FIG. 7, the system 1 includes a multifunction device 2, an ADF (Auto Document Feeder) 3, a finisher 4, a double-side reversing unit 5, an extended paper feed tray 6, a large capacity paper feed tray 7, An insert feeder 8 and a 1-bin paper discharge tray 9 are provided. It is assumed that the multifunction machine 2 includes the control devices of the above-described embodiment and the above-described modifications.

  The multifunction device 2 corresponds to the main unit of the system 1, and includes a scanner unit that electronically reads a document to generate image data, an image forming unit that forms an image based on the image data generated by the scanner unit, and a sheet. A sheet feeding unit that feeds paper, a transfer unit that transfers an image formed on a sheet, and the like (not illustrated for the scanner unit and the sheet feeding unit, and not illustrated in FIG. 7 for the image forming unit and the transfer unit). Hereinafter, the sheet on which the image is transferred may be referred to as a copy.

  The ADF 3 automatically sends a document to the multifunction device 2 (specifically, the scanner unit of the multifunction device 2).

  The finisher 4 is a so-called post-processing device having a stapler, a shift tray, and the like, and performs post-processing such as stapling on a copy copied by the multifunction machine 2. The finisher 4 is not limited to this, and any finisher such as a staple process, a punch (punching) process, and a folding process may be used.

  When copying on both sides of a sheet, the duplex reversing unit 5 reverses the sheet with the image transferred on one side and returns it to the multifunction device 2 (specifically, the transfer unit of the multifunction device 2).

  The expansion paper feed tray 6 is an expansion paper feed tray, and sends the paper to the transfer unit of the multifunction machine 2.

  The large-capacity paper feed tray 7 is a paper feed tray that can store more paper than the paper feed unit of the multifunction device 2 and the extended paper feed tray 6, and sends the paper to the transfer unit of the multifunction device 2.

  The insert feeder 8 sends a sheet such as a cover sheet or a slip sheet to the transfer unit of the multifunction machine 2.

  The 1-bin paper discharge tray 9 is a paper discharge tray having one bin as a paper discharge destination, and a copy copied by the multifunction machine 2 is discharged.

  FIG. 8 is a schematic diagram illustrating an example of a configuration related to image formation and transfer of the MFP 2 according to the embodiment and each of the modifications. As shown in FIG. 8, the multifunction machine 2 includes an image forming unit 20, driving rollers 21 and 22, an intermediate transfer belt 23, a repulsive roller 24, and a secondary transfer roller 25.

  The image forming unit 20 includes a photosensitive drum 20a, a charging device, a developing device, a primary transfer roller 20b, a cleaning device, and the like (the charging device, the developing device, and the cleaning device are not shown).

  The image forming unit 20 and an irradiation device (not shown) perform an image forming process (charging process, irradiation process, developing process, transfer process, and cleaning process) on the photoconductive drum 20a, so that the static image is formed on the photoconductive drum 20a. An electric toner pattern is formed and transferred to the intermediate transfer belt 23.

  First, in the charging step, a charging device (not shown) charges the surface of the photosensitive drum 20a that is driven to rotate.

  Subsequently, in the irradiation step, an irradiation device (not shown) irradiates the charged surface of the photosensitive drum 20a with light-modulated laser light to form an electrostatic latent image on the surface of the photosensitive drum 20a.

  Subsequently, in the developing process, a developing device (not shown) develops the electrostatic latent image formed on the photosensitive drum 20a with toner (an example of a developer). As a result, an electrostatic toner pattern, which is a toner image obtained by developing the electrostatic latent image with toner, is formed on the photosensitive drum 20a.

  Subsequently, in the transfer step, the primary transfer roller 20b transfers (primary transfer) the electrostatic toner pattern formed on the photosensitive drum 20a to the intermediate transfer belt 23. A small amount of untransferred toner remains on the photosensitive drum 20a even after the electrostatic toner pattern is transferred.

  Subsequently, in the cleaning process, a cleaning device (not shown) wipes off the untransferred toner remaining on the photosensitive drum 20a.

  Here, since the multifunction device 2 is a multifunction device that performs monochrome copying, the number of image forming units is one. However, if the multifunction device 2 can perform color copying, the number of image forming units is plural. The number of image forming units corresponding to the number of colors of toner to be used is provided. In this case, each image forming unit has a different configuration and operation, although the color of the toner to be used is different.

  The intermediate transfer belt 23 is an endless belt that is wound around a plurality of rollers such as the driving rollers 21 and 22 and the repulsive roller 24, and moves endlessly when one of the driving rollers 21 and 22 is rotationally driven. .

  The intermediate transfer belt 23 has the electrostatic toner pattern transferred by the image forming unit 20 (primary transfer roller 20 b), and conveys the transferred electrostatic toner pattern between the repulsive roller 24 and the secondary transfer roller 25. At this time, the paper P is transported between the repulsive roller 24 and the secondary transfer roller 25 in accordance with the transport timing of the electrostatic toner pattern by a paper feeding unit (not shown). For this reason, the transfer positions of the electrostatic toner pattern and the paper P match.

  A repulsive roller 24 (an example of a transfer unit) transfers an electrostatic toner pattern conveyed by the intermediate transfer belt 23 to a sheet P (secondary transfer) at a secondary transfer nip (not shown) with the secondary transfer roller 25. Transfer).

  When the electrostatic toner pattern is transferred to the paper P, the paper P is heated and pressed by a fixing device (not shown), and the electrostatic toner pattern is fixed to the paper P. Then, the sheet P on which the electrostatic toner pattern is fixed is discharged from the multi-function peripheral 2 to the 1-bin discharge tray 9 (see FIG. 7).

(Hardware configuration)
FIG. 9 is a block diagram illustrating an example of a hardware configuration of the MFP according to the embodiment and each of the modifications. As shown in FIG. 9, the multi-function device of each of the above embodiments has a configuration in which a controller 910 and an engine unit (Engine) 960 are connected by a PCI (Peripheral Component Interconnect) bus. The controller 910 is a controller that controls the entire MFP, drawing, communication, and input from the operation display unit 920. The engine unit 960 is a printer engine that can be connected to a PCI bus, and is, for example, a monochrome plotter, a 1-drum color plotter, a 4-drum color plotter, a scanner, or a fax unit. The engine unit 960 includes an image processing part such as error diffusion and gamma conversion in addition to a so-called engine part such as a plotter.

  The controller 910 includes a CPU 911, a north bridge (NB) 913, a system memory (MEM-P) 912, a south bridge (SB) 914, a local memory (MEM-C) 917, and an ASIC (Application Specific Integrated Circuit). 916 and a hard disk drive (HDD) 918, and the North Bridge (NB) 913 and the ASIC 916 are connected by an AGP (Accelerated Graphics Port) bus 915. The MEM-P 912 further includes a ROM 912a and a RAM 912b.

  The CPU 911 performs overall control of the multifunction peripheral, has a chip set including the NB 913, the MEM-P 912, and the SB 914, and is connected to other devices via the chip set.

  The NB 913 is a bridge for connecting the CPU 911 to the MEM-P 912, SB 914, and the AGP bus 915, and includes a memory controller that controls reading and writing to the MEM-P 912, a PCI master, and an AGP target.

  The MEM-P 912 is a system memory used as a memory for storing programs and data, a memory for developing programs and data, a memory for drawing printers, and the like, and includes a ROM 912a and a RAM 912b. The ROM 912a is a read-only memory used as a memory for storing programs and data, and the RAM 912b is a writable and readable memory used as a program / data development memory, a printer drawing memory, and the like.

  The SB 914 is a bridge for connecting the NB 913 to a PCI device and a peripheral device. The SB 914 is connected to the NB 913 via a PCI bus, and a network interface (I / F) unit and the like are also connected to the PCI bus.

  The ASIC 916 is an IC (Integrated Circuit) for image processing having hardware elements for image processing, and has a role of a bridge for connecting the AGP bus 915, the PCI bus, the HDD 918, and the MEM-C 917, respectively. The ASIC 916 includes a PCI target and an AGP master, an arbiter (ARB) that forms the core of the ASIC 916, a memory controller that controls the MEM-C 917, and a plurality of DMACs (Direct Memory) that perform image data rotation by hardware logic and the like. Access Controller) and a PCI unit that performs data transfer between the engine unit 960 via the PCI bus. The ASIC 916 is connected to an FCU (Fax Control Unit) 930, a USB (Universal Serial Bus) 940, and an IEEE 1394 (the Institute of Electrical and Electronics Engineers 1394) interface 950 via a PCI bus. The operation display unit 920 is directly connected to the ASIC 916.

  The MEM-C 917 is a local memory used as a copy image buffer and a code buffer, and the HDD 918 is a storage for storing image data, programs, font data, and forms.

  The AGP bus 915 is a bus interface for a graphics accelerator card proposed for speeding up graphics processing. The AGP bus 915 speeds up the graphics accelerator card by directly accessing the MEM-P 912 with high throughput. It is.

1 System 2 Multifunction machine 3 ADF
4 Finisher 5 Double-sided reversing unit 6 Extended paper feed tray 7 Large-capacity paper feed tray 8 Insert feeder 9 1-bin paper output tray 20 Image forming unit 20a Photosensitive drum 20b Primary transfer roller 21, 22 Driving roller 23 Intermediate transfer belt 24 Repulsive force Roller 25 Secondary transfer roller 100 Controller 102 ROM
110 First CPU
111 Core 112 Decoder 114 Select Signal Generation Unit 115 First RAM
120 2nd CPU
121 2nd RAM
130 3rd CPU
131 3rd RAM
910 controller 911 CPU
912 System memory 912a ROM
912b RAM
913 North Bridge 914 South Bridge 915 AGP Bus 916 ASIC
917 Local memory 918 Hard disk drive 920 Operation display unit 930 FCU
940 USB
950 IEEE1394 interface 960 engine part

JP-A-5-342170

Claims (10)

A plurality of storage units;
A processing unit for designating an address and outputting a signal corresponding to the designated address and a predetermined bit value of the designated address;
In response to the signal output from the processing unit and the predetermined bit value, a select signal for selecting one or more storage units of the plurality of storage units is generated and output to the one or more storage units. A select signal generation unit,
The processing unit is a control device that accesses the one or more storage units selected by the select signal in parallel.   The control device according to claim 1, wherein the processing unit writes the same data in parallel to the one or more storage units selected by the select signal.   If the data to be written to any one of the one or more storage units selected by the select signal has a difference with respect to the same data, the processing unit The control device according to claim 2, wherein after the same data is written in parallel, the difference data is overwritten on any of the storage units. The plurality of storage units include a nonvolatile storage unit,
The control device according to claim 2, wherein the processing unit writes data read from the nonvolatile storage unit to the one or more storage units selected by the select signal. The plurality of storage units include a volatile storage unit,
The control device according to claim 2, wherein the one or more storage units selected by the select signal are the volatile storage units. A plurality of processing units including the processing unit;
The control device according to claim 2, wherein each of the plurality of processing units reads data from a pair of storage units among the plurality of storage units. A plurality of processing units including the processing unit;
The plurality of storage units include a register,
The control device according to claim 2, wherein each of the one or more storage units selected by the select signal is a register of a pair of processing units among the plurality of processing units.   The control device according to claim 7, wherein each of the plurality of processing units reads data from a pair of storage units among the plurality of storage units.   The control device according to claim 2, wherein the data is a program.   An image forming apparatus comprising the control device according to claim 1.

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