JP2021022055A - Image forming apparatus and data transfer method - Google Patents

Abstract

To provide an image forming apparatus and data transfer method that can efficiently reduce the processing time for a plurality of execution requests for data transfer processing stored in a buffer.SOLUTION: An image forming apparatus 2 comprises: an execution instruction unit 25 that, based on an execution requests stored in a buffer 24 for data transfer processing of transferring data between a memory 6 and a slave processor 12, instructs execution of the data transfer processing to a DMAC 5; an order determination unit 26 that determines processing order of the plurality of execution requests based on the amount of data to be transferred corresponding to each of the plurality of execution requests stored in the buffer 24; and a pre-processing execution unit 27 that, during execution of the data transfer processing by the DMAC 5, executes pre-processing corresponding to the data transfer processing that is executed subsequent to the data transfer processing under execution.SELECTED DRAWING: Figure 1

Description

The present invention relates to an image forming apparatus and a data transfer method executed by the image forming apparatus.

A data communication device capable of switching a communication protocol in data communication via the serial bus for each slave device connected to the serial bus is known (see Patent Document 1).

Further, a DMA (Direct Memory Access) controller that executes a data transfer process for transferring data between an ASIC that controls a functional unit such as an image forming unit and a memory, and a buffer for storing an execution request for the data transfer process are provided. An image forming apparatus is known. In the image forming apparatus, the CPU processes the execution requests stored in the buffer in the order of storage in the buffer.

Specifically, the CPU instructs the DMA controller to execute the data transfer process based on the execution request. Further, the CPU executes preprocessing such as assigning a command and a checksum to the data transferred in the data transfer process before instructing the DMA controller to execute the data transfer process. Further, the CPU executes post-processing such as confirmation of consistency of the transferred data after the data transfer processing is executed by the DMA controller.

Japanese Unexamined Patent Publication No. 2005-196486

By the way, when the two execution requests are stored in the buffer, the CPU performs the second execution during the execution of the data transfer process corresponding to the first execution request by the DMA controller. It is possible to execute the preprocessing corresponding to the request. As a result, the execution start timing of the data transfer process corresponding to the second execution request is advanced, so that the processing time of the two execution requests stored in the buffer can be shortened.

Here, when the execution request with a small amount of transfer data is processed first, the CPU is performing the second data transfer process corresponding to the first execution request by the DMA controller. The preprocessing corresponding to the execution request may not be completed. In this case, the unfinished portion of the pre-processing is executed after the post-processing corresponding to the first execution request. Therefore, the processing time of the two execution requests stored in the buffer is extended as compared with the case where the execution request having a large amount of transferred data is processed first. Even when three or more of the execution requests are stored in the buffer, the same problem occurs, for example, when the other execution requests are processed after the execution request with the smallest amount of transferred data. ..

An object of the present invention is to provide an image forming apparatus and a data transfer method capable of efficiently shortening the processing time of a plurality of data transfer processing execution requests stored in a buffer.

The image forming apparatus according to one aspect of the present invention includes a first processor, a memory, a second processor, a data transfer unit, and a buffer. The memory and the second processor are connected to the bus. The data transfer unit executes a data transfer process for transferring data between the memory and the second processor via the bus. An execution request for the data transfer process is stored in the buffer. In addition, the first processor includes an execution instruction unit, an order determination unit, and a preprocessing execution unit. The execution instruction unit instructs the data transfer unit to execute the data transfer process based on the execution request stored in the buffer. The order determination unit determines the processing order of the plurality of execution requests by the execution instruction unit based on the amount of transfer data corresponding to each of the plurality of execution requests stored in the buffer. The pre-processing execution unit executes a predetermined pre-processing corresponding to the data transfer processing executed next to the data transfer processing during the execution of the data transfer processing by the data transfer unit.

A data transfer method according to another aspect of the present invention is a data transfer method for transferring data between a first processor, a memory connected to a bus, a second processor, and the memory and the second processor via the bus. It is executed by an image forming apparatus including a data transfer unit for executing the process and a buffer for storing the execution request of the data transfer process, and the first processor performs an instruction step, a determination step, and an execution step. Execute. In the instruction step, the data transfer unit is instructed to execute the data transfer process based on the execution request stored in the buffer. In the determination step, the processing order of the plurality of execution requests by the instruction step is determined based on the amount of transfer data corresponding to each of the plurality of execution requests stored in the buffer. In the execution step, a predetermined preprocessing corresponding to the data transfer process executed next to the data transfer process is executed during the execution of the data transfer process by the data transfer unit.

According to the present invention, it is possible to efficiently shorten the processing time of a plurality of data transfer processing execution requests stored in the buffer.

FIG. 1 is a diagram showing a configuration of an image forming apparatus according to an embodiment of the present invention. FIG. 2 is a diagram showing a processing procedure of serial communication executed by the image forming apparatus according to the embodiment of the present invention. FIG. 3 is a diagram showing a processing procedure of serial communication continuously executed by the image forming apparatus according to the embodiment of the present invention. FIG. 4 is a diagram showing a processing procedure of serial communication continuously executed by the image forming apparatus according to the embodiment of the present invention. FIG. 5 is a flowchart showing an example of communication control processing executed by the image forming apparatus according to the embodiment of the present invention. FIG. 6 is a flowchart showing an example of data communication processing executed by the image forming apparatus according to the embodiment of the present invention. FIG. 7 is a diagram showing a configuration of an image forming apparatus according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The following embodiments are examples that embody the present invention, and do not limit the technical scope of the present invention.

First, the configuration of the image forming apparatus 2 according to the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the image forming apparatus 2.

As shown in FIG. 1, the image forming apparatus 2 includes a master processor 4 (an example of a first processor in the present invention), a DMA (Direct Memory Access) controller 5 (an example of a data transfer unit in the present invention), and a memory. A serial data bus 8 (an example of a bus in the present invention), a plurality of functional units 10, and a plurality of slave processors 12 (an example of a second processor in the present invention) are provided. The master processor 4, the DMA controller 5, the memory 6, and the plurality of slave processors 12 are connected to each other so as to be able to communicate with each other via the serial data bus 8. The plurality of slave processors 12 are provided in functional units 10 that are different from each other. In FIG. 1, each of the functional units 10 is indicated by a broken line.

Each of the plurality of functional units 10 executes any one of the plurality of functions included in the image forming apparatus 2. For example, the image forming apparatus 2 has an image forming function. Further, one of the plurality of functional units 10 is an image forming unit 20 (see FIG. 7). The image forming unit 20 can execute a function of forming an image on a sheet based on image data, that is, an image forming function. The sheet used for printing in the image forming apparatus 2 is, for example, printing paper.

The slave processor 12 controls the functional unit 10 provided with the slave processor 12. That is, the slave processor 12 controls the operation of each component of the functional unit 10 provided with the slave processor 12 under the control of the master processor 4, and realizes the function corresponding to the functional unit 10. Further, the slave processor 12 notifies the master processor 4 of the detection result by the sensor included in the functional unit 10 provided with the slave processor 12. For example, the slave processor 12 is an ASIC (Application Specific Integrated Circuit).

Specifically, the slave processor 12 includes a plurality of registers 14. A register address is assigned to each of the plurality of registers 14. Control data used for controlling the functional unit 10 is stored in the register 14. The slave processor 12 controls the functional unit 10 according to the control data stored in the register 14. Further, the register 14 stores detection data indicating the detection result by the sensor connected to the slave processor 12. The detected data is transmitted to the master processor 4. For example, the master processor 4 generates the control data to be transmitted to the slave processor 12 based on the detection data received from the slave processor 12.

The memory 6 stores various data. For example, the memory 6 is a semiconductor memory such as a RAM (Random Access Memory) and a flash memory. The control data transmitted to the slave processor 12 is stored in the memory 6. Further, the detection data received from the slave processor 12 is stored in the memory 6.

The DMA controller 5 executes a data transfer process of transferring data between the memory 6 and the slave processor 12 via the serial data bus 8 in response to an instruction from the master processor 4. The data transfer process includes a first transfer process of transferring the control data stored in the memory 6 to the slave processor 12. Further, the data transfer process includes a second transfer process of transferring the detected data stored in the register 14 of the slave processor 12 to the memory 6.

As shown in FIG. 1, the memory 6 includes a buffer 24. The buffer 24 stores execution request data indicating an execution request for the data transfer process. For example, the execution request data includes transfer source information indicating a transfer source of transfer target data, transfer destination information indicating a transfer destination of transfer target data, data amount information indicating a data amount of transfer target data, and the like. The buffer 24 has a storage capacity capable of storing a plurality of the execution request data. In the image forming apparatus 2, the execution request data generated during the operation of the image forming apparatus 2 is accumulated in the buffer 24.

For example, the execution request data indicating the execution request of the first transfer process includes the transfer source information indicating the memory address in which the control data which is the transfer target data is stored, and the register address to which the control data is written. The transfer destination information to be shown and the data amount information to show the data amount of the control data are included.

Further, in the execution request data indicating the execution request of the second transfer process, the transfer source information indicating the register address in which the detection data which is the transfer target data is stored and the memory address to which the detection data is written are included. The transfer destination information to be shown and the data amount information to show the data amount of the detected data are included.

The execution request data may indicate an execution request of the data transfer process for continuously transferring a plurality of transfer target data. That is, the execution request data may include a plurality of the transfer source information, a plurality of the transfer destination information, and a plurality of the data amount information. Further, the buffer 24 may be provided outside the memory 6.

The master processor 4 controls each of the plurality of slave processors 12 by executing serial communication with each of the plurality of slave processors 12. Here, serial communication is a communication method in which serial data is sequentially transmitted one bit at a time on a transmission path in telecommunications. The master processor 4 performs serial communication according to the communication protocol set in the image forming apparatus 2. For example, the master processor 4 is a CPU (Central Processing Unit).

Specifically, the master processor 4 executes serial communication with the slave processor 12 via the DMA controller 5 based on the execution request data stored in the buffer 24.

Here, a procedure for processing serial communication executed by the image forming apparatus 2 will be described with reference to FIG. FIG. 2 is a diagram showing a processing procedure of serial communication executed by the image forming apparatus 2 together with a data processing subject and a clock 30.

The master processor 4 executes serial communication when the execution request data is stored in the buffer 24. As shown in FIG. 2, the master processor 4 executes the pre-processing corresponding to the data transfer processing before the data transfer processing based on the execution request data is executed. In the preprocessing, control information based on the communication protocol set in the image forming apparatus 2 is added to the transfer target data specified by the transfer source information included in the execution request data. For example, the control information includes commands, address information, and checksums. The command includes a command to a transfer destination device (memory 6 or slave processor 12). The address information is the forwarding destination information. The checksum includes an error detection code and is used for error detection. That is, the checksum is used to confirm the consistency of communication. In serial communication, serial data 32 including the control information and transfer target data is transferred. The pre-processing may include a process of including the preamble and the post-amble in the serial data 32. For example, the preamble is a delimiter bit string arranged at the beginning of serial data 32 in serial communication. Further, the post amble is a delimiter bit string to be included at the end of the serial data 32.

After the completion of the preprocessing, the master processor 4 instructs the DMA controller 5 to execute the data transfer process based on the execution request data. As a result, as shown in FIG. 2, the DMA controller 5 executes the DMA transfer synchronized with the clock 30 generated by the master processor 4, that is, the data transfer process. Specifically, the DMA controller 5 that receives the instruction from the master processor 4 transfers the serial data 32 from the transfer source device to the transfer destination device.

As shown in FIG. 2, the master processor 4 executes post-processing corresponding to the data transfer processing after the data transfer processing by the DMA controller 5 is completed. In the post-processing, the consistency of communication is confirmed based on the communication protocol set in the image forming apparatus 2. For example, the consistency of communication is confirmed by executing the checksum comparison process included in the serial data 32. After the completion of the post-processing, the transfer destination device executes a process of writing the transfer target data to the designated address according to the command included in the received serial data 32.

By the way, when the buffer 24 stores the two execution request data, the master processor 4 is performing the second data transfer process corresponding to the first execution request data by the DMA controller 5. It is possible to execute the preprocessing corresponding to the execution request data of.

For example, in the buffer 24, the first execution request data corresponding to the transfer of the serial data 34 shown in FIG. 3 and the second execution request data corresponding to the transfer of the serial data 36 having a smaller amount of data than the serial data 34. And is stored. In FIG. 3, the pre-processing and the post-processing corresponding to the transfer of the serial data 34 are shown as the first pre-processing and the first post-processing, respectively. Further, in FIG. 3, the pre-processing and the post-processing corresponding to the transfer of the serial data 36 are shown as the second pre-processing and the second post-processing, respectively.

In this case, the master processor 4 is performing the preprocessing (during the transfer of the serial data 34) corresponding to the second execution request data while the data transfer process corresponding to the first execution request data is being executed (during the transfer of the serial data 34). The second preprocessing) can be executed. As a result, the execution start timing of the data transfer process corresponding to the second execution request data is advanced, so that the processing time of the two execution request data stored in the buffer 24 can be shortened.

Here, when the execution request data having a small amount of transfer data is processed first, the master processor 4 is executing the data transfer process corresponding to the first execution request data by the DMA controller 5. The preprocessing corresponding to the second execution request data may not be completed. The transfer data amount is the amount of data to be transferred in the data transfer process for which execution is requested by the execution request data.

For example, suppose that the master processor 4 processes the second execution request data before the first execution request data. In this case, as shown in FIG. 4, the master processor 4 is executing the data transfer process corresponding to the second execution request data (during the transfer of the serial data 36), the first execution request data. The pretreatment (first pretreatment) corresponding to the above cannot be completed. Here, the unfinished portion of the pre-processing is executed after the post-processing (second post-processing) corresponding to the first execution request data. Therefore, the processing time of the two execution request data stored in the buffer 24 is extended as compared with the case where the first execution request data is processed first. Even when three or more of the execution request data are stored in the buffer 24, for example, when the other execution request data is processed after the execution request data having the smallest transfer data amount, the same applies. Problems arise.

On the other hand, in the image forming apparatus 2 according to the embodiment of the present invention, as described below, it is possible to efficiently shorten the processing time of the plurality of execution request data stored in the buffer 24.

Specifically, as shown in FIG. 1, the master processor 4 includes an execution instruction unit 25, an order determination unit 26, and a preprocessing execution unit 27. The master processor 4 executes a communication control program stored in a ROM (not shown). As a result, the master processor 4 functions as an execution instruction unit 25, an order determination unit 26, and a preprocessing execution unit 27. The communication control program is recorded on a computer-readable recording medium such as a CD, DVD, or flash memory, and is read from the recording medium and installed in a non-volatile storage device provided in the image forming apparatus 2. You may.

The execution instruction unit 25 instructs the DMA controller 5 to execute the data transfer process based on the execution request data stored in the buffer 24.

The order determination unit 26 determines the processing order of the plurality of execution request data by the execution instruction unit 25 based on the amount of transfer data corresponding to each of the plurality of execution request data stored in the buffer 24.

For example, the order determination unit 26 determines the processing order of the plurality of execution request data by the execution instruction unit 25 in descending order of the amount of transferred data. That is, the order determination unit 26 determines the processing order of the plurality of execution request data so that the processing order becomes faster as the amount of transferred data increases.

Further, the order determination unit 26 determines the processing order of all the execution request data stored in the buffer 24, and buffers the processing order of the execution request data stored in the buffer 24 after the determination at the time of the determination. It is subordinated to the execution request data stored in 24.

Specifically, the order determination unit 26 determines the processing order of the plurality of execution request data stored in the buffer 24 every time all the execution request data whose processing order is determined is processed.

While the DMA controller 5 is executing the data transfer process, the pre-process execution unit 27 executes the pre-process corresponding to the data transfer process executed next to the data transfer process.

[Communication control processing]
Hereinafter, the data transfer method in the present invention will be described together with the procedure of the communication control process executed by the master processor 4 in the image forming apparatus 2 with reference to FIG. Here, steps S11, S12 ... Represent the number of the processing procedure (step) executed by the master processor 4. The communication control process is executed, for example, when any function of the image forming apparatus 2 is executed in the image forming apparatus 2.

<Step S11>
First, in step S11, the master processor 4 sets the value of the variable n to 0 as an initial process. Here, the variable n is a variable used for recording the remaining number of the execution request data whose processing order is determined.

<Step S12>
In step S12, the master processor 4 determines whether or not the execution request for the data transfer process has occurred.

Here, when the master processor 4 determines that the execution request for the data transfer process has occurred (Yes side of S12), the master processor 4 shifts the process to step S13. Further, if the execution request of the data transfer process has not been generated (No side of S12), the master processor 4 waits for the generation of the execution request of the data transfer process in step S12.

<Step S13>
In step S13, the master processor 4 stores the execution request data corresponding to the generated execution request in the buffer 24.

<Step S14>
In step S14, the master processor 4 determines whether or not the value of the variable n is 0. That is, the master processor 4 determines whether or not the remaining number of the execution request data whose processing order has been determined is 0.

Here, when the master processor 4 determines that the value of the variable n is 0 (Yes side of S14), the master processor 4 shifts the process to step S15. If the value of the variable n is not 0 (No side of S14), the master processor 4 shifts the process to step S17.

<Step S15>
In step S15, the master processor 4 determines the processing order for each of the execution request data stored in the buffer 24. Here, the process of step S15 is an example of the determination step in the present invention, and is executed by the order determination unit 26 of the master processor 4.

Specifically, the master processor 4 processes each of the execution request data stored in the buffer 24 so that the processing order is higher as the amount of transferred data is larger, that is, the processing is performed at a faster timing. Determine the order. The master processor 4 can recognize the transfer data amount corresponding to each of the execution request data based on the data amount information included in the execution request data.

<Step S16>
In step S16, the master processor 4 sets the value of the variable n to a value indicating the number of execution request data whose processing order is determined in step S15.

<Step S17>
In step S17, the master processor 4 executes the data communication process described later.

<Step S18>
In step S18, the master processor 4 deletes the execution request data having the highest processing order among the execution request data stored in the buffer 24.

<Step S19>
In step S19, the master processor 4 decrements the value of the variable n. That is, the master processor 4 executes an operation of reducing the value of the variable n by 1.

<Step S20>
In step S20, the master processor 4 determines whether or not the execution request data is stored in the buffer 24.

Here, when the master processor 4 determines that the execution request data is stored in the buffer 24 (Yes side of S20), the master processor 4 shifts the process to step S14. If the execution request data is not stored in the buffer 24 (No side of S20), the master processor 4 terminates the communication control process.

[Data communication processing]
Next, the procedure of the data communication process executed in step S17 of the communication control process will be described with reference to FIG.

<Step S31>
First, in step S31, the master processor 4 determines whether or not the preprocessing corresponding to the execution request data having the highest processing order among the execution request data stored in the buffer 24 has been completed. To do. The method of this determination will be described later.

Here, when the master processor 4 determines that the pre-processing corresponding to the execution request data having the highest processing order has been completed (Yes side of S31), the master processor 4 shifts the processing to step S33. Further, if the pre-processing corresponding to the execution request data having the highest processing order is not completed (No side of S31), the master processor 4 shifts the processing to step S32.

<Step S32>
In step S32, the master processor 4 executes the pre-processing corresponding to the execution request data having the highest processing order. If a part of the pre-processing corresponding to the execution request data having the highest processing order is not completed, the master processor 4 executes the processing for the unfinished part of the pre-processing.

<Step S33>
In step S33, the master processor 4 instructs the DMA controller 5 to execute the data transfer process based on the execution request data having the highest processing order. Here, the process of step S33 is an example of the instruction step in the present invention, and is executed by the execution instruction unit 25 of the master processor 4.

<Step S34>
In step S34, the master processor 4 determines whether or not the data transfer process by the DMA controller 5 has been completed.

Here, when the master processor 4 determines that the data transfer process by the DMA controller 5 is completed (Yes side of S34), the master processor 4 shifts the process to step S39. If the data transfer process by the DMA controller 5 is not completed (No side of S34), the master processor 4 shifts the process to step S35.

<Step S35>
In step S35, the master processor 4 determines whether or not the execution request for the data transfer process has occurred.

Here, when the master processor 4 determines that the execution request for the data transfer process has occurred (Yes side of S35), the master processor 4 shifts the process to step S36. Further, if the execution request of the data transfer process has not occurred (No side of S35), the master processor 4 shifts the process to step S37.

<Step S36>
In step S36, the master processor 4 stores the execution request data corresponding to the generated execution request in the buffer 24.

By storing the execution request data in the buffer 24 in step S36, the execution request data whose processing order is determined and the execution request data whose processing order is not determined are mixed in the buffer 24. It will be. In the communication control process, when all of the execution request data in which the processing order stored in the buffer 24 is determined is processed, the execution request data in which the processing order stored in the buffer 24 is not determined is determined. The processing order is determined for each of. That is, when it is determined that the remaining number of the execution request data whose processing order is determined in step S14 is 0, the processing of step S15 is executed. As a result, the execution of the execution request data having a small amount of transfer data is repeatedly postponed as compared with the configuration in which the processing of step S15 is executed before the remaining number of the execution request data whose processing order is determined becomes 0. It is possible to avoid being made.

<Step S37>
In step S37, the master processor 4 determines whether or not the value of the variable n is 2 or more. That is, the master processor 4 determines whether or not the execution request data whose processing order has been determined remains in the buffer 24 in addition to the execution request data currently being processed.

Here, when the master processor 4 determines that the value of the variable n is 2 or more (Yes side of S37), the master processor 4 shifts the process to step S38. Further, if the value of the variable n is not 2 or more (No side of S37), the master processor 4 shifts the process to step S34.

<Step S38>
In step S38, the master processor 4 executes the preprocessing corresponding to the execution request data in the next order of processing order. That is, the master processor 4 executes the preprocessing corresponding to the execution request data whose processing order is higher than that of the execution request data currently being processed. Here, the process of step S38 is an example of the execution step in the present invention, and is executed by the preprocessing execution unit 27 of the master processor 4.

Here, the preprocessing executed in step S38 is executed until the preprocessing is completed or the data transfer processing by the DMA controller 5 is completed. If the master processor 4 finishes the preprocessing before the data transfer process by the DMA controller 5 finishes, the master processor 4 records that fact in the memory 6. If the data transfer process by the DMA controller 5 is completed before the preprocess is completed, the master processor 4 records the progress of the preprocess in the memory 6. Thereby, in step S31, the master processor 4 can determine whether or not the pre-processing corresponding to the execution request data having the highest processing order has been completed.

<Step S39>
In step S39, the master processor 4 executes the post-processing corresponding to the completed data transfer processing.

In addition, the order determination unit 26 determines the processing order in descending order of the amount of transferred data, but instead of determining the processing order, the first execution request in which the amount of transferred data is less than a predetermined threshold among the plurality of said execution request data. The data processing order may be inferior to the second execution request data in which the amount of transferred data is equal to or greater than the threshold value. For example, the threshold value is a value such that the data transfer time of the amount of data indicated by the threshold value is shorter than the time obtained by adding a predetermined time to the average processing time of the preprocessing by the master processor 4. In this case, the order determination unit 26 determines the processing order of the plurality of the second execution requests in the order of the earliest storage order in the buffer 24. Further, the order determination unit 26 determines the processing order of the plurality of first execution requests in the order of the largest amount of transferred data or the earliest storage order in the buffer 24.

Further, when the number of the execution requests stored in the buffer 24 exceeds the predetermined first reference value, the order determination unit 26 processes the processing order of all the execution request data stored in the buffer 24. You do not have to decide. Specifically, the order determination unit 26 uses the same number of execution request data as the first reference value selected in the order of earliest storage in the buffer 24 among all the execution request data stored in the buffer 24. The processing order is determined within the configured group, and the processing order of the execution request data outside the group stored in the buffer 24 at the time of the determination and the execution request data stored in the buffer 24 after the determination is determined. , May be inferior to the execution request data in the group. The first reference value may be an arbitrarily determined numerical value.

Further, the order determination unit 26 determines the processing order of the plurality of execution request data stored in the buffer 24 every time all the execution request data whose processing order is determined is processed. , The processing order may be determined as shown below. That is, the order determination unit 26 is stored in the buffer 24 when the number of undetermined execution request data whose processing order is not determined is equal to or greater than a predetermined second reference value. The processing order of all or the same number of the undetermined execution request data as the second reference value may be determined. The second reference value may be an arbitrarily determined numerical value.

For example, in the master processor 4, even if the value of the variable n is determined not to be 0 in step S14, the number of undetermined execution request data stored in the buffer 24 is equal to or greater than the second reference value. If, the processing order of each of the undetermined execution request data may be determined. In this case, the master processor 4 makes the undecided execution request inferior to the execution request data (that is, the execution request data whose processing order has been determined) different from the undecided execution request data. Determine the processing order of each data.

Further, the master processor 4 receives the undetermined execution request data stored in the buffer 24 while the processes from step S34 to step S38 are being executed, that is, during the execution of the data transfer process by the DMA controller 5. When the number is equal to or greater than the second reference value, the processing order of each of the undetermined execution request data may be determined. For example, the master processor 4 determines that the number of undetermined execution request data stored in the buffer 24 is equal to or greater than the second reference value after the preprocessing executed in step S38 is completed. It is possible to determine the processing order of each undetermined execution request data.

Next, a detailed configuration of the image forming apparatus 2 according to the present embodiment will be described with reference to FIG. 7. FIG. 7 is a diagram showing a detailed configuration of the image forming apparatus 2.

As shown in FIG. 7, of the plurality of functional units 10, one functional unit 10 is a document transport unit 16 and the other functional unit 10 is a document reading unit 18. Yet another functional unit 10 is an image forming unit 20, and yet another functional unit 10 is a transport unit 22.

The document transport unit 16 transports the document toward the document reading unit 18. The slave processor 12 of the document transfer unit 16 controls each configuration of the document transfer unit 16 based on the data (the control data) written in the register 14 (see FIG. 1). For example, the document transport unit 16 is an ADF (Auto Document Feeder).

The document reading unit 18 reads an image contained in the document. The slave processor 12 of the document reading unit 18 controls each configuration of the document reading unit 18 based on the data (the control data) written in the register 14 (see FIG. 1). For example, the document reading unit 18 is a scanner.

The image forming unit 20 forms an image on a sheet such as printing paper by an electrophotographic method. The image forming unit 20 includes a photoconductor drum 139, a charging device 140, an exposure device 142, a developing device 144, a transfer device 146, and a fixing device 148.

The photoconductor drum 139 rotates about a rotation axis. The photoconductor drum 139 has a photosensitive layer on the outer peripheral surface side. The charging device 140 charges the photosensitive layer of the photoconductor drum 139 to a predetermined potential. The exposure apparatus 142 irradiates the photosensitive layer of the photoconductor drum 139 with laser light to expose the photosensitive layer based on the image data. As a result, an electrostatic latent image is formed on the photoconductor drum 139.

The developing device 144 develops an electrostatic latent image on the photoconductor drum 139. The developing device 144 has a developing roller. The developing roller supplies toner to the photoconductor drum 139 to develop an electrostatic latent image on the photoconductor drum 139. As a result, a toner image is formed on the outer peripheral surface of the photoconductor drum 139. The transfer device 146 transfers the toner image formed on the outer peripheral surface of the photoconductor drum 139 to the sheet. The fixing device 148 heats and pressurizes the sheet to fix the toner image transferred to the sheet to the sheet.

The slave processor 12 of the image forming unit 20 has a photoconductor drum 139, a charging device 140, an exposure device 142, a developing device 144, and a transfer device based on the data (the control data) written in the register 14 (see FIG. 1). It controls 146 and the fixing device 148.

The transport unit 22 transports the sheet along the transport path in the image forming apparatus 2. The slave processor 12 of the transport unit 22 controls each configuration of the transport unit 22 based on the data (the control data) written in the register 14 (see FIG. 1). For example, the transport unit 22 includes a transport roller and a drive source (for example, a motor).

A slave processor 12 is associated with each of the document transport unit 16, the document reading unit 18, the image forming unit 20, and the transport unit 22. Each slave processor 12 processes a job request from the master processor 4 to the document transfer unit 16, the document reading unit 18, the image forming unit 20, and the transport unit 22.

As described above, in the image forming apparatus 2, the processing order of the plurality of execution request data by the master processor 4 is based on the amount of transfer data corresponding to each of the plurality of execution request data stored in the buffer 24. Is determined. As a result, it is possible to efficiently reduce the processing time of the plurality of execution request data stored in the buffer 24.

2 Image processor 4 Master processor 5 DMA controller 6 Memory 8 Serial data bus 10 Functional unit 12 Slave processor 14 Register 16 Document transfer unit 18 Document reading unit 20 Image forming unit 22 Transfer unit 24 Buffer 25 Execution instruction unit 26 Order determination unit 27 Pre-processing execution unit

Claims (8)

With the first processor
The memory connected to the bus and the second processor,
A data transfer unit that executes a data transfer process for transferring data between the memory and the second processor via the bus, and a data transfer unit.
A buffer for storing an execution request for the data transfer process is provided.
The first processor is
An execution instruction unit that instructs the data transfer unit to execute the data transfer process based on the execution request stored in the buffer.
An order determination unit that determines the processing order of the plurality of execution requests by the execution instruction unit based on the amount of transfer data corresponding to each of the plurality of execution requests stored in the buffer.
A pre-processing execution unit that executes a predetermined pre-processing corresponding to the data transfer processing that is executed next to the data transfer processing during the execution of the data transfer processing by the data transfer unit.
An image forming apparatus comprising. The order determination unit determines the processing order of a plurality of the execution requests by the execution instruction unit in descending order of the amount of transferred data.
The image forming apparatus according to claim 1. The order determination unit sets the processing order of the first execution request whose transfer data amount is less than a predetermined threshold value among the plurality of execution requests than that of the second execution request whose transfer data amount is equal to or more than the threshold value. Subordinate,
The image forming apparatus according to claim 1. The order determination unit determines the processing order of all the execution requests stored in the buffer, and the processing order of the execution requests stored in the buffer after the determination is stored in the buffer at the time of the determination. Subordinated to the above execution request,
The image forming apparatus according to any one of claims 1 to 3. When the number of the execution requests stored in the buffer is equal to or less than a predetermined first reference value, the order determination unit determines the processing order of all the execution requests stored in the buffer. Then, the processing order of the execution requests stored in the buffer after the determination is subordinated to the execution requests stored in the buffer at the time of the determination, and the number of the execution requests stored in the buffer is said. When the value exceeds the first reference value, a group composed of the same number of execution requests as the first reference value selected in the order of earliest storage in the buffer among all the execution requests stored in the buffer. The processing order is determined within the group, and the processing order of the execution request outside the group stored in the buffer at the time of the determination and the execution request stored in the buffer after the determination is determined from the execution request in the group. To subordinate,
The image forming apparatus according to any one of claims 1 to 3. The order determination unit determines the processing order of a plurality of the execution requests stored in the buffer every time all the execution requests whose processing order is determined are processed.
The image forming apparatus according to claim 4 or 5. When the number of undetermined execution requests whose processing order is not determined stored in the buffer is equal to or greater than a predetermined second reference value, the order determination unit determines the processing order of the undetermined execution requests. decide,
The image forming apparatus according to claim 4 or 5. A first processor, a memory connected to a bus, a second processor, a data transfer unit that executes a data transfer process for transferring data between the memory and the second processor via the bus, and the data transfer process. A data transfer method executed by an image forming apparatus including a buffer for storing an execution request of.
The first processor
An instruction step for instructing the data transfer unit to execute the data transfer process based on the execution request stored in the buffer, and
A determination step of determining the processing order of the plurality of execution requests by the instruction step based on the amount of transfer data corresponding to each of the plurality of execution requests stored in the buffer.
During the execution of the data transfer process by the data transfer unit, an execution step of executing a predetermined preprocess corresponding to the data transfer process executed after the data transfer process, and an execution step.
Data transfer method to perform.