JP2015115049A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer that normally writes an abnormal group having abnormal data stored in a read-only memory unit into another free area while securing capacity.SOLUTION: A microcomputer executes error correction of abnormal data when there are abnormal data, for each group stored in a ROM (S400), and executes write object determination processing for determining whether or not each group is an object to be written into a RAM on the basis of the priority level and data amount of the group, regardless of an abnormal group or a normal group(S402). When the group is not an object to be written (S404: No), the group is determined to be unnecessary and not written into the RAM (S406). When the group is an object to be written (S404: Yes) and there is a write area in the RAM (S408: Yes), data in the pertinent group of the ROM are written into the RAM (S410).

Description

  The present invention relates to a microcomputer mounted on an on-vehicle electronic control device that writes abnormal data stored in a read-only storage unit to a readable / writable storage unit.

  If an abnormality occurs in the storage unit of the electronic control unit and data such as a program or a constant cannot be read normally, normal processing cannot be executed. In this case, it is conceivable to retry reading by resetting the electronic control unit. However, there is a problem that the processing cannot be executed if the abnormality of the storage unit is not recovered even after retrying.

  In particular, in the case of an electronic control device mounted on a vehicle, even if the electronic control device is reset and retried, vehicle control cannot be executed unless the abnormality of the storage unit is recovered, and thus the vehicle cannot be run normally. Therefore, it is desirable to execute vehicle control by performing appropriate processing when an abnormality occurs in the storage unit.

  Therefore, in the technique disclosed in Patent Document 1, when the data stored in the writable storage device is abnormal, the abnormal data is corrected and written in the empty area of the same writable storage device. Then, processing is executed based on the corrected data.

Special table 2009-506445

  In a configuration in which abnormal data is corrected and written in the free space of the same writable storage device that stores abnormal data, the capacity is insufficient unless the free space of the writable storage device is secured in advance. It may be difficult to correct and write abnormal data. In addition, since the free area is not always normal, there is a possibility that the corrected data is written in the abnormal free area.

  The present invention has been made in order to solve the above-described problem, and an in-vehicle electronic control apparatus that normally writes an abnormal group having abnormal data stored in a read-only storage unit while ensuring a capacity in another free space It aims at providing the microcomputer mounted in.

  The microcomputer of the present invention detects a read-only first storage unit, a readable / writable second storage unit, first abnormality detection means for detecting an abnormality in the first storage unit, and an abnormality in the second storage unit. Among the groups stored in the second abnormality detection means and the first storage unit, at least an abnormality group having abnormality data in which the first abnormality detection means has detected an abnormality is detected. And a writing means for writing in a normal area other than the abnormal area of the storage unit.

  According to this configuration, since an abnormal group having abnormal data is written to a second readable / writable second storage unit that is different from the read-only first storage unit, it is possible to sufficiently secure a free space capacity for writing the abnormal group. In addition, since the abnormality group is written to the normal area other than the abnormal area of the second storage unit after detecting the abnormality of the second storage unit, the abnormal data can be normally written to the second storage unit.

  And since the abnormal group is written to the readable / writable second storage unit, the abnormal data is corrected and used when necessary on the second storage unit even when the abnormal data is written to the second storage unit without correction. can do. The abnormal data may be corrected and written to the second storage unit.

The block diagram which shows the microcomputer by 1st Embodiment. The schematic diagram which shows the data writing from ROM to RAM by 1st Embodiment. The flowchart which shows a process at the time of ROM abnormality. 6 is a flowchart showing a write target determination process. The flowchart which shows RAM empty area check processing. The block diagram which shows the microcomputer by 2nd Embodiment. The schematic diagram which shows the data writing from ROM to RAM by 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
As shown in FIG. 1, the microcomputer 2 includes a CPU 10, a ROM 20, a RAM 30, and a common bus 100, and is mounted on an in-vehicle electronic control device. The CPU 10 performs memory checks on the ROM 20 and the RAM 30 when the microcomputer 2 is activated and at a certain time interval after the activation or when the processing load is low.

  As shown in FIG. 2, the ROM 20 stores data for each group divided according to priority and size based on importance. Data of each group is accessed with a relative address from the head address. The head address of each group is stored in the ROM 20 as an address table in association with each group, for example. Further, the priority and size, which are the data attributes of each group, are stored in the ROM 20 as a data attribute table, for example, for all groups.

  In FIG. 2, PgGr represents program data, CstGr represents constant data, VarGr represents variable data, and Parity represents parity data as an error correction code. “*” In PgGr_ *, CstGr_ *, and VarGr_ * represents a priority. The height of the priority is A> B> C. For example, a high priority program “A” is a program related to brake control and fuel injection control, and a low priority program “C” is a program related to correction processing.

  In this embodiment, CPU10 performs vehicle control based on data, such as a program memorize | stored in ROM20 and a constant, when abnormality of ROM20 is not detected. The variable data area is secured on the RAM 30.

  When detecting an abnormality in the ROM 20, the CPU 10 writes data stored in the ROM 20 into a normal area other than the abnormal area of the RAM 30, and executes vehicle control based on data such as programs and constants written in the RAM 30. In this embodiment, when the ROM 20 is abnormal, not only an abnormal group having abnormal data but also a normal group having normal data is written in the RAM 30.

  When an abnormal group is written in the RAM 30, parity data is used as an error correction code. If the data can correct the abnormality, the data is corrected and written to the RAM 30. For example, in FIG. 2, abnormal data exists in PgGr_B of the ROM 20, and the abnormal data is corrected and written to the RAM 30.

  The data in the ROM 20 is not written unconditionally in the RAM 30 regardless of whether it is abnormal or normal, and is a target to be written in consideration of the priority and size of each group stored in the ROM 20. It is determined whether or not. For example, in FIG. 2, since the priority of PgGr_C is low, PgGr_C is not written to the RAM 30 even if there is a free space in the RAM 30. Not only the priority but also a group that is too large is not written to the RAM 30.

  In the present embodiment, when the ROM 20 is abnormal, important data having a high priority and not too large are written from the ROM 20 to the RAM 30, so that the retreat travel is performed based on the minimum data necessary for traveling the vehicle. Is realized.

  The address table associating each group with the start address of each group described above manages the start address of the group of variable data for which an area is secured on the RAM 30, and from the ROM 20 to the RAM 30 when the microcomputer 2 is started. It is desirable to copy the data to the RAM 30 and use it while correcting it appropriately in the RAM 30.

(ROM abnormal processing)
3 is executed when an abnormality in the ROM 20 is detected. In FIG. 3 and FIGS. 4 and 5 described later, “S” represents a step.

  If each group stored in the ROM 20 has abnormal data, the CPU 10 performs error correction of the abnormal data (S400), and whether or not it is a target to be written to the RAM 30 regardless of the abnormal group or the normal group. Is executed (S402). Details of the write target determination processing in S402 will be described with reference to FIG.

  When the corresponding group is not a write target (S404: No), the CPU 10 determines that the corresponding group is unnecessary, does not write it in the RAM 30 (S406), and shifts the processing to S412. The start address of the group that is not written in the RAM 30 is deleted from the address table, or data indicating that it is an unnecessary group is written.

  When the corresponding group is a write target (S404: Yes), the CPU 10 determines whether or not there is a write area in the RAM 30 (S408). The CPU 10 performs a memory check including a free space check of the RAM 30 at a certain time interval or when the processing load is low at the time of starting and after starting, and detects an abnormal region and a normal region and stores them as information. It can be determined whether or not there is a capacity for writing the group in the normal area of the RAM 30.

  If there is no writing area (S408: No), the CPU 10 determines that the corresponding group is unnecessary, does not write it to the RAM 30 (S406), and shifts the processing to S412. As described above, the start address of the group that is not written in the RAM 30 is deleted from the address table, or data indicating that it is an unnecessary group is written.

  When there is a writing area (S408: Yes), the CPU 10 writes the data of the corresponding group in the ROM 20 to the RAM 30 (S410), and shifts the processing to S412. When the data of the corresponding group in the ROM 20 is written in the RAM 30, the head address of the area written in the RAM 30 is written in the address table instead of the head address in the ROM 20 of the corresponding group.

  In S <b> 412, the CPU 10 determines whether or not the writing target determination has been completed for all groups in the ROM 20. When the determination of the write target is not completed for all groups (S412: No), the CPU 10 returns the process to S400, and when the determination of the write target is complete for all groups (S412: Yes), this The process ends.

(Write target judgment process)
The writing target determination process in FIG. 4 is a process executed in S402 in FIG. In S420, the CPU 10 determines whether the priority of the corresponding group stored in the ROM 20 is equal to or higher than a predetermined priority. When the priority is lower than the predetermined priority (S420: No), the CPU 10 returns “No” as the processing result (S422), and ends this processing.

When the priority is equal to or higher than the predetermined priority (S420: Yes), the CPU 10 determines whether or not the data amount of the corresponding group is equal to or smaller than a predetermined value (S424).
When the size is equal to or smaller than the predetermined value (S424: Yes), the CPU 10 returns “Yes” as the processing result (S426). When the size is larger than the predetermined value (S424: No), the CPU 10 returns “No” as the processing result. Is returned (S422), and this process is terminated.

(RAM free space check process)
The free space check process of the RAM 30 in FIG. 5 is executed at a constant time interval or when the processing load is low during and after activation. The empty area check in the RAM 30 may be performed for each block having a certain size or may be performed for each continuous empty area.

In S430, the CPU 10 determines whether or not there is a free area in the RAM 30. When there is no free space in the RAM 30 (S430: No), the CPU 10 ends this process.
When there is an empty area in the RAM 30 (S430: Yes), the CPU 10 determines whether or not the empty area is normal (S432). When the free area is abnormal (S432: No), the CPU 10 shifts the process to S436. If the free area is normal (S432: Yes), the CPU 10 sets the head address of the free area as a relocation address for writing data in the ROM 20 (S434).

  When the check of the empty area is not completed for all the areas of the RAM 30 (S436: No), the CPU 10 returns the process to S430, and when the check of the empty area is completed for all the areas (S436: Yes), the process is finished. To do.

[Second Embodiment]
A second embodiment of the present invention is shown in FIGS. As shown in FIG. 6, the microcomputer 4 of the second embodiment is a multi-core microcomputer including a ROM 20, cores 40 and 50 as CPUs, a global RAM 60, and a common bus 100. The local RAMs 42 and 52 are directly connected to the cores 40 and 50 without going through the common bus 100, respectively. The cores 40 and 50 are connected to the ROM 20 and the global RAM 60 via the common bus 100.

  The local RAMs 42 and 52 are each divided into a data area and a program area. The local RAMs 42 and 52 can be accessed at a higher speed than the global RAM 60. Similar to the first embodiment, the ROM 20 stores programs and constants for each group. The global RAM 60 can be accessed from either of the cores 40 and 50.

  The memory check of the local RAMs 42 and 52 is performed for each of the cores 40 and 50. The memory check of the ROM 20 and the global RAM 60 may be performed exclusively by one of the cores 40 and 50 or may be shared by the cores 40 and 50.

  When the ROM 20 is abnormal, a predetermined priority abnormality program is preferentially written in the local RAMs 42 and 52. In addition, a group of variables having a high priority is secured in advance in the local RAMs 42 and 52. The abnormal groups such as PgGr_B and PgGr_E in FIG. 7 are written in the local RAMs 42 and 52 after the error is corrected by parity data which is an error correction code.

A group of constants with low priority is written into the global RAM 60. In addition, a group of variables having low priority has an area reserved in the global RAM 60 in advance.
Also in the second embodiment, when it is determined that it is not a write target based on the priority and size of the group, the corresponding group is not written to the local RAMs 42 and 52 and the global RAM 60.

  In the first and second embodiments described above, when the ROM 20 is abnormal, not all data stored in the ROM 20 but the priority is equal to or higher than a predetermined priority and the amount of data is equal to or smaller than a predetermined value. Since the group is written from the ROM 20 to the RAM, a sufficient capacity for writing data can be secured in the RAM.

  On the other hand, even when the ROM 20 is abnormal, all data stored in the ROM 20 is stored in the RAM, so the data is written from the ROM to the RAM, which is another storage unit. It is easy to secure in RAM.

Furthermore, since an abnormality in the RAM is detected and an abnormal group is written in a normal area other than the abnormal area, data can be normally written in the RAM.
Further, since the abnormal data of the abnormal group is corrected and written to the RAM when the ROM is abnormal, the vehicle control can be continued without resetting the microcomputer many times.

  When ROM data is written to the RAM when the ROM is abnormal, the low priority group and the large data amount group are not written to the RAM. Can be executed.

[Other Embodiments]
In the above-described embodiment, not only an abnormal group but also a normal group is written in the RAM when the ROM is abnormal. On the other hand, only the abnormal group may be written in the RAM. In this case, processing is executed in both the ROM and the RAM based on the address table in which the head address of each group is stored.

Further, the abnormal data of the abnormal group may be written in the RAM without being corrected. In this case, the abnormal data may be used after correcting the abnormal data on the RAM when the abnormal group is used.
In the above embodiment, the ROM data is written into the RAM only when the ROM is abnormal. On the other hand, when the microcomputer is activated, all ROM data may always be written into the RAM regardless of whether the ROM is abnormal or normal. At that time, the processing described with reference to FIGS.

  As described above, the present invention is not limited to the above-described embodiment, and can be applied to various embodiments without departing from the gist thereof.

2, 4: Microcomputer, 10: CPU (first abnormality detection means, second abnormality detection means, writing means, correction means, determination means), 20: ROM (first storage unit), 30: RAM (second Storage unit), 40, 50: core (first abnormality detection unit, second abnormality detection unit, writing unit, correction unit, determination unit), 42, 52: local RAM (second storage unit), 60: global RAM (Second storage unit)

Claims (7)

A read-only first storage unit (20) storing data for each predetermined group;
A second readable / writable storage unit (30, 42, 52, 60);
First abnormality detection means (10, 40, 50) for detecting an abnormality in the first storage unit;
Second abnormality detection means (10, 40, 50, S432) for detecting an abnormality in the second storage unit;
Among the groups stored in the first storage unit, the second storage unit in which the second abnormality detection unit has detected an abnormality in at least an abnormality group having abnormality data in which the first abnormality detection unit has detected an abnormality. Writing means (10, 40, 50, S410) for writing in a normal area other than the abnormal area;
A microcomputer (2, 4) characterized by comprising:   2. The micro of claim 1, further comprising correction means (10, 40, 50, S <b> 400) for correcting an error in the abnormal data when the writing means writes the abnormal group in the normal area. Computer.   3. The microcomputer according to claim 1, wherein a priority is set as a data attribute for each group.   4. The microcomputer according to claim 1, wherein a size is set as a data attribute for each group.   5. The micro of claim 3, further comprising determination means (10, 40, 50, S <b> 420, S <b> 424) for determining whether to write each group in the normal area based on the data attribute. Computer. Multi-core (40, 50)
The writing means writes at least the abnormal group in the normal area of the second storage unit (42, 52) of each core;
The microcomputer (4) according to any one of claims 1 to 5, characterized in that:   7. The writing unit according to claim 1, wherein among the groups stored in the first storage unit, the normal group without the abnormal data is also written to the normal area. The microcomputer as described.

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