JP2013182243A - Musical sound generation device and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a musical sound generation device for receiving digital audio signals at various sample rates, and for processing the received digital audio signals at the same sampling rate as that of a sound source.SOLUTION: In an SPDIF reception part 16, digital audio signals transported from the outside, and encoded by a bi-phase mark system are synchronously demodulated, and the demodulated digital audio signals are over-sampled, and the over-sampled digital audio signals are converted into the same sampling rate as that of a sound source 17.

Description

  The present invention relates to a musical sound generating apparatus and program capable of receiving digital audio signals of various sampling rates and processing received digital audio signals at the same sampling rate as a sound source.

  A technique for receiving a digital audio signal and rewriting internal data of the device itself is known. For example, Patent Document 1 discloses a reproduction process in which a bit clock and a word clock are extracted from a digital audio signal supplied to an SPDIF input terminal, and stored in a memory based on upgrade data generated from the extracted bit clock and word clock An apparatus for updating a reproduction processing function by updating a program and coefficient data for use is disclosed.

JP2002-149428

  By the way, since the technique disclosed in Patent Document 1 simply receives the upgrade data transferred by the digital audio signal and updates the device function, it receives the digital audio signal of various sampling rates and receives the received digital audio. There is a problem that the signal cannot be processed at the same sampling rate as the sound source.

  The present invention has been made in view of such circumstances, and a musical sound generating apparatus and program capable of receiving digital audio signals of various sampling rates and processing the received digital audio signals at the same sampling rate as the sound source. It is intended to provide.

  In order to achieve the above object, a musical sound generator according to the present invention includes a synchronous demodulator for demodulating in synchronism with a digital audio signal encoded by a biphase mark method, and a digital audio signal demodulated by the synchronous demodulator. Oversampling means for sampling, and sampling rate conversion means for converting the digital audio signal oversampled by the oversampling means to the same sampling rate as that of the sound source.

  In the present invention, digital audio signals of various sampling rates can be received, and the received digital audio signals can be processed at the same sampling rate as the sound source.

It is a block diagram which shows the whole structure of the musical sound generator 20 by one Embodiment. 4 is a diagram illustrating a format of an SPDIF signal input to an SPDIF receiving unit 16. FIG. It is a figure for demonstrating the preamble of a SPDIF signal. 3 is a block diagram showing a configuration of a reception processing unit 100. FIG. 2 is a block diagram showing a configuration of a signal receiving unit 101. FIG. 6 is a time chart for explaining the operation of the signal receiving unit 101. It is a time chart for demonstrating the influence of input jitter. 3 is a block diagram illustrating a configuration of a sampling rate conversion unit 300. FIG. It is a block diagram which shows the structure of the sampling rate conversion part 300 by a modification.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a musical sound generator 20 according to an embodiment. In this figure, the CPU 10 controls each part of the apparatus according to a switch event generated by the operation unit 14 and an event generated by the SPDIF receiving unit 16. The characteristic processing operation of the CPU 10 according to the gist of the present invention will be described in detail later. The ROM 11 stores various program data loaded into the CPU 10. The various programs referred to here include SPDIF input processing described later.

  The RAM 12 temporarily stores various register / flag data used for processing of the CPU 10. The keyboard 13 generates performance information such as a key-on / key-off signal, a key number, and velocity according to a performance operation (press / release key operation). The operation unit 14 has various operation switches arranged on the apparatus panel, and generates a switch event corresponding to the operated switch type. The display unit 15 displays the operation state and setting state of the apparatus on the screen in accordance with the display control signal supplied from the CPU 10.

  The SPDIF receiving unit 16 receives and demodulates a SPDIF signal (digital audio signal) transported from the outside, and PCM data handled by the sound source 17 with the received and demodulated SPDIF signal (digital audio signal), for example. And a sampling rate conversion unit 300 for converting to the same sampling rate.

  The sound source 17 is configured by a well-known waveform memory reading method, and includes a plurality of sound generation channels that perform time-division operation. In the sound source 17, the SPDIF signal (digital audio signal) converted by the SPDIF receiver 16 at the sampling rate is treated as PCM waveform data to form a musical sound. The sound system 18 performs filtering such as removing unnecessary noise from the analog output signal obtained by D / A converting the output of the sound source 17, and then amplifies the signal to generate sound from the speaker.

  Next, the signal format of the SPDIF signal input to the SPDIF receiver 16 will be described with reference to FIGS. FIG. 2 is a diagram illustrating an example of an SPDIF format for transporting 2ch stereo data. The SPDIF signal is divided into block units, and one block is composed of 192 frames # 0 to # 191. One frame period corresponds to a sampling period (1 / fs) of data to be transferred. One frame is composed of two subframes (Lch subframe and Rch subframe).

  One subframe has a 32-bit width of 0SB to 31SB. Among them, a 0-bit to 3SB includes a 4-bit synchronization code Sync Code called a preamble, and an audio sample Audio Sample with a maximum length of 24 bits of 4SB to 27SB. And a 4-bit control signal of 28SB to 31SB. The transfer data of 4SB to 31SB, excluding the synchronization code Sync Code (preamble) in the subframe, is encoded (BMC encoded) by the biphase mark method in which 1 bit is represented by 2 bits.

  Since a 4-bit synchronization code Sync Code called a preamble is not bi-phase mark modulated, it is composed of 8-symbol data as shown in FIG. Specifically, in the case of “B” representing the head and Lch of frame # 0, if the last of the preceding subframe is L, “11101000” is obtained, whereas if the last of the preceding subframe is H, “ "00010111".

  In the case of “M” representing the head / Lch other than the frame # 0, if the last of the preceding subframe is L, “11100011” is obtained, whereas if the last of the preceding subframe is H, “00011101” is obtained. . In the case of “W” representing the start of the subframe / Rch, if the end of the preceding subframe is L, “11100011” is obtained. If the end of the preceding subframe is H, “00011101” is obtained.

  Finally, as shown in FIG. 3, the synchronization code Sync Code in the first subframe in frame # 0 is “B” corresponding to the start bit, the synchronization code Sync Code in the next subframe is “W”, and the next frame #. The synchronization code Sync Code in the first subframe in 1 has a subframe format in which “W” and “M” are alternately repeated until reaching the frame # 191.

  The audio sample Audio Sample following the preamble (synchronization code Sync Code) is usually 20 bits long per sample. However, if 4 bits of spare AUX are used, 24 bit long data can be handled. In other words, if the maximum is 24 bits by BMC modulation, 48 symbols of data are provided.

  The 4-bit control signal is composed of the 28SB validity V, the 29SB user data U, the 30SB channel status C, and the 31SB even parity P. The validity V is a bit indicating validity / invalidity of the audio sample Audio Sample, and is “0 (L)” if valid, and “1 (H)” if invalid. The user data U is user-defined information, and is used, for example, to represent time information such as an elapsed time from the beginning at the time of CD recording or an elapsed time in a song with 192 bits in one block.

  The channel status C is used to indicate an audio sample Audio Sample or an attribute relating to a frame (for example, information indicating a sampling period or copyright). In the even parity P, the parity check value of the transfer data from 4SB to 31SB excluding the synchronization code Sync Code (preamble) in the subframe is set.

  Next, the configuration of the SPDIF receiving unit 16 will be described. As described above, the SPDIF receiving unit 16 receives and demodulates the SPDIF signal (digital audio signal) transported from the outside, and the received and demodulated SPDIF signal (digital audio signal), for example, the sound source 17. The sampling rate conversion unit 300 converts the sampling rate to the same sampling rate as the PCM data handled in (1).

  FIG. 4 is a block diagram illustrating a configuration of the reception processing unit 100 that receives and demodulates the SPDIF signal (digital audio signal). The reception processing unit 100 includes a signal reception unit 101, a parameter generation unit 102, a biphase decoding unit 103, a preamble detection unit 104, a frame counter 105, a bit counter 106, an enable generation unit 107, an S / P first conversion unit 108, a parity A check unit 109, an S / P second conversion unit 110, a status register 111, an Lch register 112, and an Rch register 113 are provided.

  As shown in FIG. 5, the signal receiving unit 101 includes flip-flops FF 200 to 204, an edge detection unit 205, a strobe counter 206, a comparator 207, a comparator 208, and a zero comparator 209. A shift register formed by cascade-connected flip-flops FF200 to 204 receives the SPDIF signal in synchronization with the internal clock CK.

  As illustrated in FIG. 6, the edge detection unit 205 generates a change point enable signal when a change point (frame or subframe) of the SPDIF signal synchronized with the internal clock CK is detected. The change point enable signal resets the strobe counter 206. The comparator 207 generates a strobe enable signal Ena when the counter value of the strobe counter 206 coincides with the adjustment parameter P (counter maximum value), and shifts output 1 data and output 2 data from the flip-flops FF 203 to 204, respectively. .

  By the way, the maximum length that the SPDIF signal does not change is, as described above, when the preamble is “000” or “111”. For an input signal (synchronized SPDIF signal) having the preamble, the strobe counter has jitter (allowable change width) shown in FIG.

  That is, when the preamble “000” or “111” is input, the change point does not occur twice. For this reason, the strobe counter circulates at the counter maximum value specified by the adjustment parameter P, but is not reset by the change point detection, so that the worst case of fetching data according to the second strobe enable signal Ena occurs. That is, if the internal clock CK is 8 times the input signal change frequency, as shown in FIG. 7, it is possible to allow a frequency of about 1 clock or more (± 12.5%).

  Returning to FIG. 4, the configuration of the reception processing unit 100 will be described. The parameter generation unit 102 generates an adjustment parameter P in response to an instruction from the CPU 10 and supplies the adjustment parameter P to the signal reception unit 101. The adjustment parameter P includes a counter maximum value set in the comparator 207 of the signal receiving unit 101 and a strobe value set in the comparator 208. The biphase decoding unit 103 decodes and outputs the output 1 data and output 2 data output from the signal receiving unit 101 described above. Specifically, the BMC encoded symbol “01” is decoded to data “1”, “10” to data “1”, “00” to data “0”, and “11” to data “0”.

  When the preamble detection unit 104 detects the preamble pattern described above from the output 2 data output from the signal receiving unit 101, the preamble detection unit 104 supplies a reset signal corresponding to the detected content to the frame counter 105 or the bit counter 106. That is, when “B” is detected, the frame counter 105 and the bit counter 106 are reset, and when “M” is detected, the bit counter 106 is reset. The frame counter 105 counts 192 frames # 0 to # 191 that form one block. The bit counter 106 counts 32 bits of subframes in the frame counted by the frame counter 105.

  The enable generator 107 generates an enable signal based on the counter outputs of the frame counter 105 and the bit counter 106. The S / P first conversion unit 108 performs parallel conversion on the decoded 32-bit data for one subframe. The parity check unit 109 performs a parity check based on the even parity P in the subframe. The S / P converter 110 and the status register 111 store the channel status C obtained when one block (for 192 frames) is decoded. The Lch register 112 and the Rch register 113 are loaded with an audio sample Audio Sample of an Lch subframe (or Rch subframe) in accordance with an instruction from the enable generation unit 107.

  Next, the configuration of the sampling rate conversion unit 300 will be described with reference to FIG. In this figure, the selector 301 selects either the audio signal SAL read from the Lch register 112 of the reception processing unit 100 described above or the audio signal SAR read from the Rch register 113. The subtracter 302 subtracts data selected by a selector 307, which will be described later, from the data selected by the selector 301 and outputs the result.

  The multiplier 303 multiplies the output of the subtracter 302 by a predetermined coefficient and outputs the result. The adder 304 adds the output of the selector 307 described later to the output of the multiplier 303. The Lch data Z register 305 outputs the input Lch data (audio signal SAL) by one sample delay. The Rch data Z register 306 outputs the input Rch data (audio signal SAR) with a delay of one sample.

  The selector 307 selects either one sample delay output of the Lch data Z register 305 or one sample delay output of the Rch data Z register 306 and supplies the selected one to the subtracter 302 and the adder 304. The Lch data register 308 latches and outputs the 1-sample delayed output of the Lch data Z register 305 at the sampling rate of the sound source 17. The Rch data register 309 latches and outputs the one sample delayed output of the Rch data Z register 306 at the sampling rate of the sound source 17.

  In the sampling rate conversion unit 300 composed of such a first-order IIR filter, the Lch data Z register 305 and the Rch data Z register 306 are operated with oversampling 128 times higher than the SPDIF signal processing, and the next-stage Lch Sampling rate conversion is performed by latching the data register 308 and the Rch data register 309 at the sampling rate of the sound source 17.

  Note that the sampling rate conversion unit 300 can be configured as an example FIR filter illustrated in FIG. 9 in addition to the primary IIR filter illustrated in FIG. 8. That is, as shown in FIG. 9, an LchZ0 register 350 to LchZ3 register 353 that outputs 1 sample delay, an RchZ0 register 354 to RchZ3 register 357 that outputs 1 sample delay, and a selector 358 that selects the outputs of these registers 350 to 357. Prepare.

  The table control unit 361 designates an interpolation coefficient ip (n) determined by a master counter 360 value (master counter cycle) indicating the system sampling rate and a bit counter value indicating the SPDIF input sampling rate. The interpolation table 362 reads the designated interpolation coefficient ip (n) (sampling function value) and supplies the read interpolation coefficient ip (n) to the multiplier 359 as a multiplication coefficient. The multiplier 359, the adder 363, and the accumulation register 364 generate an output Output (L) (or Output (R)) expressed by the following expressions (1) and (2), and the output Output (L). Is latched in the Lch data output register 365, and the output Output (R) is latched in the Rch data output register 366.

Output (L) = ip (n−2) × LchZ0 + ip (n−1) × LchZ1 + ip (n) × LchZ2 + ip (n + 1) × LchZ3 (1)
Output (R) = ip (n−2) × RchZ0 + ip (n−1) × RchZ1 + ip (n) × RchZ2 + ip (n + 1) × RchZ3 (2)

  As described above, according to the present embodiment, demodulation is performed in synchronization with the SPDIF signal (digital audio signal) encoded by the biphase mark method without using an analog PLL, and the demodulated digital audio signal is overwritten. After sampling, it is converted to the same sampling rate as the PCM data handled by the sound source 17, so that digital audio signals of various sampling rates can be received and the received digital audio signal can be processed at the same sampling rate as the sound source.

  As mentioned above, although one Embodiment of this invention was described, this invention is not limited to it, It is included in the invention described in the claim of this-application, and its equivalent range. Hereinafter, each invention described in the scope of claims at the beginning of the present application will be additionally described.

(Appendix)
[Claim 1]
Synchronous demodulation means for demodulating in synchronization with a digital audio signal encoded by the biphase mark method;
Oversampling means for oversampling the digital audio signal demodulated by the synchronous demodulation means;
A musical sound generating apparatus comprising: a sampling rate conversion means for converting the digital audio signal oversampled by the oversampling means to the same sampling rate as that of a sound source.

[Claim 2]
On the computer,
A synchronous demodulation step for demodulating in synchronization with a digital audio signal encoded by the biphase mark method;
An oversampling step of oversampling the digital audio signal demodulated in the synchronous demodulation step;
A program for executing a sampling rate conversion step of converting the digital audio signal oversampled in the oversampling step to the same sampling rate as that of a sound source.

10 CPU
11 ROM
12 RAM
DESCRIPTION OF SYMBOLS 13 Keyboard 14 Operation part 15 Display part 16 SPDIF receiving part 17 Sound source 18 Sound system 20 Musical sound generator 100 Reception processing part 300 Sampling rate conversion part

Claims (2)

Synchronous demodulation means for demodulating in synchronization with a digital audio signal encoded by the biphase mark method;
Oversampling means for oversampling the digital audio signal demodulated by the synchronous demodulation means;
A musical sound generating apparatus comprising: a sampling rate conversion means for converting the digital audio signal oversampled by the oversampling means to the same sampling rate as that of a sound source. On the computer,
A synchronous demodulation step for demodulating in synchronization with a digital audio signal encoded by the biphase mark method;
An oversampling step of oversampling the digital audio signal demodulated in the synchronous demodulation step;
A program for executing a sampling rate conversion step of converting the digital audio signal oversampled in the oversampling step to the same sampling rate as that of a sound source.

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