JP2013157534A - Solid state image pickup device, and manufacturing method for solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup device with an improved image quality.SOLUTION: A solid state image pickup device according to the present invention has a photoelectric conversion element, a gate electrode, and a first insulation film continuously extending on a part of a floating diffusion region. Then, the solid state image pickup device has a second insulation film provided on the first insulation film. The first insulation film has a dielectric constant higher than that of the second insulation film. Then, an end of the first insulation film extending on the floating diffusion region from a top of the gate electrode is positioned in a range of 0.25 μm or less from the end on the floating diffusion region side of the gate electrode.

Description

  The present invention relates to a solid-state imaging device and a method for manufacturing the solid-state imaging device.

Patent Document 1 discloses a CMOS solid-state imaging device provided with an antireflection film covering the light receiving portion. The antireflection film extends from the light receiving portion to the transfer gate electrode, and its end face is located on the transfer gate electrode. A side spacer is provided on the side wall of the transfer gate electrode on the detection unit side, that is, on the floating diffusion region (hereinafter referred to as FD region) side.
Patent Document 2 discloses a CMOS type solid-state imaging device having a member that covers a gate electrode of a transfer transistor from above a photodiode and extends to the FD region.

JP 2000-12822 A JP 2009-38309 A

  In the solid-state imaging device described in Patent Document 1, the transfer gate electrode can be damaged by etching when the side spacer is formed.

  Further, when a contact hole for a contact plug connected to the FD region is formed in the interlayer film, an alignment error may occur. At this time, a contact hole may be disposed at a position in contact with the transfer gate electrode or on the transfer gate electrode. In the solid-state imaging device described in Patent Document 1, since the FD region side of the transfer gate electrode is in direct contact with the interlayer film, the transfer gate electrode can be damaged by etching at this time. Furthermore, the contact plug to be connected to the FD region may be connected to the transfer gate electrode instead of the FD region.

  The member described in Patent Document 2 has not been studied for materials and the like. Depending on the material, etching damage cannot be suppressed, and depending on the dielectric constant of the material, the capacity of the FD region may increase and the image quality may deteriorate.

  An object of the present invention is to provide a solid-state imaging device with improved image quality and a method for manufacturing the solid-state imaging device.

  The solid-state imaging device of the present invention includes a photoelectric conversion element, a floating diffusion region, a contact plug that electrically connects the floating diffusion region and an input node of the amplifying unit, and the photoelectric conversion device and the floating diffusion region. A gate electrode disposed between and controlling electrical continuity between the photoelectric conversion element and the floating diffusion region, the photoelectric conversion element, the gate electrode, and a portion of the floating diffusion region continuously. A first insulating film extending to the first insulating film; the photoelectric conversion element; the gate electrode; and a second diffusion layer extending on the floating diffusion region and provided on the first insulating film. In the solid-state imaging device having an insulating film, the first insulating film is the second insulating film. The end of the first insulating film, which has a higher dielectric constant than the film and extends from above the gate electrode to the floating diffusion region, is 0.25 μm from the end of the gate electrode on the floating diffusion region side. Located in the following range.

  A method for manufacturing a solid-state imaging device according to the present invention includes a photoelectric conversion element, a floating diffusion region, and a gate electrode that controls conduction between the photoelectric conversion element and the floating diffusion region. In the method, an insulating film is formed on the photoelectric conversion element, the gate electrode, and the floating diffusion region, and the photoelectric conversion element, the gate electrode, and a part of the floating diffusion region are formed. Continuously covering and forming a resist pattern having an opening on a part of the floating diffusion region; etching the insulating film using the resist pattern as a mask; and forming a first insulating film; The photoelectric conversion element and the gate are formed on the first insulating film. Has a gate electrode covers said floating diffusion region, and a step of dielectric constant to form a lower second insulating film than the first insulating film.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the solid-state imaging device with improved image quality and a solid-state imaging device can be provided.

FIG. 2 is a schematic plan view for explaining the solid-state imaging device according to the first embodiment. The cross-sectional schematic diagram for demonstrating the solid-state imaging device of 1st Embodiment. The graph for demonstrating 1st Embodiment. Sectional schematic diagram for demonstrating the manufacturing method of the solid-state imaging device of 1st Embodiment. Sectional schematic diagram for demonstrating the manufacturing method of the solid-state imaging device of 1st Embodiment. Sectional schematic diagram for demonstrating the manufacturing method of the solid-state imaging device of 1st Embodiment. The plane schematic diagram for demonstrating the modification of the solid-state imaging device of 1st Embodiment. The plane schematic diagram for demonstrating the modification of the solid-state imaging device of 1st Embodiment.

  The solid-state imaging device of the present invention includes a first insulating film that continuously extends from the photoelectric conversion element to the gate electrode and the floating diffusion region. The solid-state imaging device includes a second insulating film that is provided on the first insulating film and continuously extends to a part of the floating diffusion region. Here, the first insulating film has a dielectric constant higher than that of the second insulating film. The portion of the first insulating film extending from the gate electrode to the floating diffusion region is located in a range of 0.25 μm or less from the end of the gate electrode on the floating diffusion region side. According to such a solid-state imaging device, it is possible to suppress an increase in the capacity of the FD region.

  Specific examples will be described in detail in the following embodiments. In the following embodiments, a case where a signal charge is an electron will be described using a CMOS solid-state imaging device as an example. However, the present invention is not limited to the CMOS type solid-state imaging device. In addition, for example, the signal charge can be changed to holes by setting the conductivity type, voltage, etc. to the opposite polarity.

(First embodiment)
The solid-state imaging device of this embodiment will be described with reference to FIGS.

  FIG. 1A is a schematic plan view for explaining the solid-state imaging device of the present embodiment. FIG. 1A shows two photodiodes 103 (photoelectric conversion elements) and a plurality of transistors for reading signal charges of the photoelectric conversion elements. The plurality of transistors include, for example, a transfer transistor 106 that transfers the signal charge of the photodiode 103 and an amplification transistor 107 that amplifies a voltage based on the signal charge and reads it as a signal. The plurality of transistors includes a selection transistor 108 for selectively outputting a signal from the amplification transistor to a signal line, and a reset transistor 109 for resetting an input node of the amplification transistor. The FD region 104 serving as the drain of the transfer transistor 106 is electrically connected to the gate electrode that is the input node of the amplification transistor 107 and the source of the reset transistor 109. Here, the circuit configuration is not limited to this type. For example, the amplification transistor may be an amplification unit including a plurality of transistors.

  These elements are provided in the active region 102 delimited by the element isolation 101 of the semiconductor substrate 100. A photodiode 103 and an FD region 104 serving as a drain of the transfer transistor 106 are provided in the active region 102. A transfer gate electrode 105, which is the gate electrode of the transfer transistor, is provided between the photodiode 103 and the FD region 104, and controls their electrical conduction. Signal charges are transferred to the FD region 104. The amplification transistor 107 amplifies and outputs a signal based on the potential of the FD region 104. An insulating member 110 is provided on any element. Here, in the drawing, the position when the insulating member 110 is provided is indicated by a dotted line. The insulating member 110 is continuously provided from the top of each photodiode 103 to the transfer gate electrode 105 and a part of the FD region 104. Here, a configuration in which two photodiodes 103 share one amplification transistor, one selection transistor, and one reset transistor is shown, but the present invention is not limited to this type. In FIG. 1A, a contact 113 provided in the FD region 104, a contact 114 provided in a wiring portion continuous with the transfer gate electrode 105, and other contacts (not indicated) are shown.

  FIG. 1B is an enlarged schematic plan view of one photodiode in FIG. In FIG. 1B, the end 112 on the FD region 104 side of the insulating member 110 is positioned on the FD region 104 side by a length XX than the end 111 on the FD region 104 side of the transfer gate electrode 105. . Here, the length XX is an insulating member provided on the FD region 104 from the end 111 on the FD region 104 side of the transfer gate electrode 105 in a so-called planar layout when viewed in a plane parallel to the surface of the semiconductor substrate. It can be said that the length is 110. Here, the length is a length along the channel length direction (y-axis direction) of the transfer transistor. The length XX can also be said to be the amount of protrusion of the insulating member 110 from the transfer gate electrode 105 to the FD region 104 side. That is, the insulating member 110 protrudes (extends) from the transfer gate electrode 105 to the FD region 104 by the length XX. The end 111 is a side surface of the transfer gate electrode 105, and the end 112 is a side surface of the insulating member 110.

  2 is a schematic cross-sectional view taken along the line AB of FIG. That is, FIG. 2 is a schematic cross-sectional view of a region including one photodiode 103, one transfer gate electrode 105, and one FD region 104. In FIG. 2, the same reference numerals are given to the components corresponding to those in FIG. In FIG. 2, the semiconductor substrate 100 is, for example, an N-type silicon substrate, and includes an N-type semiconductor region 201 and a P-type semiconductor region 202. The P-type semiconductor region 202 can function as a so-called P-type well. An element isolation 101 made of, for example, a silicon oxide film is provided on the semiconductor substrate 100. A P-type semiconductor region 203, an N-type semiconductor region 204, and an N-type semiconductor region 205 constituting the photodiode 103 are included in the active region 102 that is divided by the element isolation 101 in the semiconductor region 202. Is provided. Here, the semiconductor region 203 is a semiconductor region for making the photodiode 103 into a buried photodiode. The semiconductor region 204 and the semiconductor region 205 can function as signal charge storage regions. An FD region 104 is provided apart from the photodiode 103. The FD region 104 is made of an N-type semiconductor region. A transfer gate electrode 105 is provided between the photodiode 103 and the FD region 104 and on the gate insulating film 206. The gate insulating film 206 extends from below the transfer gate electrode 105 to above the photodiode 103 and above the FD region 104. Here, the insulating member 110 covers the photodiode 103 from above the element isolation 101 adjacent to the photodiode 103. The insulating member 110 extends over the FD region 104 so as to cover the side surface and upper surface of the transfer gate electrode 105 on the photodiode 103 side and the side surface 212 on the FD region 104 side. That is, the insulating member 110 continuously extends from above the photodiode 103 to above the FD region 104 in the y-axis direction. In the y-axis direction, an insulating film 209 that extends continuously from the photodiode 103 to the FD region 104 and covers the insulating member 110 is provided. The insulating film 209 is made of a silicon oxide film, and a contact plug 210 is provided in the opening of the insulating film 209. The contact plug 210 is a plug that is electrically connected to the FD region 104 and is electrically connected to the wiring 211 provided on the insulating film 209. The wiring 211 is electrically connected to the input node of the amplification unit. An insulating film, other wiring, and the like are formed over the wiring 211, but are omitted here.

  Here, the insulating member 110 includes an insulating film 207 having a dielectric constant higher than that of the insulating film 209. In this embodiment, the insulating film 207 is a silicon nitride film and the insulating film 208 is a silicon oxide film provided on the insulating film 207, and has a uniform thickness d. Shall. For example, the insulating film 207 has a thickness of 30 nm to 60 nm and the insulating film 208 has a thickness of 140 nm to 190 nm. In this embodiment, the insulating film 207 is 50 nm, the insulating film 208 is 160 nm, and the thickness d is 210 nm. The length XX is equal to the thickness d. That is, the length XX is 0.25 μm or less. The insulating member 110 does not have to have a laminated structure, and the material and the like are not limited. Furthermore, in the case of a laminated structure, the order of lamination is also arbitrary.

  Here, the length XX will be described. First, since the insulating member 110 has a dielectric constant higher than that of the insulating film 209, when the length XX extending over the FD region 104 is increased, the parasitic capacitance of the FD region 104 is increased. Here, when the signal voltage V, the signal charge Q, and the capacitance C of the FD region 104 are V = Q / C, when the capacitance C of the FD region 104 increases, the signal charge Q is converted into the signal voltage V. The efficiency of will decrease. A decrease in efficiency means a smaller signal. Therefore, when outputting the final signal, it is necessary to amplify the signal using a later-stage amplifier to increase the signal. However, since the noise increases at the same time as the signal is amplified, the performance of the solid-state imaging device is degraded. Therefore, the length XX is set to 0.25 μm or less. With such a configuration, an increase in the capacity of the FD region 104 can be suppressed.

  FIG. 3 illustrates the relationship between the length XX of the insulating member 110 extending above the FD region 104 and dark noise. The dark noise on the vertical axis is normalized so that the amount of noise is 1 in a structure in which a side spacer is formed on the transfer gate electrode 105 as in Patent Document 1. Here, the dark noise is obtained by obtaining a signal / noise ratio in the photodiode from a signal finally output from the solid-state imaging device. That is, the signal / noise ratio in the state where the signal finally output is divided by the amplification factor. The horizontal axis of the graph of FIG. 3 is the length XX (μm) of the insulating member 110. As shown in FIG. 3, dark noise increases as the length XX increases, but is approximately 1 when the length XX is 0.25 μm or less. Therefore, by providing the insulating member 110 so that the length XX is 0.25 μm or less, an increase in the capacity of the FD region 104 can be suppressed, and dark noise of the solid-state imaging device can be suppressed.

  Next, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS. The same components as those in the other drawings are denoted by the same reference numerals, and description thereof is omitted. Also, the description of the case where it can be manufactured by a general semiconductor manufacturing technique is omitted.

  As shown in FIG. 4A, a semiconductor substrate 100 is prepared. An element isolation 101 is formed on the semiconductor substrate 100. In the present embodiment, the element isolation 101 is formed by a LOCOS method (Local Oxidation of Silicon method). However, element isolation formed by an STI method (Shallow Trench Isolation method) or element isolation by a semiconductor region that serves as a potential barrier against signal charges may be used. Further, the semiconductor substrate 100 includes an N-type semiconductor region 201 and a P-type semiconductor region 202. This is because, for example, by performing ion implantation for forming a P-type semiconductor region in an N-type semiconductor substrate, the N-type semiconductor region 201 and the P-type semiconductor region 202 in which the N-type semiconductor substrate remains are formed. It is formed. Here, the ion implantation may be performed once or a plurality of times, and when performing the ion implantation a plurality of times, the implantation energy and the dose amount of ions can be changed. After the element isolation 101 is provided, the insulating film 401 to be the gate insulating film 206 and the transfer gate electrode 105 are formed on the semiconductor substrate 100 (FIG. 4B). The gate insulating film 206 is, for example, a silicon oxide film formed by thermally oxidizing a silicon semiconductor substrate, and may be subjected to a process such as plasma nitriding. The transfer gate electrode 105 is made of a conductor such as polysilicon. The gate electrode is provided on the active region 102 and functions as a gate of the transistor. In this embodiment, a wiring portion for supplying a voltage to the gate electrode is also formed continuously with the gate electrode.

As shown in FIG. 4C, a resist pattern 402 is formed. The resist pattern 402 has an opening 403 that exposes a region where the photodiode 103 is to be formed. Here, the resist pattern 402 may be provided so as to cover the transfer gate electrode 105. Then, ion implantation 404 is performed on the semiconductor substrate 100 using the resist pattern 402 as a mask (FIG. 4D). By the ion implantation 404, an N-type semiconductor region 205 constituting the photodiode 103 is formed. Here, the ion implantation 404 is performed, for example, using arsenic or phosphorus at a substantially vertical ion implantation angle. Next, as shown in FIG. 5A, ion implantation 501 is performed to form an N-type semiconductor region 204 constituting the photodiode 103. The ion implantation 501 is performed using, for example, arsenic or phosphorous in a direction and an angle θ ₁ that penetrates under the transfer gate electrode 105. The angle θ ₁ is 15 to 50 degrees. Here, the ion implantation 501 is performed with lower ion implantation energy and smaller dose than the ion implantation 404. Thus, the N-type semiconductor region 204 and the semiconductor region 205 of the photodiode 103 are formed.

Next, a step of forming a P-type semiconductor region 203 shown in FIG. First, a resist pattern 502 is formed. The resist pattern 502 has an opening 503 that exposes a region where the photodiode 103 is to be formed. Here, the opening 503 exposes a part of the transfer gate electrode 105 on the region side where the photodiode 103 is to be formed. Then, ion implantation 504 is performed using the resist pattern 502 and the transfer gate electrode 105 as a mask to form the semiconductor region 203. The ion implantation 504 is performed with a direction and an angle θ ₂ away from the transfer gate electrode 105 using, for example, boron. Angle theta ₂ is 15 to 50 degrees. Each ion implantation 404, 501, and 504 may be accompanied by heat treatment.

Then, the FD region 104 is formed. First, a resist pattern 505 as shown in FIG. The resist pattern 505 has an opening 506 that exposes a region where the FD region 104 is to be formed. The resist pattern 505 extends from the element isolation 101 to a part of the active region 102 where the region where the FD region 104 is to be formed is provided. The opening 506 exposes a part of the transfer gate electrode 105 on the side opposite to the photodiode 103. Then, for example, phosphorus or arsenic ions are implanted to form the FD region 104 which is an N-type semiconductor region. Here, the FD region 104 is desirably formed so that its impurity concentration is 1 × 10 ¹⁹ atoms / cm ³ or less in order to suppress an increase in capacitance. The following steps are performed using the semiconductor substrate 100 on which such an element is formed. Here, the impurity concentration is a so-called NET concentration which is a difference between the n-type impurity concentration and the p-type impurity concentration.

  As shown in FIG. 6A, a stacked body of a silicon nitride film 601 and a silicon oxide film 602 is formed on the upper surface of the semiconductor substrate 100. The stacked body covers the photodiode 103, the side and upper surfaces of the transfer gate electrode 105, and the FD region 104. Then, a resist pattern 603 shown in FIG. 6B is formed. The resist pattern 603 has an end portion that is offset from the end portion 111 on the FD region 104 side of the transfer gate electrode 105 by a length XX in the y-axis direction. The resist pattern 603 has an opening 604 that exposes the stacked body provided in a part of the FD region 104. Also in the resist pattern 603, one of the side surfaces of the opening 604 is preferably located in the range of the length XX from the end 111 of the transfer gate electrode 105 toward the FD region 104. The insulating member 110 shown in FIG. 6C is formed by etching and removing the stacked body using the resist pattern 603 as a mask. By providing such a resist pattern 603, the insulating member 110 can be formed without forming a side spacer. The end portion 112 of the insulating member 110 is located in the range of the length XX from the end portion 111 of the transfer gate electrode 105 toward the FD region 104. In the present embodiment, the end 605 of the insulating member 110 opposite to the FD region 104 is positioned on the element isolation 101, but this position can be set as appropriate.

  Thereafter, an insulating film 209 made of a silicon oxide film system, for example, BPSG or the like, covering the insulating member 110 or the like is provided. This insulating film 209 has a dielectric constant lower than that of the insulating film 207 which is a silicon nitride film. Then, a hole for contact is formed in the insulating film 209 using a technique such as etching. At this time, since the insulating film 207 of the insulating member 110 is made of a material different from that of the insulating film 209, the insulating film 207 can function as an etching stop film in etching at the time of hole formation. Since the insulating film 207 covers the upper surface and side surfaces of the transfer gate electrode 105, the transfer gate electrode 105 can be protected from etching even when a positional shift occurs during the formation of holes. After that, a configuration shown in FIG. 2 can be manufactured by forming a plug in the hole and forming a wiring. Thereafter, the solid-state imaging device is completed by forming wirings, vias, and optical members such as color filters and microlenses. Here, the insulating member 110 including the insulating film 207 made of a silicon nitride film can function as an etching stop film when performing etching for forming a contact hole in the insulating film 209. Since the insulating member 110 covers the side surface and the upper surface of the transfer gate electrode 105, the transfer gate electrode 105 can be prevented from being exposed when the contact hole is formed, and the occurrence of a short circuit can be suppressed. It becomes.

  Further, as shown in FIGS. 1A and 1B, the insulating member 110 is provided with a contact 113 of the FD region 104 on a region where the contact 114 of the wiring portion continuous to the transfer gate electrode 105 is provided. It is not provided on the area. Further, the insulating member 110 is not provided on a region where a contact in another transistor is provided. With such a configuration, it is possible to etch all contact holes under the same conditions when forming the contact holes, and it is possible to form the contact holes with higher accuracy.

  As described above, the increase in the capacity of the FD region can be suppressed by the configuration of the solid-state imaging device described in the present embodiment. In addition, according to the method for manufacturing the solid-state imaging device described in the present embodiment, it is possible to suppress a short circuit of the contact hole to the transfer gate electrode while suppressing an increase in the capacity of the FD region.

  With the above-described configuration and manufacturing method, it is possible to prevent a short circuit between the transfer gate electrode 105 and the FD region 104 and damage to the transfer gate electrode 105. This is because the contact hole etching stops at the insulating film 208 even if the contact hole of the contact connected to the FD region 104 runs over the transfer gate electrode 105 due to a manufacturing error. In addition, by defining the protrusion amount (XX) of the insulating film 208 onto the FD region 104, an increase in the capacity of the FD region 104 can be suppressed.

(Modification)
A modification of the first embodiment will be described with reference to FIGS. FIGS. 7 and 8 are schematic plan views of the solid-state imaging device corresponding to FIG. 1A, and show a modification of the arrangement of the photodiodes and the insulating member 110 according to the first embodiment. In FIG. 7 and FIG. 8, the selection transistor and the like shown in FIG. The same components as those in FIG. 1A are denoted by the same reference numerals and description thereof is omitted. In the following description, one photodiode 103, one transfer gate electrode 105, and one FD region 104 are described as one set.

  First, FIG. 7A differs from FIG. 1A in which two sets are arranged in the y-axis direction, and two sets are arranged in the x-axis direction. FIG. 7B differs from FIG. 1A in which the two sets are arranged in translational symmetry, and the two sets are arranged in line symmetry with respect to the virtual line 701. Further, in FIG. 7C, four sets are arranged by shifting 90 degrees with respect to the point 702. The so-called four groups are rotationally symmetric. 7A to 7C, the insulating member 110 can be provided similarly to FIG. 1A. That is, the insulating member 110 continuously covers the side surface and the upper surface of the transfer gate electrode 105 from above the photodiode 103, extends to the FD region 104, and extends from the end of the transfer gate electrode 105. Can be provided at 0.25 μm or less.

  Next, in FIGS. 8A to 8D, a configuration in which a plurality of photodiodes 103 are covered with the same insulating member 110 will be described.

  In FIG. 1A, an N-type semiconductor region 204 and a semiconductor region 205 constituting one photodiode 103 are arranged in one active region. In FIG. 8A, two regions 801 in which an N-type semiconductor region 204 and a semiconductor region 205 are provided in one active region 102 are located. That is, two photodiodes 103 are provided. Here, the P-type semiconductor region 203 is provided in common with the two regions 801, and the two regions 801 are separated by the P-type semiconductor region. In FIG. 8B, one photodiode 103 is disposed in each of the two active regions 102, and one insulating member 110 is disposed so as to cover the two photodiodes 103. In FIG. 8C, the number of regions 801 in FIG. 8A increases from two, and four regions 801 are provided in one active region 102. In FIG. 8D, four photodiodes 103 are provided corresponding to each of the four active regions 102. 8A to 8D, one insulating member 110 is provided so as to continuously cover the plurality of photodiodes 103. Even in such a configuration, the insulating member 110 continuously covers the side and top surfaces of the transfer gate electrode 105 from above the photodiode 103, extends to the top of the FD region 104, and extends from the end of the transfer gate electrode 105. The extending length can be set to 0.25 μm or less. Such a configuration allows further miniaturization.

  8A to 8D, a plurality of photodiodes 103 may be formed to be covered with the same single microlens. With such a configuration, a focus detection signal can be obtained. In addition, the configuration in which the plurality of photodiodes 103 are covered with the same insulating member 110 is applied to the configuration shown in FIGS. 7A to 7C, not limited to FIGS. 8A to 8D. May be.

  Hereinafter, as an application example of the solid-state imaging device described above, a camera in which the solid-state imaging device is incorporated will be described as an example. The concept of a camera includes not only a device mainly intended for photographing but also a device (for example, a personal computer or a portable terminal) that is supplementarily provided with a photographing function. The camera includes the solid-state imaging device according to the present invention exemplified as the above-described embodiment, and a processing unit that processes a signal output from the solid-state imaging device. The processing unit may include, for example, an A / D converter and a processor that processes digital data output from the A / D converter.

  The solid-state imaging device of the present invention can improve the image quality of the solid-state imaging device. In addition, the embodiments and modifications can be changed as appropriate, and combinations thereof are also possible.

Claims (12)

A photoelectric conversion element;
Floating diffusion area,
A contact plug for electrically connecting the floating diffusion region and an input node of the amplifying unit;
A gate electrode disposed between the photoelectric conversion element and the floating diffusion region, and controlling electrical conduction between the photoelectric conversion element and the floating diffusion region;
The photoelectric conversion element, the gate electrode, and a first insulating film continuously extending on a part of the floating diffusion region;
In the solid-state imaging device having the photoelectric conversion element, the gate electrode, and a second insulating film continuously extending on the floating diffusion region and provided on the first insulating film,
The first insulating film has a higher dielectric constant than the second insulating film,
An end portion of the first insulating film extending from above the gate electrode to the floating diffusion region is located within a range of 0.25 μm or less from an end portion of the gate electrode on the floating diffusion region side. A solid-state imaging device. The first insulating film includes a silicon nitride film;
The solid-state imaging device according to claim 1, wherein the second insulating film includes a silicon oxide film.   The solid-state imaging device according to claim 1, further comprising an amplifying unit in which the floating diffusion region and an input node are connected. The floating diffusion region is a semiconductor region;
4. The solid-state imaging device according to claim 1, wherein an impurity concentration of the semiconductor region is 1 × 10 ¹⁹ atoms / cm ³ or less. 5. The solid-state imaging device
A photoelectric conversion element different from the photoelectric conversion element, a floating diffusion region different from the floating diffusion region, a gate electrode different from the gate electrode,
A microlens provided on the second insulating film;
Have
5. The solid-state imaging device according to claim 1, wherein the microlens covers the photoelectric conversion element and the another photoelectric conversion element. 6. In a method for manufacturing a solid-state imaging device having a photoelectric conversion element, a floating diffusion region, and a gate electrode that controls conduction between the photoelectric conversion element and the floating diffusion region,
Forming an insulating film on the photoelectric conversion element, the gate electrode, and the floating diffusion region;
Continuously covering the photoelectric conversion element, the gate electrode, and a part of the floating diffusion region, and forming a resist pattern having an opening on a part of the floating diffusion region;
Etching the insulating film using the resist pattern as a mask to form a first insulating film;
Forming a second insulating film on the first insulating film, covering the photoelectric conversion element, the gate electrode, and the floating diffusion region, and having a dielectric constant lower than that of the first insulating film; And a method of manufacturing a solid-state imaging device.   The method for manufacturing a solid-state imaging device according to claim 6, wherein a side surface of the opening of the resist pattern is located in a range of 0.25 μm from an end portion of the gate electrode toward the floating diffusion region.   8. The method of manufacturing a solid-state imaging device according to claim 6, wherein the first insulating film includes a silicon nitride film, and the second insulating film includes a silicon oxide film.   The portion of the first insulating film extending from above the gate electrode to above the floating diffusion region is located within a range of 0.25 μm or less from the end of the gate electrode on the floating diffusion region side. A method for manufacturing a solid-state imaging device according to claim 6.   The method for manufacturing a solid-state imaging device according to claim 6, further comprising a step of forming a plug connected to the floating diffusion region.   The solid-state imaging device formed by the manufacturing method of the solid-state imaging device of any one of Claims 6 thru | or 10. A solid-state imaging device according to any one of claims 1 to 5 and 11,
And a processing unit that processes a signal from the solid-state imaging device.

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