TWI685959B - Image sensor and manufacturing method therefore - Google Patents

Abstract

An image sensor including a substrate, a light sensing device, a semiconductor layer, a first gate, and a light shielding layer is provided. The light sensing device is disposed in the substrate. The semiconductor layer is disposed on the substrate at one side of the light sensing device. The first gate is disposed on the substrate between the light sensing device and the semiconductor layer. The first gate and the substrate are insulated from each other. The light shielding layer covers the semiconductor layer. The substrate has a first conductive type, and the semiconductor layer has a second conductive type.

Description

Image sensor and its manufacturing method

The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly relates to an image sensor and a manufacturing method thereof.

At present, some types of image sensors (for example, global shutter image sensors) have storage nodes in the substrate for storing signals. However, stray light can interfere with signals stored in the storage node. Therefore, how to effectively prevent stray light interference is the goal of continuous research and development.

The invention provides an image sensor and a manufacturing method thereof, which can effectively prevent stray light interference.

The invention provides an image sensor including a substrate, a photosensitive element, a semiconductor layer, a first gate electrode and a light-shielding layer. The photosensitive element is provided in the substrate. The semiconductor layer is provided on the substrate on one side of the photosensitive element. The first gate is disposed on the substrate between the photosensitive element and the semiconductor layer. The first gate and the substrate are insulated from each other. The light shielding layer covers the semiconductor layer. The substrate has a first conductivity type, and the semiconductor layer has a second conductivity type.

According to an embodiment of the invention, in the above-mentioned image sensor, the material of the semiconductor layer is, for example, epitaxial silicon.

According to an embodiment of the invention, in the above image sensor, the first gate electrode may cover at least part of the semiconductor layer, and the first gate electrode and the semiconductor layer may be insulated from each other.

According to an embodiment of the invention, in the above image sensor, the first gate may be located between the light shielding layer and the semiconductor layer, and the light shielding layer may cover the first gate and the semiconductor layer at the same time.

According to an embodiment of the invention, the image sensor may further include a dielectric layer. The dielectric layer is disposed between the first gate and the substrate.

According to an embodiment of the invention, in the image sensor, the light shielding layer may extend to at least a portion of the first gate.

According to an embodiment of the invention, in the image sensor, the light shielding layer and the semiconductor layer can be isolated from each other.

According to an embodiment of the invention, the image sensor may further include a first well area and a second well area. The first well region and the second well region are located in the substrate on both sides of the semiconductor layer. The first well area and the second well area may have a second conductivity type.

According to an embodiment of the invention, the image sensor may further include doped regions. The doped region is located in the substrate between the first well region and the second well region. The doped region may have a first conductivity type.

According to an embodiment of the invention, the image sensor may further include a second gate and a floating diffusion area. The second gate is disposed on the substrate of the semiconductor layer on the side away from the photosensitive element. The second gate and the substrate may be insulated from each other. The floating diffusion region is located in the substrate on the side of the second gate away from the semiconductor layer.

The invention provides a method for manufacturing an image sensor, which includes the following steps. Provide a base. A photosensitive element is formed in the substrate. A semiconductor layer is formed on the substrate on one side of the photosensitive element. A first gate electrode is formed on the substrate between the photosensitive element and the semiconductor layer. The first gate and the substrate are insulated from each other. A light-shielding layer covering the semiconductor layer is formed. The substrate has a first conductivity type, and the semiconductor layer has a second conductivity type.

According to an embodiment of the invention, in the method of manufacturing the image sensor, the method of forming the semiconductor layer is, for example, a selective epitaxial growth method.

According to an embodiment of the invention, in the method of manufacturing an image sensor, the first gate electrode may cover at least a part of the semiconductor layer, and the first gate electrode and the semiconductor layer may be insulated from each other.

According to an embodiment of the invention, in the method of manufacturing the image sensor, the first gate may be located between the light shielding layer and the semiconductor layer, and the light shielding layer may cover the first gate and the semiconductor layer at the same time.

According to an embodiment of the invention, in the method of manufacturing the image sensor, the light shielding layer may extend onto at least a portion of the first gate.

According to an embodiment of the invention, in the method for manufacturing an image sensor, the method further includes forming a first well region and a second well region in the substrate on both sides of the semiconductor layer. The first well area and the second well area may have a second conductivity type.

According to an embodiment of the invention, in the method of manufacturing the image sensor, the method further includes forming a doped region in the substrate between the first well region and the second well region. The doped region may have a first conductivity type.

According to an embodiment of the invention, the method for manufacturing the image sensor may further include the following steps. A second gate electrode is formed on the substrate of the semiconductor layer on the side away from the photosensitive element. The second gate and the substrate may be insulated from each other. A floating diffusion region is formed in the substrate of the second gate away from the semiconductor layer.

Based on the above, in the above-mentioned image sensor and its manufacturing method, the semiconductor layer is provided on the substrate on one side of the photosensitive element, and can be used as a part of the storage node. In addition, the light shielding layer covers the semiconductor layer. Therefore, the light shielding layer can block the stray light from irradiating the semiconductor layer, which can effectively prevent stray light interference.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

1A to 1F are cross-sectional views of a manufacturing process of an image sensor according to an embodiment of the invention.

1A, a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate, such as a silicon substrate. There may be an isolation structure 102 in the substrate 100. The isolation structure 102 is, for example, a shallow trench isolation structure (STI). The material of the isolation structure 102 is, for example, silicon oxide. In addition, the substrate 100 may have a first conductivity type. Hereinafter, the first conductivity type and the second conductivity type described may be one of the P-type conductivity type and the N-type conductivity type and the other. In this embodiment, the first conductivity type is the P-type conductivity type, and the second conductivity type is the N-type conductivity type, but the invention is not limited thereto.

The photosensitive element 104 is formed in the substrate 100. The photosensitive element 104 may be a photodiode. In this embodiment, the photosensitive element 104 may be a doped region of the second conductivity type (eg, N-type), such as a well region of the second conductivity type. The method of forming the photosensitive element 104 is, for example, an ion implantation method.

The pinned layer 106 may be formed in the substrate 100. The pinned layer 106 is located between the photosensitive element 104 and the surface of the substrate 100. The pinned layer 106 can be used to reduce dark current. The pinned layer 106 may be a heavily doped region of the first conductivity type (eg, P type). The method for forming the pinned layer 106 is, for example, ion implantation.

The well region 108 and the well region 110 separated from each other may be formed in the substrate 100. The well region 108 and the well region 110 may have a second conductivity type (eg, N type). The formation method of the well region 108 and the well region 110 is, for example, ion implantation.

A doped region 112 may be formed in the substrate 100 between the well region 108 and the well region 110. The doped region 112 may be a heavily doped region of the first conductivity type (eg, P type). The method of forming the doped region 112 is, for example, ion implantation.

In addition, those skilled in the art can determine the formation order of the photosensitive element 104, the pinned layer 106, the well region 108, the well region 110, and the doped region 112 according to process requirements.

In addition, a patterned mask layer 114 may be formed on the substrate 100. The patterned mask layer 114 may have an opening 114a exposing a portion of the substrate 100. In addition, the opening 114a may expose the doped region 112, part of the well region 108, and part of the well region 110. The patterned mask layer 114 may be a single-layer structure or a multi-layer structure. The material of the patterned mask layer 114 is, for example, silicon oxide, silicon nitride, or a combination thereof.

Referring to FIG. 1B, a semiconductor layer 116 may be formed on the substrate 100 exposed by the opening 114a. Thereby, the semiconductor layer 116 can be formed on the substrate 100 on the side of the photosensitive element 104. The top surface of the semiconductor layer 116 may be higher than the top surface of the substrate 100. The well region 108 and the well region 110 may be located in the substrate 100 on both sides of the semiconductor layer 116, and the semiconductor layer 116 may overlap the doped region 112, part of the well region 108, and part of the well region 110. The material of the semiconductor layer 116 is, for example, epitaxial silicon. The semiconductor layer 116 may have a second conductivity type (eg, N type). The method of forming the semiconductor layer 116 is, for example, a selective epitaxial growth method. In addition, in the case where the semiconductor layer 116 exceeds the opening 114a, the patterned mask layer 114 may be used as a polishing stop layer, and the semiconductor layer 116 may be subjected to a chemical mechanical polishing process.

Generally speaking, the storage node is formed by a PN diode capacitor, and the PN diode capacitor is an empty region capacitor including an N-type region and a P-type region. In addition, the above-mentioned depletion region will cover at least part of the N-type region and the P-type region, and the extent of the depletion region covering the N-type region and the P-type region depends on the concentration distribution of the N-type region and the P-type region and the applied bias Pressure.

In this embodiment, the semiconductor layer 116 of the second conductivity type can be used as a part of the storage node. In some embodiments, the semiconductor layer 116 of the second conductivity type may form a storage node with the doped region 112 of the first conductivity type. In some embodiments, the semiconductor layer 116 of the second conductivity type may also form a storage node with the substrate 100 of the first conductivity type. In addition, the well area 108 and the well area 110 can also be used as part of the storage node.

1C, the patterned mask layer 114 can be removed. The method for removing the patterned mask layer 114 is, for example, a wet etching method. The etchant used in the wet etching method is, for example, phosphoric acid or hydrofluoric acid. Those skilled in the art can select a suitable etchant according to the material of the patterned mask layer 114.

Next, a dielectric layer 118 covering the semiconductor layer 116 may be formed on the substrate 100. The material of the dielectric layer 118 is, for example, silicon oxide. The method of forming the dielectric layer 118 is, for example, a thermal oxidation method.

Then, a gate material layer 120 may be formed on the dielectric layer 118. In addition, the gate material layer 120 can be selectively subjected to a chemical mechanical polishing process, whereby the gate material layer 120 can be planarized, and the height of the gate material layer 120 can be adjusted. The gate material layer 120 may cover the semiconductor layer 116. The material of the gate material layer 120 is, for example, doped polysilicon. The gate material layer 120 may have a second conductivity type (eg, N type). The method of forming the gate material layer 120 is, for example, a chemical vapor deposition method of on-site doping.

Referring to FIG. 1D, the gate material layer 120 can be patterned by a lithography process and an etching process to form a gate 122 on the dielectric layer 118, and a gate 124 can also be formed on the dielectric layer 118. In this way, the gate electrode 122 can be formed on the substrate 100 between the photosensitive element 104 and the semiconductor layer 116, and the gate electrode 124 can be formed on the substrate 100 on the side of the semiconductor layer 116 away from the photosensitive element 104. The gate 122 and the substrate 100 may be insulated from each other by the dielectric layer 118. The gate 124 and the substrate 100 may be insulated from each other by the dielectric layer 118. In this embodiment, the gate 122 and the gate 124 are formed by the same process, but the invention is not limited to this. In other embodiments, the gate 122 and the gate 124 can also be formed by different processes.

The gate 122 may cover at least a portion of the semiconductor layer 116, and the gate 122 and the semiconductor layer 116 may be insulated from each other by the dielectric layer 118. In this embodiment, the gate electrode 122 covers the top surface and both side surfaces of the semiconductor layer 116 as an example for description, but the invention is not limited thereto. In other embodiments, the gate 122 may not cover the semiconductor layer 116.

Then, a spacer 126 may be formed on the sidewall of the gate 122, and a spacer 128 may be formed on the sidewall of the gate 124. The spacer 126 and the spacer 128 may be a single-layer structure or a multi-layer structure. The materials of the spacer 126 and the spacer 128 are, for example, silicon oxide, silicon nitride, or a combination thereof. The method for forming the partition wall 126 and the partition wall 128 can adopt a method well known to those skilled in the art, which will not be described here. In this embodiment, after the spacer 126 and the spacer 128 are formed, the dielectric layer 118 that is not covered by the gate 122, the gate 124, the spacer 126, and the spacer 128 remains on the substrate 100, so that The light shielding layer 136 (FIG. 1E) formed later is prevented from being bridged with the substrate 100, but the invention is not limited thereto. In some embodiments, after forming the spacer 126 and the spacer 128, the dielectric layer 118 not covered by the gate 122, the gate 124, the spacer 126, and the spacer 128 may be removed. In some embodiments, after the gate 122 and the gate 124 are formed, the dielectric layer 118 not covered by the gate 122 and the gate 124 may be removed.

Next, a floating diffusion region 130 may be formed in the substrate 100 on the side of the gate electrode 124 away from the semiconductor layer 116. The floating diffusion region 130 may have a second conductivity type (eg, N type). The formation method of the floating diffusion region 130 is, for example, an ion implantation method.

1E, a metal silicide layer 132 can be formed on the gate 122, and a metal silicide layer 134 can be formed on the gate 124. The material of the metal silicide layer 132 and the metal silicide layer 134 is, for example, metal silicide, such as cobalt silicide or nickel silicide. The method for forming the metal silicide layer 132 and the metal silicide layer 134 is, for example, a self-aligned metal silicide process. For example, a self-aligned metal silicide block SAB exposing the gate 122 and the gate 124 may be formed on the dielectric layer 118 through deposition, lithography, and etching processes, and then by In the alignment metal silicide process, a metal silicide layer 132 and a metal silicide layer 134 are formed on the gate 122 and the gate 124, respectively. In addition, the self-aligned metal silicide barrier layer SAB can also prevent the subsequently formed light shielding layer 136 from bridging the substrate 100.

Next, a light shielding layer 136 covering the semiconductor layer 116 is formed. The light shielding layer 136 can block the stray light from irradiating the semiconductor layer 116, thereby effectively preventing stray light interference. In this embodiment, most of the depletion regions of the PN diode capacitors as storage nodes can be located in the second conductivity type region (eg, N-type region) in the semiconductor layer 116 above the substrate 100, and a few depletion regions The first conductivity type region (eg, P-type region) in the substrate 100. Thereby, it can be ensured that the light shielding layer 136 can effectively block most of the stray light.

The light shielding layer 136 and the semiconductor layer 116 may be isolated from each other. For example, the light shielding layer 136 and the semiconductor layer 116 can be isolated from each other by the gate 122 and the dielectric layer 118. The material of the light shielding layer 136 is, for example, a metal, a metal compound, or a combination thereof, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), or Its combination. The formation method of the light-shielding layer 136 is, for example, a combination of a deposition process, a lithography process and an etching process.

In this embodiment, the gate electrode 122 may be located between the light shielding layer 136 and the semiconductor layer 116, and the light shielding layer 136 may cover the gate electrode 122 and the semiconductor layer 116 at the same time, but the invention is not limited thereto. For example, the light shielding layer 136 may cover the top surface and the periphery of the gate 122 and the semiconductor layer 116.

1F, a dielectric layer 138 covering the gate 122 and the gate 124 may be formed. The dielectric layer 138 may be a single-layer structure or a multi-layer structure. The material of the dielectric layer 138 is, for example, silicon oxide, silicon nitride, or a combination thereof. The method of forming the dielectric layer 138 is, for example, a chemical vapor deposition method.

Next, the interconnect structure 140 and the interconnect structure 142 can be formed in the dielectric layer 138. The interconnection structure 140 can be electrically connected to the gate 122 via the light shielding layer 136 and the metal silicide layer 132. The interconnect structure 142 can be electrically connected to the gate 124 via the metal silicide layer 134. The interconnection structure 140 and the interconnection structure 142 may include contact windows, wires, or a combination thereof, respectively. The materials of the interconnect structure 140 and the interconnect structure 142 are, for example, copper, aluminum, tungsten, or a combination thereof. The formation method of the interconnection structure 142 is, for example, a damascene method or a combination of a deposition process, a lithography process, and an etching process. In addition, the number of layers of the interconnect structure 140 and the number of layers of the interconnect structure 142 can be adjusted according to product requirements, and is not limited to the number of layers shown in the drawings.

Then, a color filter layer 144 may be formed on the dielectric layer 138 above the photosensitive element 104. The color filter layer 144 is, for example, a red filter layer, a green filter layer, or a blue filter layer. The material of the color filter layer 144 is, for example, a photoresist material, and the formation method of the color filter layer 144 can use spin coating, alignment, exposure, development, etc., which are well known to those skilled in the art, and will not be repeated here. Instructions.

Next, a microlens 146 may be formed on the color filter layer 144. The material of the microlens 146 is, for example, a photoresist material. The forming method of the microlens 146 is, for example, spin-coating a microlens material layer (not shown), and then using a mask to perform a lithography process and high temperature heat baking into an arc lens shape, or other technical fields have common Spin coating, alignment, exposure, development, etching, etc., which are well-known to those skilled in the art, will not be described here.

The image sensor 148 of this embodiment will be described below with reference to FIG. 1F. In addition, although the method of forming the image sensor 148 is described by taking the above method as an example, the invention is not limited thereto.

Referring to FIG. 1F, the image sensor 148 includes a substrate 100, a photosensitive element 104, a semiconductor layer 116, a gate 122, and a light-shielding layer 136. The photosensitive element 104 is provided in the substrate 100. The semiconductor layer 116 is provided on the substrate 100 on one side of the photosensitive element 104. The gate 122 is disposed on the substrate 100 between the photosensitive element 104 and the semiconductor layer 116. The gate 122 and the substrate 100 are insulated from each other. The gate 122 may cover at least part of the semiconductor layer 116, and the gate 122 and the semiconductor layer 116 may be insulated from each other. The light shielding layer 136 covers the semiconductor layer 116. In this embodiment, the gate electrode 122 may be located between the light shielding layer 136 and the semiconductor layer 116, and the light shielding layer 136 may cover the gate electrode 122 and the semiconductor layer 116 at the same time, but the invention is not limited thereto.

In addition, the image sensor 148 may further include an isolation structure 102, a pinned layer 106, a well region 108, a well region 110, a doped region 112, a dielectric layer 118, a gate 124, a spacer 126, a spacer 128, a floating At least one of the diffusion region 130, the metal silicide layer 132, the metal silicide layer 134, the dielectric layer 138, the interconnect structure 140, the interconnect structure 142, the color filter layer 144, and the microlens 146 is disposed. The isolation structure 102 is disposed in the substrate 100. The pinned layer 106 is located between the photosensitive element 104 and the surface of the substrate 100. The well region 108 and the well region 110 are located in the substrate 100 on both sides of the semiconductor layer 116. The doped region 112 is located in the substrate 100 between the well region 108 and the well region 110. The dielectric layer 118 is disposed between the gate 122 and the substrate 100. In addition, the dielectric layer 118 may be disposed between the gate 122 and the semiconductor layer 116 and between the gate 124 and the substrate 100. The gate electrode 124 is provided on the substrate 100 on the side of the semiconductor layer 116 away from the photosensitive element 104. The gate electrode 124 and the substrate 100 may be insulated from each other. The spacer 126 is located on the side wall of the gate 122. The spacer 128 is located on the side wall of the gate electrode 124. The floating diffusion region 130 is located in the substrate 100 on the side of the gate electrode 124 away from the semiconductor layer 116. The metal silicide layer 132 is provided on the gate 122. The metal silicide layer 134 is provided on the gate 124. The dielectric layer 138 covers the gate 122 and the gate 124. The interconnect structure 140 and the interconnect structure 142 are located in the dielectric layer 138, and are electrically connected to the gate 122 and the gate 124, respectively. The color filter layer 144 is disposed on the dielectric layer 138 above the photosensitive element 106. The micro lens 146 is disposed on the color filter layer 144. In some embodiments, the metal silicide layer 132 and the metal silicide layer 134 may not be formed above the gate electrode 122 and the gate electrode 124, but only the metal silicide layer is formed on the peripheral circuit.

In addition, the materials, arrangement methods, conductivity types, forming methods, and functions of the components in the image sensor 148 have been described in detail in the foregoing embodiments, and will not be described here.

Based on the above embodiment, it can be known that in the image sensor 148 and the manufacturing method thereof, the semiconductor layer 116 is disposed on the substrate 100 on the side of the photosensitive element 104, and the semiconductor layer 116 can be used as a part of the storage node. In addition, the light shielding layer 136 covers the semiconductor layer 116. Therefore, the light shielding layer 136 can block the stray light from irradiating the semiconductor layer 116, and the stray light interference can be effectively prevented.

2A to 2D are cross-sectional views of a manufacturing process of an image sensor according to another embodiment of the invention. 2A to 2D are cross-sectional views of the manufacturing process after the steps following FIG. 1B.

Hereinafter, the differences in the manufacturing methods of the image sensor 200 of FIG. 2D and the image sensor 148 of FIG. 1F will be described. Referring to FIG. 2A, in the step of forming the gate material layer 120, a chemical mechanical polishing process may be performed on the gate material layer 120 until the dielectric layer 118 above the semiconductor layer 116 is exposed. That is, the gate material layer 120 located above the semiconductor layer 116 is removed. Referring to FIG. 2B, after patterning the gate material layer 120, the gate electrode 222 may not cover the semiconductor layer 116. In addition, in the step of forming the spacer 126 and the spacer 128, the spacer 202 may be further formed on the side wall of the semiconductor layer 116. Referring to FIG. 2C, in the step of forming the light-shielding layer 236 covering the semiconductor layer 116, the light-shielding layer 236 may extend over at least a portion of the gate electrode 222, thereby further blocking stray light from irradiating the semiconductor layer 116. In this embodiment, the light shielding layer 236 may extend to the top surface and the periphery of the gate electrode 222, but the invention is not limited thereto. In other embodiments, the light shielding layer 236 may not extend onto the gate 222. In addition, the light shielding layer 236 and the semiconductor layer 116 may be isolated from each other by the self-aligned metal silicide barrier layer SAB and the dielectric layer 118 that may be left between the light shielding layer 236 and the semiconductor layer 116. In addition, the similar components in FIGS. 2A to 2D and FIGS. 1C to 1F are denoted by the same symbols, and the detailed contents thereof can be referred to the descriptions of the foregoing embodiments, and will not be described here.

Next, please refer to FIGS. 1F and 2D, the structural differences between the image sensor 200 and the image sensor 148 are as follows. The gate electrode 222 may not cover the semiconductor layer 116. In the image sensor 200, the light shielding layer 236 may extend to at least a portion of the gate electrode 222. In addition, the image sensor 200 may further include a spacer 202. The spacer 202 may be located on the sidewall of the semiconductor layer 116. In addition, the configuration methods, materials, forming methods, and functions of other components in the image sensor 200 have been described in detail in the foregoing embodiments, and will not be repeated here.

Based on the above embodiment, it can be known that in the image sensor 200 and the manufacturing method thereof, the semiconductor layer 116 is disposed on the substrate 100 on the side of the photosensitive element 104, and the semiconductor layer 116 can be used as a part of the storage node. In addition, the light shielding layer 236 covers the semiconductor layer 116. Therefore, the light shielding layer 236 can block the stray light from irradiating the semiconductor layer 116, and the stray light interference can be effectively prevented.

In summary, in the image sensor and the manufacturing method of the above embodiment, the semiconductor layer is provided on the substrate, and the semiconductor layer is covered with the light-shielding layer, so the interference of stray light can be effectively prevented.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100‧‧‧ base

102‧‧‧Isolated structure

104‧‧‧Photosensitive element

106‧‧‧Pinned layer

108, 110‧‧‧ well area

112‧‧‧Doped area

114‧‧‧Pattern cover curtain layer

116‧‧‧Semiconductor layer

118, 138‧‧‧ dielectric layer

120‧‧‧ Gate material layer

122、124、222‧‧‧Gate

126, 128, 202 ‧‧‧ spacer

130‧‧‧Floating diffusion area

132, 134‧‧‧ metal silicide layer

136, 236‧‧‧ shading layer

140、142‧‧‧Interconnect structure

144‧‧‧ color filter layer

146‧‧‧Microlens

148、200‧‧‧Image sensor

SAB‧‧‧Self-aligned metal silicide barrier

1A to 1F are cross-sectional views of a manufacturing process of an image sensor according to an embodiment of the invention. 2A to 2D are cross-sectional views of a manufacturing process of an image sensor according to another embodiment of the invention.

100‧‧‧ base

102‧‧‧Isolated structure

104‧‧‧Photosensitive element

106‧‧‧Pinned layer

108, 110‧‧‧ well area

112‧‧‧Doped area

116‧‧‧Semiconductor layer

118, 138‧‧‧ dielectric layer

122、124‧‧‧Gate

126, 128‧‧‧ spacer

130‧‧‧Floating diffusion area

132, 134‧‧‧ metal silicide layer

136‧‧‧ shading layer

140、142‧‧‧Interconnect structure

144‧‧‧ color filter layer

146‧‧‧Microlens

148‧‧‧Image sensor

SAB‧‧‧Self-aligned metal silicide barrier

Claims (18)

An image sensor comprising: a substrate; a photosensitive element provided in the substrate; a semiconductor layer provided on the substrate on one side of the photosensitive element, wherein the entire semiconductor layer is on the substrate The orthographic projection and the orthographic projection of the photosensitive element on the substrate do not overlap each other; a first gate is provided on the substrate between the photosensitive element and the semiconductor layer, wherein the first gate Insulated from the substrate; and a light-shielding layer covering the semiconductor layer, wherein the substrate has a first conductivity type, and the semiconductor layer has a second conductivity type. The image sensor as described in item 1 of the patent application range, wherein the material of the semiconductor layer includes epitaxial silicon. The image sensor according to item 1 of the patent application range, wherein the first gate electrode covers at least a part of the semiconductor layer, and the first gate electrode and the semiconductor layer are insulated from each other. The image sensor of claim 3, wherein the first gate is located between the light shielding layer and the semiconductor layer, and the light shielding layer simultaneously covers the first gate and The semiconductor layer. The image sensor as described in item 1 of the patent application further includes: a dielectric layer disposed between the first gate electrode and the substrate. The image sensor according to item 1 of the patent application scope, wherein the light shielding layer extends over at least a portion of the first gate electrode. The image sensor according to item 1 of the patent application scope, wherein the light shielding layer and the semiconductor layer are isolated from each other. The image sensor as described in item 1 of the patent application further includes: a first well region and a second well region, located in the substrate on both sides of the semiconductor layer, and having the second conductivity type. The image sensor as described in item 8 of the patent application scope further includes: a doped region, located in the substrate between the first well region and the second well region, and having the One conductivity type. The image sensor as described in item 1 of the patent application scope, further comprising: a second gate electrode disposed on the substrate on the side of the semiconductor layer away from the photosensitive element, wherein the second gate electrode An electrode and the substrate are insulated from each other; and a floating diffusion is located in the substrate on the side of the second gate away from the semiconductor layer. A method for manufacturing an image sensor, comprising: providing a substrate; forming a photosensitive element in the substrate; forming a semiconductor layer on the substrate on one side of the photosensitive element, wherein the entire semiconductor layer is on the substrate The orthographic projection on the and the orthographic projection of the photosensitive element on the substrate do not overlap each other; a first gate is formed on the substrate between the photosensitive element and the semiconductor layer An electrode, wherein the first gate electrode and the substrate are insulated from each other; and a light-shielding layer covering the semiconductor layer is formed, wherein the substrate has a first conductivity type, and the semiconductor layer has a second conductivity type. The method for manufacturing an image sensor as described in item 11 of the patent application range, wherein the method for forming the semiconductor layer includes a selective epitaxial growth method. The method of manufacturing an image sensor as described in item 11 of the patent application range, wherein the first gate electrode covers at least a part of the semiconductor layer, and the first gate electrode and the semiconductor layer are insulated from each other. The method for manufacturing an image sensor as described in item 13 of the patent application range, wherein the first gate is located between the light shielding layer and the semiconductor layer, and the light shielding layer covers the first The gate and the semiconductor layer. The method for manufacturing an image sensor as described in item 11 of the patent application range, wherein the light shielding layer extends to at least a portion of the first gate electrode. The method for manufacturing an image sensor as described in item 11 of the patent application scope further includes: forming a first well region and a second well region in the substrate on both sides of the semiconductor layer, wherein the first The well region and the second well region have the second conductivity type. The method for manufacturing an image sensor as described in item 16 of the scope of patent application further includes: forming a doped region in the substrate between the first well region and the second well region, wherein the The doped region has the first conductivity type. The method for manufacturing an image sensor as described in item 11 of the patent application scope further includes: forming a second gate on the substrate on the side of the semiconductor layer remote from the photosensitive element, wherein the first The second gate and the substrate are insulated from each other; and a floating diffusion region is formed in the substrate on the side of the second gate away from the semiconductor layer.

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