JP2013135055A - Mis semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize a threshold voltage in a MIS semiconductor device having a gate insulation film composed of ZrON.SOLUTION: In a MIS semiconductor device operating at an operating voltage of 5 V or more, and including a gate insulation film 11 on a semiconductor layer 10 composed of Si, and a gate electrode 12 on the gate insulation film 11, ZrON(where x and y satisfy x>0, y>0, 0.3≤y/x≤10 and 1.5≤0.55x+y≤1.7) is used as the gate insulation film 11. The MIS semiconductor device having such gate insulation film 11 can stably operate because there is no variation in a threshold voltage though a large voltage is applied.

Description

The present invention relates to a MIS type semiconductor device having a gate insulating film made of ZrO _x N _y (zirconium oxynitride) on a semiconductor layer and having a gate electrode on the gate insulating film and having an operating voltage of 5 V or more. The present invention also relates to a method for manufacturing the MIS type semiconductor device.

In recent years, miniaturization of semiconductor devices has progressed, and thinning of gate insulating films of transistors has been demanded. However, in the case of SiO ₂ that has been conventionally used, the leakage current increases if it is made thin. Therefore, thinning is attempted by using a high dielectric constant material instead of SiO ₂ . Examples of the high dielectric constant material include HfO ₂ , ZrO ₂ , TiO ₂ , HfO _x N _y , and ZrO _x N _y . In particular, Patent Documents 1 to 3 show MIS (Metal-Insulator-Semiconductor) type semiconductor devices using ZrO _x N _y as a gate insulating film.

In Patent Document 1, in a semiconductor device having a gate insulating film on a semiconductor substrate and a gate electrode on the gate insulating film, Zr ₂ ON ₂ or ZrO _2-2x N _{4x / 3} ( However, x is shown using 3/8 <x <3/4). Further, it is shown that the gate insulating film is crystalline or polycrystalline. The gate insulating film made of Zr ₂ ON ₂ is described to be formed by sputtering using Zr ₂ ON ₂ ceramic target, with argon as the sputtering gas, a substrate temperature of 600 to 800 ° C., sputtering It is described that the gas pressure is 0.5 to 0.2 Pa.

In Patent Document 2, in a MIS type semiconductor device having a gate insulating film made of ZrO ₂ containing nitrogen, the nitrogen concentration of the gate insulating film is higher on the channel side than on the gate electrode side, and the channel of the gate insulating film is The nitrogen concentration on the side is 10 ²⁰ to 10 ²¹ / cm ³ . Further, it is described that the gate insulating film is formed by sputtering in a mixed gas of nitrogen gas and oxygen gas diluted with argon gas at room temperature to 800 ° C. and 0.1 mPa to 1 kPa. Further, there is no particular description as to whether the gate insulating film is in a crystalline, polycrystalline, or amorphous state.

Patent Document 3 discloses a MIS type semiconductor device in which a chemical oxide layer, a high dielectric layer, a lower metal layer, a trapping metal layer, an upper metal layer, and a polycrystalline semiconductor layer are sequentially stacked on a semiconductor substrate. Yes. It is described that Si or III-V semiconductor can be used for the semiconductor substrate. Further, it is described that ZrO _x N _y (0.5 ≦ x ≦ 3, 0 ≦ y ≦ 2) can be used for the high dielectric layer. There is no particular description as to whether the high dielectric layer is in a crystalline, polycrystalline, or amorphous state. In addition, although it is described that the high dielectric layer can be formed by a CVD method, an ALD method, or the like, there is no description about formation by a sputtering method.

JP-A-2005-44835 JP 2005-217159 A JP2011-3899

The inventors have studied to adopt a high dielectric constant gate insulating film made of ZrO _x N _y and reduce the size of the MIS type power device. However, when ZrO _x N _{y is used} for the gate insulating film, the threshold voltage fluctuates when the applied voltage is increased depending on the O composition ratio x and the N composition ratio y, and the operation becomes unstable. It was. Patent Documents 1 to 3 do not describe or suggest such a problem that the threshold voltage fluctuates.

Accordingly, an object of the present invention is to stabilize the threshold voltage in a MIS type semiconductor device having a gate insulating film made of ZrO _x N _y on a semiconductor layer and having a gate electrode on the gate insulating film. is there.

According to a first aspect of the present invention, there is provided a MIS type semiconductor device having a gate insulating film made of ZrO _x N _y on a semiconductor layer and having a gate electrode on the gate insulating film and having an operating voltage of 5 V or more. The MIS type semiconductor device is amorphous, and x and y satisfy x> 0, y> 0, and 0.3 ≦ y / x ≦ 10.

  As the semiconductor layer, a Si layer, a group III nitride semiconductor layer, a group III-V semiconductor layer, a group II-VI compound semiconductor layer, a SiC layer, or the like can be used. The group III nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, an InGaN layer, an AlN layer, an AlGaInN layer, or the like. The III-V semiconductor layer is a GaAs layer, a GaP layer, a GaInP layer, or the like. The II-VI group compound semiconductor layer is a ZnO layer or the like. The semiconductor layer may be doped with n-type impurities or p-type impurities. The semiconductor layer may be the semiconductor substrate itself, or the semiconductor layer may be stacked on the semiconductor substrate or the insulating substrate. The semiconductor layer may be composed of a plurality of layers having different materials, composition ratios, conductivity types, impurity concentrations, and the like.

  The gate insulating film may be composed of a plurality of layers as long as the oxygen composition ratio x and the nitrogen composition ratio y described above are satisfied.

The semiconductor layer and the gate insulating film may be in direct contact with each other, or an insulating film or the like may be provided between the semiconductor layer and the gate insulating film. In this case, SiO ₂ , Si _x N _y , ZrO ₂ or the like can be used for the insulating film.

  The gate insulating film and the gate electrode may be in direct contact with each other, or an insulating film or a metal film may be provided between the gate insulating film and the gate electrode.

  For x and y, a more desirable range of y / x is 1 ≦ y / x ≦ 5. Also, x and y preferably satisfy 1.5 ≦ 0.55x + y ≦ 1.7. Within this range, the threshold fluctuation of the MIS semiconductor device can be further suppressed, and the operational stability can be further improved.

  Further, even if the range of x and y of the gate insulating film of the present invention is further limited to the range of x ≦ 0.5, the threshold fluctuation can be further suppressed and the operational stability is further improved. be able to.

  The MIS type semiconductor device of the present invention is particularly effective when the operating voltage is 10 V or higher. Even at such a high operating voltage, the threshold voltage fluctuation can be suppressed according to the MIS type semiconductor device of the present invention.

  Further, the MIS type semiconductor device of the present invention can be suitably used for power semiconductor elements, and can be applied to semiconductor devices such as MISFET, HFET, and IGBT.

  A second invention is a MIS type semiconductor device according to the first invention, further satisfying 1.5 ≦ 0.55x + y ≦ 1.7.

  A third invention is a MIS type semiconductor device according to the first or second invention, wherein x and y are 1 ≦ y / x ≦ 5.

  A fourth invention is a MIS type semiconductor device according to the first to third inventions, wherein x ≦ 0.5.

  A fifth invention is a MIS type semiconductor device according to any one of the first to fourth inventions, wherein the gate insulating film is provided in direct contact with the semiconductor layer.

  A sixth invention is a MIS type semiconductor device according to any one of the first to fifth inventions, wherein the semiconductor layer is a group III nitride semiconductor layer.

  A seventh invention is the MIS type semiconductor device according to the sixth invention, wherein the operating voltage is 10 V or more.

According to an eighth aspect of the present invention, there is provided a method for manufacturing a MIS type semiconductor device comprising: a step of forming a gate insulating film made of ZrO _x N _y on a semiconductor layer by a sputtering method; and a step of forming a gate electrode on the gate insulating film. In the method, in the sputtering method, the gate insulating film is made amorphous at room temperature while flowing a gas containing nitrogen gas and oxygen gas with a metal Zr as a target, and x and y are x> 0, y> 0, It is a method for manufacturing a MIS type semiconductor device, characterized in that it is formed so as to satisfy 0.3 ≦ y / x ≦ 10 and 1.5 ≦ 0.55x + y ≦ 1.7.

  A ninth invention is the method of manufacturing an MIS type semiconductor device according to the eighth invention, wherein x and y further satisfy 1.5 ≦ 0.55x + y ≦ 1.7.

  A tenth invention is the manufacture of a MIS type semiconductor device according to the eighth or ninth invention, wherein the gate insulating film is formed so that x and y satisfy 1 ≦ y / x ≦ 5. Is the method.

  An eleventh aspect of the invention is a method of manufacturing a MIS type semiconductor device according to the eighth aspect to the tenth aspect of the invention, wherein a gate insulating film is formed so as to satisfy x ≦ 0.5.

  A twelfth aspect of the invention is a method for manufacturing a MIS type semiconductor device according to the eighth to eleventh aspects of the invention, wherein the gate insulating film is formed directly on the semiconductor layer.

  A thirteenth aspect of the invention is a method of manufacturing an MIS type semiconductor device according to the eighth to twelfth aspects of the invention, wherein the semiconductor layer is a group III nitride semiconductor layer.

  A fourteenth aspect of the invention is a method for manufacturing a MIS type semiconductor device according to the eighth to thirteenth aspects of the invention, wherein the MIS type semiconductor device has an operating voltage of 5 V or more.

  A fifteenth aspect of the invention is a method of manufacturing a MIS type semiconductor device according to the fourteenth aspect of the invention, wherein the MIS type semiconductor device has an operating voltage of 10 V or more.

  According to the present invention, even when a large voltage is applied to the MIS type semiconductor device, fluctuations in the threshold voltage are suppressed and stable operation can be achieved. Although it is not clear why the gate insulating film of the present invention has such an effect of stabilizing the threshold value, the level generated by the oxygen deficiency in the gate insulating film is reduced by nitrogen in the gate insulating film. It is presumed that this is because of this. The present invention is effective for MIS type semiconductor devices having an operating voltage of 5 V or higher, particularly 10 V or higher, and can be used for power semiconductor elements. In addition, the gate insulating film according to the present invention is stable against heat treatment and can maintain an amorphous state without being crystallized up to about 800 ° C. For this reason, there are fewer restrictions on the heat treatment process after the gate insulating film is formed, and the degree of freedom in the manufacturing process is higher than in the prior art.

FIG. 3 is a cross-sectional view showing a configuration of a MIS type semiconductor device of Example 1. FIG. 6 is a diagram showing manufacturing steps of the MIS type semiconductor device of Example 1; 3 is a graph showing CV characteristics of the MIS type semiconductor device of Example 1. The graph which showed the CV characteristic of the MIS type semiconductor device of a comparative example. The figure which showed O composition ratio of the gate insulating film 11, and N composition ratio. The figure which showed the nitrogen atom concentration / oxygen atom concentration of the gate insulating film 11. FIG. 5 is a diagram showing a configuration of an HFET of Example 2. FIG. 6 shows a manufacturing process of the HFET of Example 2. FIG. 6 is a diagram showing a configuration of a diode according to Example 3.

  Hereinafter, specific examples of the present invention will be described with reference to the drawings. However, the present invention is not limited to the examples.

  FIG. 1 is a cross-sectional view showing the configuration of the MIS type semiconductor device according to the first embodiment. The MIS type semiconductor device of Example 1 includes a semiconductor layer 10, a gate insulating film 11 positioned in contact with the semiconductor layer 10, and a gate electrode 12 positioned in contact with a partial region of the gate insulating film 11. Have.

  The semiconductor layer 10 is an n-type Si substrate having a thickness of 600 μm. In addition to Si, a group III nitride semiconductor layer, a group III-V semiconductor layer, a group II-VI compound semiconductor layer, a SiC layer, or the like can be used. The group III nitride semiconductor layer is, for example, a layer of GaN, AlN, AlGaN, InGaN, AlGaInN, or the like. The III-V semiconductor layer is a layer of GaAs, GaP, GaInP, or the like, for example. The II-VI group compound semiconductor layer is a layer of ZnO, for example. Further, the conductivity type of the semiconductor layer 10 does not have to be n-type, and may be p-type or intrinsic. Further, the semiconductor layer 10 may not be a single layer, and may be composed of a plurality of layers. For example, a configuration in which layers having different materials, conductivity types, composition ratios, impurity concentrations, and the like are stacked may be used. Further, the semiconductor layer 10 may be a semiconductor substrate itself, or may be a layer laminated on a semiconductor substrate or an insulating substrate.

The gate insulating film 11 is an amorphous ZrO _x N _y having a thickness of 75 nm (where x and y are x> 0, y> 0, 0.3 ≦ y / x ≦ 10, and 1.5 ≦ 0. 55x + y ≦ 1.7).

The gate insulating film 11 may be positioned on the semiconductor layer 10 as in the first embodiment, but may be positioned on the semiconductor layer 10 with another insulating film interposed therebetween. For example, an insulating film made of SiO ₂ , Si _x N _y , ZrO ₂ or the like may be provided between the semiconductor layer 10 and the gate insulating film 11.

  Polysilicon, W, or the like can be used for the gate electrode 12. Although the gate electrode 12 may be positioned directly on the gate insulating film 11 as in the first embodiment, it may be positioned on the gate insulating film 11 through another layer. For example, another insulating film or a metal film may be provided between the gate insulating film 11 and the gate electrode 12.

In the MIS type semiconductor device of Example 1, amorphous ZrO _x N _y (where x and y are x> 0, y> 0, 0.3 ≦ y / x ≦ 10, and 1 as the gate insulating film 11). .5 ≦ 0.55x + y ≦ 1.7) is used, fluctuation of the threshold voltage is suppressed even when a large voltage of 5 V or more is applied, and stable operation is possible. Therefore, the MIS type semiconductor device of Example 1 can operate stably even when the operating voltage is 5 V or higher, particularly 10 V or higher. Further, since stable operation at such a high operating voltage is possible, it is suitable for use as a power semiconductor element such as an FET, HFET, or IGBT. In addition, the gate insulating film 11 of the MIS type semiconductor device of Example 1 does not crystallize even when heat treatment up to about 800 ° C., and can maintain an amorphous state. Therefore, the MIS type semiconductor device of Example 1 is also excellent in thermal stability.

  The N composition ratio y / x with respect to the O composition ratio of the gate insulating film 11 is more preferably 1 ≦ y / x ≦ 5. This is because fluctuations in the threshold voltage are further suppressed and a more stable operation is possible.

  Further, the O composition ratio x may further satisfy x ≦ 0.5. Also in the MIS type semiconductor device of Example 1 having the gate insulating film 11 in such a range of x and y, fluctuations in the threshold voltage are suppressed and stable operation is possible.

  Next, the manufacturing process of the MIS type semiconductor device of Example 1 will be described.

  First, the semiconductor layer 10 which is an n-type Si substrate is prepared, and the surface of the semiconductor layer 10 is cleaned using acetone, IPA (isopropyl alcohol), and ultrapure water in this order to remove oil on the surface of the semiconductor layer 10. Thereafter, the semiconductor layer 10 is immersed in buffered hydrofluoric acid to remove the natural oxide film on the surface of the semiconductor layer 10 (FIG. 2A).

Next, the gate insulating film 11 made of ZrO _x N _y is formed on the cleaned semiconductor layer 10 by ECR (Electron Cyclotron Resonance) sputtering method (FIG. 2B). Sputtering is performed using a Zr metal target in a mixed gas of nitrogen gas and nitrogen mixed with argon gas, the substrate temperature is room temperature, the pressure is 0.07 to 0.2 Pa, the RF power is 500 W, and the microwave The power is 500W. The flow rate of argon gas is 15-30 sccm, the flow rate of oxygen gas is 0.1-3.0 sccm, and the flow rate of nitrogen gas is 4.3-17 sccm. The O composition ratio and the N composition ratio of the gate insulating film 11 can be controlled by the oxygen gas flow rate and the nitrogen gas flow rate, and the ratio of the oxygen gas flow rate to the nitrogen gas flow rate is 0.012 to 0.36.

  In the ECR sputtering method, argon is used as the carrier gas, but other inert gases such as xenon may be used. In addition to ECR sputtering, magnetron sputtering or the like can be used. However, the ECR sputtering method is advantageous in that the gate insulating film 11 can be formed at a lower temperature and higher pressure than other sputtering methods.

Further, the flow rate of argon gas, the flow rate of oxygen gas, and the flow rate of nitrogen gas are not necessarily in the above ranges, but by making the above ranges, the O composition ratio x and the N composition ratio y of ZrO _x N _y The gate insulating film 11 can be formed with good controllability.

  When the gate insulating film 11 is formed under the above conditions, the O composition ratio x and the N composition ratio y of the gate insulating film 11 are x> 0, y> 0, 0.3 ≦ y / x ≦ 10, and 1.5. ≦ 0.55x + y ≦ 1.7 can be formed, and the gate insulating film 11 can be formed in an amorphous state.

Further, according to the study by the inventors, according to the ECR sputtering method under the above temperature and pressure conditions, 1.5 ≦ 0.55x + y ≦ 1.7 depending on the flow rate control of argon gas, nitrogen gas, and oxygen gas. A ZrO _x N _y film having an O composition ratio x and an N composition ratio y outside the range could not be produced. Therefore, if an amorphous ZrO _x N _y film can be produced by ECR sputtering under the present conditions, the ZrO _x N _y film has an O composition ratio x satisfying 1.5 ≦ 0.55x + y ≦ 1.7, It is assumed that the N composition ratio is y.

Further, since the gate insulating film 11 is formed in an amorphous state, it is not necessary to lattice match with the semiconductor layer 10, and besides the semiconductor layer 10 made of Si, on the insulating film such as SiO ₂ or III-V compound semiconductor. It can also be formed on a compound semiconductor layer such as a II-VI group compound semiconductor or a group III nitride semiconductor.

  In the ECR sputtering method under the above conditions, if the ratio of the oxygen gas flow rate to the nitrogen gas flow rate is 0.012 to 0.36, the gate insulating film 11 in which the fluctuation of the threshold voltage is suppressed to 1 V or less is formed. Can do. In particular, if the ratio of the oxygen gas flow rate to the nitrogen gas flow rate is 0.036 to 0.36, the threshold voltage fluctuation can be further suppressed to 0.1 V or less.

  Next, the gate electrode 12 is formed in a predetermined region on the gate insulating film 11 by a lift-off method. More specifically, a resist film is formed on the gate insulating film 11 in a region other than the predetermined region by photolithography, then an electrode film is formed on the predetermined region and the resist film by vapor deposition or the like, and then lift-off is performed. The resist film and a part of the electrode film thereon are removed and the electrode film is left only in a predetermined region, whereby the gate electrode 12 is formed only in the predetermined region on the gate insulating film 11. Thus, the MIS type semiconductor device of Example 1 shown in FIG. 1 is manufactured.

According to the manufacturing method of the MIS type semiconductor device of Example 1 described above, it is made of ZrO _x N _y and is amorphous, and the O composition ratio x and the N composition ratio y are x> 0, y> 0, 0 The gate insulating film 11 satisfying .3 ≦ y / x ≦ 10 and 1.5 ≦ 0.55x + y ≦ 1.7 can be formed. Therefore, even if the operating voltage is 5 V or higher, fluctuations in the threshold voltage can be suppressed and stable operation can be achieved.

  Further, the gate insulating film 11 formed by the above method can maintain an amorphous state even when heat treatment up to about 800 ° C. is performed, and has high reliability. As described above, since the gate insulating film 11 has high thermal stability, the threshold voltage of the MIS type semiconductor device of Example 1 is stable with almost no fluctuations due to temperature changes. Similarly, the thermal stability of the gate insulating film 11 reduces the temperature restriction in the heat treatment process after the gate insulating film 11 is formed, for example, the electrode alloying process, and the degree of freedom in the manufacturing process is increased.

  Hereinafter, specific evaluation of the MIS type semiconductor device of Example 1 is shown as an experimental example.

[Experimental Example 1]
A MIS type semiconductor device of Example 1 having an amorphous gate insulating film 11 made of ZrO _x N _y and having x of 0.79 and y of 1.2 is manufactured, and the stability of the threshold voltage is verified. did. FIG. 3 is a graph showing the CV characteristics of the MIS type semiconductor device of Example 1. The applied voltage was changed by continuously sweeping from −2 V to 5 V, from 5 V to −2 V, from −2 V to 10 V, from 10 V to −2 V, from −2 V to 15 V, from 15 V to −2 V, and from −2 V to 5 V. The voltage sweep rate was 0.1 V / s. As shown in FIG. 3, the threshold voltage hardly changes even when the applied voltage is swept as described above. In particular, even when the applied voltage is greatly changed from −2 V to 15 V and from 15 V to −2 V, the threshold voltage hardly fluctuates.

As a comparative example, a MIS type semiconductor device having the same structure as that of the MIS type semiconductor device of Example 1 except that amorphous ZrO ₂ is used as the gate insulating film 11 is manufactured, and the stability of the threshold value is increased. Verified. FIG. 4 is a graph showing the CV characteristics of the MIS type semiconductor device of the comparative example. The applied voltage was swept in the same manner as in FIG. As shown in FIG. 3, the threshold voltage greatly fluctuates when the applied voltage is swept from −2 V to 10 V, from 10 V to −2 V, and from −2 V to 15 V, and from 15 V to −2 V. Recognize. It can also be seen that the threshold voltage slightly fluctuates even when the applied voltage is swept from -2 V to 5 V and from 5 V to -2 V.

Thus, it is made of ZrO _x N _y and is amorphous, and x and y are x> 0, y> 0, 0.3 ≦ y / x ≦ 10, and 1.5 ≦ 0.55x + y ≦ 1. It can be seen that the MIS type semiconductor device of Example 1 having the gate insulating film 11 satisfying 7 is stable in operation without fluctuation of the threshold voltage even when a large voltage is applied. Further, from the results of FIG. 3, it is effective in an MIS type semiconductor device having an operating voltage of 5 V or more, particularly an operating voltage of 10 V or more, and even an MIS type semiconductor device having such an operating voltage can be stably operated. You can see that

[Experiment 2]
In the formation of the gate insulating film 11 in the MIS type semiconductor device of Example 1, the argon gas flow rate is constant at 20 sccm, the nitrogen gas flow rate is 8.5 sccm, and the oxygen gas flow rate is 0.1, 0.3, 0.5, Five samples were prepared in place of 1, 3 sccm. The gate insulating film 11 was formed in an amorphous state in any of the five samples. The O composition ratio x and N composition ratio y of the gate insulating film 11 were as shown in the graph of FIG. That is, when the oxygen gas flow rate is 0.1 sccm (oxygen gas flow rate / nitrogen gas flow rate 0.0118), x is approximately 0.2 and y is approximately 1.55 (plot 5 in FIG. 5). Is 0.3 sccm (oxygen gas flow rate / nitrogen gas flow rate is 0.0353), x is approximately 0.24, y is approximately 1.4 (plot 4 in FIG. 5), and oxygen gas flow rate is 0.5 sccm ( When oxygen gas flow rate / nitrogen gas flow rate is 0.0588, x is approximately 0.45, y is approximately 1.45 (plot 3 in FIG. 5), oxygen gas flow rate is 1 sccm (oxygen gas flow rate / nitrogen gas flow rate) X is approximately 0.76, y is approximately 1.24 (plot 2 in FIG. 5), and the oxygen gas flow rate is 3 sccm (oxygen gas flow rate / nitrogen gas flow rate is 0.3529). X is approximately 1.85, There approximately 0.55 (plot 1 in FIG. 5), was.

  From the graph of FIG. 5, in any of the five samples, the O composition ratio x and the N composition ratio y of the gate insulating film 11 are in the range where y is ± 0.1 around the straight line 0.55x + y = 1.6. In other words, it is included in the range satisfying 1.5 ≦ 0.55x + y ≦ 1.7.

FIG. 6 is a graph showing the shift amount of the threshold voltage for the five samples used in FIG. This is the threshold voltage shift amount when the applied voltage is swept from -2 V to 10 V, swept from 10 V to -2 V, and swept from -2 V to 15 V. The horizontal axis represents the nitrogen atom concentration / oxygen atom concentration (that is, y / x) of ZrO _x N _y that is the material of the gate insulating film 11, and the vertical axis represents the threshold voltage shift amount (V). As a comparative example, when y / x = 0, that is, when the gate insulating film 11 is ZrO ₂ , the applied voltage was similarly swept to investigate the shift amount of the threshold voltage. The numbers given to the plots in FIG. 6 correspond to the numbers of the plots given in FIG. In the comparative example in which the gate insulating film 11 is ZrO ₂ , the shift amount of the threshold voltage is about 4.8V, whereas in the other five samples, the shift amount of the threshold voltage is 1V or less. Thus, it was found that when the composition ratio y / x of nitrogen and oxygen in ZrO _x N _y is 0.3 ≦ y / x ≦ 10, the threshold voltage shift amount is 1 V or less. If the shift amount is 1 V or less, the MIS type semiconductor device of Example 1 having an operating voltage of 5 V or more, particularly 10 V or more can be stably operated. The reason why y / x is set to 10 or less is that since the ratio of nitrogen in ZrO _x N _y increases, the physical properties approach ZrN, which is conductive, and the function as an insulating film cannot be achieved.

  A more desirable range of y / x is 1 ≦ y / x ≦ 5. Within this range, as shown in FIG. 6, the shift amount of the threshold voltage can be 0.1 V or less, and the MIS type semiconductor device of Example 1 can be operated more stably.

  The O composition ratio x may be 0.5 or less. Even if x is within this range, x and y satisfy x> 0, y> 0, 0.3 ≦ y / x ≦ 10, and 1.5 ≦ 0.55x + y ≦ 1.7. For example, as shown in FIG. 6, the MIS type semiconductor device according to the first embodiment can reduce the threshold voltage shift amount to 1 V or less, and can operate stably.

  The MIS type semiconductor device of the present invention is not limited to the structure shown in the first embodiment, and may have any structure as long as a gate insulating film and a gate electrode are sequentially formed on the semiconductor layer. .

In the MIS type semiconductor device of Example 1, the gate insulating film 11 is a single layer. However, if the gate insulating film 11 is made of amorphous ZrO _x N _y satisfying the ranges of x and y, the O composition ratio x, N It may be composed of a plurality of layers having different composition ratios y.

  FIG. 7 is a diagram illustrating the configuration of the HFET 100 according to the second embodiment.

  The HFET 100 includes a substrate 101 made of Si, and a first carrier traveling layer 103 made of non-doped GaN located on the substrate 101 via a buffer layer 102 made of AlN.

In addition, the second carrier traveling layer 104 made of non-doped GaN formed separately on two regions separated from each other on the first carrier traveling layer 103 and the two separated second carrier traveling layers. The carrier supply layer 105 made of Al _0.25 Ga _0.75 N is provided on each 104, and the second carrier running layer 104 and the carrier supply layer 105 are heterojunctioned. The second carrier transit layer 104 and the carrier supply layer 105 are layers formed by selective regrowth.

  In addition, of the two separated carrier supply layers 105, a source electrode 106 formed on one carrier supply layer 105 and a drain electrode 107 formed on the other carrier supply layer 105 are provided. . The source electrode 106 and the drain electrode 107 are made of Ti / Al (in order of Ti and Al from the carrier supply layer 105 side).

Further, the two second carrier running layers 104 and the carrier supply are provided on the first carrier running layer 103 between which the second carrier running layer 104 and the carrier supply layer 105 are sandwiched. On the two side end faces 111 of the second carrier traveling layer 104 and the carrier supply layer 105 on the side where the regions of the layer 105 are spaced apart from each other, on the carrier supply layer 105, amorphous ZrO _x N _y (where x and y are x> 0, y> 0, 0.3 ≦ y / x ≦ 10, and 1.5 ≦ 0.55x + y ≦ 1.7).

  In addition, a gate electrode 109 formed on the first carrier traveling layer 103 where the second carrier traveling layer 104 is not formed and on the two side end surfaces 111 is provided via the insulating film 108. The gate electrode 109 is made of Ni / Au (in order of Ni and Au from the insulating film 108 side). The gate electrode 109 extends also on the carrier supply layer 105 in the vicinity of the side end face 111 via the insulating film 108 and extends 0.5 μm to the source electrode 106 side and the drain electrode 107 side, respectively. By extending in this way, when a positive voltage is applied to the gate electrode 109, more electrons can be accumulated in the vicinity of the side end face 111, and the 2DEG of the region corresponding to the lower portion of the extended gate electrode 109 is stored. The concentration can be further increased. Therefore, the on-resistance can be further reduced.

  The thickness of the first carrier transit layer 103 is 2 μm, the thickness of the second carrier transit layer 104 is 100 nm, and the thickness of the carrier supply layer 105 is 25 nm. The thickness of the insulating film 108 is 40 nm. Further, the distance between the source electrode 106 and the gate electrode 109 is 1.5 μm, the distance between the gate electrode 109 and the drain electrode 107 is 6.5 μm, and the gate electrode 109 has an asymmetrical configuration located closer to the source electrode 106. ing. In this manner, the gate electrode 109 is positioned closer to the source electrode 106 than the drain electrode 107, thereby improving the pressure resistance.

  In addition to Si, the substrate 101 may be made of any material conventionally known as a group III nitride semiconductor growth substrate, such as sapphire, SiC, ZnO, spinel, and GaN.

  In addition to AlN, GaN may be used for the buffer layer 102, or a plurality of layers such as AlN / GaN may be used. The first carrier transit layer 103 may be a group III nitride semiconductor having an arbitrary composition ratio, but GaN is desirable from the viewpoint of crystallinity and the like. The first carrier traveling layer 103 may be doped with an n-type impurity or the like, and may be composed of a plurality of layers. Further, the first carrier traveling layer 103 may be formed directly on the substrate 101 without forming the buffer layer 102.

  The second carrier transit layer 104 is GaN and the carrier supply layer 105 is AlGaN. The composition ratio of the group III nitride semiconductor is selected so that the band gap of the carrier supply layer 105 is larger than that of the second carrier transit layer 104. If so, the second carrier running layer 104 and the carrier supply layer 105 may be any group III nitride semiconductor. For example, InGaN may be used as the second carrier traveling layer 104 and GaN or AlGaN may be used as the carrier supply layer 105. The carrier supply layer 105 may be an n-type doped with an impurity such as Si. Further, a structure in which a cap layer is provided over the carrier supply layer 105 may be employed. The second carrier traveling layer 104 may have the same composition as the first carrier traveling layer 103, or may be a group III nitride semiconductor material having a different composition ratio.

  Due to the heterojunction between the second carrier transit layer 104 and the carrier supply layer 105, 2DEG is present in the vicinity of the heterojunction interface 110 between the second carrier transit layer 104 and the carrier supply layer 105 and on the second carrier transit layer 104 side. It is formed (portion shown by a dotted line in FIG. 1). Since the second carrier traveling layer 104 and the carrier supply layer 105 are formed in two regions separated from each other by the gate electrode 109, the 2DEG is also on the side where the source electrode 106 is formed on the carrier supply layer 105. It is formed separately in two regions (source-gate side) and the side where the drain electrode 107 is formed on the carrier supply layer 105 (gate-drain side).

  The source electrode 106 and the drain electrode 107 are in ohmic contact with the second carrier traveling layer 104 through the carrier supply layer 105 by a tunnel effect. In addition to Ti / Al, Ti / Au or the like can be used as a material for the source electrode 106 and the drain electrode 107. Note that a material having a Schottky contact may be used, but this is not desirable in order to reduce the on-resistance. Further, in order to obtain a good ohmic contact, the regions of the carrier supply layer 105 and the second carrier running layer 104 immediately below the source electrode 106 and the drain electrode 107 are doped with Si at a high concentration, or the source electrode 106 and the drain electrode The thickness of the carrier supply layer 105 immediately below 107 may be reduced.

The insulating film 108 serves as both a gate insulating film and a protective film. The gate insulating film is a region 108 a of the insulating film 108 that is located between the first carrier traveling layer 103, the second carrier traveling layer 104, the carrier supply layer 105, and the gate electrode 109. Of course, the gate insulating film may not serve as the protective film, and the gate insulating film portion is amorphous ZrO _x N _y (where x and y are x> 0, y> 0, 0.3 ≦ y / x ≦ 10 and 1.5 ≦ 0.55x + y ≦ 1.7), the protective film portion may be made of another material. When the protective film portion is made of another material, SiO ₂ , SiN _x , Al ₂ O ₃ , HfO ₂ , ZrO ₂ , AlN or the like can be used. In addition, although the insulating film 108 is a single layer, all or part of the insulating film 108 may be formed of a plurality of layers including a layer made of amorphous ZrO _x N _y satisfying the above x and y.

  The gate electrode 109 may be made of Ti / Al, W, polysilicon or the like in addition to Ni / Au.

  The operation of the HFET 100 according to the second embodiment will be described. In the HFET 100, in the state where the bias voltage is not applied to the gate electrode 109, 2DEG is separated into the source-gate side and the gate-drain side and is not electrically connected. Therefore, no current flows between the source and the drain, and the transistor is in the off state. That is, the HFET 100 has normally-off characteristics. On the other hand, when a bias voltage equal to or higher than the threshold voltage is applied to the gate electrode 109, the region in contact with the gate electrode 109 through the insulating film 108, that is, the first carrier traveling where the second carrier traveling layer 104 is not formed. Electrons are accumulated in the vicinity of the surface of the layer 103, in the vicinity of the side end face 111 facing the second carrier traveling layer 104 and the carrier supply layer 105, and the 2DEG on the source-gate side and the 2DEG on the gate-drain side are connected via the accumulated electrons. Electrically connected. As a result, a current flows between the source and the drain, and the device is turned on.

  Further, in this HFET 100, since the second carrier traveling layer 104 is a layer selectively regrown on the first carrier traveling layer 103, the interface between the first carrier traveling layer 103 and the second carrier traveling layer 104 is obtained. However, impurities accompanying regrowth in the second carrier transit layer 104 decrease as the distance from the first carrier transit layer 103 increases. Therefore, at the heterojunction interface 110 between the second carrier transit layer 104 and the carrier supply layer 105, almost no impurities accompanying selective regrowth are observed. In addition, the carrier supply layer 105 is a layer that is selectively regrown continuously with the second carrier traveling layer 104 after the second carrier traveling layer 104 is regrown, and therefore, the second carrier traveling layer 104. The flatness of the heterojunction interface 110 between the carrier supply layer 105 and the carrier supply layer 105 is determined by the heterogeneity between the first carrier travel layer 103 and the carrier supply layer 105 when the carrier supply layer 105 is regrown directly on the first carrier travel layer 103. It is higher than the bonding interface. Therefore, the mobility of 2DEG formed near the heterojunction interface 110 between the second carrier traveling layer 104 and the carrier supply layer 105 and on the second carrier traveling layer 104 side is not reduced. Therefore, the HFET 100 of Example 2 has a structure with low on-resistance while being normally off.

  Note that the thickness of the second carrier traveling layer 104 is sufficient to sufficiently reduce impurities mixed with regrowth at the heterojunction interface between the second carrier traveling layer 104 and the carrier supply layer 105 and to improve flatness. The thickness is preferably 50 nm or more.

  In the HFET 100, the upper end of the insulating film 108 formed on the first carrier travel layer 103 is lower than the heterojunction interface 110 between the second carrier travel layer 104 and the carrier supply layer 105 (first carrier travel layer). The thickness of the insulating film 108 is made thinner than the thickness of the second carrier traveling layer 104 so as to be closer to the position 103. Thereby, when a positive voltage is applied to the gate electrode 109, more electrons can be accumulated in the vicinity of the two side end surfaces 111. As a result, the on-resistance is further reduced.

In the HFET 100, the gate insulating film (the first carrier traveling layer 103, the second carrier traveling layer 104, and the region 108a located between the carrier supply layer 105 and the gate electrode 109 in the insulating film 108) is amorphous. ZrO _x N _y (where x and y satisfy x> 0, y> 0, 0.3 ≦ y / x ≦ 10, and 1.5 ≦ 0.55x + y ≦ 1.7) ing. Therefore, even when the HFET 100 is set to an operating voltage of 5 V or more, the threshold value does not fluctuate and stable operation can be performed.

  Next, the manufacturing process of the HFET 100 of Example 2 will be described with reference to the drawings.

  First, the buffer layer 102 made of AlN is formed on the substrate 101 made of Si by the MOCVD method. Then, the first carrier traveling layer 103 made of non-doped GaN is formed on the buffer layer 102 by MOCVD (FIG. 8A). Hydrogen and nitrogen are used for the carrier gas, ammonia is used for the nitrogen source, TMG (trimethylgallium) is used for the Ga source, and TMA (trimethylaluminum) is used for the Al source.

Next, a mask 113 made of SiO ₂ is formed in a predetermined region on the first carrier traveling layer 103 by a CVD method, and the mask 113 is not formed in two spaced regions with the mask 113 interposed therebetween. The surface of the traveling layer 103 is exposed (FIG. 8B). The mask 113 may be any material that inhibits the growth of the group III nitride semiconductor. In addition to SiO ₂ , an insulating film such as Si ₃ N ₄ , Al ₂ O ₃ , HfO ₂ , or ZrO ₂ may be used. it can.

  Next, the second carrier traveling layer 104 made of non-doped GaN is regrown on the first carrier traveling layer 103 by MOCVD. Here, since crystal growth is inhibited on the mask 113 and GaN does not grow, the second carrier traveling layer 104 is selectively regrown only on two separated regions where the mask 113 is not formed (FIG. 8 (c)). During this regrowth, the flatness of the interface between the first carrier traveling layer 103 and the second carrier traveling layer 104 is deteriorated, and impurities are mixed. However, as the second carrier transit layer 104 grows, the flatness of the surface of the second carrier transit layer 104 recovers, and the contamination of impurities accompanying regrowth also decreases.

After the second carrier traveling layer 104 is grown to a predetermined thickness, the carrier supply layer 105 made of Al _0.25 Ga _0.75 N is subsequently grown by the MOCVD method. Also in this case, since the crystal growth is inhibited on the mask 113, the carrier supply layer 105 is selectively grown only on the two second carrier traveling layers 104. When the carrier supply layer 105 is formed, the flatness of the second carrier travel layer 104 is restored and the contamination of impurities is reduced. Therefore, the heterojunction interface between the second carrier travel layer 104 and the carrier supply layer 105 is flattened. The impurities are high, and there are almost no impurities associated with regrowth in the vicinity of the interface. The mask 113 is removed after the carrier supply layer 105 is grown to a predetermined thickness (FIG. 8D).

Next, on the first carrier running layer 103 where the second carrier running layer 104 is not formed, the second carrier running layer 104 on the side where the second carrier running layer 104 and the carrier supply layer 105 in the two regions are separated and face each other. On the two side end surfaces 111 of the carrier supply layer 105 and the carrier supply layer 105, amorphous ZrO _x N _y (where x and y are x> 0, y> 0, 0.3 ≦ y / x ≦ 10). And 1.5 ≦ 0.55x + y ≦ 1.7) is formed (FIG. 8E). The insulating film 108 serves as both a gate insulating film and a protective film for the carrier supply layer 105, thereby reducing the number of manufacturing steps.

Here, the insulating film 108 is formed by using an ECR sputtering method in a mixed gas in which nitrogen and oxygen are mixed with argon gas, using a Zr metal target, the substrate temperature is room temperature, and the pressure is 0. The power is set to 07 to 0.2 Pa, the RF power is 500 W, and the microwave power is 500 W. The flow rate of argon gas is 15-30 sccm, the flow rate of oxygen gas is 0.1-3.0 sccm, and the flow rate of nitrogen gas is 4.3-17 sccm. The O composition ratio and the N composition ratio of the gate insulating film 11 can be controlled by the oxygen gas flow rate and the nitrogen gas flow rate, and the ratio of the oxygen gas flow rate to the nitrogen gas flow rate is 0.012 to 0.36. Under these conditions, amorphous ZrO _x N _y (where x and y are x> 0, y> 0, 0.3 ≦ y / x ≦ 10, and 1.5 ≦ 0.55x + y ≦ 1.7, The insulating film 108 can be formed.

  Next, the insulating film 108 in the region where the source electrode 106 and the drain electrode 107 are formed is removed to expose the carrier supply layer 105, and the source electrode 106 and the drain electrode 107 are formed on the exposed carrier supply layer 105 by vapor deposition and lift-off. Form. Further, the gate electrode 109 is formed by vapor deposition and lift-off on the first carrier running layer 103 where the second carrier running layer 104 is not formed, on the two side end faces 111 and on the carrier supply layer 105 in the vicinity of the side end face 111. . Thus, the HFET 100 shown in FIG. 1 is manufactured.

According to the method for manufacturing the HFET 100, the flatness of the heterojunction interface between the second carrier transit layer 104 and the carrier supply layer 105 is high, and almost no impurities are observed due to regrowth in the vicinity of the interface. The on-resistance can be lowered while having it. Amorphous ZrO _x N _y (where x and y satisfy x> 0, y> 0, 0.3 ≦ y / x ≦ 10, and 1.5 ≦ 0.55x + y ≦ 1.7) Therefore, even when the HFET 100 is set to an operating voltage of 5 V or more, the threshold value does not fluctuate and a stable operation can be performed.

In the method of manufacturing the HFET 100, the mask 113 used for selective growth is removed after the formation of the carrier supply layer 105. However, as the mask 113, amorphous ZrO _x N _y (where x and y are x > 0, y> 0, 0.3 ≦ y / x ≦ 10, and 1.5 ≦ 0.55x + y ≦ 1.7), and it is used as it is as a gate insulating film without being removed. May be.

  FIG. 9 is a diagram illustrating a configuration of the HFET 400 according to the third embodiment. The HFET 400 is formed by forming three pairs of the second carrier running layer 404 and the carrier supply layer 405 instead of the second carrier running layer 104 and the carrier supply layer 105 in the HFET 100 of the first embodiment. The second carrier running layer 404a, the carrier supply layer 405a, the second carrier running layer 404b, the carrier supply layer 405b, the second carrier running layer 404c, and the carrier supply layer 405c are stacked in this order from the layer 103 side. Other configurations are the same as those of the HFET 100. The three pairs of the second carrier running layer 404 and the carrier supply layer 405 are selectively regrown on the first carrier running layer 103, similarly to the second carrier running layer 104 and the carrier supply layer 105 of the HFET 100. Layer.

  The heterojunction interface 440a between the second carrier running layer 404a and the carrier supply layer 405a and the second carrier running layer 404a side, and the heterojunction interface 440b between the second carrier running layer 404b and the carrier supply layer 405b 2DEGs are formed on the carrier traveling layer 404b side and the heterojunction interface 440c between the second carrier traveling layer 404c and the carrier supply layer 405c and on the second carrier traveling layer 404c side, respectively. Further, since the second carrier transit layer 404 and the carrier supply layer 405 are layers selectively regrown on the first carrier transit layer 103, these heterojunction interfaces 440a, b, and c have high flatness. In the regions near the heterojunction interfaces 440a, b, and c, almost no impurities mixed with regrowth are observed. Therefore, in 2DEG formed in the vicinity of these heterojunction interfaces 440a, b, and c, a decrease in mobility is suppressed, and an on-resistance is reduced.

  As described above, the HFET 400 of Example 3 has a structure in which the on-resistance is further reduced because three 2DEG layers in which the decrease in mobility is suppressed are formed.

Further, in the HFET 400 of the third embodiment, as in the HFET 100 of the second embodiment, the gate insulating film (the first carrier traveling layer 103, the second carrier traveling layer 404, the carrier supply layer 405 of the insulating film 108, and the gate) As the region 108a located between the electrodes 109), amorphous ZrO _x N _y (where x and y are x> 0, y> 0, 0.3 ≦ y / x ≦ 10, and 1.5). ≦ 0.55x + y ≦ 1.7) is used. Therefore, even when the HFET 400 is set to an operating voltage of 5 V or more, the threshold value does not fluctuate and stable operation can be performed.

  In Example 3, the second carrier traveling layers 404a, b, and c all have the same composition, and the carrier supply layers 405a, b, and c all have the same composition. However, the second carrier traveling layer 404a and the carrier If the supply layer 405a, the second carrier travel layer 404b and the carrier supply layer 405b, the second carrier travel layer 404c and the carrier supply layer 405c are each heterojunction and 2DEG is formed near the interface, the second carrier travel is performed. The layers 404a, b, and c may have different compositions, and the carrier supply layers 405a, b, and c may have different compositions.

  In the second and third embodiments, the HFET is shown as a more specific example of the MIS type semiconductor device, but the present invention is not limited to this, and any semiconductor having a conventionally known MIS type structure. Applicable to the device. For example, the present invention can be applied to FETs, IGBTs (insulated gate bipolar transistors), and the like.

  The MIS type semiconductor device of the present invention is suitable for power devices such as MISFET and HFET.

10: Semiconductor layer 11: Gate insulating film 12: Gate electrode 100: HFET
101: substrate 102: buffer layer 103: first carrier traveling layer 104: second carrier traveling layer 105: carrier supply layer 106: source electrode 107: drain electrode 108: insulating film 109: gate electrode

Claims (15)

In a MIS type semiconductor device having a gate insulating film made of ZrO _x N _y on a semiconductor layer and having a gate electrode on the gate insulating film and an operating voltage of 5 V or more,
The gate insulating film is amorphous,
x and y satisfy x> 0, y> 0, and 0.3 ≦ y / x ≦ 10,
MIS type semiconductor device characterized by the above.   2. The MIS type semiconductor device according to claim 1, wherein x and y further satisfy 1.5 ≦ 0.55x + y ≦ 1.7.   The MIS type semiconductor device according to claim 1, wherein x and y satisfy 1 ≦ y / x ≦ 5.   4. The MIS type semiconductor device according to claim 1, wherein x ≦ 0.5.   5. The MIS type semiconductor device according to claim 1, wherein the gate insulating film is provided in direct contact with the semiconductor layer. 6.   6. The MIS type semiconductor device according to claim 1, wherein the semiconductor layer is a group III nitride semiconductor layer.   The MIS type semiconductor device according to claim 6, wherein the operating voltage is 10 V or more. In a method for manufacturing a MIS type semiconductor device, comprising: a step of forming a gate insulating film made of ZrO _x N _y on a semiconductor layer by a sputtering method; and a step of forming a gate electrode on the gate insulating film.
In the sputtering method, the gate insulating film is made amorphous at room temperature while flowing a gas containing nitrogen gas and oxygen gas with a metal Zr as a target, and x and y are x> 0, y> 0, and , 0.3 ≦ y / x ≦ 10.
A method for manufacturing a MIS type semiconductor device.   9. The method of manufacturing an MIS type semiconductor device according to claim 8, wherein x and y further satisfy 1.5 ≦ 0.55x + y ≦ 1.7.   10. The method of manufacturing an MIS type semiconductor device according to claim 8, wherein the gate insulating film is formed so that x and y satisfy 1 ≦ y / x ≦ 5.   11. The method for manufacturing a MIS type semiconductor device according to claim 8, wherein the gate insulating film is formed so as to satisfy x ≦ 0.5.   12. The method of manufacturing an MIS type semiconductor device according to claim 8, wherein the gate insulating film is formed directly on the semiconductor layer.   13. The method of manufacturing an MIS type semiconductor device according to claim 8, wherein the semiconductor layer is a group III nitride semiconductor layer.   14. The method of manufacturing an MIS type semiconductor device according to claim 8, wherein the MIS type semiconductor device has an operating voltage of 5 V or more.   The MIS type semiconductor device manufacturing method according to claim 14, wherein the MIS type semiconductor device has an operating voltage of 10 V or more.

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