JP2013115167A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be evenly pressurized at the time of molding and to which an insulation material is evenly attached.SOLUTION: A semiconductor device comprises: a first unit 170 which includes a first semiconductor element 10 bonded to one surface of a first substrate 30, a first heat sink 70 bonded to another surface of the first substrate 30 via a first insulating material 50 and a plurality of terminals 90, 91, 92 of different types extending laterally, and which is molded; and a second unit 180 which includes a second semiconductor element 20 bonded to one surface of a second substrate 40, a second heat sink 80 bonded to another surface of the second substrate 40 via a second insulating material 60 and a plurality of terminals 100, 101, 102 of different types extending laterally, and which is molded. The first unit and the second unit are fixed so as to face each other. Among the plurality of terminals of different types, the terminals 90, 100 which are necessary to be connected to the first unit and the second unit are arranged so as to overlap each other, and the terminals unnecessary to be connected to the first unit and the second unit are arranged so as not to overlap each other.

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a first unit having a first semiconductor element and a second unit having a second semiconductor element.

  Conventionally, in a power module for performing power conversion, a first semiconductor element is electrically connected to a high side electrode and a middle side electrode to constitute an upper arm unit, and a second semiconductor element is a middle semiconductor element. A lower arm unit is configured by being electrically connected to the side electrode and the low side electrode, and the high side electrode, the first semiconductor element, the middle side electrode, the second semiconductor element, and the low side electrode are sequentially stacked to form the high side electrode. In addition, a material sealed with a mold resin so that the outer surface of the low-side electrode is exposed is known (for example, see Patent Document 1).

JP 2006-49542 A

  However, in the configuration described in Patent Document 1 described above, since the outer surface of the high side electrode and the outer surface of the low side electrode are used as cooling surfaces, an insulating material is attached to the surfaces of the high side electrode and the low side electrode via grease. Furthermore, it is necessary to attach a heat sink or the like via grease. Here, if an insulating material is to be attached to the surfaces of both electrodes during molding, the insulating material will be pressed against the electrode with a mold from above and below, but there is a technique to absorb the thickness tolerance due to solder etc. Because there is not, the pressure is insufficient at the thin part, the pressure is applied more than necessary at the thick part, it is difficult to apply pressure uniformly, and it is difficult to apply the insulating material. There was a problem that there was.

  In view of the above, an object of the present invention is to provide a semiconductor device in which uniform pressurization during molding is easy and an insulating material is uniformly attached to a metal plate such as an electrode.

In order to achieve the above object, in a semiconductor device according to one embodiment of the present invention, a first semiconductor element is bonded to one surface of a first substrate, and the first surface is interposed with the first insulating material on the other surface. A plurality of different types of terminals electrically connected to the first semiconductor element extend laterally, and a first unit molded by a sealing resin;
A second semiconductor element is bonded to one surface of the second substrate, and a second heat radiating plate is bonded to the other surface via a second insulating material, and is electrically connected to the second semiconductor element. A plurality of different types of terminals extending sideways and having a second unit molded with a sealing resin,
The surface of the first unit on the side of the first semiconductor element and the surface of the second unit on the side of the second semiconductor element are fixed in a facing state,
Of the plurality of terminals of different types electrically connected to the first semiconductor element and the plurality of terminals of different types electrically connected to the second semiconductor element, the first unit and the first The terminals that need to be connected to the second unit are arranged so as to overlap outside the sealing resin, and the terminals that do not need to be connected to the first unit and the second unit are made of the sealing resin. It is characterized in that it is arranged so as not to overlap when viewed from above.

  According to the present invention, it is possible to provide a semiconductor device that is uniformly pressurized during molding and has a good balance in the thickness direction.

It is the figure which showed an example of the semiconductor device which concerns on Example 1 of this invention. FIG. 1A is a diagram illustrating an upper arm unit of an example of the semiconductor device according to the first embodiment. FIG. 1B is a diagram illustrating an example of the lower arm unit of the semiconductor device according to the first embodiment. FIG. 1C is a diagram illustrating an overall configuration of an example of the semiconductor device according to the first embodiment. It is a top view of an example of a semiconductor device concerning Example 1 of the present invention. FIG. 2A is a plan view of the upper arm unit of the semiconductor device according to the first embodiment. FIG. 2B is a plan view of the lower arm unit of the semiconductor device according to the first embodiment. FIG. 2C is a plan view of the semiconductor device according to the first embodiment after joining the upper arm unit and the lower arm unit. It is the figure which showed an example of the semiconductor device which concerns on Example 2 of this invention. FIG. 3A is a cross-sectional view illustrating an upper arm unit of an example of a semiconductor device according to the second embodiment. FIG. 3B is a cross-sectional view illustrating an example of the lower arm unit of the semiconductor device according to the second embodiment. FIG. 3C is a cross-sectional view illustrating a completed state of the exemplary semiconductor device according to the second embodiment. It is the figure which showed an example of the semiconductor device which concerns on Example 3 of this invention. It is the figure which showed an example of the semiconductor device which concerns on Example 4 of this invention. It is the figure which showed an example of the semiconductor device which concerns on Example 5 of this invention. FIG. 6A is a diagram illustrating an example of the semiconductor device of Example 1 according to the comparative example. FIG. 6B is a diagram illustrating an example of a semiconductor device according to the fifth embodiment. It is the figure which showed an example of the semiconductor device which concerns on Example 6 of this invention. FIG. 7A is a diagram illustrating a cross-sectional configuration when an upper arm unit and a lower arm unit are individually molded as an example of the semiconductor device according to the sixth embodiment. FIG. 7B is a diagram illustrating a cross-sectional configuration at the time of joining an upper arm unit and a lower arm unit of an example of the semiconductor device according to the sixth embodiment. It is the figure which showed an example of the upper arm unit of the semiconductor device which concerns on Example 7 of this invention. FIG. 8A is a plan view of the upper arm unit of the semiconductor device according to the seventh embodiment. FIG. 8B is a side view of the upper arm unit of the semiconductor device according to the seventh embodiment. FIG. 8C is a perspective view of the upper arm unit of the semiconductor device according to the seventh embodiment. FIG. 10 is a diagram illustrating an example of a lower arm unit of a semiconductor device according to an example 7. FIG. 9A is a plan view of the lower arm unit of the semiconductor device according to the seventh embodiment. FIG. 9B is a side view of the lower arm unit of the semiconductor device according to the seventh embodiment. FIG. 9C is a perspective view of the lower arm unit of the semiconductor device according to the seventh embodiment. FIG. 10 is a diagram illustrating an example of a completed state of a semiconductor device according to Example 7. FIG. 10A is a plan view of a completed semiconductor device according to the seventh embodiment. FIG. 10B is a side view of the completed semiconductor device according to the seventh embodiment. FIG. 10C is a perspective view of the completed semiconductor device according to the seventh embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  1 is a diagram illustrating an example of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a diagram illustrating an upper arm unit of an example of a semiconductor device according to the first embodiment, and FIG. 1B illustrates a lower arm unit of an example of the semiconductor device according to the first embodiment. FIG. 1C is a diagram illustrating an overall configuration of an example of a semiconductor device according to the first embodiment.

  1A, the upper arm unit 170 of the semiconductor device according to the first embodiment includes semiconductor elements 10 and 11, a metal plate 30, an insulating material 50, a heat radiating plate 70, a cooling fin 71, and a signal terminal. 90, an output terminal 91, a bonding wire 110, solder 120, and a sealing resin 130.

  In the upper arm unit 170, the semiconductor elements 10 and 11 are respectively joined to the metal plate 30 by solder 120. A signal terminal 90 extending to the left side and exposing the tip side portion from the sealing resin 130 is connected to the upper left surface of the semiconductor element 10 via a bonding wire 110. An output terminal 91 is connected to the upper surface of the semiconductor element 10 by solder 120. The output terminal 91 extends toward the right side, is joined to the upper surface of the semiconductor element 11 by the solder 120 on the semiconductor element 11, further extends to the right side, and the tip side is exposed from the sealing resin 130. An insulating material 50 is attached to the lower surface of the metal plate 30, and a heat dissipation plate 70 is attached to the lower surface of the insulating material 50. Cooling fins 71 are formed on the outer surface of the heat radiating plate 70. Further, only the lower surface of the heat sink 70 on which the cooling fins 71 are formed is exposed from the sealing resin 130. Other components are sealed by a sealing resin 130 except for a part of the signal terminal 90 and the output terminal 91, and are covered by being molded.

  The upper arm unit 170 is a unit of a high potential side power module and constitutes, for example, a circuit on the high potential side of an inverter. The upper arm unit 170 includes a semiconductor switching element such as a transistor.

  The semiconductor element 10 is a transistor, for example, a MOS (Metal Oxide Semiconductor) transistor or an IGBT (Insulated Gate Bipolar Transistor).

  The semiconductor element 11 is a diode. When the semiconductor element 10 is a MOS transistor, it is connected in parallel between the source and the drain. When the semiconductor element 10 is an IGBT, it is connected in parallel between the collector and the emitter.

  The metal plate 30 functions as a substrate, electrodes and heat transfer medium for the semiconductor elements 10 and 11. That is, the metal plate 30 supports the semiconductor elements 10 and 11 and electrically connects the electrodes on the lower surface of the semiconductor elements 10 and 11. The metal plate 30 also plays a role of transferring heat generated in the semiconductor elements 10 and 11 to the heat radiating plate 70 and carrying it away. Various materials can be used for the metal plate 30 as long as it is a metal material having high conductivity and thermal conductivity used for a wiring material. For example, the metal plate 30 may be made of copper.

The insulating material 50 is a material for insulating the metal plate 30 and the heat sink 70. Although the heat sink 70 is made of a metal that is a conductor, it forms a cooling surface and is exposed to the outside of the sealing resin 130. Therefore, the insulating material 50 is provided between the heat sink 70 of the metal plate 30 in order to cut off the electrical connection between the outside and the metal plate 30 via the heat sink 70. The insulating material 50, if electrically insulating the heat radiating plate 70 and the metal plate 30, it is possible to use various materials, for example, may be constituted by SiO _2.

  The heat sink 70 is a medium for releasing heat generated in the semiconductor elements 10 and 11 to the outside. Therefore, a part of the heat sink 70 is exposed to the outside without being covered with the sealing resin 130. In this embodiment, only the outer surface of the heat radiating plate 70 is exposed from the sealing resin 130.

  Cooling fins 71 are formed on the outer surface of the heat radiating plate 70. A plurality of cooling fins 71 are provided on the outer surface of the heat radiating plate 70, increase the contact area with the outside air, and increase the cooling efficiency of the heat radiating plate 70.

  The heat radiating plate 70 is made of a material having high thermal conductivity, for example, a metal material. Specifically, for example, the heat dissipation plate 70 may be made of copper, aluminum, or the like.

  The signal terminal 90 is a terminal that supplies an input signal to the semiconductor element 10. Specifically, the signal terminal 90 is connected to the gate of the semiconductor element 10 and supplies an input signal to the gate. The signal terminal 90 is electrically connected to a gate (not shown) of the semiconductor element 10 using a bonding wire 110.

  The external connection terminal 91 is a connection terminal with the external circuit of the semiconductor elements 10 and 11, and functions as an output terminal or an input terminal depending on the state of the connected external circuit or external circuit. For example, when the semiconductor device according to the present embodiment is configured as a power module and the external connection terminal 91 functions as an output terminal, predetermined power is output from the external connection terminal 91 to an external circuit. In this case, when the semiconductor element 10 is a MOS transistor, the output terminal 91 is connected to the drain, and when the semiconductor element 10 is an IGBT, the output terminal 91 is connected to the collector. Further, for example, when the semiconductor device according to the present embodiment is configured as a power module and is connected to a motor / generator, when the motor / generator functions as a motor, the external connection terminal 91 functions as an output terminal. To do. On the other hand, when the motor / generator functions as a generator, the power module functions as a charging module, and the external connection terminal 91 functions as an input terminal.

  The upper arm unit 170 includes a positive terminal (P terminal) not shown in FIG. 1 in addition to the signal terminal 90 and the external connection terminal 91, which will be described later.

  The solder 120 is a bonding material for bonding the electrodes on the lower surfaces of the semiconductor elements 10 and 11 to the metal plate 30 and bonding the bonding wires 110 and the external connection terminals 91 to the electrodes on the upper surfaces of the semiconductor elements 10 and 11. Solder 120 makes these connections both physically and electrically.

  The sealing resin 130 seals all the components other than the lower surface of the heat radiating plate 70 including the cooling fins 71, the signal terminals 90, and the distal end portions of the external connection terminals 91. It is a protective medium to prevent from. Specifically, the sealing resin 130 includes the base portions of the signal terminals 90 and the external connection terminals 91, the bonding wires 110, and the semiconductor elements 10, 11, the metal plate 30, the insulating material 50, and the lower surface of the heat sink 70. All of the solder 120 is sealed.

  The sealing resin 130 is formed by molding. The upper arm unit 170 in the vertical direction before molding has a heat dissipation plate 70 on the lower surface, but the upper surface is open. Therefore, at the time of molding, the insulating material 50 can be uniformly pressurized from multiple points at the top surface.

  Moreover, since the upper surface is open, solder joining from the upper surface side can be performed very easily. That is, even when the semiconductor elements 10 and 11 are joined on the surface of the metal plate 30, no electrode exists above the semiconductor elements 10 and 11, and the semiconductor elements 10 and 11 are not covered from the upper surface. Since it is in a state, the solder 120 can be easily supplied from above, and solder joining can be performed without any obstacles. Further, even if there is some variation in the thickness of the solder 120, no electrode or the like exists on the upper side, and the outer shape can be adjusted by molding, so that the standard required for the solder 120 can be relaxed.

  As described above, the upper arm unit 170 of the semiconductor device according to the first embodiment has a structure in which the upper surface is opened, so that the molding can be appropriately performed, and the insulating material 50 also appropriately dissipates heat from the metal plate 30. It can be provided between the plate 70.

  FIG. 1B illustrates an example of the lower arm unit 180 of the semiconductor device according to the first embodiment. The lower arm unit 180 is a power module unit on the low potential side of the semiconductor device according to the first embodiment. . The lower arm unit 180 includes semiconductor elements 20 and 21, a metal plate 40, an insulating material 60, a heat radiating plate 80, a cooling fin 81, a signal terminal 100, an external connection terminal 101, a bonding wire 111, a solder 120 and a sealing resin 140.

  The lower arm unit 180 has a configuration similar to that of the upper arm unit 170, and each component corresponds to a component of the upper arm unit 170. Specifically, the semiconductor elements 20 and 21 are the semiconductor elements 10 and 11 of the upper arm unit 170, the metal plate 40 is the metal plate 30 of the upper arm unit 170, the insulating material 60 is the insulating material 50 of the upper arm unit 170, and the heat sink. Reference numeral 80 is the heat dissipation plate 70 of the upper arm unit 170, cooling fins 81 are the cooling fins 71 of the upper arm unit 170, signal terminals 100 are the signal terminals 90 of the upper arm unit 170, and external connection terminals 101 are external connection terminals of the upper arm unit 170. 91, the bonding wire 111 corresponds to the bonding wire 110 of the upper arm unit 170, and the sealing resin 140 corresponds to the sealing resin 130 of the upper arm unit 170, respectively.

  As described above, the lower arm unit 180 includes components corresponding to the upper arm unit 170, but the external connection terminal 101 is not from the upper surface of the semiconductor element 20, but from the upper surface of the metal plate 40 to the right side. It differs from the external connection terminal 91 of the upper arm unit 170 in that it extends. This is a difference generated based on the circuit configuration in order to connect the semiconductor element 10 of the upper arm unit 170 and the semiconductor element 20 of the lower arm unit 180 in series. That is, since the electrode on the lower surface of the semiconductor element 20 and the electrode on the upper surface of the semiconductor element 10 are the output terminals, the metal plate 40 connected to the electrode on the lower surface of the semiconductor element 20 and the upper surface of the semiconductor element 10 The external connection terminal 91 connected to the electrode is electrically connected via the external connection terminal 101.

  Note that the configuration and functions of the other components of the lower arm unit 180 are the same as those of the upper arm unit 170, and thus the description thereof is omitted.

  In this manner, by separately manufacturing the upper arm unit 170 and the lower arm unit 180, the mold can be pressed from the opposite side of the heat dissipation plates 70 and 80 during molding using the sealing resins 130 and 140. Therefore, sufficient pressurization can be uniformly applied to the insulating materials 50 and 60, and a press failure can be prevented.

  In addition, when the bonding wires 110 and 111 and the external connection terminals 91 and 101 are bonded onto the semiconductor elements 10, 11, 20, and 21 or the metal plates 30 and 40, the solder 120 can be supplied from the upper side, so that solder bonding is easy. Can be done.

  FIG. 1C is a diagram illustrating a configuration after the completion of the semiconductor device according to the first embodiment. As shown in FIG. 1C, in the semiconductor device according to the first embodiment, the upper arm unit 170 is stacked on the lower arm unit 180 shown in FIG. It is formed by bonding and fixing both. The upper arm unit 170 is turned upside down from the state shown in FIG. 1A, and the surfaces of the molded sealing resins 130 and 140 are joined to each other with the cooling fins 71 positioned on the upper side. Is formed. At this time, the output terminals 91 and 101 overlap with each other on the same plane outside the sealing resins 130 and 140, and can be joined. On the other hand, the signal terminals 90 and 100 are arranged so as not to overlap when viewed from above. Details of this point will be described later.

  The upper arm unit 170 and the lower arm unit 180 can be joined by, for example, applying an adhesive to the opposing surfaces of the upper arm unit 170 and the lower arm unit 180, that is, the joining surfaces, and bonding and fixing the two. May be. Various appropriate adhesives can be used depending on the application.

  Note that the external connection terminals 91 and 101 are finally joined and electrically connected. For example, the external connection terminals 91 and 101 are joined together by welding or solder joining. In that case, for example, since the tips of the external connection terminals 91 and 101 are connected to the external terminals of the external circuit, the external connection terminals are located at the outer tip of the portion where the external connection terminals 91 and 101 overlap each other. 91 and 101 may be joined together.

  In FIG. 1C, the signal terminals 90 and 100 are arranged on the same plane, but the signal terminals 90 and 100 may be arranged on the same plane, or on the same plane. It may not be arranged. In FIG. 1C, the signal terminals 90 and 100 and the external connection terminals 91 and 101 are also arranged on the same plane of the boundary surface between the upper arm unit 170 and the lower arm unit 180. , 100 and the external connection terminals 91 and 101 may be on the same plane or may not be on the same plane. However, the external connection terminals 91 and 101 need to overlap each other so that they can be joined to each other, and thus need to be on the same plane.

  Thus, in the semiconductor device according to the first embodiment, the sealing resin 130 of the upper arm unit 170 and the sealing resin 140 of the lower arm unit 180 are directly joined, and the boundary surface does not include a metal such as an intermediate electrode. The thermal interference between the upper arm unit 170 and the lower arm unit 180 can be greatly reduced.

  Further, the boundary surface between the upper arm unit 170 and the lower arm unit 180 is formed by a joint surface between the sealing resins 130 and 140 and does not include a metal material such as an intermediate electrode. The phenomenon in which the sealing resins 130 and 140 are pulled by the metal material at the time of molding, which occurs when is made of polyamide, can be reduced, and the stress on the resin bonding surface can be relaxed.

  Further, there is no grease between the insulating material 50 and the heat radiating plate 70 and between the insulating material 60 and the heat radiating plate 80, and the heat radiating plate 70 with the cooling fins 71 and 81 directly on the insulating materials 50 and 60. , 80 are attached, the upper arm unit 170 and the lower arm unit 180 can be directly cooled from both surfaces, and sufficient cooling capacity can be ensured.

  FIG. 2 is a plan view of an example of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2A is a plan view of the upper arm unit of the semiconductor device according to the first embodiment, and FIG. 2B is a plan view of the lower arm unit of the semiconductor device according to the first embodiment. FIG. 2C is a plan view of the semiconductor device according to the first embodiment after joining the upper arm unit and the lower arm unit.

  2A, in the upper arm unit 170 according to the first embodiment, the semiconductor element 10 is disposed on the left side on the metal plate 30 and the semiconductor element 11 is disposed on the right side on the metal plate 30. A signal terminal 90 is arranged on the upper side. The bonding wire 110 is electrically connected to an electrode (not shown) on the upper surface of the semiconductor element 10 arranged on the left side of the center. The external connection terminal 91 connects the upper surface electrodes of the semiconductor element 10 and the semiconductor element 11 to each other, extends to the right front side (lower side), and penetrates outside the sealing resin 130. . In addition, a positive electrode terminal 92 is electrically connected to the upper surface of the metal plate 30 and extends to the right side to be exposed through the sealing resin 130. 2A shows a planar configuration in the sealing resin 130, the sealing resin 130 is virtually indicated by a broken line. The positive electrode terminal 92 is a power supply terminal for supplying a power supply voltage to the semiconductor device according to the first embodiment, and is connected to an external power supply (not shown).

  In FIG. 2A, the cross-sectional line of the cross-sectional view shown in FIG. The cross-sectional view shown in FIG. 1 (A) certainly matches the plan view of FIG. 2 (A), and it can be seen that the positive electrode terminal 92 is not shown.

  2B, a plan view of the lower arm unit 180 is shown. The semiconductor element 20 is disposed on the left side of the metal plate 40, and the semiconductor element 21 is disposed on the right side. This is the same as the unit 170. Similar to the upper arm unit 170, the signal terminal 100 is disposed on the left side, and is electrically connected to an electrode (not shown) on the upper surface of the semiconductor element 20 on the central left side by a bonding wire 111. ing. The external connection terminal 101 is connected to the upper surface of the metal plate 40, extends to the right heel side, and is disposed through the sealing resin 140. Note that the sealing resin 140 is virtually indicated by a broken line in the same manner as in FIG.

  On the upper surfaces of the semiconductor elements 20 and 21, a negative electrode terminal (N terminal) 102 is provided which is connected so as to straddle both, and further extends to the right side and penetrates the sealing resin 140. The negative electrode terminal 102 is a terminal on the negative electrode side and is generally a ground terminal. The negative electrode terminal 102 has the same shape and arrangement as the external connection terminal 91 of the upper arm unit 170 shown in FIG. That is, in the lower arm unit 180, contrary to the upper arm unit 170, the metal plate 40 side is the external connection terminal 101, and the upper surface side of the semiconductor elements 20 and 21 is the negative electrode terminal. In FIG. 2B, the cross-sectional line of the cross-sectional view shown in FIG. 1B is shown, but it passes through the signal terminal 100 and the external connection terminal 101, and the negative electrode terminal 102 is not shown. In that respect, it can be seen that it coincides with the cross-sectional view of FIG.

  2C, the upper arm unit 170 shown in FIG. 2A is turned upside down, and the surface shown in FIG. 2A faces the surface of the lower arm unit 180 shown in FIG. It shows the state of joining. Therefore, FIG. 2C illustrates a state where the back surface of the upper arm unit 170 illustrated in FIG. 2A is overlaid on the lower arm unit 180 illustrated in FIG.

  In FIG. 2C, the outer surface of the heat radiating plate 70 and the cooling fin 71 are arranged on the upper surface at the center portion molded by the sealing resin 130, but the upper arm unit on the left side of the molded portion. The signal terminal 90 of 170 and the signal terminal 100 of the lower arm unit 180 are arranged so as not to overlap in a top view. In addition, the external connection terminal 91, the positive electrode terminal 92, and the negative electrode terminal 102 are disposed on the right side of the molded part, but the external connection terminal 91, the positive electrode terminal 92, and the negative electrode terminal 102 are also mutually in a top view. It has an arrangement configuration that does not overlap. Although not shown in FIG. 2 (C), as shown in FIGS. 2 (A), 2 (B) and 1 (C), the lower arm is below the external connection terminal 91 of the upper arm unit 170. There is an external connection terminal 101 of the unit 180, and they overlap each other.

  That is, the external connection terminals 91 and 101 of the upper arm unit 170 and the lower arm unit 180 overlap each other in a top view, but the external connection terminals 91 and 101, the signal terminals 90 and 100, the positive terminal 92, and the negative terminal 102 is arranged so as not to overlap each other when viewed from above. By arranging such terminals so that they do not overlap each other, each of the terminals 90 to 92 and 100 to 102 can be very easily connected to other external terminals.

  As described above, according to the semiconductor device according to the first embodiment, since the upper arm unit 170 and the lower arm unit 180 are molded independently, each can be molded with sufficient and uniform pressure. Since the different types of terminals are arranged so as not to overlap each other in a top view, electrical connection with other elements can be easily performed.

  In the first embodiment, the external connection terminals 91 and 101 overlap each other, and the other signal terminals 90 and 100, the positive electrode terminal 92, and the negative electrode terminal 102 are described as examples that do not overlap each other in a top view. A plurality of different types of terminals are provided in the upper arm unit 170 and the lower arm unit 180, and the terminals that require electrical connection between the upper arm unit 170 and the lower arm unit 180 overlap with each other. As long as terminals that do not need to be electrically connected to 180 are arranged so as not to overlap each other when viewed from above, the type of electrodes is not particularly limited, and various electrodes can be set according to the application.

  This also applies to the following embodiments. In each of the following embodiments, the external connection terminals are terminals that require connection between the upper arm unit and the lower arm unit, and other signal terminals, positive electrodes The terminal and the negative terminal are explained with reference to an example in which the connection between the upper arm unit and the lower arm unit is unnecessary. However, the terminals that need to be connected to the upper arm unit and the lower arm unit are arranged to overlap each other. As long as the terminals that do not need to be connected are arranged so as not to overlap in a top view, the present invention can be applied to a semiconductor device having various terminals.

  FIG. 3 is a diagram illustrating an example of a semiconductor device according to the second embodiment of the present invention. FIG. 3A is a cross-sectional view showing an upper arm unit of an example of a semiconductor device according to the second embodiment, and FIG. 3B shows a lower arm unit of an example of the semiconductor device according to the second embodiment. FIG. 3C is a cross-sectional view illustrating a completed state of an example of the semiconductor device according to the second embodiment.

  3A, the upper arm unit 171 of the semiconductor device according to the second embodiment includes semiconductor elements 10 and 11, a metal plate 30, an insulating material 50, a heat radiating plate 70, a cooling fin 71, and a signal terminal. 90, the external connection terminal 91, the bonding wire 110, the solder 120, and the sealing resin 131 are common to the upper arm unit 170 of the semiconductor device according to the first embodiment.

  However, the upper arm unit 171 of the semiconductor device according to the second embodiment has an uneven shape 132 formed on the upper surface of the sealing resin 131 and is provided with a positioning pin 133. Different from the arm unit 170. The upper surface of the upper arm unit 171 is a surface facing the lower arm unit 181 shown in FIG. 3B. When the upper arm unit 171 and the lower arm unit 181 are fixed by joining on the facing surface, , Constituting the joining surface. The uneven shape 132 is configured for the purpose of increasing the area of the joint surface with the lower arm unit 181 and improving the adhesion. Further, the positioning pins 133 are provided for alignment when joining with the lower arm unit 181.

  Since the other components are the same as those of the upper arm unit 170 of the semiconductor device according to the first embodiment, the same reference numerals are given and description thereof is omitted.

  In FIG. 3B, the lower arm unit 181 of the semiconductor device according to the second embodiment includes semiconductor elements 20 and 21, a metal plate 40, an insulating material 60, a heat radiating plate 80, a cooling fin 81, and a signal terminal. 100, the external connection terminal 101, the bonding wire 111, the solder 120, and the sealing resin 141 are common to the lower arm unit 180 of the semiconductor device according to the first embodiment.

  However, the lower arm unit 181 of the semiconductor device according to the second embodiment is similar to the upper arm unit 171 in that an uneven shape 142 is formed on the upper surface of the sealing resin 141 and a positioning hole 143 is provided. This is different from the lower arm unit 180 of the semiconductor device according to Example 1. The upper surface of the lower arm unit 181 is a surface facing the upper arm unit 171 and constitutes a joint surface. The concavo-convex shape 142 has a structure that fits with the concavo-convex shape 132 of the upper arm unit 171 and has a role of increasing the contact area on the joint surface. Further, the positioning hole 143 has a fitting structure that fits with the positioning pin 133 of the upper arm unit 171, and the upper arm unit 171 and the lower arm unit 181 are fitted by fitting the positioning pin 133 and the positioning hole 143. The joint fixing position is determined.

  Therefore, it is preferable that a plurality of positioning pins 133 and positioning holes 143 are provided so that the joint positions can be uniquely determined.

  Since other components are the same as those of the semiconductor device according to the first embodiment, the same reference numerals are given and description thereof is omitted.

  FIG. 3C is a cross-sectional view of the semiconductor device according to the second embodiment in which the upper arm unit 171 and the lower arm unit 181 are bonded and fixed. As shown in FIG. 3C, the uneven shape 132 of the joint surface of the upper arm unit 171 and the uneven shape 142 of the joint surface of the lower arm unit 181 are fitted to each other. Due to the uneven shapes 132 and 142, the contact area can be increased as compared with the planar bonding surface, and the adhesion can be improved.

  Further, the positioning pin 133 and the positioning hole 143 are fitted to each other, and the opposing position of the upper arm unit 171 and the lower arm unit 171 is determined. This eliminates the need for complicated alignment using a jig or the like at the time of bonding, and allows the upper arm unit 171 and the lower arm unit 181 to be bonded easily.

  The upper arm unit 171 and the lower arm unit 181 are joined by, for example, applying an adhesive to the joining surface (opposing surface) and bonding the upper arm unit 171 and the lower arm unit 181 as in the first embodiment. You may make it carry out fixedly. The uneven shape 132, 142 can enhance the adhesive effect of the adhesive.

  Further, in FIG. 3, an example is given in which the concave and convex shapes 132 and 142 that enhance the adhesion, and the positioning pins 133 and the positioning holes 143 are formed on the opposing surfaces of the upper arm unit 171 and the lower arm unit 181. As described above, only the concave and convex shapes 132 and 142 may be formed, or only the positioning pins 133 and the positioning holes 143 may be formed according to applications.

  The other components have the same configuration and functions as those of the semiconductor device according to the first embodiment, and thus the same reference numerals are given and description thereof is omitted.

  As described above, according to the semiconductor device according to the second embodiment, by forming a fitting structure that fits to the joint surfaces of the upper arm unit 171 and the lower arm unit 171, the adhesion at the time of joining is improved and the joining is performed. In this case, positioning can be easily performed.

  FIG. 4 is a diagram showing an example of a semiconductor device according to Example 3 of the present invention. In FIG. 4, the semiconductor device according to the third embodiment includes an upper arm unit 172 and a lower arm unit 182. The upper arm unit 172 includes a sealing resin 134, and the lower arm unit 182 includes a sealing resin 144.

  The upper arm unit 172 includes a hook 135 in the vicinity of the surface facing the lower arm unit 182 on the side surface, and the lower arm unit 182 is also a hook that engages with the hook 135 in the vicinity of the surface facing the upper arm unit 172 on the side surface. It has a receptacle 145. The hook 135 has a key-like shape that protrudes inward from the distal end portion and extends in a thin manner having a predetermined length continuously with the outer peripheral surface of the sealing resin 134, and has a shape that can be hooked and fixed. Further, the hook receiver 145 is formed in a groove shape at a position that is a predetermined length lower than the facing surface of the sealing resin 144, and is configured such that the hook 135 is hooked.

  As described above, in the semiconductor device according to the third embodiment, the hook structures 135 and 145 that engage with each other are provided on the side surfaces of the upper arm unit 172 and the lower arm unit 182, thereby the upper arm unit 172 and the lower arm unit. 182 is fixed. By using the hook structures 135 and 145, the upper arm unit 172 and the lower arm unit 182 can be fixed in a state of facing each other without using an adhesive or the like. For example, when the semiconductor device according to the present embodiment is configured as a power module such as an inverter and is attached to a location where a cooling water channel is formed, the semiconductor device needs to be compressed and incorporated into the water channel when the water channel is formed. is there. At that time, when the upper arm unit 172 and the lower arm unit 182 are finally bonded and fixed, they are temporarily fixed as in this embodiment until then, and fixed with an adhesive at the time of final mounting. Such an installation is also possible, which can reduce the manufacturing cost.

  Even when such an installation is not performed, the semiconductor device according to this embodiment can be suitably applied when it is desired to configure the semiconductor device without using an adhesive.

  In the semiconductor device according to the third embodiment, the upper arm unit 172 includes an alignment hole 136 on the surface facing the lower arm unit 182, and the lower arm unit 182 is aligned on the surface facing the upper arm unit 172. Pins 146 are provided and are configured to be fitted together when engaged and fixed.

  Thus, also in the semiconductor device according to the third embodiment, an alignment fitting structure may be provided on the facing surface. Note that the alignment hole 136 and the alignment pin 146 may be provided as necessary, and may not be particularly provided when alignment is possible only with the hook structures 135 and 145.

  Further, the hook structures 135 and 145 may be used in combination with the adhesive described in the first and second embodiments. Thereby, the upper arm unit 172 and the lower arm unit 182 can be reliably fixed in a state of facing each other.

  Note that, in the semiconductor device according to the third embodiment, the other components are the same as those of the semiconductor device according to the first and second embodiments, and therefore, the same reference numerals are given and description thereof is omitted.

  FIG. 5 is a diagram showing an example of a semiconductor device according to Example 4 of the present invention. The semiconductor device according to the fourth embodiment includes an upper arm unit 173 and a lower arm unit 183. The upper arm unit 173 includes a sealing resin 137, and the lower arm unit 183 includes a sealing resin 147.

  In the semiconductor device according to the fourth embodiment, the semiconductor device according to the first to third embodiments is that a metal plate 150 is sandwiched between the opposed surfaces of the upper arm unit 173 and the lower arm unit 183. Is different. That is, the upper arm unit 173 and the lower arm unit 183 are joined via the metal plate 150. With this configuration, the inductance of the semiconductor device can be reduced. Since the metal plate 150 is intended to reduce inductance, it is preferable to have a certain thickness. For example, the metal plate 150 may be configured to have a thickness of 1 mm to 5 mm.

  The upper arm unit 173 and the lower arm unit 183 are joined by, for example, applying an adhesive on both surfaces of the metal plate 150, adhering the sealing resin 137 of the upper arm unit 173 on the upper surface, and lowering the lower arm unit 183 on the lower surface. You may comprise so that the sealing resin 147 of the arm unit 183 may be adhere | attached.

  In FIG. 5, the metal plate 150 is composed of two pieces of left and right ones, and a positioning hole 136 and a positioning pin 146 are provided at the center. As described above, the positioning holes 136 and the positioning pins 146 may be provided on the opposing surfaces of the upper arm unit 173 and the lower arm unit 183 as in the case of the second and third embodiments.

  Since other components are the same as those of the semiconductor device according to the first to third embodiments, the same reference numerals are given and the description thereof is omitted.

  According to the semiconductor device according to the fourth embodiment, the inductance of the semiconductor device can be reduced by inserting the metal plate 150 into the facing surfaces of the upper arm unit 173 and the lower arm unit 183.

  FIG. 6 is a diagram showing an example of a semiconductor device according to Example 5 of the present invention. FIG. 6A is a diagram illustrating an example of the semiconductor device according to the first embodiment according to the comparative example, and FIG. 6B is a diagram illustrating an example of the semiconductor device according to the fifth embodiment.

  6A, in the semiconductor device of Example 1 according to the comparative example, the connection between the external connection terminal 91 of the upper arm unit 170 and the external connection terminal 101 of the lower arm unit 180 is connected to the external connection terminals 91 and 101. It is performed on the outermost part of the overlapping part, and the welded portion 160 is formed on the outermost part. In addition, in FIG.1 and FIG.2, although the joint location of the specific external connection terminals 91 and 101 was not specified, if it considers the connection with an external terminal and it provides and constitutes a minimum junction point, The configuration is as shown in FIG. In the case of such a configuration, since the current flows between the semiconductor elements 10 and 20 through a path that passes through all the lengths of the external connection terminals 91 and 101, the circuit path becomes slightly longer.

  On the other hand, in the semiconductor device according to the fifth embodiment shown in FIG. 6B, welding is performed on the base side of the portion where the external connection terminals 91 and 101 overlap, and the semiconductor inside the outer joint 160 is disposed. A joint 161 is formed at a location closest to the elements 10 and 20. With this configuration, the current flowing between the semiconductor elements 10 and 20 passes through the welded portion 161 and the current path is shortened. Therefore, the inductance of the semiconductor device can be further reduced as compared with the semiconductor device according to FIG.

  Even in the semiconductor device according to the fifth embodiment, the external connection terminals 91 and 101 are connected to external terminals, so the outer welded portion 160 itself is required, and both the welded portions 160 and 161 are provided.

  As described above, according to the semiconductor device of Example 5, bonding is performed at a position closest to the innermost semiconductor elements 10, 11, 20, and 21 in the region where the external connection terminals 91 and 101 overlap with each other. The inductance of the device can be reduced.

  Note that the comparative example shown in FIG. 6A has an advantage in that the inductance increases but the number of junction points is small, so depending on whether importance is placed on inductance reduction or manufacturing cost reduction, A suitable form can be selected.

  Other components are the same as those of the semiconductor device according to the first embodiment, and thus the same reference numerals are given and description thereof is omitted.

  FIG. 7 is a diagram showing an example of a semiconductor device according to Example 6 of the present invention. FIG. 7A is a diagram illustrating a cross-sectional configuration when an upper arm unit and a lower arm unit of an example of the semiconductor device according to the sixth embodiment are molded separately, and FIG. 7B is a semiconductor according to the sixth embodiment. It is the figure which showed the cross-sectional structure at the time of joining of the upper arm unit and lower arm unit of an example of an apparatus.

  7A shows the upper arm unit 174 and the lower arm unit 184 of the semiconductor device according to the sixth embodiment. The external connection terminal 93 of the upper arm unit 174 and the external connection terminal 103 of the lower arm unit 184 are shown. Is integrally formed as a continuous lead frame.

  However, the upper arm unit 174 and the lower arm unit 184 are individually molded and sealed separately by the sealing resins 130 and 140, respectively. Therefore, it is possible to pressurize the insulating materials 50 and 60 sufficiently and uniformly during molding.

  In FIG. 7B, the lead frame is bent so that the signal terminal 93 overlaps the signal terminal 103 and the upper arm unit 174 is inverted and laminated on the lower arm unit 184. In addition, for example, the upper arm unit 174 and the lower arm unit 184 can be fixed in a state of facing each other by joining the facing surfaces of the upper arm unit 174 and the lower arm unit 184 to each other.

  In FIG. 7B, the overlapping portion of the signal terminal 93 and the signal terminal 103 is formed in an integrated state with the lead frame, so that it is not necessary to perform welding or the like described in the fifth embodiment. . With this configuration, junction points between the signal terminals 93 and 103 can be eliminated, and the number of junction points of the entire semiconductor device can be reduced.

  Thus, according to the semiconductor device according to the sixth embodiment, the signal terminal 93 of the upper arm unit 174 and the signal terminal 103 of the lower arm unit 184 are configured as an integrated lead frame, so that the number of connection points between the terminals can be increased. Can be reduced.

  Since other components are the same as those in the first embodiment, the same reference numerals are given and the description thereof is omitted.

  FIG. 8 is a diagram illustrating an example of the upper arm unit 175 of the semiconductor device according to the seventh embodiment of the present invention. In the semiconductor device according to the seventh embodiment, an example in which the semiconductor device according to the first embodiment is configured as a three-phase power module will be described. FIG. 8A is a plan view of the upper arm unit 175 of the semiconductor device according to the seventh embodiment, and FIG. 8B is a side view of the upper arm unit 175 of the semiconductor device according to the seventh embodiment. FIG. 8C is a perspective view of the upper arm unit 175 of the semiconductor device according to the seventh embodiment.

  8A to 8C, the upper arm unit 175 includes a heat radiating plate 72, a cooling fin 73, a sealing resin 138, a signal terminal 94, an external connection terminal 95, and a positive terminal 96. . The surface of the heat sink 72 and the cooling fins 73 are exposed on the upper surface of the upper arm unit 175, and other components are sealed with a sealing resin 138. The configuration of the semiconductor device according to the first to sixth embodiments. It is the same.

  In the semiconductor device according to the seventh embodiment, three signal terminals 94 are arranged outside the sealing resin 137 and three external connection terminals 95 are arranged side by side. Is different. This is because the semiconductor device according to Example 7 is configured as a three-phase power module, and three sets of semiconductor elements 10, 11, 20, and 21 are mounted corresponding to the three-phase components. . On the other hand, the positive electrode terminal 96 is a power supply terminal for supplying power, and may be common to three phases, so only one is provided as in the case of one phase.

  In the upper arm unit 175, the signal terminal 94, the external connection terminal 95, and the positive electrode terminal 96 are the same as the previous embodiments in that all the terminals are arranged so as not to overlap each other when viewed from above.

  In FIG. 8B, the external connection terminal 95 is disposed slightly below the positive electrode terminal 96 and is not formed on the same plane as the signal terminal 94 and the positive electrode terminal 96. However, as shown in FIGS. 8A and 8C, the signal terminal 94, the external connection terminal 95, and the positive electrode terminal 96 are arranged so as not to overlap with each other when viewed from above, so that connection with an external connection terminal is easy. There is no problem at all.

  Further, since the upper arm unit 175 is molded by itself using the sealing resin 137, sufficient and uniform pressure can be applied when performing molding.

  FIG. 9 is a diagram illustrating an example of the lower arm unit 185 of the semiconductor device according to the seventh embodiment. FIG. 9A is a plan view of the lower arm unit 185 of the semiconductor device according to the seventh embodiment. FIG. 9B is a side view of the lower arm unit 185 of the semiconductor device according to the seventh embodiment. FIG. 9C is a perspective view of the lower arm unit 185 of the semiconductor device according to the seventh embodiment.

  9A to 9C, the lower arm unit 185 of the semiconductor device according to the seventh embodiment includes semiconductor elements 22 and 23, a metal plate 41, a heat radiating plate 82, a cooling fin 83, and a signal terminal 104. An external connection terminal 105, a negative electrode terminal 106, a bonding wire 112, and a sealing resin 148. Of the three semiconductor elements 22 and 23 arranged, the semiconductor element 22 is a transistor element such as a MOS transistor or IGBT, and the semiconductor element 23 is a diode element. The three pairs of semiconductor elements 22 and 23 are each provided on an independent metal plate 41, and all the metal plates 41 are provided on one heat radiating plate 82. Further, the outside of the heat radiating plate 82 is sealed with a sealing resin 147. Three signal terminals 104 are provided corresponding to the respective semiconductor elements 22, and are connected to the gates of the semiconductor elements 22 by bonding wires 112. Further, a negative electrode terminal 106 is provided so as to cover all the semiconductor elements 22, 23 and connected to the upper surface electrodes of the semiconductor elements 22, 23, and the external connection terminals 105 are connected to the three metal plates 41, respectively. ing. The signal terminal 104, the external connection terminal 105, and the negative electrode terminal 106 are exposed outside the sealing resin 147.

  Since the lower arm unit 185 is molded by using the sealing resin 148 alone, sufficient and uniform pressurization can be performed at the time of molding.

  The three external connection terminals 105 of the lower arm unit 185 are arranged corresponding to each other so as to overlap the external connection terminals 95 of the upper arm unit 175. On the other hand, the signal terminal 104 is disposed so as not to overlap with the signal terminal 94 of the upper arm unit 175, and the negative terminal 106 is similarly disposed so as not to overlap with the positive terminal 96 of the upper arm unit 175.

  FIG. 10 is a diagram illustrating an example of a completed state of the semiconductor device according to the seventh embodiment. FIG. 10A is a plan view of a completed semiconductor device according to the seventh embodiment, and FIG. 10B is a side view of the completed semiconductor device according to the seventh embodiment. ) Is a perspective view of a completed semiconductor device according to the seventh embodiment.

  As shown in FIGS. 10A and 10C, three of the external connection terminals 95 of the upper arm unit 175 and the external connection terminals 105 of the lower arm unit 185 are respectively overlapped with each other. However, the three external connection terminals 95 and 105 do not overlap in top view. Similarly, the six signal terminals 94 and 104 do not overlap in top view. Furthermore, the positive electrode terminal 96 and the negative electrode terminal 106 do not overlap, and the signal terminals 94 and 104, the external connection terminals 95 and 105, the positive electrode terminal 96, and the negative electrode terminal 106 do not overlap in a top view. Therefore, the connection with the external connection terminal is extremely easy.

  Further, as shown in FIG. 10B, the external connection terminals 95 and 105 and the positive electrode terminal 96 are not on the same plane and have different heights, but this is not a problem in connection. .

  Note that the upper arm unit 175 and the lower arm unit 185 can be joined using an adhesive, as in the first embodiment.

  As described above, according to the semiconductor device of Example 7, the upper arm unit 175 and the lower arm unit 185 which are sufficiently pressed and molded are joined, and the three-phase is easily connected to the external terminal. It can be configured as a power module. In addition, although a three-phase power module may be comprised as a power module which fulfill | performs various objectives according to a use, you may be comprised as an inverter, for example.

  Further, in the seventh embodiment, the example in which the three-phase power module is configured using the semiconductor device according to the first embodiment has been described, but the configuration of the upper arm unit 175 and the lower arm unit 185 and the fixing method thereof are changed. Thus, a three-phase power module can be configured using the semiconductor devices according to Examples 2 to 7. Thereby, the additional effect according to each Example can be show | played.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  In particular, the embodiments can be combined within a consistent range. For example, the second embodiment and the sixth embodiment are combined to form a concave / convex shape on the joint surface, and the signal terminals are integrated by a lead frame. It is also possible to configure such as.

  The present invention can be used for various semiconductor devices, for example, a power module using a semiconductor device such as an inverter.

10, 11, 20, 21, 22, 23 Semiconductor element 30, 40, 41, 150 Metal plate 50, 60 Insulating material 70, 72, 80, 82 Heat sink 71, 73, 81, 83 Cooling fins 90, 94, 100 , 104 Signal terminal 91, 93, 95, 101, 103, 105 External connection terminal 92, 96 Positive terminal 102, 106 Negative terminal 110, 111, 112 Bonding wire 120 Solder 130, 131, 134, 137, 138, 140, 141 144, 147, 148 Sealing resin 132, 142 Concavity and convexity 133, 146 Positioning pin 136, 143 Positioning hole 160, 161 Welding part 170-175 Upper arm unit 180-185 Lower arm unit

Claims (13)

A first semiconductor element is bonded to one surface of the first substrate, and a first heat radiating plate is bonded to the other surface via a first insulating material, and is electrically connected to the first semiconductor element. A plurality of different types of terminals extending laterally, and a first unit molded by a sealing resin;
A second semiconductor element is bonded to one surface of the second substrate, and a second heat radiating plate is bonded to the other surface via a second insulating material, and is electrically connected to the second semiconductor element. A plurality of different types of terminals extending sideways and having a second unit molded with a sealing resin,
The surface of the first unit on the side of the first semiconductor element and the surface of the second unit on the side of the second semiconductor element are fixed in a facing state,
Of the plurality of terminals of different types electrically connected to the first semiconductor element and the plurality of terminals of different types electrically connected to the second semiconductor element, the first unit and the first The terminals that need to be connected to the second unit are arranged so as to overlap outside the sealing resin, and the terminals that do not need to be connected to the first unit and the second unit are made of the sealing resin. A semiconductor device, wherein the semiconductor device is arranged so as not to overlap when viewed from above.   2. The semiconductor device according to claim 1, wherein only the outer surface of the first heat radiating plate and the second heat radiating plate is exposed from the sealing resin.   3. The semiconductor device according to claim 1, wherein cooling fins are provided on the outer surfaces of the first heat radiating plate and the second heat radiating plate. 4.   4. The semiconductor device according to claim 1, wherein the first substrate and the second substrate are metal plates. 5.   The first unit and the second unit are fixed by joining opposing surfaces of the first unit and the second unit, respectively. The semiconductor device according to item.   The semiconductor device according to claim 5, wherein an uneven shape that increases a bonding surface is formed on a facing surface of the first unit and the second unit. Hook structures that can be engaged with each other are formed on side surfaces of the first unit and the second unit,
The semiconductor device according to claim 1, wherein the first unit and the second unit are fixed by the hook structure. A metal plate is inserted between the opposing surfaces of the first unit and the second unit,
The first unit and the second unit are fixed by joining opposing surfaces of the first unit and the second unit to each surface of the metal plate. The semiconductor device according to any one of 1 to 4.   9. The positioning fitting structure for fitting to each other is formed on the opposing surfaces of the first unit and the second unit. 10. Semiconductor device.   The semiconductor device according to claim 9, wherein the positioning fitting structure includes a positioning pin and a positioning hole.   11. The semiconductor device according to claim 1, wherein a terminal that needs to be connected to the first unit and the second unit is joined at a tip of an overlapping portion.   The terminal that needs to be connected to the first unit and the second unit is further joined at a position closest to the first and second semiconductor elements in the overlapping portion. 11. The semiconductor device according to 11.   11. The semiconductor device according to claim 1, wherein a terminal that needs to be connected to the first unit and the second unit is configured as an integrated lead frame.

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