JP2013110690A - Latched comparator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a latched comparator that implements a high speed reliable latch output without compromising characteristics of a differential circuit.SOLUTION: A latched comparator (1) includes at least either of: a seventh MOS transistor (QN3) having a drain-source path connected between a first node (N1) on a first current path between a first MOS transistor (Q1) and a third MOS transistor (Q3) and a second node (N2) on a second current path between a second MOS transistor (Q2) and a fifth MOS transistor (Q4), and a gate connected to an output of a first CMOS inverter; and an eighth MOS transistor (QN4) having a drain-source path connected between the first node (N1) and the second node (N2) and a gate connected to an output of a second CMOS inverter.

Description

  The present invention relates to a latched comparator with low power consumption and high reliability.

  VLSI elements have been increased in speed and power consumption, and a technique for solving the trade-off between them has been demanded. For example, a current mirror type sense amplifier used for a memory element operates at a high speed, but consumes a large amount of power because a current continuously flows through a bias transistor. On the other hand, when a latch-type sense amplifier is used for the memory element, the power consumption is suppressed while the operation speed is slow.

  On the other hand, Non-Patent Document 1 proposes a configuration of a current control type latch-type sense amplifier that can achieve both high speed and low power consumption.

  FIG. 10 shows a configuration of a latched comparator 101 as a current control type sense amplifier described in Non-Patent Document 1. The latched comparator 101 includes transistors Q0 to Q8. Transistors Q0 to Q4 are N-channel MOS transistors, and transistors Q5 to Q8 are P-channel MOS transistors.

  The source of the transistor Q0 is connected to the power supply VSS, and the drain of the transistor Q0 is connected to the sources of the transistors Q1 and Q2. A latch signal Latch is input to the gate of the transistor Q0. The transistor Q0 is a transistor for enabling the operations of the transistors Q1 to Q6 when the latched comparator 101 is latched.

  Transistor Q1 and transistor Q2 constitute a differential input pair, and the source of transistor Q1 and the source of transistor Q2 are connected to each other. The gate of the transistor Q1 is the first input terminal Vin + of the latched comparator 101, and the gate of the transistor Q2 is the second input terminal Vin− of the latched comparator 101.

  Transistor Q3 and transistor Q5 constitute a first CMOS inverter. The gate of the transistor Q3 and the gate of the transistor Q5 are connected to each other and function as an input terminal of the first CMOS inverter. The drain of the transistor Q3 and the drain of the transistor Q5 are connected to each other and function as an output terminal of the first CMOS inverter. The source of the transistor Q3 is connected to the drain of the transistor Q1. The source of the transistor Q5 is connected to the power supply VDD.

  Transistor Q4 and transistor Q6 constitute a second CMOS inverter. The gate of the transistor Q4 and the gate of the transistor Q6 are connected to each other and function as an input terminal of the second CMOS inverter. The drain of the transistor Q4 and the drain of the transistor Q6 are connected to each other and function as an output terminal of the second CMOS inverter. The source of the transistor Q4 is connected to the drain of the transistor Q2. The source of the transistor Q6 is connected to the power supply VDD.

  The input terminal of the first CMOS inverter and the output terminal of the second CMOS inverter are connected to each other and serve as the first output terminal Vout + of the latched comparator 101. The output terminal of the first CMOS inverter and the input terminal of the second CMOS inverter are connected to each other and serve as the second output terminal Vout− of the latched comparator 101.

The source of the transistor Q7 is connected to the power supply VDD, and the drain of the transistor Q7 is connected to the output terminal of the first CMOS inverter. A latch signal Latch is input to the gate of the transistor Q7. The source of the transistor Q8 is connected to the power supply VDD, and the drain of the transistor Q8 is connected to the output terminal of the second CMOS inverter. A latch signal Latch is input to the gate of the transistor Q8. The transistors Q7 and Q8 are transistors for resetting the potentials of the first output terminal Vout + and the second output terminal Vout−.
A latched comparator similar to Non-Patent Document 1 is described in Patent Document 1.

Japanese Patent Laid-Open No. 10-327066

Tsuguo Kobayashi, et al. "A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 4, APRIL 1993, pp. 523-527 (Tsuguo Kobayashi et al. “A Current-Controlled Latch Sense Amplifier and A Static Power-Saving Input Buffer for Low-Power Architecture”, I-Triple Journal of Solid-State Circuits, Volume Twoteen Eight, Number Four , April, Nineteen Nine Tissley 523-527) B. Nikolic´, et al. "Design and Optimization of Sense-Amplifier-Based Flip-Flops", Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European, 21-23 Sept. 1999, pp. 410-413 (B Nicolic et al. “Design and Optimization of Sense-Amplifier-Based Flip-Flops”, Solid-State Circuits Conference, Nineteen Ninetyine, NS First-twenty september nineteen nine nine 410-413)

  The operation of the latched comparator 101 in FIG. 10 will be described with reference to “Prior Art 1” in FIG. Assume that the input voltage to the first input terminal Vin + is Vin +, the input voltage to the second input terminal Vin− is Vin−, and Vin +> Vin−> Vt. Vt is the threshold voltage of the transistors Q1 and Q2. The output voltage of the first output terminal Vout + is Vout +, and the output voltage of the second output terminal Vout− is Vout−.

  When the latch signal Latch = Lo (low level), the latched comparator 101 performs a reset operation. Since the transistor Q0 is OFF and the transistors Q7 and Q8 are ON, the output terminals (Vout +, Vout−) and the input terminals of the first CMOS inverter and the second CMOS inverter are Hi (high level). The latch circuit is reset so that At this time, the transistors Q1 to Q6 are all turned off.

  Next, at the timing when the latch signal Latch rises from Lo to Hi, the transistors Q7 and Q8 are turned off and the reset of the latch circuit is released. At the same time, the transistor Q0 is turned on, so that the operations of the transistors Q1 to Q6 become effective. Here, since Vin +> Vin−, the transistor Q1 is turned on before the transistor Q2. Accordingly, the drain potential of the transistor Q1 is lowered before the drain potential of the transistor Q2, so that the transistor Q3 is turned on before the transistor Q4. As a result, the drain potential (output voltage Vout−) of the transistor Q3 is lowered before the drain potential (output voltage Vout +) of the transistor Q4, so that the transistor Q6 is turned on before the transistor Q5.

  The latch circuit constitutes a positive feedback so that the output of the first CMOS inverter becomes the input of the second CMOS inverter and the output of the second CMOS inverter becomes the input of the first CMOS inverter. Accordingly, the transistors Q3 and Q6 are finally turned on and the transistors Q4 and Q5 are turned off, so that the output voltage Vout + sticks to Hi and the output voltage Vout− sticks to Lo. The latch determination time t, which is the time from when the latch signal Latch rises to when the output voltages Vout + and Vout− are determined, is as short as about 10 nsec. Thus, the operation of the latched comparator 101 is very fast. The latched comparator 101 has low power consumption because a current flows through the transistor Q0 only during the latch determination time t.

  The latched comparator 101 maintains the latch operation while the latch signal Latch is Hi, that is, holds the latch output. When the latch signal Latch falls to Lo, the reset operation is started.

  However, as shown in FIG. 2, in the latch operation period in which the latch signal Latch is Hi, the input voltage Vin + falls below the input voltage Vin− (Vin−> Vin +> Vt), and the input voltage Vin + falls below the threshold voltage Vt. In the case of (Vin−> Vt> Vin +), the latch circuit cannot maintain the latch operation, and the latch output malfunctions. In this case, when the input voltage Vin + falls below the input voltage Vin−, the output voltage Vout + temporarily changes to Lo and the output voltage Vout− changes to Hi, but when the input voltage Vin + falls below the threshold voltage Vt, the transistor Q1 Is turned off, so that the source potential of the transistor Q3 becomes floating. Therefore, in each of the branch including the transistor Q1 and the branch including the transistor Q2, the voltage difference between the power supply VDD and the power supply VSS is compared with the normal time in which the drain and source of each transistor are definitely shared, The shared voltage of each transistor becomes indefinite.

  As a result, Hi and Lo of the output voltages Vout + and Vout− are not determined based on the values of the power supply VDD and VSS. For example, the output potential (Vout +) of the second CMOS inverter gradually increases due to leakage from the power supply VDD. If such a phenomenon occurs, an erroneous output that does not correspond to the input may be derived.

  Since the N well of the P-channel MOS transistor is connected to the power supply VDD, there are leakage components r1 and r2 between the power supply VDD and the drain as shown in FIG. As described above, the drain potential of the transistor Q4 gradually rises due to the leak path through the leak components r1 and r2, and eventually leads to inversion of the latch output. That is, there is a disadvantage that even if the latch signal Latch is Hi, a static state cannot be maintained.

Further, when Vin +>Vin−> Vt is satisfied from the state of Vin−> Vin +> Vt and Vin +>Vt> Vin− is satisfied, the latch output similarly malfunctions.
A malfunction of the latch output is directly connected to system instability such as garbled data and calculation error.

  Therefore, a configuration has been proposed in which the potential is prevented from becoming indefinite as described above even when one of the input voltages becomes smaller than the threshold voltage Vt (see, for example, Non-Patent Document 2).

  FIG. 12 shows a configuration of the latched comparator 102 having a configuration that prevents the potential from becoming indefinite. The latched comparator 102 has a configuration in which a transistor QN5 is added to the latched comparator 101 of FIG. The transistor QN5 is an N-channel MOS transistor, and is arranged so that the drain and source of the transistor QN5 connect the source of the transistor Q3 and the source of the transistor Q4. The gate of the transistor QN5 is connected to the power supply VDD. One end of the transistor QN5 connected to the higher one of the source of the transistor Q3 and the source of the transistor Q4 functions as a drain, and the potential of the transistor QN5 between the source of the transistor Q3 and the source of the transistor Q4 One end connected to the lower side functions as a source.

  In the latched comparator 102, when the latch signal Latch is Hi, even if the input voltage Vin + or the input voltage Vin− is smaller than the threshold voltage Vt, the OFF state of the source of the transistor Q3 and the source of the transistor Q4 Since the transistor Q1 or Q2 connected to the transistor Q1 is connected to the power supply VSS through a current path via the transistor QN5, the potential can be determined. Therefore, as shown in “Prior Art 2” in FIG. 2, the latch output state can be maintained even if the input voltage Vin + · Vin− changes.

  However, in the latched comparator 102, by adding the transistor QN5, in the operation when the latch signal Latch rises and the latch output is determined, a part of the drain current of one input transistor (Q1 or Q2) is the transistor QN5. As a result, the transconductance gm defined by the ratio of the differential output current to the differential input voltage decreases. Due to the decrease in transconductance gm, problems such as an increase in latch determination time t or an increase in noise occur. This is due to the following reason. Since the gate of the transistor QN5 is connected to the power supply VDD, the gate voltage of the transistor QN5 is higher than the gate voltages of the transistors Q3 and Q4 at the time of the latch determination operation transition when the latch signal Latch rises. Therefore, if the size of the transistor QN5 is equal to the size of the transistors Q3 and Q4, the conductance of the transistor QN5 is larger than that of the transistors Q3 and Q4, and the current leakage through the transistor QN5 cannot be ignored. As a result, the transconductance gm decreases.

  Further, in the latched comparator 102, due to the added transistor QN5, the offset voltage becomes larger than that of the latched comparator 101, and there is a problem that the performance as the comparator may be deteriorated. The differential circuit is required to match the characteristics of the pair transistors, but the transistor inevitably has element variations such as variations in the threshold voltage Vt. Further, due to the IC layout and the IC process, a mismatch of parasitic capacitance formed in the differential pair circuit also occurs. Due to these element variations and mismatches, in the first place, in the configuration of the latched comparator 101, a shift occurs in the operation point of the circuit at the initial stage of the latch operation. For example, paying attention to the drain voltages of the transistors Q1 and Q2, the transistors Q1 and Q2 ideally start the latch operation from the same drain potential, but there is actually a shift in operating point for the above reason. This shift is one of the causes of the offset voltage. Further, since the transistor QN5 whose gate is connected to the power supply VDD is added to the latched comparator 102, the current of the differential circuit flows through the transistor QN5 due to the above-described shift of the operating point. As the current flows through the transistor QN5 in this manner, the balance of the differential circuit is further lost, so that the offset voltage of the latched comparator 102 becomes larger than the offset voltage of the latched comparator 101.

  SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object of the present invention is to provide a latched comparator that performs high-speed and reliable latch output without impairing the characteristics of the differential circuit.

  A first aspect of the present invention includes a differential amplifier stage having a first MOS transistor and a second MOS transistor that constitute a differential input pair, a first CMOS inverter, and a second CMOS inverter. A latch stage in which the output of the first CMOS inverter is connected to the input of the second CMOS inverter and the output of the second CMOS inverter is connected to the input of the first CMOS inverter. A latched comparator for latching an output of the differential amplifier stage at the latch stage, wherein the first CMOS inverter outputs a first voltage level consisting of one of a high level and a low level. And outputting a second voltage level comprising the third MOS transistor and the other of the high level and the low level. The fourth MOS transistor includes a fifth MOS transistor that outputs the first voltage level, and a sixth MOS transistor that outputs the second voltage level. The first current path through which the current of the first MOS transistor flows in the differential amplification stage is connected to the output of the first CMOS inverter via the third MOS transistor. The second current path through which the current of the second MOS transistor flows in the differential amplification stage is connected to the output of the second CMOS inverter via the fifth MOS transistor, and The first voltage level serving as the output of the first CMOS inverter is set to the first current of the CMOS transistor. A first voltage source for supplying the first voltage level to the fifth CMOS transistor via the second current path and supplying the first voltage level to the fifth CMOS transistor. And supplying the second voltage level that is the output of the first CMOS inverter to the fourth MOS transistor and the output that is the output of the second CMOS inverter to the sixth MOS transistor. A second voltage source for supplying a second voltage level; a path from the first voltage source to the third MOS transistor via the first current path; and the first voltage source A first switch circuit that is inserted in a path from a voltage source to the fifth MOS transistor through the second current path and performs an opening / closing operation. The first node between the first MOS transistor and the third MOS transistor on the first current path, and the second MOS on the second current path. A seventh MOS transistor connected between the transistor and a second node between the fifth MOS transistor and having a gate connected to the output of the first CMOS inverter; At least one of an eighth MOS transistor having a source connected between the first node and the second node and a gate connected to the output of the second CMOS inverter It has more.

  According to a second aspect of the present invention, in the first aspect, the first switch circuit includes a path between the first MOS transistor and the second MOS transistor and the first voltage source. It is provided to conduct and cut off.

  According to a third aspect of the present invention, in the first aspect, the first switch circuit conducts and cuts off a path between the first MOS transistor and the third MOS transistor. A switch element; and a second switch element that conducts and cuts off a path between the second MOS transistor and the fifth MOS transistor.

  According to a fourth aspect of the present invention, in any one of the first aspect to the third aspect, a differential output is generated by performing differential amplification of two input signals, and the differential amplification is performed. A preamplifier stage is provided as an input to the stage.

  According to a fifth aspect of the present invention, in any one of the first aspect to the fourth aspect, conduction between the output of the first CMOS inverter and the second voltage source. And a second switch circuit that cuts off and a third switch circuit that turns on and off between the output of the second CMOS inverter and the second voltage source.

  According to the first aspect, when the input voltage to the first MOS transistor is Vin +, the input voltage to the second MOS transistor is Vin−, and the threshold voltage of the first and second MOS transistors is Vt. In addition, when the state of Vin +> Vin−> Vt is changed to the state of Vin−> Vt> Vin + through the state of Vin−> Vin +> Vt, the seventh MOS transistor is turned on. Accordingly, since the first MOS transistor and the third MOS transistor are connected to the first voltage source via the seventh MOS transistor, it is possible to prevent the potential from becoming unstable. Thereby, malfunction of the latch output can be prevented.

  Further, when the state of Vin−> Vin +> Vt is changed to the state of Vin +> Vt> Vin− through the state of Vin +> Vin−> Vt, the eighth MOS transistor is turned on. Accordingly, since the second MOS transistor and the fifth MOS transistor are connected to the first voltage source via the eighth MOS transistor, it is possible to prevent the potential from becoming unstable. Thereby, malfunction of the latch output can be prevented.

  In addition, since the drain currents of the seventh and eighth MOS transistors are kept small, the magnitude of the differential output current is not significantly affected even if the drain current flows through the seventh and eighth MOS transistors, and the transconductance is not affected. It can suppress that the value of decreases. As a result, it is possible to suppress an increase in latch determination time and generation of noise.

  Further, the seventh MOS transistor is turned on only when the output voltage of the first inverter changes with the latch confirmation operation, and the eighth MOS transistor has the output voltage of the second inverter with the latch confirmation operation. Since the ON state is not changed for the first time, a current that deteriorates the offset voltage does not flow between the first MOS transistor and the second MOS transistor at the initial stage of the latch operation.

  As described above, it is possible to provide a latched comparator that performs high-speed and reliable latch output without impairing the characteristics of the differential circuit.

  According to the second aspect, the first switch circuit is on the path from the first voltage source to the third MOS transistor via the first current path, and from the first voltage source. Even if the opening / closing operation is performed at an arbitrary position on the path leading to the fifth MOS transistor via the second current path, the latching operation is not affected. Therefore, in a circuit in which the first switch circuit is desired to be provided on the first voltage source side with respect to the differential input pair, it is possible to prevent malfunction of latch output, suppress reduction of transconductance, and prevent deterioration of offset voltage. .

  According to the third aspect, the first switch circuit is on the path from the first voltage source to the third MOS transistor via the first current path, and from the first voltage source. Even if the opening / closing operation is performed at an arbitrary position on the path leading to the fifth MOS transistor via the second current path, the latching operation is not affected. Therefore, in a circuit in which the first switch circuit is desired to be provided on the second voltage source side with respect to the differential input pair, it is possible to prevent malfunction of latch output, suppress reduction of transconductance, and prevent deterioration of offset voltage. .

  According to the fourth aspect, when the preamplifier stage is not provided, the gate inputs of the first and second MOS transistors are disturbed by the kickback phenomenon at the start of the latch operation, and noise is mixed in the latch result. Can be avoided.

  According to the fifth aspect, the output of the first inverter can be reset to the voltage of the second voltage source by the second switch circuit, and the output of the second inverter can be reset by the third switch circuit. It can be reset to the voltage of the two voltage sources.

The circuit diagram which shows embodiment of this invention and shows the structure of a latched comparator FIG. 1 is a timing chart showing the operation of the latched comparator in comparison with the prior art. The circuit diagram which shows the structure of the 1st modification of the latched comparator of FIG. The circuit diagram which shows the structure of the 2nd modification of the latched comparator of FIG. The circuit diagram which shows the structure of the 3rd modification of the latched comparator of FIG. The circuit diagram which shows other embodiment of this invention and shows the structure of a latched comparator 6 is a circuit diagram showing a configuration of a modified example of the latched comparator of FIG. The circuit diagram which shows further another embodiment of this invention, and shows the structure of a latched comparator 8 is a circuit diagram showing a configuration of a modified example of the latched comparator of FIG. The circuit diagram which shows a prior art and shows the structure of a 1st latched comparator Circuit diagram for explaining the leak current of the latched comparator of FIG. The circuit diagram which shows a prior art and shows the structure of a 2nd latched comparator

[First Embodiment]
The embodiment of the present invention will be described with reference to FIGS. 1 to 5 as follows.

(Latched comparator configuration)
FIG. 1 shows a configuration of a latched comparator 1 according to the present embodiment. The latched comparator 1 includes transistors Q0 to Q8 and a transistor QN3. Transistors Q0 to Q4 and transistor QN3 are N-channel MOS transistors, and transistors Q5 to Q8 are P-channel MOS transistors.

  The source of the transistor (first switch circuit) Q0 is connected to the power supply (first voltage source) VSS, and the drain of the transistor Q0 is connected to the sources of the transistors Q1 and Q2. A latch signal Latch is input to the gate of the transistor Q0. The transistor Q0 is a switching element for enabling the operations of the transistors Q1 to Q6 when the latched comparator 1 is latched, and is sufficiently overdriven by the latch signal Latch.

  The transistor (first MOS transistor) Q1 and the transistor (second MOS transistor) Q2 constitute a differential input pair, and the source of the transistor Q1 and the source of the transistor Q2 are coupled to each other. The gate of the transistor Q1 is the first input terminal Vin + of the latched comparator 1, and the gate of the transistor Q2 is the second input terminal Vin− of the latched comparator 1. The first current path through which the current of the transistor Q1 flows and the second current path through which the current of the transistor Q2 flows correspond to the differential inputs of the first input terminal Vin + and the second input terminal Vin−, respectively. Current flows. The drain of the transistor Q1 is connected to the source of the transistor Q3, and the drain of the transistor Q2 is connected to the source of the transistor Q4. As a result, the differential input pair constitutes a differential amplification stage that outputs the differential current of each current as an amplification result to a latch stage described later. The differential amplifier stage may include circuits other than the differential input pair.

  The transistor (third MOS transistor) Q3 and the transistor (fourth MOS transistor) Q5 constitute a first CMOS inverter. The gate of the transistor Q3 and the gate of the transistor Q5 are connected to each other and function as an input terminal of the first CMOS inverter. The drain of the transistor Q3 and the drain of the transistor Q5 are connected to each other and function as an output terminal of the first CMOS inverter. The source of the transistor Q3 is connected to the drain of the transistor Q1. The source of the transistor Q5 is connected to the power supply (second voltage source) VDD. Since the first current path is connected to the output of the first CMOS inverter via the transistor Q3, the power source VSS is connected to the transistor Q3 via the first current path and the output of the first CMOS inverter. As a first voltage level, Lo (low level) is supplied. The power supply VDD supplies the transistor Q5 with Hi (high level) as the second voltage level that is the output of the first CMOS inverter.

  The transistor (fifth MOS transistor) Q4 and the transistor (sixth MOS transistor) Q6 constitute a second CMOS inverter. The gate of the transistor Q4 and the gate of the transistor Q6 are connected to each other and function as an input terminal of the second CMOS inverter. The drain of the transistor Q4 and the drain of the transistor Q6 are connected to each other and function as an output terminal of the second CMOS inverter. The source of the transistor Q4 is connected to the drain of the transistor Q2. The source of the transistor Q6 is connected to the power supply VDD. Since the second current path is connected to the output of the second CMOS inverter via the transistor Q4, the power supply VSS is connected to the transistor Q4 via the second current path and the output of the second CMOS inverter. As a first voltage level, Lo (low level) is supplied. The power supply VDD supplies the transistor Q6 with Hi (high level) as the second voltage level that is the output of the second CMOS inverter.

  The input terminal of the first CMOS inverter and the output terminal of the second CMOS inverter are connected to each other and serve as the first output terminal Vout + of the latched comparator 1. The output terminal of the first CMOS inverter and the input terminal of the second CMOS inverter are connected to each other and serve as the second output terminal Vout− of the latched comparator 1. Thus, the first CMOS inverter and the second CMOS inverter constitute a latch circuit. In the latched comparator 1, a latch stage is constituted by the latch circuit. The latch stage may include a circuit other than the latch circuit.

  The source of the transistor (second switch circuit) Q7 is connected to the power supply VDD, and the drain of the transistor Q7 is connected to the output terminal of the first CMOS inverter. A latch signal Latch is input to the gate of the transistor Q7. The source of the transistor (third switch circuit) Q8 is connected to the power supply VDD, and the drain of the transistor Q8 is connected to the output terminal of the second CMOS inverter. A latch signal Latch is input to the gate of the transistor Q8. The transistor Q7 is a switch element that conducts and cuts off between the power supply VDD and the second output terminal Vout−, and resets the output of the second output terminal Vout− by conduction. The transistor Q8 is a switch element that conducts and shuts off between the power supply VDD and the first output terminal Vout +, and resets the output of the first output terminal Vout + by conduction. The transistors Q7 and Q8 are sufficiently overdriven by the latch signal Latch.

  The source of the transistor (seventh MOS transistor) QN3 is connected to the source of the transistor Q4, and the drain of the transistor QN3 is connected to the source of the transistor Q3. That is, between the drain and source of the transistor QN3 is between the node (first node) N1 between the transistors Q1 and Q3 and the node (second node) N2 between the transistors Q2 and Q4. It is connected to the. Note that the position of the node N1 is not particularly distinguished if it is between the transistors Q1 and Q3, and the position of the node N2 is not particularly distinguished if it is between the transistors Q2 and Q4. The gate of the transistor QN3 is connected to the output of the first CMOS inverter, that is, the second output terminal VOUT−.

  In the above configuration, the first current path is a path from the drain of the transistor Q0 to the source of the transistor Q3, and the second current path is from the drain of the transistor Q0 to the source of the transistor Q4. It is a route. The transistor Q0 is inserted into a path from the power supply VSS to the transistor Q3 through the first current path and a path from the power supply VSS to the transistor Q4 through the second current path to perform an opening / closing operation. Do. Here, in particular, the transistor Q0 has one switching element between the power source VSS and the connection point between the source of the transistor Q1 and the source of the transistor Q2, which is a connection point between the first current path and the second current path. The opening and closing operation is performed.

(Latched comparator operation)
Next, the operation of the latched comparator 1 of FIG. 1 will be described with reference to FIG. Assume that the input voltage to the first input terminal Vin + is Vin +, the input voltage to the second input terminal Vin− is Vin−, and Vin +>Vin−> Vt. Vt is the threshold voltage of the transistors Q1 and Q2. The output voltage of the first output terminal Vout + is Vout +, and the output voltage of the second output terminal Vout− is Vout−.

  When the latch signal Latch = Lo, the latched comparator 1 performs a reset operation. Since the transistor Q0 is OFF and the transistors Q7 and Q8 are ON, the output terminals (Vout +, Vout−) and the input terminals of the first CMOS inverter and the second CMOS inverter are in the Hi state. The latch circuit is reset. At this time, transistors Q1-Q6 and QN3 are all turned off.

  Next, at the timing when the latch signal Latch rises from Lo to Hi, the transistors Q7 and Q8 are turned off and the reset of the latch circuit is released. At the same time, the transistor Q0 is turned on, so that the operations of the transistors Q1 to Q6 become effective. Here, since Vin +> Vin−, the transistor Q1 is turned on before the transistor Q2. Accordingly, the drain potential of the transistor Q1 is lowered before the drain potential of the transistor Q2, so that the transistor Q3 is turned on before the transistor Q4. As a result, the drain potential (output voltage Vout−) of the transistor Q3 is lowered before the drain potential (output voltage Vout +) of the transistor Q4, so that the transistor Q6 is turned on before the transistor Q5.

  The latch circuit constitutes a positive feedback so that the output of the first CMOS inverter becomes the input of the second CMOS inverter and the output of the second CMOS inverter becomes the input of the first CMOS inverter. Accordingly, the transistors Q3 and Q6 are finally turned on and the transistors Q4 and Q5 are turned off, so that the output voltage Vout + sticks to Hi and the output voltage Vout− sticks to Lo. The latch determination time t, which is the time from when the latch signal Latch rises to when the output voltages Vout + and Vout− are determined, is as short as about 10 nsec. Thus, the operation of the latched comparator 1 is very fast. The latched comparator 1 has low power consumption because a current flows through the transistor Q0 only during the latch determination time t.

  The latched comparator 1 maintains the latch operation while the latch signal Latch is Hi, that is, holds the latch output. When the latch signal Latch falls to Lo, the reset operation is started.

  As shown in FIG. 2, in the latch operation period in which the latch signal Latch is Hi, the input voltage Vin + is lower than the input voltage Vin− (Vin−> Vin +> Vt), and the input voltage Vin + is lower than the threshold voltage Vt. If (Vin−> Vt> Vin +), the latched comparator 1 performs the following operation.

  When the input voltage Vin + falls below the input voltage Vin−, the output voltage Vout + changes to Lo and the output voltage Vout− changes to Hi. When the input voltage Vin + falls below the threshold voltage Vt, the transistor Q1 is turned off. However, since the gate potential of the transistor QN3 is Hi, the transistor QN3 is turned on.

  Accordingly, the source of the transistor Q3 is electrically connected to the power supply VSS via the node N1, the transistor QN3, the node N2, the transistor Q2, and the transistor Q0. As a result, the source potential of the transistor Q3 is determined, and the voltage sharing of the transistors Q1 to Q6 is stably maintained. Therefore, each of the output voltage Vout + and the output voltage Vout− stably holds a value corresponding to Vin + <Vin−. Thereby, malfunction of the latch output can be prevented.

  The transistor QN3 is turned on only when the output voltage Vout− rises to Hi together with the latch determination operation, and is therefore lower than the voltage of the power supply VDD. Therefore, the drain current of transistor QN3 is suppressed to be smaller than the drain current of transistor QN5 by the amount that the overdrive voltage of transistor QN3 is smaller than that of transistor QN5 in FIG. As a result, even if a drain current flows through the transistor QN3, the magnitude of the differential output current expressed by the difference between the current flowing through the first current path and the current flowing through the second current path is not significantly affected. It is possible to suppress a decrease in the value of transconductance gm. As a result, an increase in the latch determination time t and generation of noise can be suppressed. This is also true for the state Vin-> Vin +> Vt.

  Further, since the transistor QN3 is turned on only when the output voltage Vout− rises to Hi together with the latch determination operation, the offset voltage is deteriorated between the transistor Q1 and the transistor Q2 at the initial stage of the latch operation. Current does not flow.

(Configuration of First Modification)
In the above example, the configuration for preventing malfunction when the state changes from Vin +>Vin−> Vt to Vin−> Vt + Vin + through the state Vin−> Vin +> Vt has been described. As shown in FIG. 3, it is also possible to prevent malfunction when the state changes from Vin-> Vin +> Vt to Vin +>Vt> Vin- through the state Vin +>Vin-> Vt.

  The latched comparator 2 in FIG. 3 has a configuration in which the transistor QN3 in the latched comparator 1 in FIG. 1 is replaced with a transistor (eighth MOS transistor) QN4. Transistor QN4 is an N-channel MOS transistor. The source of transistor QN4 is connected to the source of transistor Q3, and the drain of transistor QN4 is connected to the source of transistor Q4. That is, the drain and source of the transistor QN4 are connected between the node N1 and the node N2. The gate of the transistor QN4 is connected to the output of the second CMOS inverter, that is, the first output terminal VOUT +.

  Since the operation of the latched comparator 2 is equivalent to the operation of the latched comparator 1 that is replaced symmetrically with respect to the differential pair, the description thereof is omitted.

(Configuration of Second Modification)
Further, as shown in FIG. 4, prevention of malfunction when the state of Vin +>Vin−> Vt is changed to the state of Vin−>Vt> Vin + through the state of Vin−> Vin +> Vt, and Vin−> It is possible to adopt a configuration that can prevent both malfunctions when the state changes from Vin +> Vt to Vin +>Vt> Vin- through the state Vin +>Vin-> Vt.

  The latched comparator 3 in FIG. 4 has a configuration in which the transistor QN4 in FIG. 3 is added to the latched comparator 1 in FIG. Since the principle of preventing malfunction is obvious from the description of FIGS. 1 and 2, the description is omitted.

(Configuration of third modification)
As shown in FIG. 5, it is also possible to configure a latched comparator 4 in which the channel polarity of each transistor is inverted from that of the latched comparators 1 to 3.

  The latched comparator 4 includes transistors Q0 'to Q8' and transistors QP3 and QP4. The transistors Q0 'to Q8' have a connection relationship when the channel polarities of the transistors Q0 to Q8 of the latched comparators 1 to 3 corresponding to those obtained by removing the dashes from the respective signs are reversed. Nodes N1 and N2 of the latched comparators 1 to 3 are replaced with nodes N1 'and N2' by adding a dash to the reference in the comparator 4. The transistor QP3 has a connection relationship when the transistor QN3 of the latched comparators 1 and 3 is changed to a P-channel type. The transistor QP4 has a connection relationship when the transistor QN4 of the latched comparators 2 and 3 is changed to a P-channel type. It is the same as in the latched comparators 1 to 3 that at least one of the transistor QP3 and the transistor QP4 may be provided.

  The latch signal / Latch is a signal obtained by inverting the logic of Hi and Lo of the latch signal Latch of the latched comparators 1 to 3. The first voltage source corresponds to the power supply VDD, and the second voltage source corresponds to the power supply VSS. The first voltage level corresponds to Hi, and the second voltage level corresponds to Lo.

  The transistor QP3 can prevent malfunction when the state of Vin + <Vin− <Vt is changed to the state of Vin− <Vt <Vin + through the state of Vin− <Vin + <Vt. The transistor QP4 can prevent malfunction when the state of Vin− <Vin + <Vt changes from the state of Vin + <Vin− <Vt to the state of Vin + <Vt <Vin−.

[Second Embodiment]
Another embodiment of the present invention will be described below with reference to FIGS.

(Latched comparator configuration)
FIG. 6 shows a configuration of the latched comparator 5 according to the present embodiment. The latched comparator 5 includes the transistors Q01 and Q02 as the first switch circuit in the latched comparator 1 of FIG. 1 instead of the transistor Q0.

  Transistors Q01 and Q02 are N-channel MOS transistors. The drain and source of the transistor Q01 are connected so as to be inserted between the drain of the transistor Q1 and the source of the transistor Q3. The drain and source of the transistor Q02 are connected so as to be inserted between the drain of the transistor Q2 and the source of the transistor Q4. A latch signal Latch is input to the gates of the transistors Q01 and Q02. The sources of the transistors Q1 and Q2 are connected to the power supply VSS.

  The transistor (first switch element) Q01 is a switch element that is inserted in a path from the power supply VSS to the transistor Q3 via the first current path and performs an opening / closing operation. The transistor (second switch element) Q02 is a switching element that is inserted in a path from the power source VSS to the transistor Q4 via the second current path and performs an opening / closing operation. The positions of the node N1 and the transistor Q01 may be interchanged, and the positions of the node N2 and the transistor Q02 may be interchanged.

  Thus, the first switch circuit that enables the operations of the transistors Q1 to Q6 during the latch operation period is on the path from the first voltage source to the third MOS transistor through the first current path. In addition, if it is provided so as to be opened / closed by being inserted into a path from the first voltage source to the fifth MOS transistor via the second current path, the latch operation is affected. Because there is no, the position does not matter. Therefore, the position where the first switch circuit is provided may be selected as appropriate in accordance with the target circuit configuration for inputting a signal to the differential input pair. For example, in the substrate configuration in which the source of the pair transistor cannot be connected to the substrate, the configuration of this embodiment is useful when the source is always fixed at the GND level.

(Configuration of modification)
In addition, as shown in FIG. 7, it is also possible to configure a latched comparator 6 in which the channel polarity of each transistor is inverted from the latched comparator 5.

  The latched comparator 6 is configured by removing the transistor Q0 'from the latched comparator 4 of FIG. 5 and adding a transistor Q01' and a transistor Q02 '. The transistor Q01 'is obtained by changing the transistor Q01 to a P-channel type, and the transistor Q02' is obtained by changing the transistor Q02 to a P-channel type.

[Third Embodiment]
Another embodiment of the present invention will be described below with reference to FIGS.

(Latched comparator configuration)
FIG. 8 shows a configuration of the latched comparator 7 according to the present embodiment. The latched comparator 7 has a configuration in which a preamplifier (preamplification stage) 10 is added to the latched comparator 1 of FIG.

  The preamplifier 10 includes transistors Q10 to Q15 and constant current sources I1 and I2. Transistors Q10 to Q13 are P-channel MOS transistors, and transistors Q14 and Q15 are N-channel MOS transistors.

  Transistor Q10 and transistor Q11 constitute one differential input pair. An input voltage Vin− is input to the gate of the transistor Q10, and a reference voltage Vref− is input to the gate of the transistor Q11. The constant current source I1 supplies a bias current to the differential input pair composed of the transistors Q10 and Q11.

  Transistor Q12 and transistor Q13 constitute one differential input pair. The reference voltage Vref + is input to the gate of the transistor Q12, and the input voltage Vin + is input to the gate of the transistor Q13. The constant current source I2 supplies a bias current to the differential input pair composed of the transistors Q12 and Q13.

  The drain of the transistor Q10 and the drain of the transistor Q12 are connected at the node P1, and the node P1 is further connected to the gate of the transistor Q1. The drain of the transistor Q11 and the drain of the transistor Q13 are connected at the node P2, and the node P2 is further connected to the gate of the transistor Q2.

  The transistor Q14 is diode-connected between the node P1 and the power supply VSS, and the transistor Q15 is diode-connected between the node P2 and the power supply VSS.

  The latched comparator 7 configured as described above performs differential amplification of the two input signals Vin + and Vin− by the preamplifier 10 to generate a differential output, and inputs it to the differential amplification stage configured by the transistors Q1 and Q2. And Thereby, it can be avoided that the gate input of the transistors Q1 and Q2 when the preamplifier 10 is not provided is disturbed by the kickback phenomenon at the start of the latch operation and noise is mixed into the latch output. At the start of the latch operation, a current that changes sharply in the first current path and the second current path flows depending on the timing of the latch signal Latch. Therefore, the gate having a large input impedance is connected via the gate-drain parasitic capacitance of the transistors Q1 and Q2. When noise is generated on the input side, the noise is amplified.

  In the latched comparator 7, the preamplifier 10 is provided. Therefore, even if the kickback phenomenon occurs, noise is absorbed by the large output current capacity accompanied by a gradual time change of the preamplifier 10. Therefore, noise can be prevented from being amplified by the latched comparator 7.

(Configuration of modification)
Further, as shown in FIG. 9, it is also possible to configure a latched comparator 8 in which the channel polarity of each transistor is inverted from the latched comparator 7.

  The latched comparator 8 has a configuration in which a preamplifier 10 'is added to the latched comparator 6 of FIG. The preamplifier 10 'includes transistors Q10' to Q15 'and constant current sources I1 and I2. The transistors Q10 'to Q15' have a connection relationship when the channel polarities of the transistors Q10 to Q15 included in the preamplifier 10 of the latched comparator 7 corresponding to those obtained by removing the dashes from the respective symbols are reversed. Nodes P1 and P2 of the latched comparator 7 are replaced with nodes P1 'and P2' by adding a dash to the reference in the latched comparator 8.

  The present invention can be effectively applied to various circuits including a sense amplifier of a memory circuit, a logic buffer of a logic circuit, an A / D conversion circuit that performs successive approximation of an analog / digital mixed circuit, and the like.

1-8 Latched comparator 10, 10 'Preamplifier (Preamplification stage)
Q0, Q0 'transistors (first switch circuit)
Q1, Q1 'transistors (first MOS transistors)
Q2, Q2 'transistors (second MOS transistors)
Q3, Q3 'transistor (third MOS transistor)
Q4, Q4 'transistors (fifth MOS transistors)
Q5, Q5 'transistor (fourth MOS transistor)
Q6, Q6 'transistor (sixth MOS transistor)
Q7, Q7 'transistors (second switch circuit)
Q8, Q8 'transistors (third switch circuit)
QN3, QP3 transistor (seventh MOS transistor)
QN4, QP4 transistor (eighth MOS transistor)
Q01, Q01 'transistor (first switch element)
Q02, Q02 'transistors (second switch elements)
VSS power supply (first voltage source in FIGS. 1, 3, 4, 6, 8 and second voltage source in FIGS. 5, 7, and 9)
VDD power supply (second voltage source in FIGS. 1, 3, 4, 6, and 8, first voltage source in FIGS. 5, 7, and 9)
N1, N1 'nodes (first node)
N2, N2 'node (second node)

Claims (5)

A differential amplifier stage having a first MOS transistor and a second MOS transistor constituting a differential input pair, a first CMOS inverter and a second CMOS inverter, and an output of the first CMOS inverter; Is connected to the input of the second CMOS inverter and the output of the second CMOS inverter is connected to the input of the first CMOS inverter, and the output of the differential amplifier stage Is a latched comparator that latches at the latch stage,
The first CMOS inverter includes a third MOS transistor that outputs a first voltage level composed of either one of a high level and a low level, and a second composed of the other of the high level and the low level And the second MOS inverter outputs the second voltage level and the fifth MOS transistor that outputs the first voltage level. And a sixth MOS transistor that
A first current path through which the current of the first MOS transistor flows in the differential amplification stage is connected to the output of the first CMOS inverter via the third MOS transistor, and the differential A second current path through which the current of the second MOS transistor flows in the amplification stage is connected to the output of the second CMOS inverter via the fifth MOS transistor;
The first voltage level, which is the output of the first CMOS inverter, is supplied to the third CMOS transistor through the first current path, and the second CMOS transistor is supplied with the second voltage level. A first voltage source for supplying the first voltage level as an output of the CMOS inverter via the second current path;
The second voltage level, which is the output of the first CMOS inverter, is supplied to the fourth MOS transistor, and the second level, which is the output of the second CMOS inverter, is supplied to the sixth MOS transistor. A second voltage source that provides a voltage level of:
A path from the first voltage source to the third MOS transistor via the first current path, and a fifth path from the first voltage source via the second current path. A first switch circuit inserted in a path leading to the MOS transistor and performing an opening / closing operation,
Between the drain and the source is a first node between the first MOS transistor and the third MOS transistor on the first current path, and the second MOS on the second current path. A seventh MOS transistor connected between a transistor and a second node between the fifth MOS transistor and having a gate connected to the output of the first CMOS inverter;
At least an eighth MOS transistor having a drain-source connected between the first node and the second node and a gate connected to the output of the second CMOS inverter; A latched comparator characterized by further comprising one.   The first switch circuit is provided so as to conduct and block a path between the first MOS transistor, the second MOS transistor, and the first voltage source. The latched comparator according to Item 1.   The first switch circuit includes a first switch element for conducting and blocking a path between the first MOS transistor and the third MOS transistor, the second MOS transistor, and the fifth MOS. The latched comparator according to claim 1, further comprising a second switch element that conducts and cuts off a path to and from the transistor.   4. A preamplifier stage which performs differential amplification of two input signals to generate a differential output and which is used as an input to the differential amplifier stage is provided. The latched comparator according to item 1. A second switch circuit for conducting and blocking between the output of the first CMOS inverter and the second voltage source;
5. A third switch circuit that conducts and cuts off between the output of the second CMOS inverter and the second voltage source. 5. The latched comparator described in the section.

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