JP2004214997A - Flip-flop - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip-flop capable of reducing power consumption and realizing a high-speed operation without depending on a circuit design method. <P>SOLUTION: The flip-flop is provided with a first stage latch 11 for fetching the inputted data when clock signals CK are at a high level and a second stage latch 12 for latching the latch data of the first stage latch. The first stage latch 11 is provided with a presetting part 112 capable of charging electric charges to a first output node H111 and a second output node H112 when the clock signals CK are at a low level and setting them to the high level. In the case that the level of inputted data input signals D and inversion signals Db is not changed, even when the clock signals CK are at the low level, the electric charges are not charged to the first output node H111 and the second output node H112. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a flip-flop, and more particularly to an improvement of a flip-flop using a sense amplifier.
[0002]
[Prior art]
Recent LSIs require high-speed operation at the GHz level, low-power operation, or both. In these LSIs, flip-flop circuits are widely used not only for scan mode but also for pipeline control for speeding up.
The flip-flop is one of the important factors that determine the operating frequency and power consumption of the LSI.
[0003]
However, in the high-speed operation, the time consumed by the flip-flop circuit, specifically, the ratio of the setup time and the valid delay to one clock cycle is very large, which is a large factor for speeding up. It is an obstacle. In the low power consumption operation, the flip-flop circuit operates with a clock signal (synchronous signal) such as a system clock, and the power consumption of the clock signal system is very large relative to the power consumption of the entire LSI. It is an obstacle to consumption.
[0004]
Therefore, various techniques for increasing the speed of the flip-flop and reducing the power consumption have been proposed until now.
As this high-speed operation flip-flop, a D-type flip-flop recently announced is “Sense Amplifier-Based Flip-flop” (for example, Non-Patent Document 1).
Hereinafter, this D-type flip-flop is referred to as a “sense amplifier type D-type flip-flop (SAFF)”.
[0005]
In this sense amplifier type D flip-flop, a differential sense amplifier applying an inverter loop is mounted on a first stage latch (master side latch), and an RS latch is mounted on a second stage latch (slave side latch). By combining these, a D-type flip-flop is realized.
[0006]
FIG. 42 is a circuit diagram showing a configuration example of a conventional sense amplifier type D flip-flop.
As shown in FIG. 42, the sense-amplifier D-type flip-flop 1 includes a first-stage latch (master-side latch) 2 and a second-stage latch (slave-side latch) 3 connected in cascade.
[0007]
The first stage latch 2 has p-channel MOS (PMOS) transistors PT21 to PT24 and n-channel MOS (NMOS) transistors NT21 to NT26.
[0008]
The sources of the PMOS transistors PT21 to PT24 have the power supply voltage V_DDConnected to the supply line.
The drains of the PMOS transistors PT21 and PT22 are connected to the drain of the NMOS transistor NT21, and the connection point forms an output node H1. The output node H1 is connected to the gate of the PMOS transistor PT23 and the gate of the NMOS transistor NT22.
The drains of the PMOS transistors PT23 and PT24 are connected to the drain of the NMOS transistor NT22, and the connection point constitutes an output node H2. The output node H2 is connected to the gate of the PMOS transistor PT22 and the gate of the NMOS transistor NT21.
The gates of the PMOS transistors PT21 and PT24 are connected to an input line of a clock signal (synchronization signal) CK.
[0009]
The source of the NMOS transistor NT21 is connected to the drain of the NMOS transistor NT23, and the connection point forms the intermediate node F1. The source of the NMOS transistor NT22 is connected to the drain of the NMOS transistor NT24, and the connection point forms an intermediate node F2.
The sources of the NMOS transistor NT23 and the NMOS transistor NT24 are connected to each other, and the connection point forms an intermediate node G1. This intermediate node G1 is connected to the drain of the NMOS transistor NT25, and the source of the NMOS transistor NT25 is connected to the ground potential GND.
The source and the drain of the NMOS transistor NT26 are connected to the nodes F1 and F2, respectively.
The gate of the NMOS transistor NT23 is connected to the supply line of the data input signal D, and the gate of the NMOS transistor NT24 is connected to the supply line of the inverted signal Db of the data input signal D. The gate of the NMOS transistor NT25 is connected to the supply line of the clock signal CK, and the gate of the NMOS transistor NT26 is connected to the power supply voltage V._DDConnected to the supply line.
[0010]
The second-stage latch 3 includes two-input NAND gates NA31 and NA32.
The first input terminal of the NAND gate NA31 is connected to the output node H1 of the first-stage latch 2, and the second input terminal is connected to the output terminal of the NAND gate NA32.
The first input terminal of the NAND gate NA32 is connected to the node H2 of the first stage latch 2, and the second input terminal is connected to the output terminal of the NAMD gate NA31.
Then, the second-stage latch 3 outputs data Q from the NAND gate NA31, and outputs inverted data Qb from the NAND gate NA32.
[0011]
Next, the operation of the conventional sense amplifier type D flip-flop 1 will be described with reference to the timing chart of FIG.
[0012]
The flip-flop 1 captures the value of the data input signal D in synchronization with the rising edge of the clock signal CK, and outputs data Q and inverted data Qb. The value is held for one cycle of the clock signal CK.
[0013]
During a period when the clock signal CK is at a low level (logic 0 level), the PMOS transistors PT21 and PT24 are turned on, and the NMOS transistor NT25 is cut off.
[0014]
During the period when the clock signal CK is at the low level, the PMOS transistors PT21 and PT24 behave equivalently as resistors, and through these, the nodes H1 and H2 are connected as shown in FIGS. 43 (A), (C) and (E). It is precharged to a complete logic 1 potential (high level).
Then, the PMOS transistors PT22 and PT23 are cut off. Since the gate terminals and the drain terminals of the NMOS transistors NT21 and NT22 have the same potential, they behave equivalently as diodes.
Therefore, when the power supply voltage is V_DD[V] Assuming that the threshold value of the NMOS transistor is Vtn, the potentials of the nodes F1 and F2 at this time are (V) as shown in FIGS. 43 (D) and (F)._DD−Vtn) [V]. That is, charges flow from the output nodes H1 and H2 to the intermediate nodes F1 and F2.
[0015]
As described above, when the clock signal CK is at the low level, the output nodes H1 and H2 of the first-stage latch 2 are both at the high level of logic 1, which holds the NAND-RS latch of the second-stage latch 3. Operate as mode.
[0016]
When the clock signal CK goes high, the PMOS transistors PT21 and PT24 are cut off, the NMOS transistor NT25 is turned on, and the sense amplifier operates.
Depending on the state of the data input signal D and its inverted signal Dd, one of the NMOS transistors NT23 and NT24 is cut off.
Therefore, a difference occurs between the conduction resistances of the intermediate nodes F1 and F2 with respect to the ground.
[0017]
For example, assuming that the NMOS transistor NT24 is cut off, the conduction resistance of the intermediate node F1 with respect to the ground is the sum of the resistance values of the NMOS transistor NT23 and the NMOS transistor NT25. Is the sum of the resistance values of the NMOS transistors NT26, NT23, and NT25.
Such a difference in the conduction resistance appears in the discharge speed of the charges on the output nodes H1 and H2. In the above example, since the conduction resistance of the node F1 with respect to the ground is smaller, the charge of the node H1 is discharged more quickly. At this time, the charge on the node H2 is also discharged.
However, when the potential of the output node H1 falls, the PMOS transistor PT23 turns on and the NMOS transistor NT22 cuts off, and the potential of the falling node H2 rises to obtain a complete logic 1 potential again.
[0018]
In this way, a steady state is established in the inverter loop composed of the PMOS transistors PT22 and PT23 and the NMOS transistors NT21 and NT22.
Thereafter, even if the data input signal D and its inverted signal Dd change and the transistor to be cut off changes from the NMOS transistor NT24 to the NMOS transistor NT23, this steady state is not broken.
This is because one of the NMOS transistors NT23 and NT24 is always on, and both of the intermediate nodes F1 and F2 always have a path to ground through the NMOS transistor NT26. This is because it is connected to the ground.
[0019]
Thus, as shown in FIGS. 43 (A), (C) and (E), one of the output nodes H and H2 of the first-stage latch 2 becomes logic 0 during the period when the clock signal is at the high level. Become.
In response, the RS latch of the second stage latch 3 is set or reset, and a value corresponding to the input data appears on the outputs Q and Qd.
[0020]
[Non-patent document 1]
J. See Montanaro, et al. , "A 160MHz 32b 0.5W CMOS Rlsc Microprocessor," ISSCC Digest of Technical Papers, pp. 146-64. 214-215, Feb. , 1996.
[0021]
[Problems to be solved by the invention]
However, the above-described sense-amplifier D-type flip-flop 1 can make the most of its advantage in a circuit configuration of complementary input and complementary output such as a data path circuit, but is not suitable for a random logic circuit such as an ASIC.
When all circuit methods are considered, the above-described sense amplifier type D flip-flop 1 has the following problems.
[0022]
First, if only one of the data input signal D and its inverted signal Db is input, the sense amplifier D-type flip-flop 1 has an advantage that the setup time, which is the largest factor capable of high-speed operation, is short. Is impaired.
[0023]
Next, in FIG. 42, the outputs Q and Qb are connected to the inputs of the respective NAND gates NA31 and NA32. However, when the output signal wiring is affected by crosstalk or the like, the value changes and is held as it is. There is a risk of being done.
In order to solve this, it is conceivable to provide inverters INV31 and INV32 on the output side of NAND gates NA31 and NA32, as shown in FIG. 44. However, simply providing an inverter increases the valid delay.
[0024]
Finally, charging and discharging of electric charges at each node of the first-stage latch 2 are described. At each of nodes H1, H2, F1, F2, and G1 in FIG. 42, charge of each clock is performed regardless of a change in the logic level of data input signal D and its inverted signal Db.
For example, when the data input signal D is at a high level, the charges at the nodes H1, F1, F2, and G1 are discharged, and when the inverted signal Fb is at a high level, the nodes at H2, F1, F2, and G1 are discharged. The charge is discharged.
The charge time of the charge determines the setup time, the discharge time determines the valid delay, and is one of the factors that increase the power consumption due to the clock signal.
For the above reasons, the sense amplifier type D-type flip-flop 1 described above loses the advantage of high-speed operation depending on the circuit design method.
[0025]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a flip-flop capable of reducing power consumption and realizing high-speed operation without depending on a circuit design technique.
[0026]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention relates to a first-stage latch for capturing data input when a synchronization signal having first and second potential levels is at a second potential level. , A second-stage latch for latching latch data of the first-stage latch, wherein the first-stage latch includes a first output node, a second output node, and a first intermediate node. A first intermediate node, a second intermediate node, a third intermediate node, and a second intermediate node that charges the first output node and the second output node when the synchronization signal is at the first potential level to charge the second intermediate node. A pre-setting means that can be set to a potential level of the second potential node, and the second output node conducts when the second output node is at the first potential level to connect the first output node to a second potential source; The first switch, which is held in a non-conductive state when the Switching means for conducting when the first output node is at a first potential level and connecting the second output node to a second potential source, and turning off when the second output node is at a second potential level The second switching means being held is connected between the first output node and the first intermediate node, and is kept in a non-conductive state when the second output node is at a first potential level. A third switching means that is turned on when at a second potential level, and is connected between the second output node and the second intermediate node, and the first output node is connected to the first potential node. A fourth switching means which is kept in a non-conducting state at the time of the second potential level and which conducts at the time of the second potential level, and is connected between the first intermediate node and the third intermediate node; Non-conductive when signal is at first potential level Connected between the second intermediate node and the third intermediate node, the fifth switching means being turned on at the second potential level, and being connected to the second intermediate node and the third intermediate node. The sixth switching means, which is held in a non-conductive state when the potential level is at a non-conductive level and is conductive at a second potential level, is connected between the third intermediate node and a reference potential. A seventh switching unit that is kept in a non-conductive state at the first potential level and is conductive at the second potential level, and includes a resistance component, and includes the first intermediate node and the second intermediate node; Connecting means for connecting the data input signal and the inverted signal to be input when the level of the input signal does not change, even when the synchronization signal is at the first potential level. The first output node And the second output node is not charged.
[0027]
Preferably, the second-stage latch holds, at a first node and a second node, non-inverted data and inverted data that take the first potential level and the second potential level complementarily, The pre-setting means includes: an eighth and a ninth switching element which are turned on when the synchronization signal is at the first potential level and are kept in a non-conductive state when the synchronization signal is at the second potential level; And the tenth and eleventh switching elements, which are turned on when are at the first potential level and are kept off when at the second potential level, and the inverted signal of the data input signal is at the first potential level. And the twelfth and thirteenth switching elements, which are turned on when the signal is at the first potential level and are kept in the non-conductive state when at the second potential level, and the first node of the second stage latch is at the first potential level. When conducting, the above And the fifteenth and fifteenth switching elements, which are held in a non-conductive state at the potential level of the second stage latch, conduct when the second node of the second-stage latch is at the first potential level. The sixteenth and seventeenth switching elements, which are held in a non-conductive state when at the level, conduct when the data input signal is at the second potential level, and become non-conductive when at the first potential level; An eighteenth switching element which is held and a nineteenth switching element which is turned on when the inverted signal of the data input signal is at the second potential level and is turned off when the inverted signal is at the first potential level A twentieth switching element that is conductive when the first node of the second-stage latch is at the second potential level and is kept in a non-conductive state when the first node is at the first potential level; Step latch A twenty-first switching element that conducts when the second node is at the second potential level and is kept off when the second node is at the first potential level. The eighth switching element is connected, the tenth and sixteenth switching elements are connected in series between the eighth switching element and the second potential source, and the twelfth and fourteenth switching elements are connected. An element is connected between the eighth switching element and the second potential source in parallel with the tenth and sixteenth switching elements, and is connected between the first output node and a reference potential. The eighteenth and twentieth switching elements are connected in series, the ninth switching element is connected to the second output node, and a connection between the ninth switching element and the second potential source The thirteenth and fifteenth switching elements are connected in series, and the eleventh and seventeenth switching elements are connected between the ninth switching element and the second potential source. The switching elements are connected in parallel, and the nineteenth and twenty-first switching elements are connected in series between the second output node and a reference potential.
[0028]
According to a second aspect of the present invention, there is provided a first-stage latch for capturing data input when a synchronization signal having first and second potential levels is at a second potential level; A flip-flop including a second-stage latch for latching latch data, wherein the first-stage latch includes a first output node, a second output node, and a first output node and a reference potential between the first output node and a reference potential. First and second intermediate nodes formed in order on the first signal path toward the reference potential, and on the second signal path between the second output node and the reference potential toward the reference potential Third and fourth intermediate nodes formed in order, and pre-setting means for setting the first output node and the second output node to a second potential level when the synchronization signal is at the first potential level And the second output node is A first switching means which is conductive when the potential level is 1 and connects the first output node to a second potential source, and which is kept in a non-conductive state when the potential level is the second potential level; A second output node is connected to a second potential source when one output node is at a first potential level, and the second output node is kept non-conductive at a second potential level; Switching means; third and fourth switching means which are kept non-conductive when the synchronization signal is at the first potential level and which are conductive when the synchronization signal is at the second potential level; Fifth switching means which is held in a non-conductive state when the potential level is attained and is conductive when at the second potential level, and is kept in a non-conductive state when the inverted signal of the data input signal is at the first potential level At the second potential level Sixth switching means that passes through, a seventh switching means that is kept in a non-conductive state when the first output node is at a first potential level, and is conductive when it is at a second potential level, An eighth switching means which is kept non-conductive when the second output node is at the first potential level and is conductive when the output node is at the second potential level. 7 is connected in series with the first signal path, and at least the third switching means is connected between the first output node and the first intermediate node or the first intermediate node. Connected between a node and the second intermediate node, the fourth, sixth, and eighth switching means are connected in series with the second signal path, and at least the fourth switching means is , The second Connected between an output node and the third intermediate node or between the third intermediate node and the fourth intermediate node, the pre-setting means is configured to receive the data input signal and the inverted signal Does not change, the first output node and the second output node are not charged even if the synchronization signal is at the first potential level.
[0029]
In the present invention, the third switching means is connected between the first output node and the first intermediate node, and the fifth switching means is connected to the first intermediate node and the second intermediate node. The seventh switching means is connected between the second intermediate node and the reference potential, and the fourth switching means is connected between the second output node and the third intermediate node. The sixth switching means is connected between the third intermediate node and the fourth intermediate node, and the eighth switching means is connected between the fourth intermediate node and the reference node. And the first stage latch is further connected when the second output node is at a second potential level to connect the first intermediate node to the reference potential. At the potential level of 1. A ninth switching means which is kept in a conductive state, and which conducts when the first output node is at a second potential level to connect the third intermediate node to the reference potential; And a tenth switching unit that is kept in a non-conducting state at the time of (i).
[0030]
In the present invention, the third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected to the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential, and the fourth switching means is connected between the second output node and the third output node. , The eighth switching means is connected between the third intermediate node and the fourth intermediate node, and the sixth switching means is connected to the fourth intermediate node. Connected to the reference potential, the first-stage latch further conducts when the second output node is at a second potential level, and connects the second intermediate node to the reference potential. At the first potential level Ninth switching means, which is kept in a non-conducting state when the first output node is at a second potential level and is connected to connect the fourth intermediate node to the reference potential. And a tenth switching means which is kept in a non-conductive state at the potential level of
[0031]
In the present invention, the third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected to the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential, and the fourth switching means is connected between the second output node and the third output node. , The eighth switching means is connected between the third intermediate node and the fourth intermediate node, and the sixth switching means is connected to the fourth intermediate node. Connected to the reference potential, the first-stage latch further conducts when the second output node is at a second potential level and connects the first intermediate node to the reference potential. At the first potential level Ninth switching means, which is kept in a non-conducting state when the first output node is at a second potential level, and conducts to connect the third intermediate node to the reference potential. And a tenth switching means which is kept in a non-conductive state at the potential level of
[0032]
In the present invention, the third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected to the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential, and the fourth switching means is connected between the second output node and the third output node. , The eighth switching means is connected between the third intermediate node and the fourth intermediate node, and the sixth switching means is connected to the fourth intermediate node. Connected to the reference potential, the first-stage latch further conducts when the second output node is at a second potential level, and the second intermediate node and the fourth intermediate node And the first A ninth switching means which is kept in a non-conducting state when the signal is at a level, and which conducts when the first output node is at a second potential level, and is connected to the second intermediate node and the fourth intermediate node. And a tenth switching means that is kept in a non-conductive state at the first potential level.
[0033]
In the present invention, the third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected to the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential, and the fourth switching means is connected between the second output node and the third output node. , The eighth switching means is connected between the third intermediate node and the fourth intermediate node, and the sixth switching means is connected to the fourth intermediate node. The first-stage latch is connected between the reference potential and the first-stage latch, and further includes a connection unit that includes a resistance component and connects the second intermediate node and the fourth intermediate node.
[0034]
In the present invention, the fifth switching means is connected between the first output node and the first intermediate node, and the third switching means is connected to the first intermediate node and the second intermediate node. The seventh switching means is connected between the second intermediate node and the reference potential, and the sixth switching means is connected between the second output node and the third output node. , The fourth switching means is connected between the third intermediate node and the fourth intermediate node, and the eighth switching means is connected to the fourth intermediate node. Connected to the reference potential, the first-stage latch further conducts when the second output node is at a second potential level, and is connected to the first output node and the first intermediate node. And the first Ninth switching means which is kept in a non-conducting state when the signal is at a level, and which conducts when the first output node is at a second potential level and which is connected to the second output node and the third intermediate node. And a tenth switching means that is kept in a non-conductive state at the first potential level.
[0035]
In the present invention, the fifth switching means is connected between the first output node and the first intermediate node, and the third switching means is connected to the first intermediate node and the second intermediate node. The seventh switching means is connected between the second intermediate node and the reference potential, and the sixth switching means is connected between the second output node and the third output node. , The fourth switching means is connected between the third intermediate node and the fourth intermediate node, and the eighth switching means is connected to the fourth intermediate node. The first-stage latch is connected between the reference potential and the first-stage latch, and further includes a connection unit that includes a resistance component and connects the second intermediate node and the fourth intermediate node.
[0036]
Preferably, the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process.
[0037]
Preferably, when the output signal level of the first-stage latch changes and a signal opposite to the second-stage latch is held, the second-stage latch simultaneously changes the output signal of the first-stage latch. And a circuit for invalidating the reciprocal signal held in the second-stage latch and transmitting it to the final output signal.
[0038]
According to the present invention, for example, while the synchronization signal is at the first potential level, the third and fourth switching means are turned off.
When there is a change in the level of the input data signal, in other words, the level of the first node of the second-stage latch and the level of the data input signal, and the level of the second node of the second-stage latch and the data input When the level of the inverted signal of the signal is different, the pre-setting means charges the first and second output nodes during the period in which the synchronization signal is at the first potential level, and charges the first and second output nodes. Are precharged to a second potential level of logic one.
At this time, since the third and fourth switching means are in a non-conductive state, no charge is charged in the first intermediate and the third intermediate.
On the other hand, the switching elements other than the first and second switching elements are the switching elements. The first output node and the second output node become conductive when precharged to a high level.
As a result, regardless of the state of the data input signal and the inverted signal, the first and second intermediate nodes are discharged to the first potential level through the corresponding switching elements.
Therefore, while the synchronization signal is at the first potential level, the charge is performed only on the first output node and the second output node.
Next, when the synchronizing signal goes high, the precharging by the pre-setting means is stopped, and the third and fourth switching means are turned on.
Here, for example, when the data input signal D is supplied to the fifth switching element at the second potential level and the inverted signal Db is supplied to the sixth switching element at the first potential level, the fifth switching element becomes Conduct. At this time, the sixth switching element remains off.
As a result, the first signal path is electrically connected from the first output node to the ground potential GND. Therefore, the charge charged in the first output node is discharged through each switching element. As a result, the first output node goes to the first potential level, and data of a predetermined level is output from the second stage latch.
[0039]
When there is no change in the level of the input data signal, in other words, the level of the first node of the second stage latch and the level of the data input signal, and the level of the second node of the second latch and the data input When the level of the inverted signal is the same, the charge is not performed on the first and second output nodes by the pre-setting unit even during the period when the synchronization signal is at the first potential level.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
First embodiment
FIG. 1 is a circuit diagram showing a first embodiment of a sense amplifier type D flip-flop according to the present invention.
[0041]
As shown in FIG. 1, the sense amplifier D-type flip-flop 10 includes a first-stage latch 11 and a second-stage latch 12, which are cascaded.
In the following description, the first potential is a ground potential (0 V) level, and the second potential is a power supply voltage V_DDLevel.
[0042]
The first-stage latch 11 includes PMOS transistors PT111 to PT122, NMOS transistors NT111 to NT120, a first output node H111, a second output node H112, a first intermediate node F111, a second intermediate node F112, and a third Intermediate node G111.
In this case, a first switching element is formed by the PMOS transistor PT112, a second switching element is formed by the PMOS transistor PT113, a third switching element is formed by the NMOS transistor NT111, and a fourth switching element is formed by the NMOS transistor NT112. An element is configured, a fifth switching unit is configured by the NMOS transistor NT113, a sixth switching unit is configured by the NMOS transistor NT114, and a seventh switching unit is configured by the NMOS transistor NT115. The connection means is constituted by the NMOS transistor NT116.
[0043]
The latch unit 111 includes the PMOS transistors PT112 and PT113 and the NMOS transistors NT111 to NT116.
The pre-setting unit 112 is configured by the PMOS transistors PT111 and PT114 to PT122 and the NMOS transistors NT117 to NT120.
The PMOS transistor PT111 forms an eighth switching element, the PMOS transistor PT114 forms a ninth switching element, the PMOS transistor PT115 forms a sixteenth switching element, and the PMOS transistor PT116 forms a fifteenth switching element. The PMOS transistor PT117 forms a tenth switching element, the PMOS transistor PT118 forms a thirteenth switching element, the PMOS transistor PT119 forms a fourteenth switching element, and the PMOS transistor PT120 forms a seventeenth switching element. A twelfth switching element is constituted by a PMOS transistor PT121, and a PMOS transistor PT121 is constituted by a PMOS transistor PT121. The star PT122 forms an eleventh switching element, the NMOS transistor NT117 forms an eighteenth switching element, the NMOS transistor NT118 forms a nineteenth switching element, and the NMOS transistor NT119 forms a twentieth switching element. And the NMOS transistor NT120 constitute a twenty-first switching element.
[0044]
The sources of the PMOS transistors PT112, PT113, PT117, PT118, PT121, and PT122 are connected to the power supply voltage V._DDConnected to the supply line.
The drains of the PMOS transistors PT111 and PT112 are connected to the drains of the NMOS transistor NT111 and the NMOS transistor NT117, and the connection point constitutes a first output node H111. The first output node H111 is connected to the gate of the PMOS transistor PT113 and the gate of the NMOS transistor NT112.
The drains of the PMOS transistors PT113 and PT114 are connected to the drains of the NMOS transistor NT112 and the NMOS transistor NT118, and the connection point constitutes a second output node H112. Further, the second output node H112 is connected to the gate of the PMOS transistor PT112 and the gate of the NMOS transistor NT111.
The gates of the PMOS transistors PT111 and PT114 are connected to the input line for the clock signal CK.
[0045]
In the latch section 111, the source of the NMOS transistor NT111 is connected to the drain of the NMOS transistor NT113, and the connection point forms a first intermediate node F111. The source of the NMOS transistor NT112 is connected to the drain of the NMOS transistor NT114, and the connection point forms a second intermediate node F112.
The sources of the NMOS transistor NT113 and the NMOS transistor NT114 are connected to each other, and the connection point forms a third intermediate node G111. This third intermediate node G111 is connected to the drain of the NMOS transistor NT115, and the source of the NMOS transistor NT115 is connected to the ground potential GND.
The source and the drain of the NMOS transistor NT116 are connected to the first intermediate node F111 and the second intermediate node F112, respectively.
The gate of the NMOS transistor NT113 is connected to the supply line of the data input signal D, and the gate of the NMOS transistor NT114 is connected to the supply line of the inverted signal Db of the data input signal D. The gate of the NMOS transistor NT115 is connected to the supply line of the clock signal CK, and the gate of the NMOS transistor 1T216 is connected to the power supply voltage V_DDConnected to the supply line.
[0046]
In the pre-setting unit 112, the source of the PMOS transistor PT111 is connected to the drains of the PMOS transistors PT115 and PT119. The source of the PMOS transistor PT115 is connected to the drain of the PMOS transistor PT117, and the source of the PMOS transistor PT119 is connected to the drain of the PMOS transistor PT121.
The source of the NMOS transistor NT117 is connected to the source of the NMOS transistor NT119, and the source of the NMOS transistor NT119 is connected to the ground potential GND.
The source of the PMOS transistor PT114 is connected to the drains of the PMOS transistors PT116 and PT120. The source of the PMOS transistor PT116 is connected to the drain of the PMOS transistor PT118, and the source of the PMOS transistor PT120 is connected to the drain of the PMOS transistor PT122.
The source of the NMOS transistor NT118 is connected to the source of the NMOS transistor NT120, and the source of the NMOS transistor NT120 is connected to the ground potential GND.
The gates of the PMOS transistors PT117, PT122 and the NMOS transistor NT117 are connected to a data input signal D supply line. The gates of the PMOS transistors PT118 and PT121 and the NMOS transistor NT118 are connected to the supply line of the inverted signal Db of the data input signal D.
The gates of the PMOS transistors PT115 and PT120 and the NMOS transistor NT120 are connected to an output terminal (node I122: an output line of the inverted data Qb in this embodiment) of the NAND gate NA122 of the second-stage latch 12. The gates of the PMOS transistors PT116 and PT119 and the NMOS transistor NT119 are connected to an output terminal (node I121: an output line of data Q in the present embodiment) of the NAND gate NA121 of the second-stage latch 12.
[0047]
The second-stage latch 12 includes two-input NAND gates NA121 and NA122.
The first input terminal of the NAND gate NA121 is connected to the first output node H111 of the first-stage latch 11, and the second input terminal is connected to the output terminal (node I122) of the NAND gate NA122.
The first input terminal of the NAND gate NA122 is connected to the second node H112 of the first-stage latch 11, and the second input terminal is connected to the output terminal (node I121) of the NAMD gate NA121.
[0048]
Next, the operation of the sense amplifier type D flip-flop 10 of FIG. 1 will be described with reference to the timing chart of FIG. In the following description, the first potential level (ground potential) is set to a low level, and the second potential level (power supply voltage V_DDLevel) High level.
[0049]
The flip-flop 10 captures the value of the data input signal D in synchronization with the rising edge of the clock signal CK, and outputs data Q and inverted data Qb. The value is held for one cycle of the clock signal CK.
[0050]
Here, for example, it is assumed that the output data Q from the second-stage latch 12 is held at a low level and the output inverted data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and the inverted signal Db thereof is supplied at a low level. The overall operation when data Qb are supplied at different levels (level mismatch) will be described.
[0051]
During a period when the clock signal (synchronization signal) CK is at a low level (logic 0 level), the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistor NT115 is cut off.
Further, since the output data Q is held at the low level and the inverted output data Qb is held at the high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115, PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at a high level and the inverted signal Db is supplied at a low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117, PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistors, through which the first output node H111 and the second output node H112 connect to the power supply voltage V._DD2 (A), (C) and (E), and is precharged to a complete logic 1 potential (high level) as shown in FIGS. .
Then, the PMOS transistors PT112 and PT113 are cut off. Since the gate terminals and the drain terminals of the NMOS transistors NT111 and NT112 have the same potential, they behave equivalently as diodes.
Therefore, when the power supply voltage is V_DD[V], assuming that the threshold value of the NMOS transistor is Vthn, the potentials of the first intermediate node F111 and the second intermediate node F112 at this time are as shown in FIGS. 2D and 2F. (V_DD−Vthn) [V].
[0052]
When the clock signal CK goes high, the PMOS transistors PT111 and PT114 are cut off, the NMOS transistor NT115 is turned on, and the latch unit (sense amplifier) 111 operates.
Further, since the data input signal D is at the high level and the inverted signal Dd is at the low level, the NMOS transistor NT113 is turned on and the NMOS transistor NT214 is cut off.
Therefore, a difference occurs between the conduction resistances of the first intermediate node F111 and the second intermediate node F112 with respect to the ground.
[0053]
In this case, since the NMOS transistor NT114 is cut off, the conduction resistance of the first intermediate node F111 with respect to the ground is the sum of the resistance values of the NMOS transistor NT113 and the NMOS transistor NT115, whereas the second intermediate node F111 has the second resistance. Is the sum of the resistance values of the NMOS transistors NT116, NT113, and NT115.
Such a difference in the conduction resistance appears in the discharge speed of the charges on the first output node H111 and the second output node H112. In this case, since the first intermediate node F111 has a smaller conduction resistance with respect to the ground, the charge of the first output node H111 is discharged more quickly as shown in FIG. 2C. At this time, as shown in FIG. 2E, the charge on the second output node H112 is also discharged.
However, the decrease in the potential of the first output node H111 turns on the PMOS transistor PT113 and cuts off the NMOS transistor NT112, and the potential of the falling second output node H112 increases. Get the potential.
[0054]
Thus, a steady state is established in the inverter loop including the PMOS transistors PT112 and PT113 and the NMOS transistors NT111 and NT112.
Thereafter, even if the data input signal D and its inverted signal Dd change and the transistor to be cut off changes from the NMOS transistor NT114 to the NMOS transistor NT113, this steady state is not broken.
This is because one of the NMOS transistors NT113 and NT114 is always on and both the intermediate nodes F111 and F112 have a path to ground through the NMOS transistor NT116. This is because it is connected to the ground.
[0055]
In this manner, as shown in FIGS. 2A, 2C, and 2E, the first output node H111 of the first-stage latch 21 is at the low level and the second output node is at the second level while the clock signal CK is at the high level. Output node H112 attains a high level.
[0056]
Since the data input signal D is at the high level and the inverted signal Db is at the low level, and the first output node H111 is at the low level, as shown in FIG. High-level data Q is output from NAND gate NA111.
Further, the output data Qb of the NAND gate NA112 becomes low level.
[0057]
In the following, it is assumed that the output data Q by the second-stage latch 12 is held at a high level and the output inverted data Qb is held at a low level.
That is, assuming that the first output node H111 is at the low level and the second output data H112 is at the high level, the operation of the pre-setting unit 112 will be mainly described for the first to tenth states.
[0058]
Under this condition, when the clock signal (synchronization signal) CK is at a low level (logic 0 level), the data input signal D is at a high level, and the inversion signal Db is at a low level, each transistor is in the first state. Become like
That is, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistor NT115 is cut off.
Further, since the output data Q is held at the high level and the inverted output data Qb is held at the low level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned off, and the PMOS transistors PT115, PT120 and the NMOS transistor NT119 are turned off. Turns on.
Since the data input signal D is supplied at a high level and the inverted signal Db is supplied at a low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117, PT122 and the NMOS transistor NT118 are kept off. Is done.
[0059]
Therefore, the PMOS transistors PT111 and PT114 are on, but the first output node H111 and the second output node H112 are connected to the power supply voltage V_DDAnd the first output node H111 and the second output node H112 are not charged.
Then, since the NMOS transistors NT117 and NT19 are in the ON state, the first output node H111 is electrically connected to the ground potential GND, the electric charge is discharged, and the low level is maintained.
At this time, the PMOS transistor PT113 of the latch unit 111 is in the on state, the second output node H112 is at the high level, but the PMOS transistor PT114 is on, the PMOS transistor PT116 is off, the PMOS transistor PT118 is on, and the PMOS transistor PT120 is Since the ON state, the PMOS transistor PT122, and the NMOS transistors NT118, NT120 are in the OFF state, the charge is not charged during the low-level period of the clock signal CK, and the low-level drive does not exist. Therefore, the second output node H112 is held at a high level by the PMOS transistor PT113.
In this case, the levels of the output data Q and Qb of the second-stage latch 12 do not change.
[0060]
In the second state in which the clock signal CK has changed to the high level from the first state, the PMOS transistors PT111 and PT114 are turned off and the NMOS transistor NT115 is turned on, but there is no level change at each node.
[0061]
In the third state in which the data input signal D changes to low level and the inverted signal Db changes to high level from the second state, the first output node H111 is at low level in the first and second states, The transistor PT113 is in an on state, the second output node H112 is at a high level, and the NMOS transistor NT111 is in an on state and is complementary and stable.
Then, the path for driving the first output node H111 to a low level is from the NMOS transistor NT111 → the first intermediate node F111 → the NMOS transistor NT112 → the third intermediate node G111 → the NMOS transistor 115 to the NMOS transistor NT111 → first. , The intermediate node F111 → the NMOS transistor NT116 → the second intermediate node F112 → the NMOS transistor NT114 → the third intermediate node G111 → the NMOS transistor 115, but there is no level change at each node.
[0062]
In the fourth state in which the clock signal CK has changed to the low level from the third state, the PMOS transistor PT111 is turned on, the PMOS transistor PT114 is turned on, and the NMOS transistor NT115 is turned off.
At this time, the PMOS transistor PT115 is already on, the PMOS transistor PT117 is on, the PMOS transistor PT120 is on, the PMOS transistor PT122 is on, the NMOS transistor NT117 is off, the NMOS transistor NT119 is on, the NMOS transistor NT118 is on, and the NMOS transistor NT120 is on. Since each state is off, the charge described above occurs during the period when the clock signal CK is at the low level, and both the first output node H111 and the second output node H112 are at the high level.
However, in this case, the levels of the output data Q and Qb of the second-stage latch 12 do not change.
[0063]
In the fifth state in which the clock signal CK has changed to the high level from the fourth state, the PMOS transistor PT111 is turned off, the PMOS transistor PT114 is turned off, the NMOS transistor NT115 is turned on, and the NMOS transistor NT112 → the second intermediate node The second output node H112 is driven to a low level through the path of F112 → NMOS transistor NT114 → third intermediate node G111 → NMOS transistor NT115.
At this time, the first output node H111 is maintained at the high level by the PMOS transistor PT112.
In this case, the level of the output data Q and Qb of the second-stage latch 12 changes to a low level and the data Qb changes to a high level, and is held.
[0064]
The sixth state in which the clock CK has changed to the low level from the fifth state is a state completely opposite to the first state.
In this case, the levels of the output data Q and Qb of the second-stage latch 12 do not change.
[0065]
In the case of the seventh state in which the clock signal CK has changed to the high level from the sixth state, the state is exactly the opposite of the second state, and the PMOS transistor PT111 is turned off, the PMOS transistor PT114 is turned off, and the NMOS Only the transistor NT115 is turned on, and there is no change in each node.
[0066]
The eighth state in which the data input signal D changes to the high level and the inverted signal Db changes to the low level from the seventh state is a state completely opposite to the third state, and corresponds to the sixth and seventh states. In this state, the second output node H112 is at a low level, the PMOS transistor PT112 is in an on state, the first output node H112 is at a high level, and the NMOS transistor NT112 is in an on state and is complementary and stable.
The path for driving the second output node H112 to low level is from the NMOS transistor NT112 → the second intermediate node F112 → the NMOS transistor NT114 → the third intermediate node G111 → the NMOS transistor 115 to the NMOS transistor NT112 → second , The intermediate node F112 → the NMOS transistor NT116 → the first intermediate node F111 → the NMOS transistor NT113 → the third intermediate node G111 → the NMOS transistor 115, but there is no level change at each node.
[0067]
In the ninth state in which the clock signal CK has changed to the low level from the eighth state, the state is exactly the opposite of the fourth state, and the PMOS transistor PT111 is turned on, the PMOS transistor PT114 is turned on, and the NMOS transistor PT114 is turned on. The transistor NT115 is turned off. At this time, the PMOS transistor PT119 is already on, the PMOS transistor PT121 is on, the PMOS transistor PT116 is on, the PMOS transistor PT118 is on, the NMOS transistor NT117 is on, the NMOS transistor NT119 is off, and the NMOS transistor NT118 is on. Is off, and the NMOS transistor NT120 is in the on state, so that the above-described charge occurs, and both the first output node H111 and the second output node H112 are high. The Le.
However, in this case, the levels of the output data Q and Qb of the second-stage latch 12 do not change.
[0068]
In the case of the tenth state in which the clock signal has changed to the high level from the ninth state, the state is exactly the opposite of the fifth state, in which the PMOS transistor PT111 is turned off, the PMOS transistor PT114 is turned off, and the NMOS transistor NT115 is turned on, and the first output node H111 is driven to a low level through the path of NMOS transistor NT111 → first intermediate node F111 → NMOS transistor NT113 → third intermediate node G111 → NMOS transistor NT115.
The second output node H112 is maintained at a high level by the PMOS transistor PT113.
In this case, the level of the output data Q and Qb of the second-stage latch 12 changes to the high level of the data Q and changes to the low level of the data Qb, and is held.
[0069]
Next, the state where the clock signal CK has changed to the low level from the tenth state is nothing but the first state.
[0070]
As described above, according to the first embodiment, when the input data signal does not change (when the levels of the input signal to the first-stage latch and the output signal of the second-stage latch match) ) Does not charge the electric charge in the first stage by the clock signal, so that the power consumption of the clock system can be significantly reduced.
[0071]
Second embodiment
FIG. 3 is a circuit diagram showing a second embodiment of the sense amplifier type D flip-flop according to the present invention.
[0072]
The second embodiment differs from the above-described first embodiment in that inverters INV121-1 and INV122-1 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-1. .
[0073]
Other configurations are the same as those of the above-described first embodiment.
[0074]
According to the second embodiment, there is an advantage that power consumption can be reduced and the influence of crosstalk and the like can be suppressed.
[0075]
Third embodiment
FIG. 4 is a circuit diagram showing a third embodiment of the sense amplifier type D flip-flop according to the present invention.
[0076]
The third embodiment is different from the first embodiment in that the second-stage latch 12-2 transmits a change in the output signal of the first-stage (previous-stage) latch to the final output signal in a short time. Has been established.
[0077]
Specifically, the second-stage latch 12-2 is constituted by four 2-input NAND gates NA121-2 to NA124-2.
A first input terminal of the NAND gate NA121-2 is connected to a first output node H111 of the first-stage latch 11, and a second input terminal is an output terminal of the NAND gate NA122-2 and a first input of the NAND gate NA124-2. These terminals are connected to terminals, and these connection points constitute a node I121-2.
A first input terminal of the NAND gate NA122-2 is connected to the second node H112 of the first-stage latch 11, and a second input terminal is an output terminal of the NAMD gate NA121-2 and a first input terminal of the NAND gate NA123-2. , And these connection points constitute a node I122-2.
The second input terminal of the NAND gate NA123-1 is connected to the second node H112 of the first-stage latch 11, and the second input terminal of the NAND gate NA124-2 is connected to the first node H111 of the first-stage latch 11. Have been.
Then, the second-stage latch 12-2 outputs the data Q from the NAND gate NA124-2 and outputs the inverted data Qb from the NAND gate NA123-2.
[0078]
For example, assuming that the data input signal D is at a high level and the inverted signal Db is at a low level, the first output node H111 goes to a low level, and quickly goes higher than the NAND gate NA124-2 of the second-stage latch 12-2. The level data Q is output.
Further, the output data Qb of the NAND gate NA123-2 goes low via the NAND gate NA121-2.
[0079]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0080]
According to the third embodiment, the second stage latch 12-2 is provided with a circuit for transmitting the output signal change of the preceding first stage latch to the final output signal in a short time. In addition to the effects described above, a high level can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0081]
Fourth embodiment
FIG. 5 is a circuit diagram showing a fourth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0082]
The fourth embodiment differs from the first embodiment in the circuit configuration of the second-stage latch 12-3.
[0083]
Specifically, as shown in FIG. 5, the second-stage latch 12-3 has inverters INV121-3 to INV124-3, a PMOS transistor PT123-3, and an NMOS transistor NT121-3.
[0084]
The source of the PMOS transistor PT123-3 is the power supply voltage V_DD, And the drain is connected to the drain of the NMOS transistor NT121-3, and this connection point constitutes the node J121-3. The source of the NMOS transistor NT121-3 is connected to the ground potential GND.
The input terminal of the inverter INV121-3 is connected to the first output node H111 of the first-stage latch 11, and the output terminal is connected to the gate of the NMOS transistor NT121-3. Here, a connection point between the output terminal of the inverter INV121-3 and the gate of the NMOS transistor NT121-3 is defined as a node / H111.
The node J121-3 is connected to the input terminals of the inverters INV122-3 and INV123-3 and the output terminal of the inverter INV124-3.
The output terminal of the inverter INV123-3 is connected to the input terminal of the inverter INV124-3, and the connection point forms a node J122-3. A latch is formed by the inverters INV123-3 and INV124-3.
Then, the second-stage latch 12-3 outputs the data Q from the output terminal of the inverter INV122-3.
[0085]
In this case, for example, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output node of inverter INV121-3 of second stage latch 12-3. / 111 becomes high level. At this time, the second output node H112 of the first-stage latch 11 is at a high level.
As a result, the NMOS transistor NT121-3 turns on, the PMOS transistor PT123-3 turns off, the node J121-3 becomes low level, and the high-level data Q is output from the inverter INV122-3 immediately.
The data at the node J121-3 is maintained at the low level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-3 and INV124-3.
[0086]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0087]
According to the fourth embodiment, in the second-stage latch 12-3, a circuit for transmitting a change in the output signal of the previous-stage latch to the final output signal in a short time is provided. As a result, a high level can be output more quickly than in a conventional circuit, so that high-speed operation is possible.
[0088]
Fifth embodiment
FIG. 6 is a circuit diagram showing a fifth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0089]
The fifth embodiment is different from the above-described fourth embodiment in that the second-stage latch 12-4 holds the output signal of the first-stage latch 11 at the same time when the opposite signal is held. The circuit configuration is such that the reciprocal signal held in the second-stage latch is invalidated.
Specifically, the inverter INV124-4 constituting the cross latch is constituted by a clocked inverter (Clocked Inverter) connected to the nodes / H111 and H112.
[0090]
In this case, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output node of inverter INV121-3 of second stage latch 12-4. / H111 is at a high level. At this time, the second output node H112 of the first-stage latch 11 is at a high level.
As a result, the NMOS transistor NT123-3 turns on, the PMOS transistor PT123-3 turns off, and the node J121-3 becomes low level.
At this time, the clocked inverter INV124-4 cannot output the high level, and the high-level data Q is output immediately from the inverter INV122-3.
Therefore, high-level data Q is output quickly from inverter INV122-3 without preventing node J121-3 from changing to low level.
Further, the data at the node J121-3 is held at the low level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-3 and INV124-4.
[0091]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0092]
According to the fifth embodiment, in addition to the effect of the fourth embodiment, high-level data can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0093]
Sixth embodiment
FIG. 7 is a circuit diagram showing a sixth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0094]
The sixth embodiment differs from the first embodiment in the configuration of the latch unit 200 of the first-stage latch 11-5.
[0095]
Specifically, the latch unit 200 of the first-stage latch 11-5 according to the seventh embodiment includes PMOS transistors PT212 and PT213, NMOS transistors NT211 to NT218, a first output node H211 and a second output node. H212, a first intermediate node F211, a second intermediate node G211, a third intermediate node F212, and a fourth intermediate node G212.
[0096]
Among these components, the PMOS transistor PT212 forms a first switching element, the PMOS transistor PT213 forms a second switching element, the NMOS transistor NT211 forms a third switching element, and the NMOS transistor NT215 forms a third switching element. A fourth switching element is configured, a fifth switching element is configured by the NMOS transistor NT212, a sixth switching element is configured by the NMOS transistor NT216, and a seventh switching element is configured by the NMOS transistor NT213. An eighth switching element is constituted by NT217, and a ninth switching element is constituted by NMOS transistor NT214. Tenth switching element is constituted by register NT218.
[0097]
The ninth switching element is constituted by the PMOS transistor PT111, the tenth switching element is constituted by the PMOS transistor PT114, the seventeenth switching element is constituted by the PMOS transistor PT115, and the sixteenth switching element is constituted by the PMOS transistor PT116. , An eleventh switching element is constituted by the PMOS transistor PT117, a fourteenth switching element is constituted by the PMOS transistor PT118, a fifteenth switching element is constituted by the PMOS transistor PT119, and an eighteenth switching element is constituted by the PMOS transistor PT120. A switching element is formed, and a thirteenth switching element is formed by the PMOS transistor PT121. A twelfth switching element is constituted by the transistor PT122, a nineteenth switching element is constituted by the NMOS transistor NT117, a twentieth switching element is constituted by the NMOS transistor NT118, and a twenty-first switching element is constituted by the NMOS transistor NT119. , A twenty-second switching element is constituted by the NMOS transistor NT120.
[0098]
In the latch section 200, the sources of the PMOS transistors PT212 and PT213 are connected to the power supply voltage V_DD(Second potential source). The drain of the PMOS transistor PT212 is connected to the drain of the NMOS transistor NT211 and the first output node H111.
Further, the first output node H111 is connected to the gate of the PMOS transistor PT213 and the gates of the NMOS transistors NT217 and NT218.
The drain of the PMOS transistor PT213 is connected to the drain of the NMOS transistor NT215 and the second output node H112. The second output node H112 is connected to the gate of the PMOS transistor PT212 and the gates of the NMOS transistors NT213 and NT214.
The gates of the NMOS transistors NT211 and NT215 are connected to the first potential level (ground level) and the second potential level (power supply voltage V_DDLevel) is connected to an input line of a clock signal (synchronization signal) CK which takes a level.
[0099]
The source of the NMOS transistor NT211 is connected to the drain of the NMOS transistor NT212, and the connection point forms a first intermediate node F211. The source of the NMOS transistor NT212 is connected to the drain of the NMOS transistor NT213, and the connection point forms a second intermediate node G211. The source of the NMOS transistor NT213 is connected to the ground potential (reference potential) GND. The drain of the NMOS transistor NT214 is connected to the first intermediate node F211 and the source is grounded to the ground potential GND.
A first signal path SP211 is formed by the NMOS transistor NT211 reaching the ground potential from the first output node H111, the first intermediate node F211, the NMOS transistor NT212, the second intermediate node G211 and the NMOS transistor NT213. .
The gate of the NMOS transistor NT212 is connected to the supply line for the data input signal D.
[0100]
The source of the NMOS transistor NT215 is connected to the drain of the NMOS transistor NT216, and the connection point forms a third intermediate node F212. The source of the NMOS transistor NT216 is connected to the drain of the NMOS transistor NT217, and the connection point constitutes a fourth intermediate node G212. The source of the NMOS transistor NT217 is connected to the ground potential GND. The drain of the NMOS transistor NT218 is connected to the third intermediate node F212, and the source is grounded to the ground potential GND.
A second signal path SP212 is formed by the NMOS transistor NT215, the third intermediate node F212, the NMOS transistor NT216, the fourth intermediate node G212, and the NMOS transistor NT217 that reach the ground potential from the second output node H112. .
The gate of the NMOS transistor NT216 is connected to the supply line of the inverted signal Db of the data input signal D.
[0101]
Next, the operation of the sense amplifier type D flip-flop 10-5 will be described focusing on the latch unit 200 of the first stage latch 10-5.
[0102]
Here, it is assumed that the output data Q from the second-stage latch 12 is held at a low level, and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the input data D on the non-inverting side and the input data Db on the inverted side are output data Q and output. Description will be made assuming that data Qb is supplied at different levels (levels do not match).
[0103]
The flip-flop 10-5 captures the value of the data input signal D in synchronization with the rising edge of the clock signal CK, and outputs data Q and inverted data Qb. The value is held for one cycle of the clock signal CK.
[0104]
While the clock signal CK is at the low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0105]
Further, since the output data Q is held at the low level and the inverted output data Qb is held at the high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115, PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at a high level and the inverted signal Db is supplied at a low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117, PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistors, through which the first output node H111 and the second output node H112 connect to the power supply voltage V._DDIs electrically connected to the supply line (second potential source), and is precharged to a complete logic 1 potential (high level).
[0106]
Then, the PMOS transistors PT212 and PT213 are cut off.
At this time, since the NMOS transistors NT211 and NT215 are cut off, the first intermediate node F211 and the third intermediate node F212 are not charged.
On the other hand, the NMOS transistors NT213, NT214, NT217, and NT218 are turned on when the first output node H111 and the second output node H112 are precharged to a high level.
As a result, regardless of the states of the data input signal D and the inverted signal Db, the first intermediate node F211 passes through the NMOS transistor NT214, the second intermediate node G211 passes through the NMOS transistor NT213, and the third intermediate node F212 passes through the NMOS transistor NT212. The electric charge of the fourth intermediate node G212 is discharged through the NMOS transistor NT217 through NT218 and becomes low level.
Therefore, during the period when the clock signal CK is at the low level, the charge is performed only on the first output node H111 and the second output node H112.
[0107]
Next, when the clock signal CK goes high, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Therefore, when the power supply voltage is V_DD[V] Assuming that the threshold value of the NMOS transistor is Vthn, the potentials of the first intermediate node F211 and the second intermediate node F212 at this time are (V_DD−Vthn) [V].
Here, when the data input signal D is supplied to the gate of the NMOS transistor NT212 at a high level and the inverted signal Db is supplied to the gate of the NMOS transistor NT216 at a low level, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first signal path SP211 is electrically connected from the first output node H111 to the ground potential GND. Therefore, the electric charge charged in the first output node H111 is discharged through the NMOS transistors NT211 to NT213 and NT214. As a result, the first output node H111 becomes low level, and the high-level data Q is output from the NAND gate NA121 of the second stage latch 12.
[0108]
On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
However, the decrease in the potential of the first output node H111 turns on the PMOS transistor PT213 and cuts off the NMOS transistor NT218, so that the potential of the second output node H112, which has fallen, rises again, and complete logic 1 Obtain the potential and keep the high level.
[0109]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed.
[0110]
That is, when the data input signal D is supplied to the gate of the NMOS transistor NT212 when the data input signal D is at a low level, and the inverted signal Db is supplied to the gate of the NMOS transistor NT216 at the high level, the NMOS transistor NT212 is turned off and the NMOS transistor NT216 is turned on. . At this time, the NMOS transistor NT217 remains on.
As a result, the second signal path SP212 is electrically connected from the second output node H112 to the ground potential GND. Therefore, the electric charge charged in the second output node H112 is discharged through the NMOS transistors NT215 to NT217 and NT218. As a result, the first output node H112 becomes low level, and the high-level data Qb is output from the NAND gate NA122 of the second stage latch 12.
[0111]
On the other hand, the electric charge of the first output node H111 is discharged for a very short time when the second output node H112 changes from the high level to the low level.
However, when the potential of the second output node H112 falls, the PMOS transistor PT212 turns on and the NMOS transistor NT214 cuts off, and the potential of the first output node H111 which has fallen rises, again causing the complete logic 1 to fall. Obtain the potential and keep the high level.
[0112]
The operation of the pre-setting unit 112 is performed in the same manner as in the above-described first embodiment, and a detailed description thereof is omitted here.
[0113]
As described above, when the first output node H111 and the second output node H112 are recharged, the NMOS transistor NT211 connected between the first output node H111 and the first intermediate node F211 and the second transistor H2 Of the NMOS transistor NT215 connected between the output node H112 and the third intermediate node F212 is cut off, so that the charge is performed only on the first output node H111 and the second output node H112. .
As described above, the amount of charge to be charged is smaller than that of the conventional circuit, and the number of transistors that contribute to discharging is larger than that of the conventional circuit.
[0114]
That is, according to the sixth embodiment, the amount of charge charged in the first-stage latch 11 can be reduced and the charging time can be shortened as compared with the conventional sense amplifier type D flip-flop, so that the setup time can be reduced. Can be shortened. Further, since the charge charged in the first-stage latch 11-5 can be quickly discharged, the output signal of the first-stage latch 11-5 can be determined in a short time, and the valid delay can be reduced. Is possible.
As a result, there is an advantage that high-speed operation can be realized without depending on a circuit design technique, and power consumption can be reduced.
[0115]
According to the sixth embodiment, when the input data signal does not change (when the level of the input signal to the first-stage latch and the level of the output signal of the second-stage latch match), Since charge is not charged in the first stage by the clock signal, the power consumption of the clock system can be significantly reduced.
[0116]
Seventh embodiment
FIG. 8 is a circuit diagram showing a seventh embodiment of the sense amplifier type D flip-flop according to the present invention.
[0117]
The seventh embodiment differs from the above-described sixth embodiment in that inverters INV121-6 and INV122-6 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-1. .
[0118]
Other configurations are the same as those of the above-described seventh embodiment.
[0119]
According to the seventh embodiment, the influence of crosstalk and the like can be suppressed.
The setup time can be shortened by the first-stage latch 11-5 in the preceding stage, and the output signal of the first-stage latch 11-5 can be determined in a short time, thereby reducing the valid delay. Therefore, even if the valid delay is lengthened by inserting an inverter, high-speed operation can be realized without depending on the circuit design method as a whole, and the advantage that power consumption can be reduced can be achieved. is there.
[0120]
Eighth embodiment
FIG. 9 is a circuit diagram showing an eighth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0121]
The eighth embodiment is different from the sixth embodiment in that the second-stage latch 12-7 transmits a change in the output signal of the first-stage (previous-stage) latch to the final output signal in a short time. Has been established.
[0122]
Specifically, the second-stage latch 12-7 is constituted by four 2-input NAND gates NA121-7 to NA124-7.
A first input terminal of the NAND gate NA121-7 is connected to the first output node H111 of the first-stage latch 11-5, and a second input terminal is connected to the output terminal of the NAND gate NA122-7 and the NAND gate NA124-7. It is connected to one input terminal, and these connection points constitute a node I121-7.
A first input terminal of the NAND gate NA122-7 is connected to the second node H112 of the first stage latch 11-5, and a second input terminal is an output terminal of the NAMD gate NA121-7 and a first input terminal of the NAND gate NA123-7. They are connected to input terminals, and these connection points constitute a node I122-7.
The second input terminal of the NAND gate NA123-7 is connected to the second node H112 of the first-stage latch 11-5, and the second input terminal of the NAND gate NA124-7 is connected to the first node of the first-stage latch 11-7. It is connected to the node H111.
Then, the second-stage latch 12-7 outputs data Q from the NAND gate NA124-7 and outputs inverted data Qb from the NAND gate NA123-7.
[0123]
For example, assuming that the data input signal D is at a high level and the inverted signal Db is at a low level, the first output node H111 goes to a low level and quickly goes higher than the NAND gate NA124-7 of the second stage latch 12-7. The level data Q is output.
The output data Qb of the NAND gate NA123-7 goes low via the NAND gate NA121-7.
[0124]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0125]
According to the eighth embodiment, the second stage latch 12-7 is provided with a circuit for transmitting a change in the output signal of the preceding first stage latch to the final output signal in a short time. In addition to the effects described above, a high level can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0126]
Ninth embodiment
FIG. 10 is a circuit diagram showing a ninth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0127]
The ninth embodiment differs from the sixth embodiment in the circuit configuration of the second-stage latch 12-8.
[0128]
Specifically, as shown in FIG. 10, the second stage latch 12-8 has inverters INV121-8 to INV124-8, a PMOS transistor PT123-8, and an NMOS transistor NT121-8.
[0129]
The source of the PMOS transistor PT123-8 has the power supply voltage V_DD, And the drain is connected to the drain of the NMOS transistor NT121-8, and this connection point constitutes the node J121-8. The source of the NMOS transistor NT121-8 is connected to the ground potential GND.
The input terminal of the inverter INV121-8 is connected to the first output node H111 of the first-stage latch 11-5, and the output terminal is connected to the gate of the NMOS transistor NT121-8. Here, a connection point between the output terminal of the inverter INV121-8 and the gate of the NMOS transistor NT121-8 is defined as a node / H111.
The node J121-8 is connected to the input terminals of the inverters INV122-8 and INV123-8 and the output terminal of the inverter INV124-8.
The output terminal of the inverter INV123-8 is connected to the input terminal of the inverter INV124-8, and the connection point forms the node J122-8. A latch is formed by the inverters INV123-8 and INV124-8.
Then, the second-stage latch 12-8 outputs the data Q from the output terminal of the inverter INV122-8.
[0130]
In this case, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output node of inverter INV121-8 of second stage latch 12-8. / 111 becomes high level. At this time, the second output node H112 of the first-stage latch 11-5 is at a high level.
As a result, the NMOS transistor NT121-8 turns on, the PMOS transistor PT123-8 turns off, the node J121-8 goes low, and the high-level data Q is output immediately from the inverter INV122-8.
The data at the node J121-8 is maintained at the low level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-8 and INV124-8.
[0131]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0132]
According to the ninth embodiment, since the second stage latch 12-8 is provided with a circuit for transmitting a change in the output signal of the first stage latch to the final output signal in a short time, the effect of the sixth embodiment is obtained. In addition to the above, a high level can be output more quickly than a conventional circuit, so that high-speed operation is possible.
[0133]
Tenth embodiment
FIG. 11 is a circuit diagram showing a sense amplifier D-type flip-flop according to a tenth embodiment of the present invention.
[0134]
The tenth embodiment is different from the above-described ninth embodiment in that the second-stage latch 12-9 outputs a change in the output signal of the first-stage latch 11-9 when an opposite signal is held. At the same time, the circuit configuration is such that the reciprocal signal held in the second-stage latch is invalidated.
Specifically, the inverter INV124-9 constituting the cross latch is constituted by a clocked inverter (Clocked Inverter) connected to the nodes / H111 and H112.
[0135]
In this case, for example, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output node of inverter INV121-8 of second stage latch 12-9. / H111 is at a high level. At this time, the second output node H112 of the first-stage latch 11-5 is at a high level.
As a result, the NMOS transistor NT121-8 turns on, the PMOS transistor PT123-8 turns off, and the node J121-8 becomes low level.
At this time, the clocked inverter INV124-9 cannot output a high level, and the high-level data Q is promptly output from the inverter INV122-8.
Therefore, high-level data Q is output from inverter INV122-8 quickly without preventing node J121-8 from changing to low level.
The data at the node J121-8 is maintained at the low level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-8 and INV124-9.
[0136]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0137]
According to the tenth embodiment, in addition to the effects of the ninth embodiment, high-level data can be output more quickly than a conventional circuit, so that high-speed operation is possible.
[0138]
Eleventh embodiment
FIG. 12 is a circuit diagram showing an eleventh embodiment of the sense amplifier type D flip-flop according to the present invention.
[0139]
The eleventh embodiment differs from the above-described sixth embodiment in the configuration of the latch section of the first-stage latch 11-10.
Specifically, in the latch unit 210 according to the eleventh embodiment, the connection position of the NMOS transistor NT212 as the fifth switching element and the NMOS transistor NT213 as the seventh switching element in the first signal path SP211 And the connection position of the drain of the NMOS transistor NT214 as the ninth switching element, and the connection position of the NMOS transistor NT216 as the sixth switching element and the NMOS transistor NT217 as the eighth switching element in the second signal path SP212. , And the connection position of the drain of the NMOS transistor NT218 as the tenth switching element is changed.
[0140]
Specifically, in the first signal path SP211, the drain of the NMOS transistor NT212 is connected to the second intermediate node G211, the source is connected to the ground potential GND, and the drain of the NMOS transistor NT213 is connected to the first intermediate node F211. And the source is connected to the second intermediate node G211. Further, the drain of the NMOS transistor NT214 is connected to the second intermediate node G211 instead of the first intermediate node F211.
Similarly, in the second signal path SP212, the drain of the NMOS transistor NT216 is connected to the fourth intermediate node G212, the source is connected to the ground potential GND, and the drain of the NMOS transistor NT217 is connected to the third intermediate node F212. Then, the source is connected to the fourth intermediate node G212. Further, the drain of the NMOS transistor NT218 is connected to the fourth intermediate node G212 instead of the third intermediate node F212.
[0141]
Next, the operation of the sense amplifier type D flip-flop 10-10 shown in FIG. 12 will be described.
[0142]
Here, it is assumed that the output data Q from the second-stage latch 12 is held at a low level, and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the input data D on the non-inverting side and the input data Db on the inverted side are output data Q and output. Description will be made assuming that data Qb is supplied at different levels (levels do not match).
[0143]
While the clock signal CK is at the low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0144]
Further, since the output data Q is held at the low level and the inverted output data Qb is held at the high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115, PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at a high level and the inverted signal Db is supplied at a low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117, PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistors, through which the first output node H111 and the second output node H112 connect to the power supply voltage V._DDIs electrically connected to the supply line (second potential source), and is precharged to a complete logic 1 potential (high level).
[0145]
Then, the PMOS transistors PT212 and PT213 are cut off.
At this time, since the NMOS transistors NT211 and NT215 are cut off, the first intermediate node F211 and the third intermediate node F212 are not charged.
On the other hand, the NMOS transistors NT213, NT214, NT217, and NT218 are turned on when the first output node H111 and the second output node H112 are precharged to a high level.
As a result, regardless of the states of the data input signal D and the inverted signal Db, the first intermediate node F211 and the second intermediate node G211 are connected through the NMOS transistors NT213 and NT214 to the third intermediate node F212 and the fourth intermediate node. G212 is discharged to a low level through the NMOS transistors NT217 and NT218.
Therefore, during the period when the clock signal CK is at the low level, the charge is performed only on the first output node H111 and the second output node H112.
[0146]
Next, when the clock signal CK goes high, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Here, when the data input signal D is supplied to the gate of the NMOS transistor NT212 at a high level and the inverted signal Db is supplied to the gate of the NMOS transistor NT216 at a low level, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first output node H111 is electrically connected to the ground potential GND. Therefore, the charge charged in the first output node H111 is discharged through the NMOS transistors NT211, NT213 and NT214. As a result, the first output node H111 becomes low level, and the high-level data Q is output from the NAND gate NA121 of the second stage latch 12.
[0147]
On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
However, the decrease in the potential of the first output node H111 turns on the PMOS transistor PT213, cuts off the NMOS transistors NT217 and NT218, increases the falling potential of the second output node H112, and completes the logic again. 1 is obtained and the high level is maintained.
[0148]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0149]
The operation of the pre-setting unit 112 is performed in the same manner as in the above-described first embodiment, and a detailed description thereof will be omitted here.
[0150]
According to the eleventh embodiment, the same effects as those of the above-described sixth embodiment can be obtained.
[0151]
Twelfth embodiment
FIG. 13 is a circuit diagram showing a twelfth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0152]
The twelfth embodiment is different from the above-described eleventh embodiment in that inverters INV121-11 and INV122-11 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-11. .
[0153]
Other configurations are the same as those of the above-described eleventh embodiment.
[0154]
According to the twelfth embodiment, the influence of crosstalk and the like can be suppressed.
The setup time can be shortened by the first-stage latch 11-10 at the preceding stage, and the output signal of the first-stage latch 11-10 can be determined in a short time, thereby reducing the valid delay. Therefore, even if the valid delay becomes longer by inserting an inverter, the overall advantage is that high-speed operation can be realized and power consumption can be reduced without depending on the circuit design method. is there.
[0155]
13th embodiment
FIG. 14 is a circuit diagram showing a thirteenth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0156]
The difference between the thirteenth embodiment and the eleventh embodiment is that the second stage latch 12-12 transmits a change in the output signal of the first stage (previous stage) latch to the final output signal in a short time. Has been established.
[0157]
Specifically, the second-stage latch 12-12 is configured by four 2-input NAND gates NA121-12 to NA124-12.
A first input terminal of NAND gate NA121-12 is connected to first output node H111 of first stage latch 11-10, and a second input terminal is an output terminal of NAND gate NA122-12 and a second input terminal of NAND gate NA124-12. 1 input terminal, and these connection points constitute a node I121-12.
A first input terminal of the NAND gate NA122-12 is connected to the second node H112 of the first-stage latch 11-10, and a second input terminal is an output terminal of the NAMD gate NA121-12 and a first input terminal of the NAND gate NA123-12. These terminals are connected to input terminals, and these connection points constitute a node I122-12.
The second input terminal of the NAND gate NA123-12 is connected to the second node H112 of the first-stage latch 11-10, and the second input terminal of the NAND gate NA124-12 is connected to the first input of the first-stage latch 11-10. It is connected to the node H111.
Then, the second-stage latch 12-12 outputs data Q from the NAND gate NA124-12 and outputs inverted data Qb from the NAND gate NA123-12.
[0158]
For example, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 goes to a low level, and quickly goes higher than NAND gate NA124-12 of second stage latch 12-12. The level data Q is output.
The output data Qb of the NAND gate NA123-12 goes low via the NAND gate NA121-12.
[0159]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0160]
According to the thirteenth embodiment, the second stage latch 12-12 is provided with a circuit for transmitting a change in the output signal of the preceding first stage latch to the final output signal in a short time. In addition to the effects of the embodiment, a high level can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0161]
14th embodiment
FIG. 15 is a circuit diagram showing a fourteenth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0162]
The fourteenth embodiment differs from the eleventh embodiment in the circuit configuration of the second-stage latches 12-13.
[0163]
Specifically, as shown in FIG. 15, the second stage latch 12-13 has inverters INV121-13 to INV124-13, a PMOS transistor PT123-13, and an NMOS transistor NT121-13.
[0164]
The source of the PMOS transistor PT123-13 is at the power supply voltage V_DD, And the drain is connected to the drain of the NMOS transistor NT121-13, and this connection point constitutes the node J121-13. The source of the NMOS transistor NT121-13 is connected to the ground potential GND.
The input terminal of the inverter INV121-13 is connected to the first output node H111 of the first-stage latch 11-10, and the output terminal is connected to the gate of the NMOS transistor NT121-13. Here, a connection point between the output terminal of the inverter INV121-13 and the gate of the NMOS transistor NT121-13 is referred to as a node / H111.
The node J121-13 is connected to the input terminals of the inverters INV122-13 and INV123-13 and the output terminal of the inverter INV124-13.
The output terminal of the inverter INV123-13 is connected to the input terminal of the inverter INV124-13, and the connection point forms the node J122-13. A latch is constituted by the inverters INV123-13 and INV124-13.
Then, the second-stage latch 12-13 outputs the data Q from the output terminal of the inverter INV122-13.
[0165]
In this case, for example, if data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output node of inverter INV121-13 of second-stage latch 12-13. / 111 becomes high level. At this time, the second output node H112 of the first-stage latch 11-10 is at a high level.
As a result, the NMOS transistor NT121-13 turns on, the PMOS transistor PT123-13 turns off, the node J121-13 goes low, and the high-level data Q is output from the inverter INV122-13 immediately.
Note that the level of the data at the node J121-13 is maintained even when the clock signal CK is switched to a low level by the cross latch of the inverters INV123-13 and INV124-13.
[0166]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0167]
According to the fourteenth embodiment, the second stage latches 12-13 are provided with a circuit for transmitting a change in the output signal of the first stage latch to the final output signal in a short time. In addition to the effect of the embodiment, a high level can be output more quickly than a conventional circuit, so that high-speed operation is possible.
[0168]
15th embodiment
FIG. 16 is a circuit diagram showing a sense amplifier D-type flip-flop according to a fifteenth embodiment of the present invention.
[0169]
The fifteenth embodiment is different from the above-described fourteenth embodiment in that the second-stage latch 12-14 outputs a change in the output signal of the first-stage latch 11-10 when an opposite signal is held. At the same time, the circuit configuration is such that the reciprocal signal held in the second-stage latch is invalidated.
Specifically, the inverter INV124-14 constituting the cross latch is constituted by a clocked inverter (Clocked Inverter) connected to the nodes / H111 and H112.
[0170]
In this case, for example, if data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output node of inverter INV121-13 of second stage latch 12-14. / H111 is at a high level. At this time, the second output node H112 of the first-stage latch 11-10 is at a high level.
As a result, the NMOS transistor NT121-13 turns on, the PMOS transistor PT123-13 turns off, and the node J121-13 goes to low level.
At this time, the clocked inverter INV124-14 cannot output a high level, and the high-level data Q is output immediately from the inverter INV122-13.
Therefore, high-level data Q is output from inverter INV122-13 immediately without preventing node J121-13 from changing to low level.
Further, the data at the node J121-13 is maintained at the low level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-13 and INV124-14.
[0171]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0172]
According to the fifteenth embodiment, in addition to the effects of the fourteenth embodiment, high-level data can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0173]
Sixteenth embodiment
FIG. 17 is a circuit diagram showing a sense amplifier D-type flip-flop according to a sixteenth embodiment of the present invention.
[0174]
The sixteenth embodiment differs from the above-described sixth embodiment in the configuration of the latch section of the first-stage latches 11-15.
Specifically, in the latch unit 215 according to the sixteenth embodiment, the connection position of the NMOS transistor NT212 as the fifth switching element and the NMOS transistor NT213 as the seventh switching element in the first signal path SP211 In addition, the connection position between the NMOS transistor NT216 as the sixth switching element and the NMOS transistor NT217 as the eighth switching element in the second signal path SP212 is changed.
[0175]
Specifically, in the first signal path SP211, the drain of the NMOS transistor NT212 is connected to the second intermediate node G211, the source is connected to the ground potential GND, and the drain of the NMOS transistor NT213 is connected to the first intermediate node F211. And the source is connected to the second intermediate node G211.
Similarly, in the second signal path SP212, the drain of the NMOS transistor NT216 is connected to the fourth intermediate node G212, the source is connected to the ground potential GND, and the drain of the NMOS transistor NT217 is connected to the third intermediate node F212. Then, the source is connected to the fourth intermediate node G212.
[0176]
Next, the operation of the sense amplifier type D flip-flop 10-4 of FIG. 17 will be described.
[0177]
Here, it is assumed that the output data Q from the second-stage latch 12 is held at a low level, and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the input data D on the non-inverting side and the input data Db on the inverted side are output data Q and output. Description will be made assuming that data Qb is supplied at different levels (levels do not match).
[0178]
While the clock signal CK is at the low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0179]
Further, since the output data Q is held at the low level and the inverted output data Qb is held at the high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115, PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at a high level and the inverted signal Db is supplied at a low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117, PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistors, through which the first output node H111 and the second output node H112 connect to the power supply voltage V._DDIs electrically connected to the supply line (second potential source), and is precharged to a complete logic 1 potential (high level).
[0180]
Then, the PMOS transistors PT212 and PT213 are cut off.
At this time, since the NMOS transistors NT211 and NT215 are cut off, the first intermediate node F211 and the third intermediate node F212 are not charged.
On the other hand, the NMOS transistors NT213, NT214, NT217, and NT218 are turned on when the first output node H111 and the second output node H112 are precharged to a high level.
As a result, regardless of the states of the data input signal D and the inverted signal Db, the first intermediate node F211 is discharged through the NMOS transistor NT214, and the third intermediate node F212 is discharged through the NMOS transistor NT218 to be at a low level.
Therefore, during the period when the clock signal CK is at the low level, the charge is performed only on the first output node H111 and the second output node H112.
[0181]
Next, when the clock signal CK goes high, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Here, when the data input signal D is supplied to the gate of the NMOS transistor NT212 at a high level and the inverted signal Db is supplied to the gate of the NMOS transistor NT216 at a low level, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first signal path SP211 is electrically connected from the first output node H111 to the ground potential GND. Therefore, the electric charge charged in the first output node H111 is discharged through the NMOS transistors NT211 to NT213 and NT214. As a result, the first output node H111 becomes low level, and the high-level data Q is output from the NAND gate NA121 of the second stage latch 12.
[0182]
On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
However, the decrease in the potential of the first output node H111 turns on the PMOS transistor PT213, cuts off the NMOS transistors NT217 and NT218, increases the falling potential of the second output node H112, and completes the logic again. 1 is obtained and the high level is maintained.
[0183]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0184]
The operation of the pre-setting unit 112 is performed in the same manner as in the above-described first embodiment, and a detailed description thereof will be omitted here.
[0185]
According to the sixteenth embodiment, the same effects as those of the above-described sixth embodiment can be obtained.
[0186]
Seventeenth embodiment
FIG. 18 is a circuit diagram showing a seventeenth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0187]
The seventeenth embodiment is different from the above-described sixteenth embodiment in that inverters INV121-16 and INV122-16 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-16. .
[0188]
Other configurations are the same as those of the above-described sixteenth embodiment.
[0189]
According to the seventeenth embodiment, it is possible to suppress the influence of crosstalk and the like.
Further, the setup time can be shortened by the first-stage latch 11-15 in the preceding stage, and the output signal of the first-stage latch 11-15 can be determined in a short time, thereby reducing the valid delay. Therefore, even if the valid delay is lengthened by inserting an inverter, high-speed operation can be realized without depending on the circuit design method as a whole, and the advantage that power consumption can be reduced can be achieved. is there.
[0190]
18th embodiment
FIG. 19 is a circuit diagram showing an eighteenth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0191]
The nineteenth embodiment is different from the sixteenth embodiment in that the second-stage latch 12-17 transmits a change in the output signal of the first-stage (previous-stage) latch to the final output signal in a short time. Has been established.
[0192]
Specifically, the second-stage latch 12-17 is constituted by four 2-input NAND gates NA121-17 to NA124-17.
A first input terminal of the NAND gate NA121-17 is connected to the first output node H111 of the first-stage latch 11-15, and a second input terminal is connected to the output terminal of the NAND gate NA122-17 and the first input terminal of the NAND gate NA124-17. The input terminal is connected to one input terminal, and these connection points constitute a node I121-17.
A first input terminal of the NAND gate NA122-17 is connected to the second node H112 of the first-stage latch 11-15, and a second input terminal is connected to the output terminal of the NAMD gate NA121-17 and the first input terminal of the NAND gate NA123-17. These terminals are connected to input terminals, and these connection points constitute a node I122-17.
A second input terminal of the NAND gate NA123-17 is connected to the second node H112 of the first-stage latch 11-15, and a second input terminal of the NAND gate NA124-17 is connected to the first node of the first-stage latch 11-15. It is connected to the node H111.
Then, the second-stage latch 12-17 outputs the data Q from the NAND gate NA124-17, and outputs the inverted data Qb from the NAND gate NA123-17.
[0193]
For example, if the data input signal D is at a high level and the inverted signal Db is at a low level, the first output node H111 goes to a low level, and quickly goes to a high level from the NAND gate NA124-17 of the second-stage latch 12-17. Is output.
The output data Qb of the NAND gate NA123-17 goes low via the NAND gate NA121-17.
[0194]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0195]
According to the eighteenth embodiment, the second stage latch 12-17 is provided with a circuit for transmitting a change in the output signal of the preceding first stage latch to the final output signal in a short time. In addition to the effects of the embodiment, a high level can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0196]
19th embodiment
FIG. 20 is a circuit diagram showing a nineteenth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0197]
The twentieth embodiment differs from the above-described sixteenth embodiment in the circuit configuration of the second-stage latches 12-18.
[0198]
Specifically, as shown in FIG. 20, the second-stage latch 12-18 has inverters INV121-18 to INV124-18, a PMOS transistor PT123-18, and an NMOS transistor NT121-18.
[0199]
The source of the PMOS transistor PT123-18 has the power supply voltage V_DD, And the drain is connected to the drain of the NMOS transistor NT121-18, and this connection point constitutes the node J121-18. The source of the NMOS transistor NT121-18 is connected to the ground potential GND.
The input terminal of the inverter INV121-18 is connected to the first output node H111 of the first-stage latch 11-15, and the output terminal is connected to the gate of the NMOS transistor NT121-18. Here, a connection point between the output terminal of the inverter INV121-18 and the gate of the NMOS transistor NT121-18 is referred to as a node / H111.
The node J121-18 is connected to the input terminals of the inverters INV122-18 and INV123-18 and the output terminal of the inverter INV124-18.
The output terminal of the inverter INV123-18 is connected to the input terminal of the inverter INV124-18, and the connection point forms a node J122-18. A latch is constituted by the inverters INV123-18 and INV124-18.
Then, the second-stage latch 12-18 outputs the data Q from the output terminal of the inverter INV122-18.
[0200]
In this case, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output node of inverter INV121-18 of second stage latch 12-18. / 111 becomes high level. At this time, the second output node H112 of the first-stage latch 11-15 is at a high level.
As a result, the NMOS transistor NT121-18 turns on, the PMOS transistor PT123-18 turns off, the node J121-18 goes low, and the high-level data Q is output immediately from the inverter INV122-18.
The level of the data at the node J121-18 is maintained even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-18 and INV124-18.
[0201]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0202]
According to the nineteenth embodiment, the second stage latch 12-19 is provided with a circuit for transmitting the output signal change of the first stage latch to the final output signal in a short time. In addition to the effect of the embodiment, a high level can be output more quickly than a conventional circuit, so that high-speed operation is possible.
[0203]
Twentieth embodiment
FIG. 21 is a circuit diagram showing a twentieth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0204]
The twentieth embodiment is different from the above-described nineteenth embodiment in that the second-stage latch 12-19 outputs a change in the output signal of the first-stage latch 11-15 when an opposite signal is held. At the same time, the circuit configuration is such that the reciprocal signal held in the second-stage latch is invalidated.
Specifically, the inverter INV124-19 constituting the cross latch is constituted by a clocked inverter (Clocked Inverter) connected to nodes / H111 and H112.
[0205]
In this case, for example, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output node of inverter INV121-18 of second stage latch 12-19. / H111 is at a high level. At this time, the second output node H112 of the first-stage latch 11-15 is at a high level.
As a result, the NMOS transistor NT121-18 turns on, the PMOS transistor PT123-18 turns off, and the node J121-18 becomes low level.
At this time, the clocked inverter INV124-19 cannot output a high level, and the high-level data Q is output immediately from the inverter INV122-18.
Therefore, high-level data Q is output from inverter INV122-18 immediately without preventing node J121-18 from changing to low level.
Further, the data at the node J121-18 is held at the low level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-18 and INV124-19.
[0206]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0207]
According to the twentieth embodiment, in addition to the effects of the nineteenth embodiment, high-level data can be output more quickly than in a conventional circuit, so that high-speed operation is possible.
[0208]
21st embodiment
FIG. 22 is a circuit diagram showing a twenty-first embodiment of the sense amplifier type D flip-flop according to the present invention.
[0209]
The difference between the twenty-first embodiment and the sixth embodiment is the configuration of the latch section of the first-stage latch 11-20.
Specifically, in the latch unit 220 according to the twenty-first embodiment, the connection position of the source of the NMOS transistor NT214 as the ninth switching element and the connection of the source of the NMOS transistor NT218 as the tenth switching element The position has changed.
[0210]
Specifically, the source of the NMOS transistor NT214 is connected to the fourth intermediate node G212 instead of being grounded.
Similarly, the source of the NMOS transistor NT218 is connected to the second intermediate node G211 instead of being grounded.
[0211]
Next, the operation of the sense amplifier type D flip-flop 10-20 of FIG. 22 will be described.
[0212]
Here, it is assumed that the output data Q from the second-stage latch 12 is held at a low level, and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the input data D on the non-inverting side and the input data Db on the inverted side are output data Q and output. Description will be made assuming that data Qb is supplied at different levels (levels do not match).
[0213]
While the clock signal CK is at the low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0214]
Further, since the output data Q is held at the low level and the inverted output data Qb is held at the high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115, PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at a high level and the inverted signal Db is supplied at a low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117, PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistors, through which the first output node H111 and the second output node H112 connect to the power supply voltage V._DDIs electrically connected to the supply line (second potential source), and is precharged to a complete logic 1 potential (high level).
[0215]
Then, the PMOS transistors PT212 and PT213 are cut off.
At this time, since the NMOS transistors NT211 and NT215 are cut off, the first intermediate node F211 and the third intermediate node F212 are not charged.
On the other hand, the NMOS transistors NT213, NT214, NT217, and NT218 are turned on when the first output node H211 and the second output node H212 are precharged to a high level.
Further, since one of the data input signal D and the inverted signal Db is at a high level, either the NMOS transistor NT212 or the NMOS transistor NT216 is in the ON state.
As a result, the first intermediate node F211 and the second intermediate node G211 are discharged at the low level through the NMOS transistors NT213 and NT212 or the NMOS transistors NT213, NT214, NT218, and NT216 and are held at the low level. .
Similarly, the third intermediate node F212 and the fourth intermediate node G212 are discharged through the NMOS transistors NT217 and NT216 or the NMOS transistors NT217, NT214, NT218, and NT212, and are held at a low level. .
Therefore, during the period when the clock signal CK is at the low level, the charge is performed only on the first output node H111 and the second output node H112.
[0216]
Next, when the clock signal CK goes high, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Therefore, when the power supply voltage is V_DD[V] Assuming that the threshold value of the NMOS transistor is Vthn, the potentials of the first intermediate node F211 and the second intermediate node F212 at this time are (V_DD−Vthn) [V]. Here, when the data input signal D is supplied to the gate of the NMOS transistor NT212 at a high level and the inverted signal Db is supplied to the gate of the NMOS transistor NT216 at a low level, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first signal path SP211 is electrically connected from the first output node H111 to the ground potential GND. Therefore, the electric charge charged in the first output node H111 is discharged through the NMOS transistors NT211 to NT213. As a result, the first output node H111 becomes low level, and the high-level data Q is output from the NAND gate NA121 of the second stage latch 12.
[0217]
On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
However, the decrease in the potential of the first output node H111 turns on the PMOS transistor PT213, cuts off the NMOS transistors NT217 and NT218, increases the falling potential of the second output node H112, and completes the logic again. 1 is obtained and the high level is maintained.
[0218]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0219]
The operation of the pre-setting unit 112 is performed in the same manner as in the above-described first embodiment, and a detailed description thereof will be omitted here.
[0220]
According to the twenty-first embodiment, the same effects as those of the above-described sixth embodiment can be obtained.
[0221]
Twenty-second embodiment
FIG. 23 is a circuit diagram showing a twenty-second embodiment of the sense amplifier type D flip-flop according to the present invention.
[0222]
The twenty-second embodiment is different from the twenty-first embodiment in that inverters INV121-21 and INV122-21 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-21. .
[0223]
Other configurations are the same as those of the above-described twenty-first embodiment.
[0224]
According to the twenty-second embodiment, the influence of crosstalk and the like can be suppressed.
Further, the setup time can be shortened by the first-stage latch 11-20 at the preceding stage, and the output signal of the first-stage latch 11-20 can be determined in a short time, thereby reducing the valid delay. Therefore, even if the valid delay is lengthened by inserting an inverter, high-speed operation can be realized without depending on the circuit design method as a whole, and the advantage that power consumption can be reduced can be achieved. is there.
[0225]
Twenty-third embodiment
FIG. 24 is a circuit diagram showing a twenty-third embodiment of the sense amplifier type D flip-flop according to the present invention.
[0226]
The twenty-third embodiment is different from the twenty-first embodiment in that the second-stage latch 12-22 transmits the output signal change of the first-stage (previous-stage) latch to the final output signal in a short time. Has been established.
[0227]
Specifically, the second-stage latch 12-22 is constituted by four 2-input NAND gates NA121-22 to NA124-22.
A first input terminal of the NAND gate NA121-22 is connected to the first output node H111 of the first stage latch 11-20, and a second input terminal is connected to the output terminal of the NAND gate NA122-22 and the second input terminal of the NAND gate NA124-22. 1 input terminal, and these connection points constitute a node I121-22.
A first input terminal of the NAND gate NA122-22 is connected to the second node H112 of the first stage latch 11-20, and a second input terminal is connected to the output terminal of the NAMD gate NA121-22 and the first terminal of the NAND gate NA123-22. These terminals are connected to input terminals, and these connection points constitute a node I122-22.
The second input terminal of the NAND gate NA123-22 is connected to the second node H112 of the first stage latch 11-20, and the second input terminal of the NAND gate NA124-22 is connected to the first node of the first stage latch 11-20. It is connected to the node H111.
Then, the second-stage latch 12-22 outputs data Q from the NAND gate NA124-22, and outputs inverted data Qb from the NAND gate NA123-22.
[0228]
For example, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 goes to a low level and quickly goes higher than NAND gate NA124-22 of second stage latch 12-22. The level data Q is output.
Further, the output data Qb of the NAND gate NA123-22 goes to a low level via the NAND gate NA121-22.
[0229]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0230]
According to the twenty-third embodiment, the second stage latch 12-22 has a circuit for transmitting the output signal change of the preceding first stage latch to the final output signal in a short time. In addition to the effects of the embodiment, a high level can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0231]
Twenty-fourth embodiment
FIG. 25 is a circuit diagram showing a twenty-fourth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0232]
The twenty-fourth embodiment differs from the twenty-first embodiment in the circuit configuration of the second-stage latches 12-23.
[0233]
Specifically, as shown in FIG. 25, the second-stage latch 12-23 has inverters INV121-23 to INV124-23, a PMOS transistor PT123-23, and an NMOS transistor NT121-23.
[0234]
The source of the PMOS transistors PT123-23 is the power supply voltage V_DDAnd the drain is connected to the drain of the NMOS transistor NT121-23, and this connection point constitutes the node J121-23. The sources of the NMOS transistors NT121-23 are connected to the ground potential GND.
The input terminal of the inverter INV121-23 is connected to the first output node H111 of the first-stage latch 11-20, and the output terminal is connected to the gate of the NMOS transistor NT121-23. Here, a connection point between the output terminal of the inverter INV121-23 and the gate of the NMOS transistor NT121-23 is referred to as a node / H111.
The node J121-23 is connected to the input terminals of the inverters INV122-23 and INV123-23 and the output terminal of the inverter INV124-23.
The output terminal of the inverter INV123-23 is connected to the input terminal of the inverter INV124-23, and the connection point forms the node J122-23. A latch is constituted by these inverters INV123-23 and INV124-23.
Then, the second-stage latch 12-23 outputs the data Q from the output terminal of the inverter INV122-23.
[0235]
In this case, for example, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level and output node of inverter INV121-23 of second stage latch 12-23. / 111 becomes high level. At this time, the second output node H112 of the first-stage latch 11-20 is at a high level.
As a result, the NMOS transistor NT121-23 turns on, the PMOS transistor PT123-23 turns off, the node J121-23 goes low, and the high-level data Q is output immediately from the inverter INV122-23.
The data at the node J121-23 is maintained at the low level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-23 and INV124-23.
[0236]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0237]
According to the twenty-fourth embodiment, the second stage latches 12-23 are provided with a circuit for transmitting a change in the output signal of the first stage latch to the final output signal in a short time. In addition to the effect of the embodiment, a high level can be output more quickly than a conventional circuit, so that high-speed operation is possible.
[0238]
Twenty-fifth embodiment
FIG. 26 is a circuit diagram showing a twenty-fifth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0239]
The twenty-fifth embodiment is different from the above-described twenty-fourth embodiment in that the second-stage latch 12-24 outputs a change in the output signal of the first-stage latch 11-20 when an opposite signal is held. At the same time, the circuit configuration is such that the reciprocal signal held in the second-stage latch is invalidated.
Specifically, the inverters INV124-24 constituting the cross latch are constituted by clocked inverters (Clocked Inverters) connected to the nodes / H111 and H112.
[0240]
In this case, for example, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output node of inverter INV121-23 of second stage latch 12-24. / H111 is at a high level. At this time, the second output node H112 of the first-stage latch 11-20 is at a high level.
As a result, the NMOS transistor NT121-23 turns on, the PMOS transistor PT123-23 turns off, and the node J121-23 goes low.
At this time, the clocked inverters INV124-24 cannot output a high level, and the high-level data Q is output immediately from the inverters INV122-23.
Therefore, high-level data Q is output from inverter INV122-23 promptly without preventing node J121-23 from changing to low level.
The data at the node J121-23 is maintained at the low level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-23 and INV124-24.
[0241]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0242]
According to the twenty-fifth embodiment, in addition to the effect of the twenty-fourth embodiment, high-level data can be output more quickly than a conventional circuit, so that high-speed operation is possible.
[0243]
26th embodiment
FIG. 27 is a circuit diagram showing a twenty-sixth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0244]
The twenty-sixth embodiment is different from the twenty-first embodiment in the configuration of the latch section of the first-stage latches 11-25.
Specifically, in the latch unit 225 according to the twenty-sixth embodiment, the gates of the second intermediate node G211 and the fourth intermediate node G212 are connected to the power supply voltage V_DDAre connected by an NMOS transistor NT219 which functions as an on-resistance and is connected to the supply line.
[0245]
Other configurations are the same as those of the above-described twenty-first embodiment.
[0246]
The operation according to the twenty-sixth embodiment is basically performed in the same manner as the operation according to the twenty-first embodiment, and a detailed description thereof will be omitted.
[0247]
According to the twenty-sixth embodiment, the same effects as those of the sixth and twenty-first embodiments can be obtained.
[0248]
Twenty-seventh embodiment
FIG. 28 is a circuit diagram showing a twenty-seventh embodiment of the sense amplifier type D flip-flop according to the present invention.
[0249]
The twenty-seventh embodiment is different from the twenty-sixth embodiment in that the inverters INV121-26 and INV122-26 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-26. .
[0250]
Other configurations are the same as those in the twenty-sixth embodiment described above.
[0251]
According to the twenty-seventh embodiment, the influence of crosstalk and the like can be suppressed.
In addition, the setup time can be shortened by the first-stage latch 11-25 at the preceding stage, and the output signal of the first-stage latch 11-25 can be determined in a short time, thereby reducing the valid delay. Therefore, even if the valid delay is lengthened by inserting an inverter, high-speed operation can be realized without depending on the circuit design method as a whole, and the advantage that power consumption can be reduced can be achieved. is there.
[0252]
Twenty-eighth embodiment
FIG. 29 is a circuit diagram showing a twenty-eighth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0253]
The twenty-eighth embodiment differs from the twenty-sixth embodiment in that the second-stage latch 12-27 transmits a change in the output signal of the first-stage (previous-stage) latch to the final output signal in a short time. Has been established.
[0254]
Specifically, the second-stage latch 12-27 is constituted by four 2-input NAND gates NA121-27 to NA124-27.
A first input terminal of NAND gate NA121-27 is connected to first output node H111 of first stage latch 11-25, and a second input terminal is an output terminal of NAND gate NA122-27 and a second input terminal of NAND gate NA124-27. 1 input terminal, and these connection points constitute a node I121-27.
A first input terminal of the NAND gate NA122-27 is connected to the second node H112 of the first-stage latch 11-25, and a second input terminal is connected to the output terminal of the NAMD gate NA121-27 and the first input terminal of the NAND gate NA123-27. The input terminals are connected to each other, and these connection points constitute a node I122-27.
The second input terminal of the NAND gate NA123-27 is connected to the second node H112 of the first stage latch 11-25, and the second input terminal of the NAND gate NA124-27 is connected to the first node of the first stage latch 11-25. It is connected to the node H111.
Then, the second-stage latch 12-27 outputs data Q from the NAND gate NA124-27, and outputs inverted data Qb from the NAND gate NA123-27.
[0255]
For example, if the data input signal D is at a high level and the inverted signal Db is at a low level, the first output node H111 goes to a low level and quickly goes high from the NAND gate NA124-27 of the second-stage latch 12-27. The level data Q is output.
The output data Qb of the NAND gates NA123-27 goes low via the NAND gates NA121-27.
[0256]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0257]
According to the twenty-eighth embodiment, the second stage latch 12-27 is provided with a circuit for transmitting a change in the output signal of the preceding first stage latch to the final output signal in a short time. In addition to the effects of the embodiment, a high level can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0258]
Twenty-ninth embodiment
FIG. 30 is a circuit diagram showing a twenty-ninth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0259]
The difference between the twenty-ninth embodiment and the twenty-sixth embodiment lies in the circuit configuration of the second-stage latches 12-28.
[0260]
Specifically, as shown in FIG. 30, the second-stage latch 12-28 has inverters INV121-28 to INV124-28, a PMOS transistor PT123-28, and an NMOS transistor NT121-28.
[0261]
The source of the PMOS transistor PT123-28 is the power supply voltage V_DD, And the drain is connected to the drain of the NMOS transistor NT121-28, and this connection point constitutes the node J121-28. The source of the NMOS transistor NT121-28 is connected to the ground potential GND.
The input terminal of the inverter INV121-28 is connected to the first output node H111 of the first-stage latch 11-25, and the output terminal is connected to the gate of the NMOS transistor NT121-28. Here, a connection point between the output terminal of the inverter INV121-28 and the gate of the NMOS transistor NT121-28 is defined as a node / H111.
Node J121-28 is connected to the input terminals of inverters INV122-28 and INV123-28 and the output terminal of inverter INV124-28.
The output terminal of the inverter INV123-28 is connected to the input terminal of the inverter INV124-28, and the connection point forms a node J122-28. A latch is formed by the inverters INV123-28 and INV124-28.
Then, the second-stage latch 12-28 outputs data Q from the output terminal of the inverter INV122-28.
[0262]
In this case, for example, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output node of inverter INV121-28 of second stage latch 12-28. / 111 becomes high level. At this time, the second output node H112 of the first-stage latch 11-25 is at a high level.
As a result, the NMOS transistor NT121-28 turns on, the PMOS transistor PT123-28 turns off, the node J121-28 goes low, and the high-level data Q is output immediately from the inverter INV122-28.
Note that the level of the data at the nodes J121-28 is maintained even when the clock signal CK is switched to a low level by the cross latch of the inverters INV123-28 and INV124-28.
[0263]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0264]
According to the twenty-ninth embodiment, the second stage latch 12-28 is provided with a circuit for transmitting the change in the output signal of the first stage latch to the final output signal in a short time. In addition to the effect of the embodiment, a high level can be output more quickly than a conventional circuit, so that high-speed operation is possible.
[0265]
30th embodiment
FIG. 31 is a circuit diagram showing a thirtieth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0266]
The difference of the thirtieth embodiment from the twenty-ninth embodiment is that the second-stage latch 12-29 outputs the change of the output signal of the first-stage latch 11-25 when the opposite signal is held. At the same time, the circuit configuration is such that the reciprocal signal held in the second-stage latch is invalidated.
More specifically, the inverter INV124-29 constituting the cross latch is constituted by a clocked inverter (Clocked Inverter) connected to the nodes / H111 and H112.
[0267]
In this case, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output node of inverter INV121-28 of second stage latch 12-29. / H111 is at a high level. At this time, the second output node H112 of the first-stage latch 11-25 is at a high level.
As a result, the NMOS transistor NT121-28 turns on, the PMOS transistor PT123-28 turns off, and the node J121-28 goes low.
At this time, the clocked inverter INV124-29 cannot output a high level, and the high-level data Q is output immediately from the inverter INV122-28.
Therefore, high-level data Q is output from inverter INV122-28 promptly without preventing node J121-28 from changing to low level.
Further, the data at the nodes J121-28 is held at the low level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-28 and INV124-29.
[0268]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0269]
According to the thirtieth embodiment, in addition to the effects of the twenty-ninth embodiment, high-level data can be output more quickly than in a conventional circuit, so that high-speed operation is possible.
[0270]
31st embodiment
FIG. 32 is a circuit diagram showing a thirty-first embodiment of the sense amplifier type D flip-flop according to the present invention.
[0271]
The thirty-first embodiment differs from the above-described sixth embodiment in the configuration of the latch section of the first-stage latches 11-30.
Specifically, in the latch section 230 according to the thirty-first embodiment, the connection position of the NMOS transistor NT211 as the third switching element and the NMOS transistor NT215 as the fifth switching element in the first signal path SP211 And the connection position of the drain of the NMOS transistor NT214 as the ninth switching element, and the connection position of the NMOS transistor NT215 as the fourth switching element and the NMOS transistor NT216 as the sixth switching element in the second signal path SP212. , And the connection position of the drain of the NMOS transistor NT218 as the tenth switching element.
[0272]
Specifically, in the first signal path SP211, the drain of the NMOS transistor NT211 is connected to the first intermediate node F211, the source is connected to the second intermediate node G211 and the drain of the NMOS transistor NT212 is connected to the first intermediate node F211. The output H111 is connected, and the source is connected to the first intermediate node F211. The drain of the NMOS transistor NT214 is connected to the first output node H111, and the source is connected to the first intermediate node F211.
Similarly, in the second signal path SP212, the drain of the NMOS transistor NT215 is connected to the third intermediate node F212, the source is connected to the fourth intermediate node G212, and the drain of the NMOS transistor NT216 is connected to the second output H112. And the source is connected to the third intermediate node F212. The drain of the NMOS transistor NT218 is connected to the second output node H112, and the source is connected to the third intermediate node F212.
[0273]
Next, the operation of the sense amplifier type D flip-flop 10-30 of FIG. 32 will be described.
[0274]
Here, it is assumed that the output data Q from the second-stage latch 12 is held at a low level, and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the input data D on the non-inverting side and the input data Db on the inverted side are output data Q and output. Description will be made assuming that data Qb is supplied at different levels (levels do not match).
[0275]
While the clock signal CK is at the low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0276]
Further, since the output data Q is held at the low level and the inverted output data Qb is held at the high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115, PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at a high level and the inverted signal Db is supplied at a low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117, PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistors, through which the first output node H111 and the second output node H112 connect to the power supply voltage V._DDIs electrically connected to the supply line (second potential source), and is precharged to a complete logic 1 potential (high level).
[0277]
Then, the PMOS transistors PT212 and PT213 are cut off.
At this time, since the NMOS transistors NT211 and NT215 are cut off, the second intermediate node G212 and the fourth intermediate node G212 are not charged.
On the other hand, the NMOS transistors NT213, NT214, NT217, and NT218 are turned on when the first output node H111 and the second output node H112 are precharged to a high level.
Further, since one of the data input signal D and the inverted signal Db is at a high level, either the NMOS transistor NT212 or the NMOS transistor NT216 is in the ON state.
As a result, the first intermediate node F211 and the third intermediate node F212_DD-Vth) level.
The second intermediate node G211 is discharged at the low level through the NMOS transistor NT213.
Similarly, the electric charge of the fourth intermediate node G212 is discharged through the NMOS transistor NT217 and is maintained at the low level.
Therefore, during the period when the clock signal CK is at the low level, charge is charged only to the first output node H111 and the second output node H112, and to the first intermediate node F211 and the third intermediate node F212. Done.
[0278]
Next, when the clock signal CK goes high, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Here, when the data input signal D is supplied to the gate of the NMOS transistor NT212 at a high level and the inverted signal Db is supplied to the gate of the NMOS transistor NT216 at a low level, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first signal path SP211 is electrically connected from the first output node H111 to the ground potential GND. Therefore, the electric charge charged in the first output node H111 is discharged through the NMOS transistors NT211 to NT213 and NT214. As a result, the first output node H111 becomes low level, and the high-level data Q is output from the NAND gate NA121 of the second stage latch 12.
[0279]
On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
However, the decrease in the potential of the first output node H111 turns on the PMOS transistor PT213, cuts off the NMOS transistors NT217 and NT218, increases the falling potential of the second output node H112, and completes the logic again. 1 is obtained and the high level is maintained.
[0280]
When the data input signal D is at a high level, the level of the fourth intermediate node G212 becomes (V_DD-Vth) / 2 level.
[0281]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
In this case, the level of the fourth intermediate node G212 is the ground level, but the level of the second intermediate node G211 is (V_DD-Vth) / 2 level.
[0282]
The operation of the pre-setting unit 112 is performed in the same manner as in the above-described first embodiment, and a detailed description thereof will be omitted here.
[0283]
According to the thirty-first embodiment, the same effects as those of the above-described sixth embodiment can be obtained.
[0284]
32nd embodiment
FIG. 33 is a circuit diagram showing a 32nd embodiment of the sense amplifier type D flip-flop according to the present invention.
[0285]
The 32nd embodiment differs from the 31st embodiment in that the inverters INV121-31 and INV122-31 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-31. .
[0286]
Other configurations are the same as those of the above-described thirty-first embodiment.
[0287]
According to the thirty-second embodiment, the influence of crosstalk and the like can be suppressed.
Further, the setup time can be shortened by the first-stage latch 11-30 at the preceding stage, and the output signal of the first-stage latch 11-30 can be determined in a short time, thereby reducing the valid delay. Therefore, even if the valid delay is lengthened by inserting an inverter, high-speed operation can be realized without depending on the circuit design method as a whole, and the advantage that power consumption can be reduced can be achieved. is there.
[0288]
33rd embodiment
FIG. 34 is a circuit diagram showing a thirty-third embodiment of the sense amplifier type D flip-flop according to the present invention.
[0289]
The thirty-third embodiment is different from the thirty-first embodiment in that the second-stage latch 12-32 transmits a change in the output signal of the first-stage (previous-stage) latch to the final output signal in a short time. Has been established.
[0290]
Specifically, the second-stage latch 12-32 is configured by four 2-input NAND gates NA121-32 to NA124-32.
A first input terminal of the NAND gate NA121-32 is connected to the first output node H111 of the first-stage latch 11-30, and a second input terminal is connected to the output terminal of the NAND gate NA122-32 and the second input terminal of the NAND gate NA124-32. These terminals are connected to one input terminal, and these connection points constitute a node I121-32.
A first input terminal of the NAND gate NA122-32 is connected to a second node H112 of the first-stage latch 11-30, and a second input terminal is an output terminal of the NAMD gate NA121-32 and a first input terminal of the NAND gate NA123-32. Nodes I122-32 are connected to input terminals, and these connection points constitute nodes I122-32.
The second input terminal of NAND gate NA123-32 is connected to the second node H112 of first stage latch 11-30, and the second input terminal of NAND gate NA124-32 is connected to the first node of first stage latch 11-30. It is connected to the node H111.
Then, the second-stage latch 12-32 outputs the data Q from the NAND gate NA124-32, and outputs the inverted data Qb from the NAND gate NA123-32.
[0291]
For example, if the data input signal D is at a high level and the inverted signal Db is at a low level, the first output node H111 goes to a low level and quickly goes higher than the NAND gate NA124-32 of the second stage latch 12-32. The level data Q is output.
The output data Qb of the NAND gates NA123-32 goes low through the NAND gates NA121-32.
[0292]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0293]
According to the thirty-third embodiment, in the second-stage latch 12-32, a circuit for transmitting a change in the output signal of the preceding first-stage latch to the final output signal in a short time is provided. In addition to the effects of the embodiment, a high level can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0294]
34th embodiment
FIG. 35 is a circuit diagram showing a 34th embodiment of the sense amplifier type D flip-flop according to the present invention.
[0295]
The thirty-fourth embodiment differs from the thirty-first embodiment in the circuit configuration of the second-stage latches 12-33.
[0296]
Specifically, as shown in FIG. 35, the second-stage latch 12-33 has inverters INV121-33 to INV124-33, a PMOS transistor PT123-33, and an NMOS transistor NT121-33.
[0297]
The source of the PMOS transistor PT123-33 is the power supply voltage V_DD, And the drain is connected to the drain of the NMOS transistor NT121-33, and this connection point constitutes the node J121-33. The sources of the NMOS transistors NT121-33 are connected to the ground potential GND.
The input terminal of the inverter INV121-33 is connected to the first output node H111 of the first-stage latch 11-30, and the output terminal is connected to the gate of the NMOS transistor NT121-33. Here, a connection point between the output terminal of the inverter INV121-33 and the gate of the NMOS transistor NT121-33 is defined as a node / H111.
Nodes J121-33 are connected to the input terminals of the inverters INV122-33 and INV123-33 and the output terminals of the inverters INV124-33.
The output terminal of the inverter INV123-33 is connected to the input terminal of the inverter INV124-33, and the connection point constitutes the node J122-33. A latch is formed by the inverters INV123-33 and INV124-33.
Then, the second-stage latches 12-33 output the data Q from the output terminals of the inverters INV122-33.
[0298]
In this case, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output nodes of inverters INV121-33 of second stage latches 12-33. / 111 becomes high level. At this time, the second output node H112 of the first-stage latch 11-30 is at the high level.
As a result, the NMOS transistor NT121-33 turns on, the PMOS transistor PT123-33 turns off, the node J121-33 goes low, and the high-level data Q is output immediately from the inverter INV122-33.
Note that the data at the nodes J121-33 is maintained at the low level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-33 and INV124-33.
[0299]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0300]
According to the thirty-fourth embodiment, in the second-stage latches 12-33, a circuit for transmitting a change in the output signal of the first-stage latch to the final output signal in a short time is provided. In addition to the effect of the embodiment, a high level can be output more quickly than a conventional circuit, so that high-speed operation is possible.
[0301]
35th embodiment
FIG. 36 is a circuit diagram showing a 35th embodiment of the sense amplifier type D flip-flop according to the present invention.
[0302]
The thirty-fifth embodiment is different from the above-described thirty-fourth embodiment in that the second-stage latch 12-34 outputs the change in the output signal of the first-stage latch 11-30 when an opposite signal is held. At the same time, the circuit configuration is such that the reciprocal signal held in the second-stage latch is invalidated.
Specifically, the inverters INV124-34 constituting the cross latch are constituted by clocked inverters (Clocked Inverters) connected to the nodes / H111 and H112.
[0303]
In this case, for example, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output nodes of inverters INV121-33 of second stage latches 12-34. / H111 is at a high level. At this time, the second output node H112 of the first-stage latch 11-30 is at the high level.
As a result, the NMOS transistor NT121-33 turns on, the PMOS transistor PT123-33 turns off, and the node J121-33 goes low.
At this time, the clocked inverters INV124-34 cannot output a high level, and the high-level data Q is output immediately from the inverters INV122-33.
Therefore, high-level data Q is output from inverters INV122-33 immediately without preventing nodes J121-33 from changing to low level.
The data at the nodes J121-33 is held at the low level even when the clock signal CK is switched to the low level by the cross latch between the inverters INV123-33 and INV124-34.
[0304]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0305]
According to the thirty-fifth embodiment, in addition to the effects of the thirty-fourth embodiment, high-level data can be output more quickly than in a conventional circuit, so that high-speed operation is possible.
[0306]
36th embodiment
FIG. 37 is a circuit diagram showing a 36th embodiment of the sense amplifier type D flip-flop according to the present invention.
[0307]
The thirty-sixth embodiment is different from the twenty-sixth embodiment in the configuration of the latch section of the first-stage latches 11-35.
Specifically, in the latch section 235 according to the thirty-sixth embodiment, the connection position between the NMOS transistor NT211 as the third switching element and the NMOS transistor NT215 as the fifth switching element in the first signal path SP211 Further, the connection position between the NMOS transistor NT215 as the fourth switching element and the NMOS transistor NT216 as the sixth switching element in the second signal path SP212 is changed.
[0308]
Specifically, in the first signal path SP211, the drain of the NMOS transistor NT211 is connected to the first intermediate node F211, the source is connected to the second intermediate node G211 and the drain of the NMOS transistor NT212 is connected to the first intermediate node F211. The output H111 is connected, and the source is connected to the first intermediate node F211. The drain of the NMOS transistor NT214 is connected to the first output node H111, and the source is connected to the first intermediate node F211.
Similarly, in the second signal path SP212, the drain of the NMOS transistor NT215 is connected to the third intermediate node F212, the source is connected to the fourth intermediate node G212, and the drain of the NMOS transistor NT216 is connected to the second output H112. And the source is connected to the third intermediate node F212. The drain of the NMOS transistor NT218 is connected to the second output node H112, and the source is connected to the third intermediate node F212.
[0309]
Next, the operation of the sense amplifier type D flip-flop 10-35 of FIG. 37 will be described.
Here, it is assumed that the output data Q from the second-stage latch 12 is held at a low level, and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the input data D on the non-inverting side and the input data Db on the inverted side are output data Q and output. Description will be made assuming that data Qb is supplied at different levels (levels do not match).
[0310]
While the clock signal CK is at the low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0311]
Further, since the output data Q is held at the low level and the inverted output data Qb is held at the high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115, PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at a high level and the inverted signal Db is supplied at a low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117, PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistors, through which the first output node H111 and the second output node H112 connect to the power supply voltage V._DDIs electrically connected to the supply line (second potential source), and is precharged to a complete logic 1 potential (high level).
[0312]
Then, the PMOS transistors PT212 and PT213 are cut off.
At this time, since the NMOS transistors NT211 and NT215 are cut off, the second intermediate node G212 and the fourth intermediate node G212 are not charged.
On the other hand, the NMOS transistors NT213, NT214, NT217, and NT218 are turned on when the first output node H111 and the second output node H112 are precharged to a high level.
Further, since one of the data input signal D and the inverted signal Db is at a high level, either the NMOS transistor NT212 or the NMOS transistor NT216 is in the ON state.
As a result, the first intermediate node F211 and the third intermediate node F212_DD-Vth) level.
In addition, the second intermediate node G211 is discharged through the NMOS transistor NT212 or the NMOS transistors NT219 and NT216, and is kept at a low level.
Similarly, the electric charge of the fourth intermediate node G212 is discharged through the NMOS transistor NT216 or the NMOS transistors NT219 and NT212 and is maintained at the low level.
Therefore, during the period when the clock signal CK is at the low level, charge is charged only to the first output node H111 and the second output node H112, and to the first intermediate node F211 and the third intermediate node F212. Done.
[0313]
Next, when the clock signal CK goes high, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Here, when the data input signal D is supplied to the gate of the NMOS transistor NT212 at a high level and the inverted signal Db is supplied to the gate of the NMOS transistor NT216 at a low level, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first signal path SP211 is electrically connected from the first output node H111 to the ground potential GND. Therefore, the electric charge charged in the first output node H111 is discharged through the NMOS transistors NT211 to NT213. As a result, the first output node H111 becomes low level, and the high-level data Q is output from the NAND gate NA121 of the second stage latch 12.
[0314]
On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
However, the decrease in the potential of the first output node H111 turns on the PMOS transistor PT213, cuts off the NMOS transistors NT217 and NT218, increases the falling potential of the second output node H112, and completes the logic again. 1 is obtained and the high level is maintained.
[0315]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0316]
The operation of the pre-setting unit 112 is performed in the same manner as in the above-described first embodiment, and a detailed description thereof will be omitted here.
[0317]
According to the thirty-sixth embodiment, the same effects as those of the sixth and twenty-sixth embodiments can be obtained.
[0318]
37th embodiment
FIG. 38 is a circuit diagram showing a thirty-seventh embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0319]
The 37th embodiment differs from the 36th embodiment in that the inverters INV121-36 and INV122-36 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-36. .
[0320]
Other configurations are the same as those of the above-described thirty-sixth embodiment.
[0321]
According to the thirty-seventh embodiment, the influence of crosstalk and the like can be suppressed.
Further, the setup time can be shortened by the first-stage latch 11-35 in the preceding stage, and the output signal of the first-stage latch 11-35 can be determined in a short time, thereby reducing the valid delay. Therefore, even if the valid delay is lengthened by inserting an inverter, high-speed operation can be realized without depending on the circuit design method as a whole, and the advantage that power consumption can be reduced can be achieved. is there.
[0322]
38th embodiment
FIG. 39 is a circuit diagram showing a thirty-eighth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0323]
The thirty-eighth embodiment is different from the thirty-sixth embodiment in that the second-stage latch 12-37 transmits a change in the output signal of the first-stage (previous-stage) latch to the final output signal in a short time. Has been established.
[0324]
Specifically, the second-stage latch 12-37 is configured by four 2-input NAND gates NA121-37 to NA124-37.
A first input terminal of the NAND gate NA121-72 is connected to the first output node H111 of the first-stage latch 11-35, and a second input terminal is connected to the output terminal of the NAND gate NA122-37 and the second input terminal of the NAND gate NA124-37. These terminals are connected to one input terminal, and these connection points constitute nodes I121-37.
The first input terminal of the NAND gate NA122-32 is connected to the second node H112 of the first-stage latch 11-35, and the second input terminal is the output terminal of the NAMD gate NA121-37 and the first input terminal of the NAND gate NA123-37. These terminals are connected to input terminals, and these connection points constitute a node I1122-37.
A second input terminal of the NAND gate NA123-37 is connected to the second node H112 of the first-stage latch 11-35, and a second input terminal of the NAND gate NA124-37 is connected to the first node of the first-stage latch 11-35. It is connected to the node H111.
Then, the second-stage latch 12-37 outputs the data Q from the NAND gates NA124-37, and outputs the inverted data Qb from the NAND gates NA123-37.
[0325]
For example, assuming that the data input signal D is at a high level and the inverted signal Db is at a low level, the first output node H111 goes to a low level and quickly goes high from the NAND gate NA124-37 of the second stage latch 12-37. The level data Q is output.
The output data Qb of the NAND gates NA123-37 goes low through the NAND gates NA121-37.
[0326]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0327]
According to the thirty-eighth embodiment, in the second-stage latches 12-37, a circuit for transmitting the output signal change of the preceding first-stage latch to the final output signal in a short time is provided. In addition to the effects of the embodiment, a high level can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0328]
39th embodiment
FIG. 40 is a circuit diagram showing a thirty-ninth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0329]
The 39th embodiment differs from the 36th embodiment in the circuit configuration of the second-stage latches 12-33.
[0330]
Specifically, as shown in FIG. 40, the second-stage latch 12-38 has inverters INV121-38 to INV124-38, a PMOS transistor PT123-38, and an NMOS transistor NT121-38.
[0331]
The source of the PMOS transistors PT123-38 is at the power supply voltage V_DD, And the drain is connected to the drain of the NMOS transistor NT121-38, and this connection point constitutes the node J121-38. Further, the sources of the NMOS transistors NT121-NT38 are connected to the ground potential GND.
The input terminal of the inverter INV121-38 is connected to the first output node H111 of the first-stage latch 11-35, and the output terminal is connected to the gate of the NMOS transistor NT121-38. Here, a connection point between the output terminal of the inverter INV121-38 and the gate of the NMOS transistor NT121-38 is defined as a node / H111.
Nodes J121-33 are connected to the input terminals of the inverters INV122-38 and INV123-38 and the output terminals of the inverters INV124-38.
The output terminals of the inverters INV123-38 and the input terminals of the inverters INV124-38 are connected, and the connection point constitutes a node J122-38. A latch is formed by the inverters INV123-38 and INV124-38.
Then, the second-stage latch 12-38 outputs the data Q from the output terminal of the inverter INV122-38.
[0332]
In this case, for example, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level, and output nodes of inverters INV121-38 of second stage latches 12-38. / 111 becomes high level. At this time, the second output node H112 of the first-stage latches 11-35 is at a high level.
As a result, the NMOS transistor NT121-38 turns on, the PMOS transistor PT123-38 turns off, the node J121-38 goes low, and the high-level data Q is output immediately from the inverter INV122-38.
Note that the level of the data at the nodes J121-38 is maintained even when the clock signal CK is switched to a low level by the cross latch of the inverters INV123-38 and INV124-38.
[0333]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0334]
According to the thirty-ninth embodiment, the second stage latch 12-38 is provided with a circuit for transmitting the output signal change of the first stage latch to the final output signal in a short time. In addition to the effect of the embodiment, a high level can be output more quickly than a conventional circuit, so that high-speed operation is possible.
[0335]
40th embodiment
FIG. 41 is a circuit diagram showing a fortieth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0336]
The fortieth embodiment is different from the forty-third embodiment in that the second-stage latches 12-39 change the output signal of the first-stage latches 11-35 when the opposite signal is held. At the same time, the circuit configuration is such that the reciprocal signal held in the second-stage latch is invalidated.
More specifically, the inverter INV124-39 constituting the cross latch is constituted by a clocked inverter (Clocked Inverter) connected to nodes / H111 and H112.
[0337]
In this case, for example, assuming that data input signal D is at a high level and inverted signal Db is at a low level, first output node H111 is at a low level and output nodes of inverters INV121-38 of second stage latches 12-39. / H111 is at a high level. At this time, the second output node H112 of the first-stage latches 11-35 is at a high level.
As a result, the NMOS transistor NT121-38 turns on, the PMOS transistor PT123-38 turns off, and the node J121-38 goes low.
At this time, the clocked inverters INV124-39 cannot output a high level, and the high-level data Q is output immediately from the inverters INV122-38.
Therefore, high-level data Q is output from inverters INV 122-38 promptly without preventing nodes J121-38 from changing to low level.
The data at the nodes J121-38 is held at the low level even when the clock signal CK is switched to the low level by the cross latch between the inverters INV123-38 and INV124-39.
[0338]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation reverse to the above-described operation is performed. Here, the detailed description is omitted.
[0339]
According to the forty-first embodiment, in addition to the effects of the thirty-ninth embodiment, high-level data can be output more quickly than in a conventional circuit, so that high-speed operation is possible.
[0340]
【The invention's effect】
As described above, according to the present invention, when the input data signal does not change (when the level of the input signal to the first-stage latch and the level of the output signal of the second-stage latch match), Since charge is not charged in the first stage by the clock signal, the power consumption of the clock system can be significantly reduced.
Further, according to the present invention, there is an advantage that high-speed operation can be realized without depending on a circuit design technique, and power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 2 is a timing chart for explaining the operation of the D-type flip-flop in FIG.
FIG. 3 is a circuit diagram showing a second embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 4 is a circuit diagram showing a third embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 5 is a circuit diagram showing a fourth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 6 is a circuit diagram showing a fifth embodiment of the sense amplifier type D flip-flop according to the present invention.
FIG. 7 is a circuit diagram showing a sixth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 8 is a circuit diagram showing a seventh embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 9 is a circuit diagram showing an eighth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 10 is a circuit diagram showing a ninth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 11 is a circuit diagram showing a tenth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 12 is a circuit diagram showing an eleventh embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 13 is a circuit diagram showing a twelfth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 14 is a circuit diagram showing a thirteenth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 15 is a circuit diagram showing a sense amplifier D-type flip-flop according to a fourteenth embodiment of the present invention;
FIG. 16 is a circuit diagram showing a sense amplifier D-type flip-flop according to a fifteenth embodiment of the present invention;
FIG. 17 is a circuit diagram showing a sense amplifier type D flip-flop according to a sixteenth embodiment of the present invention;
FIG. 18 is a circuit diagram showing a seventeenth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 19 is a circuit diagram illustrating a sense amplifier D-type flip-flop according to an eighteenth embodiment of the present invention;
FIG. 20 is a circuit diagram showing a nineteenth embodiment of the sense amplifier type D flip-flop according to the present invention.
FIG. 21 is a circuit diagram showing a twentieth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 22 is a circuit diagram showing a twenty-first embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 23 is a circuit diagram showing a sense amplifier D-type flip-flop according to a twenty-second embodiment of the present invention.
FIG. 24 is a circuit diagram showing a twenty-third embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 25 is a circuit diagram illustrating a sense amplifier D-type flip-flop according to a twenty-fourth embodiment of the present invention;
FIG. 26 is a circuit diagram showing a twenty-fifth embodiment of the sense amplifier type D flip-flop according to the present invention.
FIG. 27 is a circuit diagram showing a twenty-sixth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 28 is a circuit diagram showing a twenty-seventh embodiment of the sense amplifier D-type flip-flop according to the present invention.
FIG. 29 is a circuit diagram showing a twenty-eighth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 30 is a circuit diagram showing a twenty-ninth embodiment of a sense amplifier type D flip-flop according to the present invention.
FIG. 31 is a circuit diagram illustrating a sense amplifier D-type flip-flop according to a thirtieth embodiment of the present invention;
FIG. 32 is a circuit diagram showing a thirty-first embodiment of the sense amplifier type D flip-flop according to the present invention.
FIG. 33 is a circuit diagram showing a 32nd embodiment of the sense amplifier type D flip-flop according to the present invention;
FIG. 34 is a circuit diagram showing a sense amplifier D-type flip-flop according to a thirty-third embodiment of the present invention;
FIG. 35 is a circuit diagram showing a 34th embodiment of the sense amplifier type D flip-flop according to the present invention;
FIG. 36 is a circuit diagram showing a 35th embodiment of the sense amplifier type D flip-flop according to the present invention;
FIG. 37 is a circuit diagram showing a 36th embodiment of the sense amplifier type D flip-flop according to the present invention;
FIG. 38 is a circuit diagram showing a 37th embodiment of the sense amplifier type D flip-flop according to the present invention;
FIG. 39 is a circuit diagram showing a 38th embodiment of the sense amplifier type D flip-flop according to the present invention;
FIG. 40 is a circuit diagram showing a sense amplifier D-type flip-flop according to a thirty-ninth embodiment of the present invention;
FIG. 41 is a circuit diagram illustrating a sense amplifier D-type flip-flop according to a fortieth embodiment of the present invention.
FIG. 42 is a circuit diagram showing a first configuration example of a conventional sense amplifier type D flip-flop.
FIG. 43 is a timing chart for explaining the operation of the D-type flip-flop in FIG. 42;
FIG. 44 is a circuit diagram showing a second configuration example of a conventional sense amplifier type D flip-flop.
[Explanation of symbols]
10, 10-1 to 10-39 ... sense amplifier type D flip-flop, 11, 11-5, 11-10, 11-15, 11-20, 11-25, 11-30, 11-35 ... first Stage latches, 12, 12-1 to 12-39,... Second stage latches, PT111 to PT123, PT212 to PT213,... PMOS transistors, NT111 to NT120, NT211 to NT219,. SP212: second signal path, NA121, NA122, NA121-2 to NA124-37: NAND gate, INV121-1 to INV124-39, inverter, 111, 200, 210, 215, 220, 225, 230, 235, latch Unit, 112... Pre-setting unit.

Claims (27)

A first-stage latch for taking in data input when the synchronization signal having the first and second potential levels is at the second potential level, and a second-stage latch for latching the latch data of the first-stage latch And a flip-flop comprising
The first stage latch includes:
A first output node;
A second output node;
A first intermediate node;
A second intermediate node;
A third intermediate node;
Pre-setting means capable of charging the first output node and the second output node when the synchronization signal is at the first potential level and setting the second output node to the second potential level;
The second output node conducts when the first output level is at the first potential level, connects the first output node to a second potential source, and maintains the non-conduction state at the second potential level. 1 switching means;
The first output node is conductive when the first output level is at the first potential level, connects the second output node to a second potential source, and is kept non-conductive at the second potential level. 2 switching means;
Connected between the first output node and the first intermediate node, held in a non-conductive state when the second output node is at a first potential level, and Third switching means for conducting;
Connected between the second output node and the second intermediate node, held in a non-conductive state when the first output node is at a first potential level, and Fourth switching means for conducting;
A third node, which is connected between the first intermediate node and the third intermediate node, is held in a non-conductive state when the data input signal is at the first potential level and is conductive when the data input signal is at the second potential level 5 switching means;
It is connected between the second intermediate node and the third intermediate node, is held in a non-conductive state when the inverted signal of the data input signal is at the first potential level, and is held when the inverted signal of the data input signal is at the second potential level. Sixth switching means for conducting,
Seventh switching means which is connected between the third intermediate node and a reference potential, is kept non-conductive when the synchronization signal is at the first potential level, and is conductive when it is at the second potential level When,
A connection unit that includes a resistance component and connects the first intermediate node and the second intermediate node;
The pre-setting means, when the levels of the input data input signal and the inverted signal do not change, keeps the first output node and the second output node even if the synchronization signal is at the first potential level. A flip-flop that does not charge the output node. The second-stage latch holds, at a first node and a second node, non-inverted data and inverted data that take the first potential level and the second potential level complementarily,
The pre-setting means,
Eighth and ninth switching elements that are turned on when the synchronization signal is at the first potential level and are kept off when the synchronization signal is at the second potential level;
Tenth and eleventh switching elements that conduct when the data input signal is at the first potential level and are kept in a non-conductive state when the data input signal is at the second potential level;
A twelfth and a thirteenth switching element, which are turned on when the inverted signal of the data input signal is at the first potential level and are kept off when the inverted signal is at the second potential level;
Fourteenth and fifteenth switching elements that conduct when the first node of the second-stage latch is at the first potential level and are kept non-conductive when the second node is at the second potential level;
Sixteenth and seventeenth switching elements that conduct when the second node of the second-stage latch is at the first potential level and are kept off when the second node is at the second potential level;
An eighteenth switching element which is turned on when the data input signal is at the second potential level and is kept off when at the first potential level;
A nineteenth switching element that is turned on when the inverted signal of the data input signal is at the second potential level and is kept off when the inverted signal is at the first potential level;
A twentieth switching element which conducts when a first node of the second-stage latch is at a second potential level and is kept in a non-conductive state when the first node is at the first potential level;
A twenty-first switching element that is conductive when a second node of the second-stage latch is at a second potential level and is kept in a non-conductive state when the second node is at the first potential level;
The eighth switching element is connected to the first output node, and the tenth and sixteenth switching elements are connected in series between the eighth switching element and the second potential source. Twelfth and fourteenth switching elements are connected in parallel with the tenth and sixteenth switching elements between the eighth switching element and the second potential source, and are connected to the first output node and The eighteenth and twentieth switching elements are connected in series with a reference potential,
The ninth switching element is connected to the second output node, and the thirteenth and fifteenth switching elements are connected in series between the ninth switching element and the second potential source. Eleventh and seventeenth switching elements are connected in parallel to the thirteenth and fifteenth switching elements between the ninth switching element and the second potential source, and are connected to the second output node. 2. The flip-flop according to claim 1, wherein said nineteenth and twenty-first switching elements are connected in series between said reference potential and said reference potential. 2. The flip-flop according to claim 1, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first-stage latch changes and a signal opposite to the second-stage latch is held, the second-stage latch simultaneously outputs the second-stage latch when the output signal of the first-stage latch changes. 4. The flip-flop according to claim 3, further comprising a circuit for invalidating the reciprocal signal held in the stage latch and transmitting the inverted signal to a final output signal. A first-stage latch for taking in data input when the synchronization signal having the first and second potential levels is at the second potential level, and a second-stage latch for latching the latch data of the first-stage latch And a flip-flop comprising
The first stage latch includes:
A first output node;
A second output node;
First and second intermediate nodes sequentially formed on the first signal path between the first output node and the reference potential toward the reference potential;
Third and fourth intermediate nodes sequentially formed on the second signal path between the second output node and the reference potential toward the reference potential;
Pre-setting means for setting the first output node and the second output node to a second potential level when the synchronization signal is at the first potential level;
The second output node conducts when the first output level is at the first potential level, connects the first output node to a second potential source, and maintains the non-conduction state at the second potential level. 1 switching means;
The first output node is conductive when the first output level is at the first potential level, connects the second output node to a second potential source, and is kept non-conductive at the second potential level. 2 switching means;
Third and fourth switching means which are kept non-conductive when the synchronization signal is at a first potential level and are conductive when at the second potential level;
Fifth switching means which is kept off when the data input signal is at the first potential level and is conductive when it is at the second potential level;
Sixth switching means which is kept non-conductive when the inverted signal of the data input signal is at a first potential level and is conductive when it is at a second potential level;
A seventh switching means which is kept non-conductive when the first output node is at the first potential level and is conductive when it is at the second potential level;
Eighth switching means which is kept off when the second output node is at the first potential level and is conductive when it is at the second potential level;
Has,
The third, fifth, and seventh switching means are connected in series to the first signal path, and at least the third switching means includes a first output node and a first intermediate node. Or between the first intermediate node and the second intermediate node,
The fourth, sixth, and eighth switching means are connected in series to the second signal path, and at least the fourth switching means is connected to the second output node and the third intermediate node. Or between the third intermediate node and the fourth intermediate node,
The pre-setting means, when the levels of the input data input signal and the inverted signal do not change, keeps the first output node and the second output node even if the synchronization signal is at the first potential level. A flip-flop that does not charge the output node. The second-stage latch holds, at a first node and a second node, non-inverted data and inverted data that take the first potential level and the second potential level complementarily,
The pre-setting means,
Ninth and tenth switching elements that conduct when the synchronization signal is at the first potential level and are kept non-conductive when the synchronization signal is at the second potential level;
Eleventh and twelfth switching elements that conduct when the data input signal is at the first potential level and are kept non-conductive when the data input signal is at the second potential level;
Thirteenth and fourteenth switching elements, which conduct when the inverted signal of the data input signal is at the first potential level and are kept in a non-conductive state when the inverted signal is at the second potential level;
Fifteenth and sixteenth switching elements that conduct when the first node of the second-stage latch is at the first potential level and are kept non-conductive when the second node is at the second potential level;
Seventeenth and eighteenth switching elements, which conduct when the second node of the second-stage latch is at the first potential level, and are kept non-conductive when the second node is at the second potential level;
A nineteenth switching element which is turned on when the data input signal is at the second potential level and is kept off when at the first potential level;
A twentieth switching element which conducts when the inverted signal of the data input signal is at the second potential level and is kept in a non-conductive state when the inverted signal is at the first potential level;
A twenty-first switching element that conducts when a first node of the second-stage latch is at a second potential level and is kept off when the first node is at the first potential level;
A second switching element that is conductive when the second node of the second-stage latch is at a second potential level and is kept in a non-conductive state when the second node is at the first potential level;
The ninth switching element is connected to the first output node, and the eleventh and seventeenth switching elements are connected in series between the ninth switching element and the second potential source. Thirteenth and fifteenth switching elements are connected in parallel with the eleventh and seventeenth switching elements between the ninth switching element and the second potential source, and are connected to the first output node and The nineteenth and twenty-first switching elements are connected in series between a reference potential and
The tenth switching element is connected to the second output node, and the fourteenth and sixteenth switching elements are connected in series between the tenth switching element and the second potential source. Twelfth and eighteenth switching elements are connected in parallel with the fourteenth and sixteenth switching elements between the tenth switching element and the second potential source, and are connected to the second output node. 6. The flip-flop according to claim 5, wherein said twentieth and twenty-second switching elements are connected in series between said reference potential and said reference potential. The third switching means is connected between the first output node and the first intermediate node, and the fifth switching means is connected between the first intermediate node and the second intermediate node. And the seventh switching means is connected between the second intermediate node and the reference potential,
The fourth switching means is connected between the second output node and the third intermediate node, and the sixth switching means is connected between the third intermediate node and the fourth intermediate node. And the eighth switching means is connected between the fourth intermediate node and the reference potential,
The first stage latch further includes:
A ninth state in which the second output node conducts when the second potential level is at the second potential level and connects the first intermediate node to the reference potential, and is kept non-conductive when the second output node is at the first potential level Switching means;
The first output node conducts when the second potential level is at the second potential level, connects the third intermediate node to the reference potential, and maintains the non-conduction state at the first potential level. 6. The flip-flop according to claim 5, comprising switching means. 8. The flip-flop according to claim 7, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first-stage latch changes and a signal opposite to the second-stage latch is held, the second-stage latch simultaneously outputs the second-stage latch when the output signal of the first-stage latch changes. 9. The flip-flop according to claim 8, further comprising a circuit for invalidating the reciprocal signal held in the stage latch and transmitting the signal to a final output signal. The third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected between the first intermediate node and the second intermediate node. , The fifth switching means is connected between the second intermediate node and the reference potential,
The fourth switching means is connected between the second output node and the third intermediate node, and the eighth switching means is connected between the third intermediate node and the fourth intermediate node. , The sixth switching means is connected between the fourth intermediate node and the reference potential,
The first stage latch further includes:
A ninth state in which the second output node conducts when the second potential level is at the second potential level, connects the second intermediate node to the reference potential, and is kept in a non-conductive state at the first potential level Switching means;
The first output node conducts when the second potential level is at the second potential level, connects the fourth intermediate node to the reference potential, and maintains the non-conduction state at the first potential level. 6. The flip-flop according to claim 5, comprising switching means. 11. The flip-flop according to claim 10, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first-stage latch changes and a signal opposite to the second-stage latch is held, the second-stage latch simultaneously outputs the second-stage latch when the output signal of the first-stage latch changes. 12. The flip-flop according to claim 11, further comprising a circuit for invalidating the reciprocal signal held in the stage latch and transmitting the inverted signal to a final output signal. The third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected between the first intermediate node and the second intermediate node. , The fifth switching means is connected between the second intermediate node and the reference potential,
The fourth switching means is connected between the second output node and the third intermediate node, and the eighth switching means is connected between the third intermediate node and the fourth intermediate node. , The sixth switching means is connected between the fourth intermediate node and the reference potential,
The first stage latch further includes:
A ninth state in which the second output node conducts when the second potential level is at the second potential level and connects the first intermediate node to the reference potential, and is kept non-conductive when the second output node is at the first potential level Switching means;
The first output node conducts when the second potential level is at the second potential level, connects the third intermediate node to the reference potential, and maintains the non-conduction state at the first potential level. 6. The flip-flop according to claim 5, comprising switching means. 14. The flip-flop according to claim 13, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first-stage latch changes and a signal opposite to the second-stage latch is held, the second-stage latch simultaneously outputs the second-stage latch when the output signal of the first-stage latch changes. 15. The flip-flop according to claim 14, further comprising a circuit for invalidating the reciprocal signal held in the stage latch and transmitting the inverted signal to a final output signal. The third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected between the first intermediate node and the second intermediate node. , The fifth switching means is connected between the second intermediate node and the reference potential,
The fourth switching means is connected between the second output node and the third intermediate node, and the eighth switching means is connected between the third intermediate node and the fourth intermediate node. , The sixth switching means is connected between the fourth intermediate node and the reference potential,
The first stage latch further includes:
The second output node conducts when the second output node is at the second potential level, connects the second intermediate node and the fourth intermediate node, and is kept in a non-conductive state when the second output node is at the first potential level. Ninth switching means,
The first output node is conductive when the second output node is at the second potential level, connects the second intermediate node and the fourth intermediate node, and is kept non-conductive when the first output node is at the first potential level. The flip-flop according to claim 5, further comprising: tenth switching means. 17. The flip-flop according to claim 16, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first-stage latch changes and a signal opposite to the second-stage latch is held, the second-stage latch simultaneously outputs the second-stage latch when the output signal of the first-stage latch changes. 18. The flip-flop according to claim 17, further comprising a circuit for invalidating the reciprocal signal held in the stage latch and transmitting the inverted signal to a final output signal. The third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected between the first intermediate node and the second intermediate node. , The fifth switching means is connected between the second intermediate node and the reference potential,
The fourth switching means is connected between the second output node and the third intermediate node, and the eighth switching means is connected between the third intermediate node and the fourth intermediate node. , The sixth switching means is connected between the fourth intermediate node and the reference potential,
The first stage latch further includes:
6. The flip-flop according to claim 5, further comprising connection means including a resistance component and connecting said second intermediate node and said fourth intermediate node. 20. The flip-flop according to claim 19, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first-stage latch changes and a signal opposite to the second-stage latch is held, the second-stage latch simultaneously outputs the second-stage latch when the output signal of the first-stage latch changes. 21. The flip-flop according to claim 20, further comprising a circuit for invalidating the reciprocal signal held in the stage latch and transmitting the inverted signal to a final output signal. The fifth switching means is connected between the first output node and the first intermediate node, and the third switching means is connected between the first intermediate node and the second intermediate node. And the seventh switching means is connected between the second intermediate node and the reference potential,
The sixth switching means is connected between the second output node and the third intermediate node, and the fourth switching means is connected between the third intermediate node and the fourth intermediate node. And the eighth switching means is connected between the fourth intermediate node and the reference potential,
The first stage latch further includes:
The second output node is conductive when the second potential level is at the second potential level to connect the first output node to the first intermediate node, and is kept in a non-conductive state when the second output node is at the first potential level. Ninth switching means,
The first output node is conductive when the second potential level is at the second potential level to connect the second output node to the third intermediate node, and is kept non-conductive at the first potential level. The flip-flop according to claim 5, further comprising: tenth switching means. 23. The flip-flop according to claim 22, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first-stage latch changes and a signal opposite to the second-stage latch is held, the second-stage latch simultaneously outputs the second-stage latch when the output signal of the first-stage latch changes. 24. The flip-flop according to claim 23, further comprising a circuit for invalidating the reciprocal signal held in the stage latch and transmitting the inverted signal to a final output signal. The fifth switching means is connected between the first output node and the first intermediate node, and the third switching means is connected between the first intermediate node and the second intermediate node. And the seventh switching means is connected between the second intermediate node and the reference potential,
The sixth switching means is connected between the second output node and the third intermediate node, and the fourth switching means is connected between the third intermediate node and the fourth intermediate node. And the eighth switching means is connected between the fourth intermediate node and the reference potential,
The first stage latch further includes:
6. The flip-flop according to claim 5, further comprising connection means including a resistance component and connecting said second intermediate node and said fourth intermediate node. 26. The flip-flop according to claim 25, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first-stage latch changes and a signal opposite to the second-stage latch is held, the second-stage latch simultaneously outputs the second-stage latch when the output signal of the first-stage latch changes. 27. The flip-flop according to claim 26, further comprising a circuit for invalidating the reciprocal signal held in the stage latch and transmitting the inverted signal to a final output signal.

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