JP4122970B2 - flip flop - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a flip-flop, and more particularly to an improvement of a flip-flop using a sense amplifier.
[0002]
[Prior art]
Recent LSIs are required to operate at high speeds in the GHz level, operate at low power consumption, or both. In these LSIs, flip-flop circuits are widely used not only for the scan mode but also for pipeline control for speeding up.
The flip-flop is one of the important factors that determine the operating frequency and power consumption of the LSI.
[0003]
However, in the high-speed operation, the time consumed by the flip-flop circuit, specifically, the ratio of the setup time (set up time) and the valid delay (valid delay) to one clock cycle is very large. It is an obstacle. In the low power consumption operation, the flip-flop circuit operates with a clock signal (synchronization signal) such as a system clock, and the power consumption in the clock signal system is very large with respect to the power consumption of the entire LSI. It is an obstacle to consumption.
[0004]
Thus, various methods have been proposed until now to increase the speed of flip-flops and reduce power consumption.
As this high-speed operation flip-flop, “Sense Amplifier-Based Flip-flop” (for example, Non-Patent Document 1) is a D-type flip-flop announced recently.
Hereinafter, this D-type flip-flop is referred to as a “sense amplifier type D-type flip-flop (SAFF)”.
[0005]
In this sense amplifier type D flip-flop, a differential sense amplifier applying an inverter loop is mounted on the first stage latch (master side latch), an RS latch is mounted on the second stage latch (slave side latch), This is combined to realize a D-type flip-flop.
[0006]
FIG. 42 is a circuit diagram showing a configuration example of a conventional sense amplifier type D flip-flop.
As shown in FIG. 42, the sense amplifier D-type flip-flop 1 is configured by cascading a first stage latch (master side latch) 2 and a second stage latch (slave side latch) 3.
[0007]
The first-stage latch 2 includes p-channel MOS (PMOS) transistors PT21 to PT24 and n-channel MOS (NMOS) transistors NT21 to NT26.
[0008]
The sources of the PMOS transistors PT21 to PT24 are the power supply voltage V_DDConnected to the supply line.
The drains of the PMOS transistors PT21 and PT22 are connected to the drain of the NMOS transistor NT21, and an output node H1 is configured by the connection point. The output node H1 is connected to the gate of the PMOS transistor PT23 and the gate of the NMOS transistor NT22.
The drains of the PMOS transistors PT23 and PT24 are connected to the drain of the NMOS transistor NT22, and an output node H2 is configured by the connection point. The output node H2 is connected to the gate of the PMOS transistor PT22 and the gate of the NMOS transistor NT21.
The gates of the PMOS transistors PT21 and PT24 are connected to the input line of the clock signal (synchronization signal) CK.
[0009]
The source of the NMOS transistor NT21 is connected to the drain of the NMOS transistor NT23, and an intermediate node F1 is constituted by the connection point. The source of the NMOS transistor NT22 is connected to the drain of the NMOS transistor NT24, and the connection point forms an intermediate node F2.
The sources of the NMOS transistor NT23 and the NMOS transistor NT24 are connected to each other, and an intermediate node G1 is configured by the connection point. The intermediate node G1 is connected to the drain of the NMOS transistor NT25, and the source of the NMOS transistor NT25 is connected to the ground potential GND.
The sources and drains of the NMOS transistor NT26 are connected to the nodes F1 and F2, respectively.
The gate of the NMOS transistor NT23 is connected to the supply line of the data input signal D, and the gate of the NMOS transistor NT24 is connected to the supply line of the inverted signal Db of the data input signal D. The gate of the NMOS transistor NT25 is connected to the supply line of the clock signal CK, and the gate of the NMOS transistor NT26 is the power supply voltage V_DDConnected to the supply line.
[0010]
The second stage latch 3 is composed of two-input NAND gates NA31 and NA32.
The first input terminal of the NAND gate NA31 is connected to the output node H1 of the first stage latch 2, and the second input terminal is connected to the output terminal of the NAND gate NA32.
The first input terminal of the NAND gate NA32 is connected to the node H2 of the first stage latch 2, and the second input terminal is connected to the output terminal of the NAMD gate NA31.
The second-stage latch 3 outputs data Q from the NAND gate NA31 and outputs inverted data Qb from the NAND gate NA32.
[0011]
Next, the operation of the conventional sense amplifier type D flip-flop 1 will be described with reference to the timing chart of FIG.
[0012]
The flip-flop 1 takes in the value of the data input signal D in synchronization with the rising edge of the clock signal CK, and outputs data Q and inverted data Qb. The value is held for one cycle of the clock signal CK.
[0013]
During a period when the clock signal CK is at a low level (logic 0 level), the PMOS transistors PT21 and PT24 are turned on, and the NMOS transistor NT25 is cut off.
[0014]
During the period when the clock signal CK is at a low level, the PMOS transistors PT21 and PT24 equivalently behave as resistors, and the nodes H1 and H2 pass through these as shown in FIGS. 43 (A), (C) and (E), It is precharged to a complete logic 1 potential (high level).
Then, the PMOS transistors PT22 and PT23 are cut off. The NMOS transistors NT21 and NT22 equivalently behave as diodes because the gate terminal and the drain terminal have the same potential.
Therefore, the power supply voltage is V_DD[V] If the threshold value of the NMOS transistor is Vtn, the potentials of the nodes F1 and F2 at this time are (V) as shown in FIGS._DD-Vtn) [V]. That is, charges flow from the output nodes H1 and H2 side to the intermediate nodes F1 and F2.
[0015]
As described above, when the clock signal CK is at the low level, the output nodes H1 and H2 of the first stage latch 2 are both at the logic 1 high level, which holds the NAND-RS latch of the second stage latch 3. Operate as a mode.
[0016]
When the clock signal CK becomes high level, the PMOS transistors PT21 and PT24 are cut off, the NMOS transistor NT25 is turned on, and the sense amplifier operates.
Depending on the state of the data input signal D and its inverted signal Dd, one of the NMOS transistor NT23 and the NMOS transistor NT24 is cut off.
Therefore, there is a difference between the conduction resistances of the intermediate nodes F1 and F2 with respect to the ground.
[0017]
For example, assuming that the NMOS transistor NT24 is cut off, the conduction resistance of the intermediate node F1 with respect to the ground is the sum of the resistance values of the NMOS transistor NT23 and the NMOS transistor NT25, whereas in the case of the intermediate node F2. Is the sum of the resistance values of the NMOS transistor NT26, NMOS transistor NT23 and NMOS transistor NT25.
Such a difference in conduction resistance appears in the discharge rate of charges on the output nodes H1 and H2. In the previous example, since the conduction resistance of the node F1 with respect to the ground is smaller, the charge of the node H1 is discharged more quickly. At this time, the charge on the node H2 is also discharged.
However, when the potential of the output node H1 is lowered, the PMOS transistor PT23 is turned on and the NMOS transistor NT22 is cut off, and the potential of the lowered node H2 is raised to obtain a complete logic 1 potential again.
[0018]
In this way, a steady state is established in the inverter loop composed of the PMOS transistors PT22 and PT23 and the NMOS transistors NT21 and NT22.
Thereafter, even if the data input signal D and its inverted signal Dd change and the transistor to be cut off changes from the NMOS transistor NT24 to the NMOS transistor NT23, this steady state is not destroyed.
This is because any one of the NMOS transistors NT23 and NT24 is always on, and both the intermediate nodes F1 and F2 always have a path to the ground through the NMOS transistor NT26. This is because it is connected to the ground.
[0019]
In this way, as shown in FIGS. 43A, 43C, and 43E, one of the output nodes H, H2 of the first-stage latch 2 is set to logic 0 during the period when the clock signal is at the high level. Become.
In response, the RS latch of the second stage latch 3 is set or reset, and values corresponding to the input data appear at the outputs Q and Qd.
[0020]
[Non-Patent Document 1]
J. et al. Montanaro, et al. "A 160 MHz 32b 0.5 W CMOS RlSC Microprocessor," ISSCC Digest of Technical Papers, pp. 214-215, Feb. , 1996.
[0021]
[Problems to be solved by the invention]
However, the above-described sense amplifier type D flip-flop 1 can make maximum use of complementary input and complementary output circuit configurations such as a data path circuit, but is not suitable for a random logic circuit such as an ASIC.
When all circuit methods are considered, the above-described sense amplifier type D flip-flop 1 has the following problems.
[0022]
First, if only one of the data input signal D or its inverted signal Db is used as an input, the sense amplifier type D flip-flop 1 has an advantage that the setup time which is the largest factor capable of high-speed operation is short. Is damaged.
[0023]
Next, in FIG. 42, the outputs Q and Qb are connected to the inputs of the NAND gates NA31 and NA32, but when the output signal wiring is affected by crosstalk or the like, the value changes and is held as it is. There is a risk of being.
In order to solve this problem, as shown in FIG. 44, it is conceivable to provide inverters INV31 and INV32 on the output side of NAND gates NA31 and NA32. However, simply providing an inverter increases the valid delay.
[0024]
Finally, charge and discharge of charges at each node of the first stage latch 2 is performed. In each of the nodes H1, H2, F1, F2, and G1 in FIG. 42, the charge of each clock is charged regardless of the change in the logic level of the data input signal D and its inverted signal Db.
For example, when the data input signal D is at a high level, the charges at the nodes H1, F1, F2, and G1 are discharged. When the inverted signal Fb is at a high level, the signals at the nodes at H2, F1, F2, and G1 are discharged. The charge is discharged.
Charge charging time is one of the factors affecting the setup delay, and discharging time is one of the factors that affect the valid delay, and is also one of the factors that increase the power consumption due to the clock signal.
For the above reasons, the sense amplifier type D flip-flop 1 described above depends on the circuit design method and loses the advantage of high-speed operation.
[0025]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a flip-flop capable of reducing power consumption and realizing high-speed operation without depending on a circuit design method.
[0026]
[Means for Solving the Problems]
  In order to achieve the above object, a first aspect of the present invention is a first-stage latch that takes in data that is input when a synchronization signal that takes the first and second potential levels is at the second potential level. A flip-flop including a second stage latch for latching latch data of the first stage latch, wherein the first stage latch includes a first output node, a second output node, and a first intermediate node. A second node, a second intermediate node, a third intermediate node, and the second output node by charging the first output node and the second output node when the synchronization signal is at a first potential level. Pre-setting means that can be set to a potential level of the second output node, and the second output node is conductive when the second output node is at the first potential level.Potential levelA first switching means connected to a potential source and held in a non-conductive state at a second potential level; and conductive when the first output node is at a first potential level; Output nodeOf the second potential levelA second switching means connected to a potential source and held in a non-conductive state at a second potential level; connected between the first output node and the first intermediate node; Third switching means which is held in a non-conductive state when the two output nodes are at the first potential level and is conductive when the second output node is at the second potential level; the second output node; and the second intermediate node A fourth switching means connected between the first output node and the first output node is held in a non-conductive state when the first output node is at a first potential level, and is turned on when the first output node is at a second potential level; Fifth switching means connected between the intermediate node and the third intermediate node, held in a non-conductive state when the data input signal is at the first potential level, and conductive when at the second potential level. And the second intermediate node and the above A sixth switching means connected to the intermediate node of the third node, held in a non-conductive state when the inverted signal of the data input signal is at the first potential level, and conductive when at the second potential level; Seventh switching means connected between the third intermediate node and a reference potential, held in a non-conductive state when the synchronization signal is at the first potential level, and conductive when at the second potential level. And connecting means for connecting the first intermediate node and the second intermediate node, including a resistance component, and the pre-setting means,An output terminal of a first NAND circuit which is supplied with the data input signal and a signal from the second output terminal of the second latch and performs a logical operation; an inverted signal of the data input signal; and the second latch The first NAND circuit is connected in parallel to the output terminal of the second NAND circuit which is supplied with a signal from the first output terminal and logically operated, and the parallel connection point is driven through the first switching circuit driven by the synchronization signal. The data input signal and the signal from the first output terminal of the second latch are connected to the output terminal of the third NAND circuit that performs a logical operation, and the output terminal of the third NAND circuit is connected to the first NAND terminal. An output terminal of a fourth NAND circuit connected to one output node and logically operated by the signal from the data input signal and the second output terminal of the second latch, and the data input signal Inverted signal and The second latch circuit is connected in parallel to the output terminal of the fifth NAND circuit which is supplied with a signal from the first output terminal of the second latch and logically operates, and the parallel connection point is driven by the synchronization signal. Through the switching circuit, the data input signal and the signal from the first output terminal of the second latch are connected to the output terminal of a sixth NAND circuit that performs a logical operation. An output terminal is connected to the second output node.
[0027]
Preferably, the second stage latch holds normal data and inverted data that take the first potential level and the second potential level in a complementary manner at the first node and the second node, and The presetting means is turned on when the synchronization signal is at the first potential level, and is held in a non-conductive state when the synchronization signal is at the second potential level, and the data input signal Are turned on when the first potential level is set, and when the second potential level is turned on, the tenth and eleventh switching elements held in the non-conductive state, and the inverted signal of the data input signal are the first potential. The twelfth and thirteenth switching elements that are conductive at the level and held in the non-conductive state at the second potential level, and the first node of the second-stage latch is at the first potential level. When conducting, the above The fourteenth and fifteenth switching elements held in a non-conducting state at the potential level of the second stage and the second node of the second-stage latch are conducted at the first potential level, and the second potential The sixteenth and seventeenth switching elements held in a non-conducting state at the time of the level are conducted when the data input signal is at the second potential level, and are brought into the non-conducting state at the first potential level. The eighteenth switching element to be held and the nineteenth switching element to be turned on when the inverted signal of the data input signal is at the second potential level and held in the non-conductive state at the first potential level. A twentieth switching element that conducts when the first node of the second-stage latch is at the second potential level and is held non-conductive when the first node is at the first potential level; Stage latch And a 21st switching element that is conductive when the second node is at the second potential level and is held in a non-conductive state when the second node is at the first potential level. The eighth switching element is connected, the tenth and sixteenth switching elements are connected in series between the eighth switching element and the second potential source, and the twelfth and fourteenth switching elements are connected. An element is connected in parallel with the tenth and sixteenth switching elements between the eighth switching element and the second potential source, and the element is connected between the first output node and a reference potential. The eighteenth and twentieth switching elements are connected in series, the ninth switching element is connected to the second output node, and between the ninth switching element and the second potential source. The thirteenth and fifteenth switching elements are connected in series, and the eleventh and seventeenth switching elements are connected between the ninth switching element and the second potential source. The nineteenth and twenty-first switching elements are connected in series to the switching element, and are connected in series between the second output node and the reference potential.
[0028]
  According to a second aspect of the present invention, there is provided a first stage latch for capturing data inputted when a synchronizing signal having the first and second potential levels is at the second potential level, and the first stage latch A flip-flop including a second stage latch for latching latch data, wherein the first stage latch includes a first output node, a second output node, the first output node and a reference potential The first and second intermediate nodes formed in this order in the first signal path toward the reference potential, and the second signal path between the second output node and the reference potential toward the reference potential Third and fourth intermediate nodes formed in sequence and pre-setting means for setting the first output node and the second output node to the second potential level when the synchronization signal is at the first potential level And the second output node First conducting the first output node a second when the potential levelPotential levelA first switching means connected to a potential source and held in a non-conductive state at a second potential level; and conductive when the first output node is at a first potential level; Output nodeOf the second potential levelA second switching means connected to the potential source and held in a non-conductive state at the second potential level; and held in a non-conductive state when the synchronization signal is at the first potential level; Third and fourth switching means that conduct when at the potential level, and fifth switching that is held in the non-conducting state when the data input signal is at the first potential level and is conducted when at the second potential level Means, a sixth switching means which is held in a non-conductive state when the inverted signal of the data input signal is at a first potential level and is conductive when at a second potential level, and the first output node is A seventh switching means which is held in a non-conductive state when at the first potential level and is conductive when at the second potential level; and a non-conductive state when the second output node is at the first potential level Held in the second An eighth switching means that conducts at a potential level of the first, the third, the fifth, and the seventh switching means are connected in series to the first signal path, and at least the third switching means. The switching means is connected between the first output node and the first intermediate node, or between the first intermediate node and the second intermediate node, and the fourth, sixth, And the eighth switching means are connected in series to the second signal path, and at least the fourth switching means is between the second output node and the third intermediate node or the third switching node. Between the intermediate node and the fourth intermediate node, and the pre-setting meansAn output terminal of a first NAND circuit which is supplied with the data input signal and a signal from the second output terminal of the second latch and performs a logical operation; an inverted signal of the data input signal; and the second latch The first NAND circuit is connected in parallel to the output terminal of the second NAND circuit which is supplied with a signal from the first output terminal and logically operated, and the parallel connection point is driven through the first switching circuit driven by the synchronization signal. The data input signal and the signal from the first output terminal of the second latch are connected to the output terminal of the third NAND circuit that performs a logical operation, and the output terminal of the third NAND circuit is connected to the first NAND terminal. An output terminal of a fourth NAND circuit connected to one output node and logically operated by the signal from the data input signal and the second output terminal of the second latch, and the data input signal Inverted signal and The second latch circuit is connected in parallel to the output terminal of the fifth NAND circuit which is supplied with a signal from the first output terminal of the second latch and logically operates, and the parallel connection point is driven by the synchronization signal. Through the switching circuit, the data input signal and the signal from the first output terminal of the second latch are connected to the output terminal of a sixth NAND circuit that performs a logical operation. An output terminal is connected to the second output node.
[0029]
In the present invention, the third switching means is connected between the first output node and the first intermediate node, and the fifth switching means is the first intermediate node and the second intermediate node. The seventh switching means is connected between the second intermediate node and the reference potential, and the fourth switching means is connected to the second output node and the third intermediate node. And the sixth switching means is connected between the third intermediate node and the fourth intermediate node, and the eighth switching means is connected to the fourth intermediate node and the reference. The first-stage latch is further connected when the second output node is at the second potential level, and connects the first intermediate node to the reference potential; When the potential level is 1 The ninth switching means held in the conductive state is electrically connected to the first output node when the first output node is at the second potential level, and the third intermediate node is connected to the reference potential. And a tenth switching means held in a non-conducting state.
[0030]
In the present invention, the third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected to the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential, and the fourth switching means is connected to the second output node and the third node. The eighth switching means is connected between the third intermediate node and the fourth intermediate node, and the sixth switching means is connected to the fourth intermediate node. The first stage latch is further connected when the second output node is at the second potential level, and connects the second intermediate node to the reference potential. Of the first potential level The ninth switching means held in a non-conducting state at the time, and the first switching node is turned on when the first output node is at the second potential level, and the fourth intermediate node is connected to the reference potential. And a tenth switching means held in a non-conducting state at a potential level of.
[0031]
In the present invention, the third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected to the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential, and the fourth switching means is connected to the second output node and the third node. The eighth switching means is connected between the third intermediate node and the fourth intermediate node, and the sixth switching means is connected to the fourth intermediate node. The first stage latch is further connected when the second output node is at the second potential level, and connects the first intermediate node to the reference potential. Of the first potential level The ninth switching means held in a non-conducting state at the time, and the first switching node is turned on when the first output node is at the second potential level, and the third intermediate node is connected to the reference potential. And a tenth switching means held in a non-conducting state at a potential level of.
[0032]
In the present invention, the third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected to the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential, and the fourth switching means is connected to the second output node and the third node. The eighth switching means is connected between the third intermediate node and the fourth intermediate node, and the sixth switching means is connected to the fourth intermediate node. The first stage latch is connected between the reference potential and the first stage latch is further turned on when the second output node is at a second potential level, and the second intermediate node and the fourth intermediate node. And connect the first power A ninth switching means held in a non-conductive state at a level, and the second switching node and the fourth intermediate node that are turned on when the first output node is at a second potential level; And a tenth switching means which is held in a non-conductive state at the first potential level.
[0033]
In the present invention, the third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is connected to the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential, and the fourth switching means is connected to the second output node and the third node. The eighth switching means is connected between the third intermediate node and the fourth intermediate node, and the sixth switching means is connected to the fourth intermediate node. The first-stage latch is connected between the reference potential and further includes a connection means including a resistance component and connecting the second intermediate node and the fourth intermediate node.
[0034]
According to the present invention, the fifth switching means is connected between the first output node and the first intermediate node, and the third switching means is the first intermediate node and the second intermediate node. The seventh switching means is connected between the second intermediate node and the reference potential, and the sixth switching means is connected to the second output node and the third node. The fourth switching means is connected between the third intermediate node and the fourth intermediate node, and the eighth switching means is connected to the fourth intermediate node. The first stage latch is connected between the reference potential and the first stage latch is further turned on when the second output node is at the second potential level, and the first output node and the first intermediate node. And connect the first power A ninth switching means held in a non-conductive state at a level, and the second output node and the third intermediate node which are turned on when the first output node is at a second potential level; And a tenth switching means which is held in a non-conductive state at the first potential level.
[0035]
In the present invention, the fifth switching means is connected between the first output node and the first intermediate node, and the third switching means is the first intermediate node and the second intermediate node. The seventh switching means is connected between the second intermediate node and the reference potential, and the sixth switching means is connected to the second output node and the third node. The fourth switching means is connected between the third intermediate node and the fourth intermediate node, and the eighth switching means is connected to the fourth intermediate node. The first-stage latch is connected between the reference potential and further includes a connection means including a resistance component and connecting the second intermediate node and the fourth intermediate node.
[0036]
Preferably, the second stage latch includes a circuit for outputting a data signal to be latched by the first stage latch in parallel with the latch processing.
[0037]
Preferably, in the second stage latch, when the output signal level of the first stage latch changes and an opposite signal is held in the second stage latch, simultaneously with the change of the output signal of the first stage latch. And a circuit for invalidating the reciprocal signal held in the second stage latch and transmitting it to the final output signal.
[0038]
According to the present invention, for example, during the period when the synchronization signal is at the first potential level, the third and fourth switching means are in a non-conductive state.
When there is a change in the level of the input data signal, in other words, the level of the second stage latch first node and the level of the data input signal, and the level of the second stage latch second node and the data input When the level of the inverted signal of the signal is different, the pre-setting means charges the first and second output nodes while the synchronization signal is at the first potential level, and the first and second output nodes are charged. Are precharged to a logic 1 second potential level.
At this time, since the third and fourth switching means are in a non-conducting state, no charge is charged in the first intermediate and the third intermediate.
On the other hand, switching elements other than the first and second switching elements are switching elements. The first output node and the second output node become conductive as they are precharged to a high level.
As a result, regardless of the state of the data input signal and the inverted signal, the first and second intermediate nodes are discharged to the first potential level through the corresponding switching elements.
Therefore, charge is charged only to the first output node and the second output node during the period in which the synchronization signal is at the first potential level.
Next, when the synchronization signal becomes a high level, precharging by the pre-setting unit is stopped, and the third and fourth switching units are turned on.
For example, when the data input signal D is supplied to the fifth switching element at the second potential level and the inverted signal Db is supplied to the sixth switching element at the first potential level, the fifth switching element is Conduct. At this time, the sixth switching element remains nonconductive.
As a result, the first signal path is electrically connected from the first output node to the ground potential GND. Therefore, the electric charge charged in the first output node is discharged through each switching element. As a result, the first output node is set to the first potential level, and data of a predetermined level is output from the second-stage latch.
[0039]
If there is no change in the level of the input data signal, in other words, the level of the second-stage latch first node and the level of the data input signal, and the level of the second-stage latch second node and the data input When the level of the inverted signal of the signal is the same, charge is not charged to the first and second output nodes by the pre-setting means even when the synchronization signal is at the first potential level.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment
FIG. 1 is a circuit diagram showing a first embodiment of a sense amplifier type D flip-flop according to the present invention.
[0041]
As shown in FIG. 1, the sense amplifier D-type flip-flop 10 is configured by cascading a first stage latch 11 and a second stage latch 12.
In the following description, the first potential is the ground potential (0 V) level, and the second potential is the power supply voltage V._DDLevel.
[0042]
The first stage latch 11 includes PMOS transistors PT111 to PT122, NMOS transistors NT111 to NT120, a first output node H111, a second output node H112, a first intermediate node F111, a second intermediate node F112, and a third Intermediate node G111.
In this case, the PMOS transistor PT112 constitutes a first switching element, the PMOS transistor PT113 constitutes a second switching element, the NMOS transistor NT111 constitutes a third switching element, and the NMOS transistor NT112 constitutes a fourth switching element. The element is configured, the NMOS transistor NT113 constitutes a fifth switching means, the NMOS transistor NT114 constitutes a sixth switching means, and the NMOS transistor NT115 constitutes a seventh switching means. The NMOS transistor NT116 constitutes a connection means.
[0043]
The PMOS transistor PT112, PT113 and the NMOS transistors NT111 to NT116 constitute a latch unit 111.
Further, a pre-setting unit 112 is configured in the PMOS transistors PT111 and PT114 to PT122 and the NMOS transistors NT117 to NT120.
The PMOS transistor PT111 constitutes an eighth switching element, the PMOS transistor PT114 constitutes a ninth switching element, the PMOS transistor PT115 constitutes a sixteenth switching element, and the PMOS transistor PT116 constitutes a fifteenth switching element. The tenth switching element is configured by the PMOS transistor PT117, the thirteenth switching element is configured by the PMOS transistor PT118, the fourteenth switching element is configured by the PMOS transistor PT119, and the seventeenth switching element is configured by the PMOS transistor PT120. The twelfth switching element is configured by the PMOS transistor PT121, and the PMOS transistor PT121 is configured. The star PT122 constitutes an eleventh switching element, the NMOS transistor NT117 constitutes an eighteenth switching element, the NMOS transistor NT118 constitutes a nineteenth switching element, and the NMOS transistor NT119 constitutes a twentieth switching element. The twenty-first switching element is constituted by the NMOS transistor NT120.
[0044]
The sources of the PMOS transistors PT112, PT113, PT117, PT118, PT121, and PT122 are connected to the power supply voltage V._DDConnected to the supply line.
The drains of the PMOS transistors PT111 and PT112 are connected to the drains of the NMOS transistor NT111 and the NMOS transistor NT117, and the first output node H111 is configured by the connection point. The first output node H111 is connected to the gate of the PMOS transistor PT113 and the gate of the NMOS transistor NT112.
The drains of the PMOS transistors PT113 and PT114 are connected to the drains of the NMOS transistor NT112 and the NMOS transistor NT118, and the connection point constitutes the second output node H112. The second output node H112 is connected to the gate of the PMOS transistor PT112 and the gate of the NMOS transistor NT111.
The gates of the PMOS transistors PT111 and PT114 are connected to the input line of the clock signal CK.
[0045]
In the latch unit 111, the source of the NMOS transistor NT111 is connected to the drain of the NMOS transistor NT113, and the connection point constitutes a first intermediate node F111. The source of the NMOS transistor NT112 is connected to the drain of the NMOS transistor NT114, and the connection point constitutes a second intermediate node F112.
The sources of the NMOS transistor NT113 and the NMOS transistor NT114 are connected to each other, and a third intermediate node G111 is configured by the connection point. The third intermediate node G111 is connected to the drain of the NMOS transistor NT115, and the source of the NMOS transistor NT115 is connected to the ground potential GND.
The source and drain of the NMOS transistor NT116 are connected to the first intermediate node F111 and the second intermediate node F112, respectively.
The gate of the NMOS transistor NT113 is connected to the supply line of the data input signal D, and the gate of the NMOS transistor NT114 is connected to the supply line of the inverted signal Db of the data input signal D. The gate of the NMOS transistor NT115 is connected to the supply line of the clock signal CK, and the gate of the NMOS transistor 1T216 is the power supply voltage V_DDConnected to the supply line.
[0046]
  In the pre-setting unit 112, the source of the PMOS transistor PT111 is connected to the drains of the PMOS transistors PT115 and PT119. The source of the PMOS transistor PT115 is connected to the drain of the PMOS transistor PT117, and the source of the PMOS transistor PT119 is connected to the drain of the PMOS transistor PT121.
  The source of the NMOS transistor NT117 is the NMOS transistor NT119.drainThe source of the NMOS transistor NT119 is connected to the ground potential GND.
  The source of the PMOS transistor PT114 is connected to the drains of the PMOS transistors PT116 and PT120. The source of the PMOS transistor PT116 is connected to the drain of the PMOS transistor PT118, and the source of the PMOS transistor PT120 is connected to the drain of the PMOS transistor PT122.
  The source of the NMOS transistor NT118 is the NMOS transistor NT120.drainAnd the source of the NMOS transistor NT120 is connected to the ground potential GND.
  The gates of the PMOS transistors PT117 and PT122 and the NMOS transistor NT117 are connected to the data input signal D supply line. The gates of the PMOS transistors PT118 and PT121 and the NMOS transistor NT118 are connected to the supply line of the inverted signal Db of the data input signal D.
  The gates of the PMOS transistors PT115 and PT120 and the NMOS transistor NT120 are connected to the output terminal (node I122: output line of the inverted data Qb in this embodiment) of the NAND gate NA122 of the second stage latch 12. The gates of the PMOS transistors PT116 and PT119 and the NMOS transistor NT119 are connected to the NAND gate NA121 of the second-stage latch 12 to the output terminal (node I121: in this embodiment, the output line of the data Q).
[0047]
The second stage latch 12 is composed of 2-input NAND gates NA121 and NA122.
The first input terminal of the NAND gate NA121 is connected to the first output node H111 of the first stage latch 11, and the second input terminal is connected to the output terminal (node I122) of the NAND gate NA122.
The first input terminal of the NAND gate NA122 is connected to the second node H112 of the first stage latch 11, and the second input terminal is connected to the output terminal (node I121) of the NAMD gate NA121.
[0048]
Next, the operation of the sense amplifier type D flip-flop 10 of FIG. 1 will be described in relation to the timing chart of FIG. In the following description, the first potential level (ground potential) is set to low level, and the second potential level (power supply voltage V_DDLevel) High level.
[0049]
The flip-flop 10 takes in the value of the data input signal D in synchronization with the rising edge of the clock signal CK, and outputs data Q and inverted data Qb. The value is held for one cycle of the clock signal CK.
[0050]
Here, for example, it is assumed that the output data Q from the second stage latch 12 is held at a low level and the output inverted data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the normal input data D and the inverted input data Db are output data Q and output. The overall operation when data Qb is supplied at different levels (level mismatch) will be described.
[0051]
During the period when the clock signal (synchronization signal) CK is at a low level (logic 0 level), the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistor NT115 is cut off.
Since the output data Q is held at a low level and the output inverted data Qb is held at a high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115 and PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at the high level and the inverted signal Db is supplied at the low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117 and PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistances, through which the first output node H111 and the second output node H112 are connected to the power supply voltage V_DDAre electrically connected to the first supply line (second potential source) and precharged to a complete logic 1 potential (high level) as shown in FIGS. 2 (A), (C), and (E). .
Then, the PMOS transistors PT112 and PT113 are cut off. The NMOS transistors NT111 and NT112 behave equivalently as diodes because the gate terminal and the drain terminal have the same potential.
Therefore, the power supply voltage is V_DD[V] If the threshold value of the NMOS transistor is Vthn, the potentials of the first intermediate node F111 and the second intermediate node F112 at this time are as shown in FIGS. (V_DD-Vthn) [V].
[0052]
  When the clock signal CK becomes high level, the PMOS transistors PT111 and PT114 are cut off, the NMOS transistor NT115 is turned on, and the latch unit (sense amplifier) 111 operates.
  Since the data input signal D is at the high level and the inverted signal Dd is at the low level, the NMOS transistor NT113 is turned on, and the NMOS transistor NT114Is cut off.
  Therefore, a difference occurs in the conduction resistances of the first intermediate node F111 and the second intermediate node F112 with respect to the ground.
[0053]
In this case, since the NMOS transistor NT114 is cut off, the conduction resistance of the first intermediate node F111 with respect to the ground is the sum of the resistance values of the NMOS transistor NT113 and the NMOS transistor NT115, whereas In the case of the intermediate node F112, the sum of the resistance values of the NMOS transistor NT116, the NMOS transistor NT113, and the NMOS transistor NT115 is obtained.
Such a difference in conduction resistance appears in the discharge rate of charges on the first output node H111 and the second output node H112. In this case, since the conduction resistance of the first intermediate node F111 with respect to the ground is smaller, as shown in FIG. 2C, the charge of the first output node H111 is discharged more quickly. At this time, as shown in FIG. 2E, the charge on the second output node H112 is also discharged.
However, when the potential of the first output node H111 is lowered, the PMOS transistor PT113 is turned on, the NMOS transistor NT112 is cut off, and the potential of the second output node H112 that has been lowered rises, and again becomes a complete logic one. Get the potential.
[0054]
In this way, a steady state is established in the inverter loop composed of the PMOS transistors PT112 and PT113 and the NMOS transistors NT111 and NT112.
Thereafter, even if the data input signal D and its inverted signal Dd change and the transistor to be cut off changes from the NMOS transistor NT114 to the NMOS transistor NT113, this steady state is not destroyed.
This is because one of the NMOS transistors NT113 and NT114 is always on, and both the intermediate nodes F111 and F112 always have a path to the ground through the NMOS transistor NT116. This is because it is connected to the ground.
[0055]
In this manner, as shown in FIGS. 2A, 2C, and 2E, the first output node H111 of the first stage latch 21 is at the low level and the second level during the period in which the clock signal CK is at the high level. Output node H112 becomes high level.
[0056]
  Since the data input signal D is at the high level, the inverted signal Db is at the low level, and the first output node H111 is at the low level.2As shown in (H), high-level data Q is immediately output from the NAND gate NA111 of the second-stage latch 12.
  Further, the output data Qb of the NAND gate NA112 becomes low level.
[0057]
In the following, it is assumed that the output data Q by the second-stage latch 12 is held at a high level and the inverted output data Qb is held at a low level as preconditions.
That is, assuming that the first output node H111 is at a low level and the second output data H112 is at a high level, the operation of the pre-setting unit 112 will be described focusing on the first to tenth states.
[0058]
Under this condition, first, as a first state, when the clock signal (synchronization signal) CK is low level (logic 0 level), the data input signal D is high level, and the inverted signal Db is low level, each transistor It becomes like this.
That is, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistor NT115 is cut off.
Since the output data Q is held at a high level and the inverted output data Qb is held at a low level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned off, and the PMOS transistors PT115 and PT120 and the NMOS transistor NT119 are turned off. Is turned on.
Since the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are kept on, and the PMOS transistors PT117 and PT122 and the NMOS transistor NT118 are kept off. Is done.
[0059]
Therefore, although the PMOS transistors PT111 and PT114 are on, the first output no H111 and the second output node H112 are at the power supply voltage V_DDIn this state, the first output node H111 and the second output node H112 are not charged.
Since the NMOS transistors NT117 and NT19 are in the on state, the first output node H111 is electrically connected to the ground potential GND, the electric charge is discharged, and is held at the low level.
At this time, the PMOS transistor PT113 of the latch unit 111 is in an on state and the second output node H112 is at a high level, but the PMOS transistor PT114 is on, the PMOS transistor PT116 is off, the PMOS transistor PT118 is on, and the PMOS transistor PT120 is on. Since the on state, the PMOS transistor PT122 are off, and the NMOS transistors NT118 and NT120 are off, charge is not charged during the period when the clock signal CK is at the low level, and there is no low level drive. Therefore, the second output node H112 is held at a high level by the PMOS transistor PT113.
In this case, there is no change in the level of the output data Q and Qb of the second stage latch 12.
[0060]
In the second state in which the clock signal CK changes from the first state to the high level, the PMOS transistors PT111 and PT114 are turned off and the NMOS transistor NT115 is turned on, and the level of each node is not changed.
[0061]
In the third state in which the data input signal D changes from the second state to the low level and its inverted signal Db changes to the high level, the first output node H111 is at the low level and the PMOS in the first and second states. When the transistor PT113 is on, the second output node H112 is at a high level, and the NMOS transistor NT111 is on and is complementarily stable.
A path for driving the first output node H111 to the low level is from the NMOS transistor NT111 → the first intermediate node F111 → the NMOS transistor NT112 → the third intermediate node G111 → the NMOS transistor 115, and then the NMOS transistor NT111 → the first transistor. The intermediate node F111 → the NMOS transistor NT116 → the second intermediate node F112 → the NMOS transistor NT114 → the third intermediate node G111 → the NMOS transistor 115, there is no change in the level of each node.
[0062]
In the fourth state in which the clock signal CK changes to the low level from the third state, the PMOS transistor PT111 is turned on, the PMOS transistor PT114 is turned on, and the NMOS transistor NT115 is turned off.
At this time, the PMOS transistor PT115 is already on, the PMOS transistor PT117 is on, the PMOS transistor PT120 is on, the PMOS transistor PT122 is on, the NMOS transistor NT117 is off, the NMOS transistor NT119 is on, the NMOS transistor NT118 is on, and the NMOS transistor NT120 is on Since each state is OFF, the above-described charge charging occurs while the clock signal CK is at a low level, and both the first output node H111 and the second output node H112 are at a high level.
However, in this case, there is no change in the levels of the output data Q and Qb of the second stage latch 12.
[0063]
In the fifth state in which the clock signal CK changes from the fourth state to the high level, the PMOS transistor PT111 is turned off, the PMOS transistor PT114 is turned off, the NMOS transistor NT115 is turned on, and the NMOS transistor NT112 → second intermediate node The second output node H112 is driven to a low level through a path of F112 → NMOS transistor NT114 → third intermediate node G111 → NMOS transistor NT115.
At this time, the first output node H111 is maintained at the high level by the PMOS transistor PT112.
In this case, the levels of the output data Q and Qb of the second-stage latch 12 change and hold the data Q to the low level and the data Qb to the high level.
[0064]
In the sixth state in which the clock CK is changed to the low level from the fifth state, the state is completely opposite to the first state.
In this case, there is no change in the level of the output data Q and Qb of the second stage latch 12.
[0065]
In the seventh state in which the clock signal CK changes from the sixth state to the high level, the state is completely opposite to the second state, the PMOS transistor PT111 is turned off, the PMOS transistor PT114 is turned off, and the NMOS is turned off. Only the transistor NT115 is turned on, and there is no change in each node.
[0066]
In the eighth state in which the data input signal D changes from the seventh state to the high level and its inverted signal Db changes to the low level, the state is completely opposite to the third state. In this state, the second output node H112 is at a low level, the PMOS transistor PT112 is on, the first output node H112 is at a high level, and the NMOS transistor NT112 is on and complementarily stabilized.
Then, the path for driving the second output node H112 to the low level is from the NMOS transistor NT112 → the second intermediate node F112 → the NMOS transistor NT114 → the third intermediate node G111 → the NMOS transistor 115, and then the NMOS transistor NT112 → the second The intermediate node F112 → the NMOS transistor NT116 → the first intermediate node F111 → the NMOS transistor NT113 → the third intermediate node G111 → the NMOS transistor 115, the level of each node does not change.
[0067]
In the ninth state in which the clock signal CK changes from the eighth state to the low level, the state is exactly the reverse of the fourth state, the PMOS transistor PT111 is turned on, the PMOS transistor PT114 is turned on, and the NMOS The transistor NT115 is turned off. At this time, the PMOS transistor PT119 is already on, the PMOS transistor PT121 is on, the PMOS transistor PT116 is on, the PMOS transistor PT118 is on, the NMOS transistor NT117 is on, the NMOS transistor NT119 is off, and the NMOS transistor NT118 Since the NMOS transistor NT120 is in the on state, the above-described charge charging occurs, and both the first output node H111 and the second output node H112 are high. The Le.
However, in this case, there is no change in the levels of the output data Q and Qb of the second stage latch 12.
[0068]
In the tenth state in which the clock signal changes from the ninth state to the high level, the state is exactly the reverse of the fifth state, the PMOS transistor PT111 is turned off, the PMOS transistor PT114 is turned off, and the NMOS transistor NT115 is turned on, and the first output node H111 is driven to a low level through a path of NMOS transistor NT111 → first intermediate node F111 → NMOS transistor NT113 → third intermediate node G111 → NMOS transistor NT115.
The second output node H112 is maintained at a high level by the PMOS transistor PT113.
In this case, the levels of the output data Q and Qb of the second-stage latch 12 change and hold the data Q to the high level and the data Qb to the low level.
[0069]
Next, the state in which the clock signal CK changes to the low level from the tenth state is nothing but the first state.
[0070]
As described above, according to the first embodiment, when the input data signal does not change (when the level of the input signal to the first stage latch and the output signal of the second stage latch match) ) Does not charge the first stage with the clock signal, so that the clock system power consumption can be greatly reduced.
[0071]
Second embodiment
FIG. 3 is a circuit diagram showing a second embodiment of the sense amplifier type D flip-flop according to the present invention.
[0072]
The second embodiment is different from the first embodiment described above in that inverters INV121-1 and INV122-1 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-1. .
[0073]
Other configurations are the same as those of the first embodiment described above.
[0074]
According to the second embodiment, there is an advantage that power consumption can be reduced and the influence of crosstalk and the like can be suppressed.
[0075]
Third embodiment
FIG. 4 is a circuit diagram showing a third embodiment of the sense amplifier type D flip-flop according to the present invention.
[0076]
The third embodiment is different from the first embodiment described above in that in the second stage latch 12-2, the output signal change of the first stage (previous stage) latch is transmitted to the final output signal in a short time. It is in having established.
[0077]
Specifically, the second stage latch 12-2 is configured by four 2-input NAND gates NA121-2 to NA124-2.
The first input terminal of the NAND gate NA121-2 is connected to the first output node H111 of the first stage latch 11, the second input terminal is the output terminal of the NAND gate NA122-2, and the first input of the NAND gate NA124-2. A node I121-2 is configured by these connection points.
The first input terminal of the NAND gate NA122-2 is connected to the second node H112 of the first stage latch 11, the second input terminal is the output terminal of the NAMD gate NA121-2, and the first input terminal of the NAND gate NA123-2. The node I122-2 is configured by these connection points.
The second input terminal of the NAND gate NA123-1 is connected to the second node H112 of the first stage latch 11, and the second input terminal of the NAND gate NA124-2 is connected to the first node H111 of the first stage latch 11. Has been.
The second-stage latch 12-2 outputs data Q from the NAND gate NA124-2, and outputs inverted data Qb from the NAND gate NA123-2.
[0078]
For example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, which is immediately higher than the NAND gate NA124-2 of the second stage latch 12-2. Level data Q is output.
Further, the output data Qb of the NAND gate NA123-2 becomes low level via the NAND gate NA121-2.
[0079]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0080]
According to the third embodiment, the second-stage latch 12-2 is provided with the circuit for transmitting the output signal change of the first-stage latch of the previous stage to the final output signal in a short time. Therefore, the first embodiment In addition to the above effect, a high level can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0081]
Fourth embodiment
FIG. 5 is a circuit diagram showing a fourth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0082]
The fourth embodiment is different from the first embodiment described above in the circuit configuration of the second-stage latch 12-3.
[0083]
Specifically, as shown in FIG. 5, the second-stage latch 12-3 includes inverters INV121-3 to INV124-3, a PMOS transistor PT123-3, and an NMOS transistor NT121-3.
[0084]
The source of the PMOS transistor PT123-3 is the power supply voltage V_DDThe drain is connected to the drain of the NMOS transistor NT121-3, and a node J121-3 is configured by this connection point. The source of the NMOS transistor NT121-3 is connected to the ground potential GND.
The input terminal of the inverter INV121-3 is connected to the first output node H111 of the first stage latch 11, and the output terminal is connected to the gate of the NMOS transistor NT121-3. Here, a connection point between the output terminal of the inverter INV121-3 and the gate of the NMOS transistor NT121-3 is defined as a node / H111.
Node J121-3 is connected to the input terminals of inverters INV122-3 and INV123-3 and the output terminal of inverter INV124-3.
Further, the output terminal of the inverter INV123-3 and the input terminal of the inverter INV124-3 are connected, and a node J122-3 is configured by the connection point. These inverters INV123-3 and INV124-3 constitute a latch.
Then, the second stage latch 12-3 outputs data Q from the output terminal of the inverter INV122-3.
[0085]
In this case, for example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and the output node of the inverter INV121-3 of the second-stage latch 12-3. / 111 becomes a high level. At this time, the second output node H112 of the first stage latch 11 is at a high level.
As a result, the NMOS transistor NT121-3 is turned on, the PMOS transistor PT123-3 is turned off, the node J121-3 becomes low level, and the high-level data Q is immediately output from the inverter INV122-3.
Note that the data of the node J121-3 is maintained even when the clock signal CK is switched to a low level by the cross latch of the inverters INV123-3 and INV124-3.
[0086]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0087]
According to the fourth embodiment, since the second stage latch 12-3 is provided with the circuit for transmitting the output signal change of the previous stage latch to the final output signal in a short time, in addition to the effects of the first embodiment. Thus, since a high level can be output more quickly than the conventional circuit, high-speed operation is possible.
[0088]
Fifth embodiment
FIG. 6 is a circuit diagram showing a fifth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0089]
The fifth embodiment is different from the above-described fourth embodiment in that the second stage latch 12-4 has the same output signal change from the first stage latch 11 as long as the contradictory signals are held. The circuit configuration is to invalidate the reciprocal signal held in the second stage latch.
Specifically, the inverter INV124-4 configuring the cross latch is configured by a clocked inverter connected to the nodes / H111 and H112.
[0090]
In this case, for example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and the output node of the inverter INV121-3 of the second-stage latch 12-4. / H111 goes high. At this time, the second output node H112 of the first stage latch 11 is at a high level.
As a result, the NMOS transistor NT123-3 is turned on, the PMOS transistor PT123-3 is turned off, and the node J121-3 becomes low level.
At this time, the clocked inverter INV124-4 cannot output a high level, and the high level data Q is promptly output from the inverter INV122-3.
Therefore, high-level data Q is immediately output from inverter INV122-3 without preventing node J121-3 from changing to a low level.
Further, the data of the node J121-3 is maintained even when the clock signal CK is switched to a low level by the cross latch of the inverters INV123-3 and INV124-4.
[0091]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0092]
According to the fifth embodiment, in addition to the effects of the fourth embodiment, high-level data can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0093]
Sixth embodiment
FIG. 7 is a circuit diagram showing a sixth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0094]
The sixth embodiment is different from the first embodiment described above in the configuration of the latch unit 200 of the first stage latch 11-5.
[0095]
Specifically, the latch unit 200 of the first stage latch 11-5 according to the seventh embodiment includes PMOS transistors PT212 and PT213, NMOS transistors NT211 to NT218, a first output node H211 and a second output node. H212, a first intermediate node F211, a second intermediate node G211, a third intermediate node F212, and a fourth intermediate node G212.
[0096]
Among these components, the PMOS transistor PT212 constitutes a first switching element, the PMOS transistor PT213 constitutes a second switching element, the NMOS transistor NT211 constitutes a third switching element, and the NMOS transistor NT215 constitutes The fourth switching element is configured, the NMOS transistor NT212 configures the fifth switching element, the NMOS transistor NT216 configures the sixth switching element, the NMOS transistor NT213 configures the seventh switching element, and the NMOS transistor NT217 constitutes an eighth switching element, NMOS transistor NT214 constitutes a ninth switching element, and NMOS transistor Tenth switching element is constituted by register NT218.
[0097]
The PMOS transistor PT111 constitutes a ninth switching element, the PMOS transistor PT114 constitutes a tenth switching element, the PMOS transistor PT115 constitutes a seventeenth switching element, and the PMOS transistor PT116 constitutes a sixteenth switching element. The PMOS transistor PT117 constitutes the eleventh switching element, the PMOS transistor PT118 constitutes the fourteenth switching element, the PMOS transistor PT119 constitutes the fifteenth switching element, and the PMOS transistor PT120 constitutes the eighteenth switching element. A switching element is configured, and the PMOS transistor PT121 forms a thirteenth switching element, and the PMOS transistor The transistor PT122 constitutes the twelfth switching element, the NMOS transistor NT117 constitutes the nineteenth switching element, the NMOS transistor NT118 constitutes the twentieth switching element, and the NMOS transistor NT119 constitutes the twenty-first switching element. The NMOS transistor NT120 constitutes a twenty-second switching element.
[0098]
In the latch unit 200, the sources of the PMOS transistors PT212 and PT213 are connected to the power supply voltage V._DDConnected to the supply line (second potential source). The drain of the PMOS transistor PT212 is connected to the drain of the NMOS transistor NT211 and the first output node H111.
The first output node H111 is connected to the gate of the PMOS transistor PT213 and the gates of the NMOS transistors NT217 and 218.
The drain of the PMOS transistor PT213 is connected to the drain of the NMOS transistor NT215 and the second output node H112. The second output node H112 is connected to the gate of the PMOS transistor PT212 and the gates of the NMOS transistors NT213 and NT214.
The gates of the NMOS transistors NT211 and NT215 are connected to the first potential level (ground level) and the second potential level (power supply voltage V_DDLevel) is connected to an input line of a clock signal (synchronization signal) CK.
[0099]
The source of the NMOS transistor NT211 is connected to the drain of the NMOS transistor NT212, and the connection point constitutes a first intermediate node F211. The source of the NMOS transistor NT212 is connected to the drain of the NMOS transistor NT213, and the connection point constitutes a second intermediate node G211. The source of the NMOS transistor NT213 is connected to the ground potential (reference potential) GND. The drain of the NMOS transistor NT214 is connected to the first intermediate node F211 and the source is grounded to the ground potential GND.
The first signal path SP211 is formed by the NMOS transistor NT211, the first intermediate node F211, the NMOS transistor NT212, the second intermediate node G211, and the NMOS transistor NT213 that reach the ground potential from the first output node H111. .
The gate of the NMOS transistor NT212 is connected to the supply line of the data input signal D.
[0100]
The source of the NMOS transistor NT215 is connected to the drain of the NMOS transistor NT216, and the connection point constitutes a third intermediate node F212. The source of the NMOS transistor NT216 is connected to the drain of the NMOS transistor NT217, and the connection point forms a fourth intermediate node G212. The source of the NMOS transistor NT217 is connected to the ground potential GND. The drain of the NMOS transistor NT218 is connected to the third intermediate node F212, and the source is grounded to the ground potential GND.
A second signal path SP212 is formed by the NMOS transistor NT215, the third intermediate node F212, the NMOS transistor NT216, the fourth intermediate node G212, and the NMOS transistor NT217 that reach the ground potential from the second output node H112. .
The gate of the NMOS transistor NT216 is connected to the supply line of the inverted signal Db of the data input signal D.
[0101]
Next, the operation of the sense amplifier type D flip-flop 10-5 will be described focusing on the latch unit 200 of the first stage latch 10-5.
[0102]
Here, it is assumed that the output data Q by the second-stage latch 12 is held at a low level and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the normal input data D and the inverted input data Db are output data Q and output. In the following description, it is assumed that data Qb is supplied at different levels (level mismatch).
[0103]
The flip-flop 10-5 takes in the value of the data input signal D in synchronization with the rising edge of the clock signal CK, and outputs data Q and inverted data Qb. The value is held for one cycle of the clock signal CK.
[0104]
During the period when the clock signal CK is at a low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0105]
Since the output data Q is held at a low level and the output inverted data Qb is held at a high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115 and PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at the high level and the inverted signal Db is supplied at the low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117 and PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistances, through which the first output node H111 and the second output node H112 are connected to the power supply voltage V_DDAre electrically connected to the first supply line (second potential source) and precharged to a complete logic 1 potential (high level).
[0106]
Then, the PMOS transistors PT212 and PT213 are cut off.
At this time, since the NMOS transistors NT211 and NT215 are cut off, the first intermediate node F211 and the third intermediate node F212 are not charged.
On the other hand, the NMOS transistors NT213, NT214, NT217, and NT218 are turned on when the first output node H111 and the second output node H112 are precharged to a high level.
As a result, regardless of the state of the data input signal D and the inverted signal Db, the first intermediate node F211 passes through the NMOS transistor NT214, the second intermediate node G211 passes through the NMOS transistor NT213, and the third intermediate node F212 passes through the NMOS transistor NT213. Through NT218, the fourth intermediate node G212 is discharged through the NMOS transistor NT217 and becomes low level.
Therefore, charge is performed only on the first output node H111 and the second output node H112 while the clock signal CK is at a low level.
[0107]
Next, when the clock signal CK becomes high level, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Therefore, the power supply voltage is V_DD[V] If the threshold value of the NMOS transistor is Vthn, the potentials of the first intermediate node F211 and the second intermediate node F212 at this time are (V_DD-Vthn) [V].
Here, when the data input signal D is high level and supplied to the gate of the NMOS transistor NT212, and the inverted signal Db is supplied low level to the gate of the NMOS transistor NT216, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first signal path SP211 is electrically connected from the first output node H111 to the ground potential GND. Therefore, the charge charged in the first output node H111 is discharged through the NMOS transistors NT211 to NT213 and NT214. As a result, the first output node H111 is set to the low level, and the high-level data Q is output from the NAND gate NA121 of the second-stage latch 12.
[0108]
On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
However, when the potential of the first output node H111 is lowered, the PMOS transistor PT213 is turned on, the NMOS transistor NT218 is cut off, and the potential of the second output node H112 that has been lowered rises again, and the complete logic 1 is again achieved. Obtain potential and hold high level.
[0109]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed.
[0110]
That is, when the data input signal D is low and supplied to the gate of the NMOS transistor NT212, and the inverted signal Db is supplied high and supplied to the gate of the NMOS transistor NT216, the NMOS transistor NT212 is turned off and the NMOS transistor NT216 is turned on. . At this time, the NMOS transistor NT217 remains on.
As a result, the second signal path SP212 is electrically connected from the second output node H112 to the ground potential GND. Therefore, the charge charged in the second output node H112 is discharged through the NMOS transistors NT215 to NT217 and NT218. As a result, the first output node H112 becomes low level, and high level data Qb is output from the NAND gate NA122 of the second stage latch 12.
[0111]
On the other hand, the electric charge of the first output node H111 is discharged for a very short time when the second output node H112 changes from the high level to the low level.
However, when the potential of the second output node H112 is lowered, the PMOS transistor PT212 is turned on, the NMOS transistor NT214 is cut off, and the potential of the first output node H111 that has been lowered is raised, and again a complete logic 1 is obtained. Obtain potential and hold high level.
[0112]
Since the operation of the pre-setting unit 112 is performed in the same manner as in the first embodiment described above, detailed description thereof is omitted here.
[0113]
As described above, when the first output node H111 and the second output node H112 are precharged, the NMOS transistor NT211 connected between the first output node H111 and the first intermediate node F211 and the second output node H211 Since the NMOS transistor NT215 connected between the output node H112 and the third intermediate node F212 is cut off, the charge is charged only to the first output node H111 and the second output node H112. .
As described above, since the charge to be charged is less than that of the conventional circuit and the number of transistors contributing to the discharge is more than that of the conventional circuit, it is possible to operate at higher speed than the conventional circuit.
[0114]
That is, according to the sixth embodiment, compared to the conventional sense amplifier type D flip-flop, the amount of charge charged by the first-stage latch 11 can be reduced, and the charging time can be shortened. It can be shortened. In addition, since the charge charged in the first stage latch 11-5 can be discharged quickly, the output signal of the first stage latch 11-5 can be determined in a short time, and the valid delay can be shortened. Is possible.
As a result, there is an advantage that high-speed operation can be realized and power consumption can be reduced without depending on a circuit design method.
[0115]
Further, according to the sixth embodiment, when the input data signal does not change (when the level of the input signal to the first stage latch and the output signal of the second stage latch match), Since the charge is not charged in the first stage by the clock signal, the power consumption of the clock system can be greatly reduced.
[0116]
Seventh embodiment
FIG. 8 is a circuit diagram showing a seventh embodiment of the sense amplifier type D flip-flop according to the present invention.
[0117]
The seventh embodiment differs from the sixth embodiment described above in that inverters INV121-6 and INV122-6 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-1. .
[0118]
Other configurations are the same as those of the seventh embodiment described above.
[0119]
According to the seventh embodiment, the influence of crosstalk or the like can be suppressed.
Further, the first stage latch 11-5 in the previous stage can shorten the setup time, and the output signal of the first stage latch 11-5 can be determined in a short time, thereby reducing the valid delay. Therefore, even if an inverter is inserted and the valid delay becomes longer, the overall advantage is that high-speed operation can be realized and power consumption can be reduced without depending on the circuit design method. is there.
[0120]
Eighth embodiment
FIG. 9 is a circuit diagram showing an eighth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0121]
The eighth embodiment is different from the sixth embodiment described above in that in the second stage latch 12-7, the output signal change of the first stage (previous stage) latch is transmitted to the final output signal in a short time. It is in having established.
[0122]
Specifically, the second stage latch 12-7 is configured by four 2-input NAND gates NA121-7 to NA124-7.
The first input terminal of the NAND gate NA121-7 is connected to the first output node H111 of the first stage latch 11-5, and the second input terminal is the output terminal of the NAND gate NA122-7 and the first input node of the NAND gate NA124-7. The node I121-7 is configured by these connection points connected to one input terminal.
The first input terminal of the NAND gate NA122-7 is connected to the second node H112 of the first stage latch 11-5, the second input terminal is the output terminal of the NAMD gate NA121-7, and the first input of the NAND gate NA123-7. The node I122-7 is configured by these connection points connected to the input terminals.
The second input terminal of the NAND gate NA123-7 is connected to the second node H112 of the first stage latch 11-5, and the second input terminal of the NAND gate NA124-7 is the first input of the first stage latch 11-7. It is connected to the node H111.
The second-stage latch 12-7 outputs data Q from the NAND gate NA124-7, and outputs inverted data Qb from the NAND gate NA123-7.
[0123]
For example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and is quickly higher than the NAND gate NA124-7 of the second stage latch 12-7. Level data Q is output.
Further, the output data Qb of the NAND gate NA123-7 becomes a low level via the NAND gate NA121-7.
[0124]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0125]
According to the eighth embodiment, since the second stage latch 12-7 is provided with the circuit for transmitting the output signal change of the first stage latch of the previous stage to the final output signal in a short time, the sixth embodiment In addition to the above effect, a high level can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0126]
Ninth embodiment
FIG. 10 is a circuit diagram showing a ninth embodiment of a sense amplifier D-type flip-flop according to the present invention.
[0127]
The ninth embodiment is different from the sixth embodiment described above in the circuit configuration of the second-stage latch 12-8.
[0128]
Specifically, the second stage latch 12-8 includes inverters INV121-8 to INV124-8, a PMOS transistor PT123-8, and an NMOS transistor NT121-8, as shown in FIG.
[0129]
The source of the PMOS transistor PT123-8 is the power supply voltage V_DDThe drain is connected to the drain of the NMOS transistor NT121-8, and a node J121-8 is constituted by this connection point. The source of the NMOS transistor NT121-8 is connected to the ground potential GND.
The input terminal of the inverter INV121-8 is connected to the first output node H111 of the first stage latch 11-5, and the output terminal is connected to the gate of the NMOS transistor NT121-8. Here, a connection point between the output terminal of the inverter INV121-8 and the gate of the NMOS transistor NT121-8 is defined as a node / H111.
Node J121-8 is connected to the input terminals of inverters INV122-8 and INV123-8 and the output terminal of inverter INV124-8.
Further, the output terminal of the inverter INV123-8 and the input terminal of the inverter INV124-8 are connected, and a node J122-8 is configured by the connection point. These inverters INV123-8 and INV124-8 constitute a latch.
The second stage latch 12-8 outputs data Q from the output terminal of the inverter INV122-8.
[0130]
In this case, for example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and the output node of the inverter INV121-8 of the second stage latch 12-8. / 111 becomes a high level. At this time, the second output node H112 of the first stage latch 11-5 is at the high level.
As a result, the NMOS transistor NT121-8 is turned on, the PMOS transistor PT123-8 is turned off, the node J121-8 becomes low level, and the high level data Q is immediately output from the inverter INV122-8.
Note that the data of the node J121-8 is maintained even when the clock signal CK is switched to a low level by the cross latch of the inverters INV123-8 and INV124-8.
[0131]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0132]
According to the ninth embodiment, since the second stage latch 12-8 is provided with the circuit for transmitting the output signal change of the first stage latch to the final output signal in a short time, the effect of the sixth embodiment is achieved. In addition, since a high level can be output more quickly than the conventional circuit, high-speed operation is possible.
[0133]
Tenth embodiment
FIG. 11 is a circuit diagram showing a tenth embodiment of the sense amplifier type D-type flip-flop according to the present invention.
[0134]
The difference between the tenth embodiment and the ninth embodiment described above is that the second stage latch 12-9 is different from the output signal change of the first stage latch 11-9 when the contradictory signals are held. At the same time, the circuit configuration is such that the reciprocal signal held in the second stage latch is invalidated.
Specifically, the inverter INV124-9 constituting the cross latch is constituted by a clocked inverter connected to the nodes / H111 and H112.
[0135]
In this case, for example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and the output node of the inverter INV121-8 of the second stage latch 12-9. / H111 goes high. At this time, the second output node H112 of the first stage latch 11-5 is at the high level.
As a result, the NMOS transistor NT121-8 is turned on, the PMOS transistor PT123-8 is turned off, and the node J121-8 becomes low level.
At this time, the clocked inverter INV124-9 cannot output the high level, and the high level data Q is promptly output from the inverter INV122-8.
Therefore, the high-level data Q is output from the inverter INV122-8 promptly without preventing the node J121-8 from changing to the low level.
In addition, the data of the node J121-8 is maintained even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-8 and INV124-9.
[0136]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0137]
According to the tenth embodiment, in addition to the effects of the ninth embodiment, high-level data can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0138]
Eleventh embodiment
FIG. 12 is a circuit diagram showing an eleventh embodiment of the sense amplifier type D flip-flop according to the present invention.
[0139]
The difference between the eleventh embodiment and the sixth embodiment described above is the configuration of the latch section of the first stage latch 11-10.
Specifically, in the latch unit 210 according to the eleventh embodiment, the connection position of the NMOS transistor NT212 as the fifth switching element and the NMOS transistor NT213 as the seventh switching element in the first signal path SP211, And the connection position of the drain of the NMOS transistor NT214 as the ninth switching element, and the connection position of the NMOS transistor NT216 as the sixth switching element and the NMOS transistor NT217 as the eighth switching element in the second signal path SP212 , And the connection position of the drain of the NMOS transistor NT218 as the tenth switching element.
[0140]
Specifically, in the first signal path SP211, the drain of the NMOS transistor NT212 is connected to the second intermediate node G211, the source is connected to the ground potential GND, and the drain of the NMOS transistor NT213 is connected to the first intermediate node F211. And the source is connected to the second intermediate node G211. Further, the drain of the NMOS transistor NT214 is connected to the second intermediate node G211 instead of the first intermediate node F211.
Similarly, in the second signal path SP212, the drain of the NMOS transistor NT216 is connected to the fourth intermediate node G212, the source is connected to the ground potential GND, and the drain of the NMOS transistor NT217 is connected to the third intermediate node F212. The source is connected to the fourth intermediate node G212. The drain of the NMOS transistor NT218 is connected to the fourth intermediate node G212 instead of the third intermediate node F212.
[0141]
Next, the operation of the sense amplifier type D flip-flop 10-10 in FIG. 12 will be described.
[0142]
Here, it is assumed that the output data Q by the second-stage latch 12 is held at a low level and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the normal input data D and the inverted input data Db are output data Q and output. In the following description, it is assumed that data Qb is supplied at different levels (level mismatch).
[0143]
During the period when the clock signal CK is at a low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0144]
Since the output data Q is held at a low level and the output inverted data Qb is held at a high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115 and PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at the high level and the inverted signal Db is supplied at the low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117 and PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistances, through which the first output node H111 and the second output node H112 are connected to the power supply voltage V_DDAre electrically connected to the first supply line (second potential source) and precharged to a complete logic 1 potential (high level).
[0145]
Then, the PMOS transistors PT212 and PT213 are cut off.
At this time, since the NMOS transistors NT211 and NT215 are cut off, the first intermediate node F211 and the third intermediate node F212 are not charged.
On the other hand, the NMOS transistors NT213, NT214, NT217, and NT218 are turned on when the first output node H111 and the second output node H112 are precharged to a high level.
As a result, regardless of the state of the data input signal D and the inverted signal Db, the first intermediate node F211 and the second intermediate node G211 pass through the NMOS transistors NT213 and NT214 and pass through the third intermediate node F212 and the fourth intermediate node. The charge of G212 is discharged through the NMOS transistors NT217 and NT218 and becomes low level.
Therefore, charge is performed only on the first output node H111 and the second output node H112 while the clock signal CK is at a low level.
[0146]
Next, when the clock signal CK becomes high level, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Here, when the data input signal D is high level and supplied to the gate of the NMOS transistor NT212, and the inverted signal Db is supplied low level to the gate of the NMOS transistor NT216, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first output node H111 is electrically connected to the ground potential GND. Therefore, the charge charged in the first output node H111 is discharged through the NMOS transistors NT211, NT213, and NT214. As a result, the first output node H111 is set to the low level, and the high-level data Q is output from the NAND gate NA121 of the second-stage latch 12.
[0147]
On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
However, when the potential of the first output node H111 is lowered, the PMOS transistor PT213 is turned on, the NMOS transistors NT217 and NT218 are cut off, and the potential of the second output node H112 that has been lowered is raised, and again the complete logic A potential of 1 is obtained and held at a high level.
[0148]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0149]
Since the operation of the pre-setting unit 112 is performed in the same manner as in the first embodiment described above, detailed description thereof is omitted here.
[0150]
According to the eleventh embodiment, the same effects as those of the sixth embodiment described above can be obtained.
[0151]
12th embodiment
FIG. 13 is a circuit diagram showing a twelfth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0152]
The difference between the twelfth embodiment and the eleventh embodiment is that the inverters INV121-11 and INV122-11 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-11. .
[0153]
Other configurations are the same as those in the eleventh embodiment.
[0154]
According to the twelfth embodiment, the influence of crosstalk or the like can be suppressed.
Further, the first stage latch 11-10 in the previous stage can shorten the setup time, and the output signal of the first stage latch 11-10 can be determined in a short time, thereby reducing the valid delay. Therefore, even if an inverter is inserted and the valid delay becomes longer, the overall advantage is that high-speed operation can be realized and power consumption can be reduced without depending on the circuit design method. is there.
[0155]
13th Embodiment
FIG. 14 is a circuit diagram showing a thirteenth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0156]
The thirteenth embodiment differs from the eleventh embodiment described above in that, in the second stage latch 12-12, a circuit for transmitting the output signal change of the first stage (previous stage) latch to the final output signal in a short time. It is in having established.
[0157]
Specifically, the second stage latch 12-12 is configured by four 2-input NAND gates NA121-12 to NA124-12.
The first input terminal of the NAND gate NA121-12 is connected to the first output node H111 of the first stage latch 11-10, and the second input terminal is the output terminal of the NAND gate NA122-12 and the first input node of the NAND gate NA124-12. The node I121-12 is configured by these connection points connected to one input terminal.
The first input terminal of the NAND gate NA122-12 is connected to the second node H112 of the first stage latch 11-10, the second input terminal is the output terminal of the NAMD gate NA121-12, and the first input of the NAND gate NA123-12. The node I122-12 is constituted by these connection points connected to the input terminals.
The second input terminal of the NAND gate NA123-12 is connected to the second node H112 of the first stage latch 11-10, and the second input terminal of the NAND gate NA124-12 is the first input of the first stage latch 11-10. It is connected to the node H111.
The second-stage latch 12-12 outputs data Q from the NAND gate NA124-12, and outputs inverted data Qb from the NAND gate NA123-12.
[0158]
For example, if the data input signal D is at a high level and the inverted signal Db is at a low level, the first output node H111 is at a low level, and is quickly higher than the NAND gate NA124-12 of the second-stage latch 12-12. Level data Q is output.
Further, the output data Qb of the NAND gate NA123-12 becomes low level via the NAND gate NA121-12.
[0159]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0160]
According to the thirteenth embodiment, since the second stage latch 12-12 is provided with the circuit for transmitting the change of the output signal of the first stage latch of the previous stage to the final output signal in a short time, In addition to the effects of the embodiment, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0161]
Fourteenth embodiment
FIG. 15 is a circuit diagram showing a fourteenth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0162]
The difference between the fourteenth embodiment and the eleventh embodiment is the circuit configuration of the second-stage latch 12-13.
[0163]
Specifically, as shown in FIG. 15, the second stage latch 12-13 includes inverters INV121-13 to INV124-13, a PMOS transistor PT123-13, and an NMOS transistor NT121-13.
[0164]
The source of the PMOS transistor PT123-13 is the power supply voltage V_DDThe drain is connected to the drain of the NMOS transistor NT121-13, and a node J121-13 is configured by this connection point. The source of the NMOS transistor NT121-13 is connected to the ground potential GND.
The input terminal of the inverter INV121-13 is connected to the first output node H111 of the first stage latch 11-10, and the output terminal is connected to the gate of the NMOS transistor NT121-13. Here, a connection point between the output terminal of the inverter INV121-13 and the gate of the NMOS transistor NT121-13 is defined as a node / H111.
Node J121-13 is connected to the input terminals of inverters INV122-13 and INV123-13 and the output terminal of inverter INV124-13.
Further, the output terminal of the inverter INV123-13 and the input terminal of the inverter INV124-13 are connected, and a node J122-13 is configured by the connection point. These inverters INV123-13 and INV124-13 constitute a latch.
Then, the second stage latch 12-13 outputs data Q from the output terminal of the inverter INV122-13.
[0165]
In this case, for example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and the output node of the inverter INV121-13 of the second stage latch 12-13. / 111 becomes a high level. At this time, the second output node H112 of the first stage latch 11-10 is at the high level.
As a result, the NMOS transistor NT121-13 is turned on, the PMOS transistor PT123-13 is turned off, the node J121-13 becomes low level, and the high level data Q is immediately output from the inverter INV122-13.
Note that the data of the node J121-13 is maintained at the level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-13 and INV124-13.
[0166]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0167]
According to the fourteenth embodiment, since the second stage latch 12-13 is provided with the circuit for transmitting the output signal change of the first stage latch to the final output signal in a short time, the sixth and eleventh embodiments In addition to the effect of the mode, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0168]
15th embodiment
FIG. 16 is a circuit diagram showing a fifteenth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0169]
The fifteenth embodiment is different from the fourteenth embodiment described above in that the second-stage latch 12-14 is different from the output signal change of the first-stage latch 11-10 when the opposite signals are held. At the same time, the circuit configuration is such that the reciprocal signal held in the second stage latch is invalidated.
Specifically, the inverter INV124-14 constituting the cross latch is constituted by a clocked inverter (Clocked Inverter) connected to the nodes / H111 and H112.
[0170]
In this case, for example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and the output node of the inverter INV121-13 of the second stage latch 12-14. / H111 goes high. At this time, the second output node H112 of the first stage latch 11-10 is at the high level.
As a result, the NMOS transistor NT121-13 is turned on, the PMOS transistor PT123-13 is turned off, and the node J121-13 becomes low level.
At this time, the clocked inverter INV124-14 cannot output a high level, and the high level data Q is promptly output from the inverter INV122-13.
Therefore, the high-level data Q is output from the inverter INV122-13 promptly without preventing the node J121-13 from changing to the low level.
The data of the node J121-13 is maintained even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-13 and INV124-14.
[0171]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0172]
According to the fifteenth embodiment, in addition to the effects of the fourteenth embodiment, high-level data can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0173]
Sixteenth embodiment
FIG. 17 is a circuit diagram showing a sixteenth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0174]
The difference between the sixteenth embodiment and the sixth embodiment is the configuration of the latch portion of the first stage latch 11-15.
Specifically, in the latch unit 215 according to the sixteenth embodiment, the connection position of the NMOS transistor NT212 as the fifth switching element and the NMOS transistor NT213 as the seventh switching element in the first signal path SP211, In addition, the connection position of the NMOS transistor NT216 as the sixth switching element and the NMOS transistor NT217 as the eighth switching element in the second signal path SP212 is changed.
[0175]
Specifically, in the first signal path SP211, the drain of the NMOS transistor NT212 is connected to the second intermediate node G211, the source is connected to the ground potential GND, and the drain of the NMOS transistor NT213 is connected to the first intermediate node F211. And the source is connected to the second intermediate node G211.
Similarly, in the second signal path SP212, the drain of the NMOS transistor NT216 is connected to the fourth intermediate node G212, the source is connected to the ground potential GND, and the drain of the NMOS transistor NT217 is connected to the third intermediate node F212. The source is connected to the fourth intermediate node G212.
[0176]
Next, the operation of the sense amplifier type D flip-flop 10-4 in FIG. 17 will be described.
[0177]
Here, it is assumed that the output data Q by the second-stage latch 12 is held at a low level and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the normal input data D and the inverted input data Db are output data Q and output. In the following description, it is assumed that data Qb is supplied at different levels (level mismatch).
[0178]
During the period when the clock signal CK is at a low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0179]
Since the output data Q is held at a low level and the output inverted data Qb is held at a high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115 and PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at the high level and the inverted signal Db is supplied at the low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117 and PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistances, through which the first output node H111 and the second output node H112 are connected to the power supply voltage V_DDAre electrically connected to the first supply line (second potential source) and precharged to a complete logic 1 potential (high level).
[0180]
Then, the PMOS transistors PT212 and PT213 are cut off.
At this time, since the NMOS transistors NT211 and NT215 are cut off, the first intermediate node F211 and the third intermediate node F212 are not charged.
On the other hand, the NMOS transistors NT213, NT214, NT217, and NT218 are turned on when the first output node H111 and the second output node H112 are precharged to a high level.
As a result, regardless of the state of the data input signal D and the inverted signal Db, the first intermediate node F211 is discharged through the NMOS transistor NT214, and the third intermediate node F212 is discharged through the NMOS transistor NT218 to be at the low level.
Therefore, charge is performed only on the first output node H111 and the second output node H112 while the clock signal CK is at a low level.
[0181]
Next, when the clock signal CK becomes high level, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Here, when the data input signal D is high level and supplied to the gate of the NMOS transistor NT212, and the inverted signal Db is supplied low level to the gate of the NMOS transistor NT216, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first signal path SP211 is electrically connected from the first output node H111 to the ground potential GND. Therefore, the charge charged in the first output node H111 is discharged through the NMOS transistors NT211 to NT213 and NT214. As a result, the first output node H111 is set to the low level, and the high-level data Q is output from the NAND gate NA121 of the second-stage latch 12.
[0182]
On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
However, when the potential of the first output node H111 is lowered, the PMOS transistor PT213 is turned on, the NMOS transistors NT217 and NT218 are cut off, and the potential of the second output node H112 that has been lowered is raised, and again the complete logic A potential of 1 is obtained and held at a high level.
[0183]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0184]
Since the operation of the pre-setting unit 112 is performed in the same manner as in the first embodiment described above, detailed description thereof is omitted here.
[0185]
According to the sixteenth embodiment, effects similar to those of the sixth embodiment described above can be obtained.
[0186]
Seventeenth embodiment
FIG. 18 is a circuit diagram showing a seventeenth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0187]
The seventeenth embodiment differs from the sixteenth embodiment described above in that inverters INV121-16 and INV122-16 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-16. .
[0188]
Other configurations are the same as those in the sixteenth embodiment described above.
[0189]
According to the seventeenth embodiment, the influence of crosstalk or the like can be suppressed.
Further, the first stage latch 11-15 in the previous stage can shorten the setup time, and the output signal of the first stage latch 11-15 can be determined in a short time, thereby shortening the valid delay. Therefore, even if an inverter is inserted and the valid delay becomes longer, the overall advantage is that high-speed operation can be realized and power consumption can be reduced without depending on the circuit design method. is there.
[0190]
18th embodiment
FIG. 19 is a circuit diagram showing an eighteenth embodiment of the sense amplifier type D flip-flop according to the present invention.
[0191]
The nineteenth embodiment differs from the sixteenth embodiment described above in that in the second stage latch 12-17, the output signal change of the first stage (previous stage) latch is transmitted to the final output signal in a short time. It is in having established.
[0192]
Specifically, the second-stage latch 12-17 is constituted by four 2-input NAND gates NA121-17 to NA124-17.
The first input terminal of the NAND gate NA121-17 is connected to the first output node H111 of the first stage latch 11-15, and the second input terminal is the output terminal of the NAND gate NA122-17 and the first input node of the NAND gate NA124-17. The node I121-17 is configured by these connection points connected to one input terminal.
The first input terminal of the NAND gate NA122-17 is connected to the second node H112 of the first stage latch 11-15, the second input terminal is the output terminal of the NAMD gate NA121-17, and the first input of the NAND gate NA123-17. The node I122-17 is configured by the connection points connected to the input terminals.
The second input terminal of the NAND gate NA123-17 is connected to the second node H112 of the first stage latch 11-15, and the second input terminal of the NAND gate NA124-17 is the first input of the first stage latch 11-15. It is connected to the node H111.
The second-stage latch 12-17 outputs data Q from the NAND gate NA124-17 and outputs inverted data Qb from the NAND gate NA123-17.
[0193]
For example, if the data input signal D is at high level and its inverted signal Db is at low level, the first output node H111 is at low level, promptly becoming higher than the NAND gate NA124-17 of the second stage latch 12-17. Data Q is output.
Further, the output data Qb of the NAND gate NA123-17 becomes low level via the NAND gate NA121-17.
[0194]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0195]
According to the eighteenth embodiment, the second stage latch 12-17 is provided with a circuit for transmitting the output signal change of the first stage latch of the preceding stage to the final output signal in a short time. In addition to the effects of the embodiment, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0196]
Nineteenth embodiment
FIG. 20 is a circuit diagram showing a nineteenth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0197]
The difference between the twentieth embodiment and the sixteenth embodiment is the circuit configuration of the second-stage latch 12-18.
[0198]
Specifically, as shown in FIG. 20, the second stage latch 12-18 includes inverters INV121-18 to INV124-18, a PMOS transistor PT123-18, and an NMOS transistor NT121-18.
[0199]
The source of the PMOS transistor PT123-18 is the power supply voltage V_DDThe drain is connected to the drain of the NMOS transistor NT121-18, and a node J121-18 is constituted by this connection point. The source of the NMOS transistor NT121-18 is connected to the ground potential GND.
The input terminal of the inverter INV121-18 is connected to the first output node H111 of the first stage latch 11-15, and the output terminal is connected to the gate of the NMOS transistor NT121-18. Here, a connection point between the output terminal of the inverter INV121-18 and the gate of the NMOS transistor NT121-18 is defined as a node / H111.
Node J121-18 is connected to the input terminals of inverters INV122-18 and INV123-18 and to the output terminal of inverter INV124-18.
Further, the output terminal of the inverter INV123-18 and the input terminal of the inverter INV124-18 are connected, and a node J122-18 is configured by the connection point. These inverters INV123-18 and INV124-18 constitute a latch.
Then, the second stage latch 12-18 outputs data Q from the output terminal of the inverter INV122-18.
[0200]
In this case, for example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and the output node of the inverter INV121-18 of the second stage latch 12-18. / 111 becomes a high level. At this time, the second output node H112 of the first stage latch 11-15 is at the high level.
As a result, the NMOS transistor NT121-18 is turned on, the PMOS transistor PT123-18 is turned off, the node J121-18 goes to the low level, and the high level data Q is immediately output from the inverter INV122-18.
Note that the data of the node J121-18 is maintained even when the clock signal CK is switched to a low level by the cross latch of the inverters INV123-18 and INV124-18.
[0201]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0202]
According to the nineteenth embodiment, since the second stage latch 12-19 is provided with the circuit for transmitting the output signal change of the first stage latch to the final output signal in a short time, the sixth and sixteenth embodiments In addition to the effect of the mode, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0203]
20th embodiment
FIG. 21 is a circuit diagram showing a twentieth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0204]
The difference between the twentieth embodiment and the nineteenth embodiment described above is that the second stage latch 12-19 is different from the output signal change of the first stage latch 11-15 when the contradictory signals are held. At the same time, the circuit configuration is such that the reciprocal signal held in the second stage latch is invalidated.
Specifically, the inverter INV124-19 constituting the cross latch is constituted by a clocked inverter (Clocked Inverter) connected to the nodes / H111 and H112.
[0205]
In this case, for example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and the output node of the inverter INV121-18 of the second stage latch 12-19. / H111 goes high. At this time, the second output node H112 of the first stage latch 11-15 is at the high level.
As a result, the NMOS transistor NT121-18 is turned on, the PMOS transistor PT123-18 is turned off, and the node J121-18 becomes low level.
At this time, the clocked inverter INV124-19 cannot output the high level, and the high level data Q is promptly output from the inverter INV122-18.
Therefore, the high-level data Q is output from the inverter INV122-18 promptly without preventing the node J121-18 from changing to the low level.
The data of the node J121-18 is maintained at the level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-18 and INV124-19.
[0206]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0207]
According to the twentieth embodiment, in addition to the effects of the nineteenth embodiment, high-level data can be output more quickly than in the conventional circuit, so that high-speed operation is possible.
[0208]
21st embodiment
FIG. 22 is a circuit diagram showing a twenty-first embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0209]
The difference between the twenty-first embodiment and the sixth embodiment is the configuration of the latch section of the first-stage latch 11-20.
Specifically, in the latch unit 220 according to the twenty-first embodiment, the connection position of the source of the NMOS transistor NT214 as the ninth switching element and the connection of the source of the NMOS transistor NT218 as the tenth switching element The position has been changed.
[0210]
Specifically, the source of the NMOS transistor NT214 is connected to the fourth intermediate node G212 instead of being grounded.
Similarly, the source of the NMOS transistor NT218 is connected to the second intermediate node G211 instead of being grounded.
[0211]
Next, the operation of the sense amplifier type D flip-flop 10-20 of FIG. 22 will be described.
[0212]
Here, it is assumed that the output data Q by the second-stage latch 12 is held at a low level and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the normal input data D and the inverted input data Db are output data Q and output. In the following description, it is assumed that data Qb is supplied at different levels (level mismatch).
[0213]
During the period when the clock signal CK is at a low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0214]
Since the output data Q is held at a low level and the output inverted data Qb is held at a high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115 and PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at the high level and the inverted signal Db is supplied at the low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117 and PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistances, through which the first output node H111 and the second output node H112 are connected to the power supply voltage V_DDAre electrically connected to the first supply line (second potential source) and precharged to a complete logic 1 potential (high level).
[0215]
Then, the PMOS transistors PT212 and PT213 are cut off.
At this time, since the NMOS transistors NT211 and NT215 are cut off, the first intermediate node F211 and the third intermediate node F212 are not charged.
On the other hand, the NMOS transistors NT213, NT214, NT217, and NT218 are turned on when the first output node H211 and the second output node H212 are precharged to a high level.
Since either one of the data input signal D and the inverted signal Db is at a high level, either the NMOS transistor NT212 or the NMOS transistor NT216 is in an on state.
As a result, the first intermediate node F211 and the second intermediate node G211 are held at a low level by discharging electric charges through the NMOS transistor NT213 and the NMOS transistor NT212 or the NMOS transistors NT213, NT214, NT218, and NT216. .
Similarly, in the third intermediate node F212 and the fourth intermediate node G212, electric charges are discharged through the NMOS transistor NT217 and the NMOS transistor NT216, or the NMOS transistors NT217, NT214, NT218, and NT212 and held at the low level. .
Therefore, charge is performed only on the first output node H111 and the second output node H112 while the clock signal CK is at a low level.
[0216]
Next, when the clock signal CK becomes high level, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Therefore, the power supply voltage is V_DD[V] If the threshold value of the NMOS transistor is Vthn, the potentials of the first intermediate node F211 and the second intermediate node F212 at this time are (V_DD-Vthn) [V]. Here, when the data input signal D is high level and supplied to the gate of the NMOS transistor NT212, and the inverted signal Db is supplied low level to the gate of the NMOS transistor NT216, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first signal path SP211 is electrically connected from the first output node H111 to the ground potential GND. Therefore, the charge charged in the first output node H111 is discharged through the NMOS transistors NT211 to NT213. As a result, the first output node H111 is set to the low level, and the high-level data Q is output from the NAND gate NA121 of the second-stage latch 12.
[0217]
On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
However, when the potential of the first output node H111 is lowered, the PMOS transistor PT213 is turned on, the NMOS transistors NT217 and NT218 are cut off, and the potential of the second output node H112 that has been lowered is raised, and again the complete logic A potential of 1 is obtained and held at a high level.
[0218]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0219]
Since the operation of the pre-setting unit 112 is performed in the same manner as in the first embodiment described above, detailed description thereof is omitted here.
[0220]
According to the twenty-first embodiment, the same effect as that of the sixth embodiment described above can be obtained.
[0221]
Twenty-second embodiment
FIG. 23 is a circuit diagram showing a twenty-second embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0222]
The difference between the twenty-second embodiment and the twenty-first embodiment is that the inverters INV121-21 and INV122-21 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-21. .
[0223]
Other configurations are the same as those in the twenty-first embodiment described above.
[0224]
According to the twenty-second embodiment, the influence of crosstalk or the like can be suppressed.
In addition, the first stage latch 11-20 in the previous stage can shorten the setup time, and the output signal of the first stage latch 11-20 can be determined in a short time, thereby shortening the valid delay. Therefore, even if an inverter is inserted and the valid delay becomes longer, the overall advantage is that high-speed operation can be realized and power consumption can be reduced without depending on the circuit design method. is there.
[0225]
23rd embodiment
FIG. 24 is a circuit diagram showing a twenty-third embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0226]
The difference between the twenty-third embodiment and the twenty-first embodiment is that the second stage latch 12-22 transmits a change in the output signal of the first stage (previous stage) latch to the final output signal in a short time. It is in having established.
[0227]
Specifically, the second stage latch 12-22 is configured by four two-input NAND gates NA121-22 to NA124-22.
The first input terminal of the NAND gate NA121-22 is connected to the first output node H111 of the first stage latch 11-20, and the second input terminal is the output terminal of the NAND gate NA122-22 and the first input node of the NAND gate NA124-22. The node I121-22 is configured by these connection points connected to one input terminal.
The first input terminal of the NAND gate NA122-22 is connected to the second node H112 of the first stage latch 11-20, the second input terminal is the output terminal of the NAMD gate NA121-22, and the first input of the NAND gate NA123-22. The node I122-22 is configured by the connection points connected to the input terminals.
The second input terminal of the NAND gate NA123-22 is connected to the second node H112 of the first stage latch 11-20, and the second input terminal of the NAND gate NA124-22 is the first stage of the first stage latch 11-20. It is connected to the node H111.
The second-stage latch 12-22 outputs data Q from the NAND gate NA124-22 and outputs inverted data Qb from the NAND gate NA123-22.
[0228]
For example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, which is immediately higher than the NAND gate NA124-22 of the second stage latch 12-22. Level data Q is output.
Further, the output data Qb of the NAND gate NA123-22 becomes a low level via the NAND gate NA121-22.
[0229]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0230]
According to the twenty-third embodiment, the second stage latch 12-22 is provided with a circuit for transmitting the output signal change of the first stage latch of the previous stage to the final output signal in a short time. In addition to the effects of the embodiment, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0231]
24th embodiment
FIG. 25 is a circuit diagram showing a twenty-fourth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0232]
The twenty-fourth embodiment is different from the twenty-first embodiment in the circuit configuration of the second-stage latch 12-23.
[0233]
Specifically, as shown in FIG. 25, the second stage latch 12-23 includes inverters INV121-23 to INV124-23, a PMOS transistor PT123-23, and an NMOS transistor NT121-23.
[0234]
The source of the PMOS transistor PT123-23 is the power supply voltage V_DDThe drain is connected to the drain of the NMOS transistor NT121-23, and the node J121-23 is constituted by this connection point. The source of the NMOS transistor NT121-23 is connected to the ground potential GND.
The input terminal of the inverter INV121-23 is connected to the first output node H111 of the first stage latch 11-20, and the output terminal is connected to the gate of the NMOS transistor NT121-23. Here, a connection point between the output terminal of the inverter INV121-23 and the gate of the NMOS transistor NT121-23 is a node / H111.
Node J121-23 is connected to the input terminals of inverters INV122-23 and INV123-23 and the output terminal of inverter INV124-23.
Further, the output terminal of the inverter INV123-23 and the input terminal of the inverter INV124-23 are connected, and a node J122-23 is configured by the connection point. These inverters INV123-23 and INV124-23 constitute a latch.
The second stage latch 12-23 outputs data Q from the output terminal of the inverter INV122-23.
[0235]
In this case, for example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and the output node of the inverter INV121-23 of the second stage latch 12-23. / 111 becomes a high level. At this time, the second output node H112 of the first stage latch 11-20 is at a high level.
As a result, the NMOS transistor NT121-23 is turned on, the PMOS transistor PT123-23 is turned off, the node J121-23 becomes low level, and the high level data Q is output from the inverter INV122-23 promptly.
Note that the data of the node J121-23 is maintained even when the clock signal CK is switched to a low level by the cross latch of the inverters INV123-23 and INV124-23.
[0236]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0237]
According to the twenty-fourth embodiment, since the second stage latch 12-23 is provided with the circuit for transmitting the output signal change of the first stage latch to the final output signal in a short time, the sixth and twenty-first embodiments. In addition to the effect of the mode, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0238]
25th embodiment
FIG. 26 is a circuit diagram showing a twenty-fifth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0239]
The difference between the twenty-fifth embodiment and the twenty-fourth embodiment described above is that the second-stage latch 12-24 is different from the change in the output signal of the first-stage latch 11-20 when the opposite signals are held. At the same time, the circuit configuration is such that the reciprocal signal held in the second stage latch is invalidated.
Specifically, the inverter INV124-24 configuring the cross latch is configured by a clocked inverter connected to the nodes / H111 and H112.
[0240]
In this case, for example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and the output node of the inverter INV121-23 of the second stage latch 12-24. / H111 goes high. At this time, the second output node H112 of the first stage latch 11-20 is at a high level.
As a result, the NMOS transistor NT121-23 is turned on, the PMOS transistor PT123-23 is turned off, and the node J121-23 becomes low level.
At this time, the clocked inverter INV124-24 cannot output the high level, and the high level data Q is promptly output from the inverter INV122-23.
Therefore, the high-level data Q is output from the inverter INV122-23 promptly without preventing the node J121-23 from changing to the low level.
Further, the data of the node J121-23 is maintained at the level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-23 and INV124-24.
[0241]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0242]
According to the twenty-fifth embodiment, in addition to the effects of the twenty-fourth embodiment, high-level data can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0243]
26th embodiment
FIG. 27 is a circuit diagram showing a twenty-sixth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0244]
The difference between the twenty-sixth embodiment and the twenty-first embodiment is the configuration of the latch portion of the first stage latch 11-25.
Specifically, in the latch unit 225 according to the twenty-sixth embodiment, the second intermediate node G211 and the fourth intermediate node G212 are connected at the gate to the power supply voltage V_DDThe NMOS transistor NT219 functioning as an on-resistance connected to the supply line is connected.
[0245]
Other configurations are the same as those in the twenty-first embodiment described above.
[0246]
Since the operation according to the twenty-sixth embodiment is basically performed in the same manner as the operation of the twenty-first embodiment described above, detailed description thereof is omitted here.
[0247]
According to the twenty-sixth embodiment, the same effects as those of the sixth and twenty-first embodiments described above can be obtained.
[0248]
27th embodiment
FIG. 28 is a circuit diagram showing a twenty-seventh embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0249]
The difference between the twenty-seventh embodiment and the twenty-sixth embodiment is that inverters INV121-26 and INV122-26 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-26. .
[0250]
Other configurations are the same as those in the twenty-sixth embodiment described above.
[0251]
According to the twenty-seventh embodiment, the influence of crosstalk or the like can be suppressed.
In addition, the first stage latch 11-25 in the previous stage can shorten the setup time, and the output signal of the first stage latch 11-25 can be determined in a short time, thereby shortening the valid delay. Therefore, even if an inverter is inserted and the valid delay becomes longer, the overall advantage is that high-speed operation can be realized and power consumption can be reduced without depending on the circuit design method. is there.
[0252]
28th embodiment
FIG. 29 is a circuit diagram showing a twenty-eighth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0253]
The difference between the twenty-eighth embodiment and the twenty-sixth embodiment is that the second stage latch 12-27 transmits a change in the output signal of the first stage (previous stage) latch to the final output signal in a short time. It is in having established.
[0254]
Specifically, the second stage latch 12-27 is configured by four 2-input NAND gates NA121-27 to NA124-27.
The first input terminal of the NAND gate NA121-27 is connected to the first output node H111 of the first stage latch 11-25, and the second input terminal is the output terminal of the NAND gate NA122-27 and the first input node of the NAND gate NA124-27. A node I121-27 is configured by these connection points connected to one input terminal.
The first input terminal of the NAND gate NA122-27 is connected to the second node H112 of the first stage latch 11-25, the second input terminal is the output terminal of the NAMD gate NA121-27, and the first input of the NAND gate NA123-27. The node I122-27 is configured by these connection points connected to the input terminals.
The second input terminal of the NAND gate NA123-27 is connected to the second node H112 of the first stage latch 11-25, and the second input terminal of the NAND gate NA124-27 is the first input of the first stage latch 11-25. It is connected to the node H111.
The second-stage latch 12-27 outputs data Q from the NAND gate NA124-27 and outputs inverted data Qb from the NAND gate NA123-27.
[0255]
For example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and is quickly higher than the NAND gate NA124-27 of the second stage latch 12-27. Level data Q is output.
Further, the output data Qb of the NAND gate NA123-27 becomes low level via the NAND gate NA121-27.
[0256]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0257]
According to the twenty-eighth embodiment, since the second stage latch 12-27 is provided with the circuit for transmitting the change in the output signal of the first stage latch of the preceding stage to the final output signal in a short time, In addition to the effects of the embodiment, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0258]
29th embodiment
FIG. 30 is a circuit diagram showing a twenty-ninth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0259]
The difference between the twenty-ninth embodiment and the twenty-sixth embodiment is the circuit configuration of the second-stage latches 12-28.
[0260]
Specifically, as shown in FIG. 30, the second-stage latch 12-28 includes inverters INV121-28 to INV124-28, a PMOS transistor PT123-28, and an NMOS transistor NT121-28.
[0261]
The source of the PMOS transistor PT123-28 is the power supply voltage V_DDThe drain is connected to the drain of the NMOS transistor NT121-28, and a node J121-28 is constituted by this connection point. The source of the NMOS transistor NT121-28 is connected to the ground potential GND.
The input terminal of the inverter INV121-28 is connected to the first output node H111 of the first stage latch 11-25, and the output terminal is connected to the gate of the NMOS transistor NT121-28. Here, a connection point between the output terminal of the inverter INV121-28 and the gate of the NMOS transistor NT121-28 is a node / H111.
Node J121-28 is connected to the input terminals of inverters INV122-28 and INV123-28 and the output terminal of inverter INV124-28.
Further, the output terminal of the inverter INV123-28 and the input terminal of the inverter INV124-28 are connected, and a node J122-28 is configured by the connection point. These inverters INV123-28 and INV124-28 constitute a latch.
The second-stage latch 12-28 outputs data Q from the output terminal of the inverter INV122-28.
[0262]
In this case, for example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and the output node of the inverter INV121-28 of the second stage latch 12-28. / 111 becomes a high level. At this time, the second output node H112 of the first stage latch 11-25 is at the high level.
As a result, the NMOS transistor NT121-28 is turned on, the PMOS transistor PT123-28 is turned off, the node J121-28 becomes low level, and the high level data Q is output from the inverter INV122-28 immediately.
Note that the data of the node J121-28 is maintained at the level even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-28 and INV124-28.
[0263]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0264]
According to the twenty-ninth embodiment, since the second stage latch 12-28 is provided with the circuit for transmitting the output signal change of the first stage latch to the final output signal in a short time, the sixth and twenty-sixth implementations. In addition to the effect of the mode, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0265]
30th embodiment
FIG. 31 is a circuit diagram showing a 30th embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0266]
The difference between the thirtieth embodiment and the twenty-ninth embodiment is that the second-stage latch 12-29 is different from the output signal change of the first-stage latch 11-25 when the opposite signals are held. At the same time, the circuit configuration is such that the reciprocal signal held in the second stage latch is invalidated.
Specifically, the inverter INV124-29 constituting the cross latch is constituted by a clocked inverter (Clocked Inverter) connected to the nodes / H111 and H112.
[0267]
In this case, for example, if the data input signal D is high level and its inverted signal Db is low level, the first output node H111 is low level, and the output node of the inverter INV121-28 of the second stage latch 12-29. / H111 goes high. At this time, the second output node H112 of the first stage latch 11-25 is at the high level.
As a result, the NMOS transistor NT121-28 is turned on, the PMOS transistor PT123-28 is turned off, and the node J121-28 becomes low level.
At this time, the clocked inverter INV124-29 cannot output a high level, and the high level data Q is promptly output from the inverter INV122-28.
Therefore, high-level data Q is output from the inverter INV122-28 promptly without preventing the node J121-28 from changing to the low level.
The data of the node J121-28 is maintained even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-28 and INV124-29.
[0268]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0269]
According to the thirtieth embodiment, in addition to the effects of the twenty-ninth embodiment, high-level data can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0270]
31st embodiment
FIG. 32 is a circuit diagram showing a thirty-first embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0271]
The difference between the thirty-first embodiment and the sixth embodiment is the configuration of the latch section of the first stage latch 11-30.
Specifically, in the latch unit 230 according to the thirty-first embodiment, the connection position of the NMOS transistor NT211 as the third switching element and the NMOS transistor NT215 as the fifth switching element in the first signal path SP211; And the connection position of the drain of the NMOS transistor NT214 as the ninth switching element, and the connection position of the NMOS transistor NT215 as the fourth switching element and the NMOS transistor NT216 as the sixth switching element in the second signal path SP212 , And the connection position of the drain of the NMOS transistor NT218 as the tenth switching element.
[0272]
  Specifically, in the first signal path SP211, the drain of the NMOS transistor NT211 is connected to the first intermediate node F211, the source is connected to the second intermediate node G211, and the drain of the NMOS transistor NT212 is connected to the first intermediate node F211. outputnodeH111 is connected, and the source is connected to the first intermediate node F211. The drain of the NMOS transistor NT214 is connected to the first output node H111, and the source is connected to the first intermediate node F211.
  Similarly, in the second signal path SP212, the drain of the NMOS transistor NT215 is connected to the third intermediate node F212, the source is connected to the fourth intermediate node G212, and the drain of the NMOS transistor NT216 is connected to the second output.nodeH112 is connected, and the source is connected to the third intermediate node F212. The drain of the NMOS transistor NT218 is connected to the second output node H112, and the source is connected to the third intermediate node F212.
[0273]
Next, the operation of the sense amplifier type D flip-flop 10-30 in FIG. 32 will be described.
[0274]
Here, it is assumed that the output data Q by the second-stage latch 12 is held at a low level and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the normal input data D and the inverted input data Db are output data Q and output. In the following description, it is assumed that data Qb is supplied at different levels (level mismatch).
[0275]
During the period when the clock signal CK is at a low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0276]
Since the output data Q is held at a low level and the output inverted data Qb is held at a high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115 and PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at the high level and the inverted signal Db is supplied at the low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117 and PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistances, through which the first output node H111 and the second output node H112 are connected to the power supply voltage V_DDAre electrically connected to the first supply line (second potential source) and precharged to a complete logic 1 potential (high level).
[0277]
Then, the PMOS transistors PT212 and PT213 are cut off.
At this time, since the NMOS transistors NT211 and NT215 are cut off, the second intermediate node G212 and the fourth intermediate node G212 are not charged.
On the other hand, the NMOS transistors NT213, NT214, NT217, and NT218 are turned on when the first output node H111 and the second output node H112 are precharged to a high level.
Since either one of the data input signal D and the inverted signal Db is at a high level, either the NMOS transistor NT212 or the NMOS transistor NT216 is in an on state.
As a result, the first intermediate node F211 and the third intermediate node F212 have (V_DD−Vth) level.
Further, the second intermediate node G211 is held at a low level as the charge is discharged through the NMOS transistor NT213.
Similarly, the fourth intermediate node G212 is held at a low level as the charge is discharged through the NMOS transistor NT217.
Therefore, in the period in which the clock signal CK is at the low level, the charge is charged only to the first output node H111 and the second output node H112, and the first intermediate node F211 and the third intermediate node F212. Done.
[0278]
Next, when the clock signal CK becomes high level, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Here, when the data input signal D is high level and supplied to the gate of the NMOS transistor NT212, and the inverted signal Db is supplied low level to the gate of the NMOS transistor NT216, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first signal path SP211 is electrically connected from the first output node H111 to the ground potential GND. Therefore, the charge charged in the first output node H111 is discharged through the NMOS transistors NT211 to NT213 and NT214. As a result, the first output node H111 is set to the low level, and the high-level data Q is output from the NAND gate NA121 of the second-stage latch 12.
[0279]
On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
However, when the potential of the first output node H111 is lowered, the PMOS transistor PT213 is turned on, the NMOS transistors NT217 and NT218 are cut off, and the potential of the second output node H112 that has been lowered is raised, and again the complete logic A potential of 1 is obtained and held at a high level.
[0280]
When the data input signal D is at a high level, the level of the fourth intermediate node G212 is (V_DD−Vth) / 2 level.
[0281]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
In this case, the level of the fourth intermediate node G212 is the ground level, but the second intermediate node G211 is (V_DD−Vth) / 2 level.
[0282]
Since the operation of the pre-setting unit 112 is performed in the same manner as in the first embodiment described above, detailed description thereof is omitted here.
[0283]
According to the thirty-first embodiment, the same effects as those of the sixth embodiment described above can be obtained.
[0284]
Thirty-second embodiment
FIG. 33 is a circuit diagram showing a thirty-second embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0285]
The difference between the thirty-second embodiment and the thirty-first embodiment is that inverters INV121-31 and INV122-31 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-31. .
[0286]
Other configurations are the same as those in the thirty-first embodiment described above.
[0287]
According to the thirty-second embodiment, the influence of crosstalk or the like can be suppressed.
Further, the first stage latch 11-30 in the previous stage can shorten the setup time, and the output signal of the first stage latch 11-30 can be determined in a short time, thereby reducing the valid delay. Therefore, even if an inverter is inserted and the valid delay becomes longer, the overall advantage is that high-speed operation can be realized and power consumption can be reduced without depending on the circuit design method. is there.
[0288]
Thirty-third embodiment
FIG. 34 is a circuit diagram showing a thirty-third embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0289]
The difference between the thirty-third embodiment and the thirty-first embodiment is that in the second-stage latch 12-32, the output signal change of the first-stage (previous) latch is transmitted to the final output signal in a short time. It is in having established.
[0290]
Specifically, the second stage latch 12-32 is configured by four 2-input NAND gates NA121-32 to NA124-32.
The first input terminal of the NAND gate NA121-32 is connected to the first output node H111 of the first stage latch 11-30, the second input terminal is the output terminal of the NAND gate NA122-32 and the first input node of the NAND gate NA124-32. The node I121-32 is configured by these connection points connected to one input terminal.
The first input terminal of the NAND gate NA122-32 is connected to the second node H112 of the first stage latch 11-30, and the second input terminal is the output terminal of the NAMD gate NA121-32 and the first input of the NAND gate NA123-32. The node I122-32 is configured by these connection points connected to the input terminals.
The second input terminal of the NAND gate NA123-32 is connected to the second node H112 of the first stage latch 11-30, and the second input terminal of the NAND gate NA124-32 is the first input of the first stage latch 11-30. It is connected to the node H111.
The second-stage latch 12-32 outputs data Q from the NAND gate NA124-32 and outputs inverted data Qb from the NAND gate NA123-32.
[0291]
For example, if the data input signal D is at a high level and the inverted signal Db is at a low level, the first output node H111 is at a low level, and is quickly higher than the NAND gate NA124-32 of the second stage latch 12-32. Level data Q is output.
Further, the output data Qb of the NAND gate NA123-32 becomes low level through the NAND gate NA121-32.
[0292]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0293]
According to the thirty-third embodiment, the second-stage latch 12-32 is provided with a circuit for transmitting the change in the output signal of the first-stage latch in the preceding stage to the final output signal in a short time. In addition to the effects of the embodiment, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0294]
34th embodiment
FIG. 35 is a circuit diagram showing a thirty-fourth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0295]
The 34th embodiment differs from the 31st embodiment described above in the circuit configuration of the second stage latch 12-33.
[0296]
Specifically, as shown in FIG. 35, the second stage latch 12-33 includes inverters INV121-33 to INV124-33, a PMOS transistor PT123-33, and an NMOS transistor NT121-33.
[0297]
The source of the PMOS transistor PT123-33 is the power supply voltage V_DDThe drain is connected to the drain of the NMOS transistor NT121-33, and a node J121-33 is constituted by this connection point. The source of the NMOS transistor NT121-33 is connected to the ground potential GND.
The input terminal of the inverter INV121-33 is connected to the first output node H111 of the first stage latch 11-30, and the output terminal is connected to the gate of the NMOS transistor NT121-33. Here, a connection point between the output terminal of the inverter INV121-33 and the gate of the NMOS transistor NT121-33 is a node / H111.
Node J121-33 is connected to the input terminals of inverters INV122-33 and INV123-33 and the output terminal of inverter INV124-33.
Further, the output terminal of the inverter INV123-33 and the input terminal of the inverter INV124-33 are connected, and a node J122-33 is configured by the connection point. These inverters INV123-33 and INV124-33 constitute a latch.
The second stage latch 12-33 outputs data Q from the output terminal of the inverter INV122-33.
[0298]
In this case, for example, if the data input signal D is high level and its inverted signal Db is low level, the first output node H111 is low level, and the output node of the inverter INV121-33 of the second stage latch 12-33. / 111 becomes a high level. At this time, the second output node H112 of the first stage latch 11-30 is at the high level.
As a result, the NMOS transistor NT121-33 is turned on, the PMOS transistor PT123-33 is turned off, the node J121-33 becomes low level, and the high level data Q is quickly output from the inverter INV122-33.
Note that the data of the node J121-33 is maintained even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-33 and INV124-33.
[0299]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0300]
According to the thirty-fourth embodiment, since the second stage latch 12-33 is provided with the circuit for transmitting the change in the output signal of the first stage latch to the final output signal in a short time, the sixth and thirty-first embodiments. In addition to the effect of the mode, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0301]
35th embodiment
FIG. 36 is a circuit diagram showing a 35th embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0302]
The difference between the thirty-fifth embodiment and the thirty-fourth embodiment described above is that the second-stage latch 12-34 is different from the output signal change of the first-stage latch 11-30 when the opposite signals are held. At the same time, the circuit configuration is such that the reciprocal signal held in the second stage latch is invalidated.
Specifically, the inverter INV124-34 constituting the cross latch is constituted by a clocked inverter connected to nodes / H111 and H112.
[0303]
In this case, for example, if the data input signal D is high level and its inverted signal Db is low level, the first output node H111 is low level, and the output node of the inverter INV121-33 of the second stage latch 12-34. / H111 goes high. At this time, the second output node H112 of the first stage latch 11-30 is at the high level.
As a result, the NMOS transistor NT121-33 is turned on, the PMOS transistor PT123-33 is turned off, and the node J121-33 becomes low level.
At this time, the clocked inverter INV124-34 cannot output the high level, and the high level data Q is promptly output from the inverter INV122-33.
Therefore, the high-level data Q is output from the inverter INV122-33 promptly without preventing the node J121-33 from changing to the low level.
Further, the data of the node J121-33 is maintained even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-33 and INV124-34.
[0304]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0305]
According to the thirty-fifth embodiment, in addition to the effects of the thirty-fourth embodiment, high-level data can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0306]
36th embodiment
FIG. 37 is a circuit diagram showing a thirty-sixth embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0307]
The difference between the thirty-sixth embodiment and the twenty-sixth embodiment is the configuration of the latch portion of the first stage latch 11-35.
Specifically, in the latch unit 235 according to the thirty-sixth embodiment, the connection position of the NMOS transistor NT211 as the third switching element and the NMOS transistor NT215 as the fifth switching element in the first signal path SP211; In addition, the connection position of the NMOS transistor NT215 as the fourth switching element and the NMOS transistor NT216 as the sixth switching element in the second signal path SP212 is changed.
[0308]
  Specifically, in the first signal path SP211, the drain of the NMOS transistor NT211 is connected to the first intermediate node F211, the source is connected to the second intermediate node G211, and the drain of the NMOS transistor NT212 is connected to the first intermediate node F211. outputnodeH111 is connected and the source is connected to the first intermediate node F211.
  Similarly, in the second signal path SP212, the drain of the NMOS transistor NT215 is connected to the third intermediate node F212, the source is connected to the fourth intermediate node G212, and the drain of the NMOS transistor NT216 is connected to the second output.nodeH112 is connected and the source is connected to the third intermediate node F212.
[0309]
Next, the operation of the sense amplifier type D flip-flop 10-35 of FIG. 37 will be described.
Here, it is assumed that the output data Q by the second-stage latch 12 is held at a low level and the inverted output data Qb is held at a high level.
First, at this time, for example, the data input signal D is supplied at a high level and its inverted signal Db is supplied at a low level. That is, the normal input data D and the inverted input data Db are output data Q and output. In the following description, it is assumed that data Qb is supplied at different levels (level mismatch).
[0310]
During the period when the clock signal CK is at a low level, the PMOS transistors PT111 and PT114 are turned on, and the NMOS transistors NT211 and NT215 are cut off.
[0311]
Since the output data Q is held at a low level and the output inverted data Qb is held at a high level, the PMOS transistors PT116 and PT119 and the NMOS transistor NT120 are turned on, and the PMOS transistors PT115 and PT120 and the NMOS transistor NT119 are turned on. Turns off.
Since the data input signal D is supplied at the high level and the inverted signal Db is supplied at the low level, the PMOS transistors PT118 and PT121 and the NMOS transistor NT117 are turned on, and the PMOS transistors PT117 and PT122 and the NMOS transistor NT118 are turned off. Become.
As a result, the PMOS transistors PT121, PT119, PT111 and PT118, PT116, PT114 behave equivalently as resistances, through which the first output node H111 and the second output node H112 are connected to the power supply voltage V_DDAre electrically connected to the first supply line (second potential source) and precharged to a complete logic 1 potential (high level).
[0312]
  Then, the PMOS transistors PT212 and PT213 are cut off.
  At this time, since the NMOS transistors NT211 and NT215 are cut off, the second intermediate node G212 and the fourth intermediate node G212 are not charged.
  On the other hand, NMOS transistor NT213, NT217 isThe first output node H111 and the second output node H112 are turned on when they are precharged to a high level.
  Since either one of the data input signal D and the inverted signal Db is at a high level, either the NMOS transistor NT212 or the NMOS transistor NT216 is in an on state.
  As a result, the first intermediate node F211 and the third intermediate node F212 are at the (VDD-Vth) level.
  Further, the second intermediate node G211 is held at a low level as the charge is discharged through the NMOS transistor NT212 or the NMOS transistors NT219 and NT216.
  Similarly, the fourth intermediate node G212 is held at a low level as the charge is discharged through the NMOS transistor NT216 or the NMOS transistors NT219 and NT212.
  Therefore, in the period in which the clock signal CK is at the low level, the charge is charged only to the first output node H111 and the second output node H112, and the first intermediate node F211 and the third intermediate node F212. Done.
[0313]
Next, when the clock signal CK becomes high level, the PMOS transistors PT111 and PT114 are turned off, and the NMOS transistors NT211 and NT215 are turned on.
Here, when the data input signal D is high level and supplied to the gate of the NMOS transistor NT212, and the inverted signal Db is supplied low level to the gate of the NMOS transistor NT216, the NMOS transistor NT212 is turned on and the NMOS transistor NT216 is turned off. Become. At this time, the NMOS transistor NT213 remains on.
As a result, the first signal path SP211 is electrically connected from the first output node H111 to the ground potential GND. Therefore, the charge charged in the first output node H111 is discharged through the NMOS transistors NT211 to NT213. As a result, the first output node H111 is set to the low level, and the high-level data Q is output from the NAND gate NA121 of the second-stage latch 12.
[0314]
  On the other hand, the electric charge of the second output node H112 is discharged for a very short time when the first output node H111 changes from the high level to the low level.
  However, when the potential of the first output node H111 decreases, the PMOS transistor PT213 is turned on, and the NMOS transistor NT21.7 isThe potential of the second output node H112, which is cut off and rises, rises, obtains a complete logic 1 potential again, and maintains a high level.
[0315]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0316]
Since the operation of the pre-setting unit 112 is performed in the same manner as in the first embodiment described above, detailed description thereof is omitted here.
[0317]
According to the thirty-sixth embodiment, effects similar to those of the sixth and twenty-sixth embodiments described above can be obtained.
[0318]
37th embodiment
FIG. 38 is a circuit diagram showing a thirty-seventh embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0319]
The difference between the thirty-seventh embodiment and the thirty-sixth embodiment is that inverters INV121-36 and INV122-36 are arranged on the output side of the NAND gates NA121 and NA122 of the second-stage latch 12-36. .
[0320]
Other configurations are the same as those in the thirty-sixth embodiment described above.
[0321]
According to the thirty-seventh embodiment, the influence of crosstalk or the like can be suppressed.
In addition, the first stage latch 11-35 in the previous stage can shorten the setup time, and the output signal of the first stage latch 11-35 can be determined in a short time, thereby reducing the valid delay. Therefore, even if an inverter is inserted and the valid delay becomes longer, the overall advantage is that high-speed operation can be realized and power consumption can be reduced without depending on the circuit design method. is there.
[0322]
38th embodiment
FIG. 39 is a circuit diagram showing a 38th embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0323]
The difference between the thirty-eighth embodiment and the thirty-sixth embodiment is that, in the second stage latch 12-37, a circuit for transmitting the output signal change of the first stage (previous stage) latch to the final output signal in a short time. It is in having established.
[0324]
Specifically, the second stage latch 12-37 is configured by four 2-input NAND gates NA121-37 to NA124-37.
The first input terminal of the NAND gate NA121-72 is connected to the first output node H111 of the first stage latch 11-35, and the second input terminal is the output terminal of the NAND gate NA122-37 and the first input node of the NAND gate NA124-37. A node I121-37 is configured by these connection points connected to one input terminal.
The first input terminal of the NAND gate NA122-32 is connected to the second node H112 of the first stage latch 11-35, the second input terminal is the output terminal of the NAMD gate NA121-37, and the first input of the NAND gate NA123-37. The node I1122-37 is configured by these connection points connected to the input terminals.
The second input terminal of the NAND gate NA123-37 is connected to the second node H112 of the first stage latch 11-35, and the second input terminal of the NAND gate NA124-37 is the first input of the first stage latch 11-35. It is connected to the node H111.
The second-stage latch 12-37 outputs data Q from the NAND gate NA124-37 and outputs inverted data Qb from the NAND gate NA123-37.
[0325]
For example, if the data input signal D is at a high level and its inverted signal Db is at a low level, the first output node H111 is at a low level, and is quickly higher than the NAND gate NA124-37 of the second stage latch 12-37. Level data Q is output.
Further, the output data Qb of the NAND gate NA123-37 becomes low level through the NAND gate NA121-37.
[0326]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0327]
According to the thirty-eighth embodiment, the second stage latch 12-37 is provided with a circuit for transmitting the output signal change of the first stage latch of the previous stage to the final output signal in a short time. In addition to the effects of the embodiment, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0328]
39th embodiment
FIG. 40 is a circuit diagram showing a 39th embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0329]
The difference between the thirty-ninth embodiment and the thirty-sixth embodiment is the circuit configuration of the second-stage latch 12-33.
[0330]
Specifically, as shown in FIG. 40, the second stage latch 12-38 includes inverters INV121-38 to INV124-38, a PMOS transistor PT123-38, and an NMOS transistor NT121-38.
[0331]
The source of the PMOS transistor PT123-38 is the power supply voltage V_DDThe drain is connected to the drain of the NMOS transistor NT121-38, and a node J121-38 is constituted by this connection point. The source of the NMOS transistor NT121-38 is connected to the ground potential GND.
The input terminal of the inverter INV121-38 is connected to the first output node H111 of the first stage latch 11-35, and the output terminal is connected to the gate of the NMOS transistor NT121-38. Here, a connection point between the output terminal of the inverter INV121-38 and the gate of the NMOS transistor NT121-38 is a node / H111.
Node J121-33 is connected to the input terminals of inverters INV122-38 and INV123-38 and the output terminal of inverter INV124-38.
Further, the output terminal of the inverter INV123-38 and the input terminal of the inverter INV124-38 are connected, and a node J122-38 is configured by the connection point. These inverters INV123-38 and INV124-38 constitute a latch.
The second-stage latch 12-38 outputs data Q from the output terminal of the inverter INV122-38.
[0332]
In this case, for example, if the data input signal D is high level and its inverted signal Db is low level, the first output node H111 is low level, and the output node of the inverter INV121-38 of the second stage latch 12-38. / 111 becomes a high level. At this time, the second output node H112 of the first stage latch 11-35 is at the high level.
As a result, the NMOS transistor NT121-38 is turned on, the PMOS transistor PT123-38 is turned off, the node J121-38 becomes low level, and the high-level data Q is immediately output from the inverter INV122-38.
Note that the data of the node J121-38 is maintained even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-38 and INV124-38.
[0333]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0334]
According to the thirty-ninth embodiment, since the second stage latch 12-38 is provided with the circuit for transmitting the output signal change of the first stage latch to the final output signal in a short time, the sixth and thirty-sixth implementations are provided. In addition to the effect of the mode, a high level can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0335]
40th embodiment
FIG. 41 is a circuit diagram showing a 40th embodiment of the sense amplifier D-type flip-flop according to the present invention.
[0336]
The 40th embodiment differs from the 39th embodiment described above in that the second stage latch 12-39 is different from the output signal change of the first stage latch 11-35 when the opposite signals are held. At the same time, the circuit configuration is such that the reciprocal signal held in the second stage latch is invalidated.
Specifically, the inverter INV124-39 constituting the cross latch is constituted by a clocked inverter (Clocked Inverter) connected to the nodes / H111 and H112.
[0337]
In this case, for example, if the data input signal D is high level and its inverted signal Db is low level, the first output node H111 is low level, and the output node of the inverter INV121-38 of the second stage latch 12-39. / H111 goes high. At this time, the second output node H112 of the first stage latch 11-35 is at the high level.
As a result, the NMOS transistor NT121-38 is turned on, the PMOS transistor PT123-38 is turned off, and the node J121-38 becomes low level.
At this time, the clocked inverter INV124-39 cannot output the high level, and the high level data Q is promptly output from the inverter INV122-38.
Therefore, the high-level data Q is output from the inverter INV122-38 immediately without preventing the node J121-38 from changing to the low level.
Further, the data of the node J121-38 is maintained even when the clock signal CK is switched to the low level by the cross latch of the inverters INV123-38 and INV124-39.
[0338]
When the data input signal D is at a low level and the inverted signal Db is at a high level, an operation opposite to the above-described operation is performed. Detailed description thereof is omitted here.
[0339]
According to the forty-first embodiment, in addition to the effects of the thirty-ninth embodiment, high-level data can be output more quickly than the conventional circuit, so that high-speed operation is possible.
[0340]
【The invention's effect】
As described above, according to the present invention, when the input data signal does not change (when the input signal to the first stage latch and the output signal of the second stage latch match), Since the charge is not charged in the first stage by the clock signal, the power consumption of the clock system can be greatly reduced.
Further, according to the present invention, there is an advantage that high speed operation can be realized and power consumption can be reduced without depending on a circuit design method.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of a sense amplifier type D flip-flop according to the present invention;
FIG. 2 is a timing chart for explaining the operation of the D-type flip-flop of FIG. 1;
FIG. 3 is a circuit diagram showing a second embodiment of a sense amplifier type D flip-flop according to the present invention;
FIG. 4 is a circuit diagram showing a third embodiment of a sense amplifier type D flip-flop according to the present invention;
FIG. 5 is a circuit diagram showing a fourth embodiment of a sense amplifier type D flip-flop according to the present invention;
FIG. 6 is a circuit diagram showing a fifth embodiment of a sense amplifier type D flip-flop according to the present invention;
FIG. 7 is a circuit diagram showing a sixth embodiment of a sense amplifier type D flip-flop according to the present invention;
FIG. 8 is a circuit diagram showing a seventh embodiment of a sense amplifier D-type flip-flop according to the present invention;
FIG. 9 is a circuit diagram showing an eighth embodiment of a sense amplifier type D flip-flop according to the present invention;
FIG. 10 is a circuit diagram showing a ninth embodiment of a sense amplifier D-type flip-flop according to the present invention;
FIG. 11 is a circuit diagram showing a tenth embodiment of a sense amplifier D-type flip-flop according to the present invention;
FIG. 12 is a circuit diagram showing an eleventh embodiment of a sense amplifier type D flip-flop according to the present invention;
FIG. 13 is a circuit diagram showing a twelfth embodiment of a sense amplifier D-type flip-flop according to the present invention;
FIG. 14 is a circuit diagram showing a thirteenth embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 15 is a circuit diagram showing a fourteenth embodiment of a sense amplifier D-type flip-flop according to the present invention;
FIG. 16 is a circuit diagram showing a fifteenth embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 17 is a circuit diagram showing a sixteenth embodiment of a sense amplifier D-type flip-flop according to the present invention;
FIG. 18 is a circuit diagram showing a seventeenth embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 19 is a circuit diagram showing an eighteenth embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 20 is a circuit diagram showing a nineteenth embodiment of the sense amplifier D-type flip-flop according to the present invention.
FIG. 21 is a circuit diagram showing a twentieth embodiment of a sense amplifier D-type flip-flop according to the present invention;
FIG. 22 is a circuit diagram showing a twenty-first embodiment of a sense amplifier D-type flip-flop according to the present invention;
FIG. 23 is a circuit diagram showing a twenty-second embodiment of a sense amplifier D-type flip-flop according to the present invention;
FIG. 24 is a circuit diagram showing a twenty-third embodiment of a sense amplifier D-type flip-flop according to the present invention;
FIG. 25 is a circuit diagram showing a twenty-fourth embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 26 is a circuit diagram showing a twenty-fifth embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 27 is a circuit diagram showing a twenty-sixth embodiment of a sense amplifier D-type flip-flop according to the present invention;
FIG. 28 is a circuit diagram showing a twenty-seventh embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 29 is a circuit diagram showing a twenty-eighth embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 30 is a circuit diagram showing a twenty-ninth embodiment of the sense amplifier D-type flip flop according to the present invention;
FIG. 31 is a circuit diagram showing a 30th embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 32 is a circuit diagram showing a thirty-first embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 33 is a circuit diagram showing a thirty-second embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 34 is a circuit diagram showing a thirty-third embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 35 is a circuit diagram showing a thirty-fourth embodiment of the sense amplifier D-type flip-flop according to the present invention.
FIG. 36 is a circuit diagram showing a 35th embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 37 is a circuit diagram showing a thirty-sixth embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 38 is a circuit diagram showing a thirty-seventh embodiment of the sense amplifier D-type flip-flop according to the present invention.
FIG. 39 is a circuit diagram showing a 38th embodiment of the sense amplifier D-type flip-flop according to the present invention;
FIG. 40 is a circuit diagram showing a 39th embodiment of the sense amplifier D-type flip-flop according to the present invention;
41 is a circuit diagram showing a 40th embodiment of a sense amplifier D-type flip-flop according to the present invention; FIG.
FIG. 42 is a circuit diagram showing a first configuration example of a conventional sense amplifier type D flip-flop.
43 is a timing chart for explaining the operation of the D-type flip-flop of FIG. 42;
FIG. 44 is a circuit diagram showing a second configuration example of a conventional sense amplifier type D flip-flop.
[Explanation of symbols]
10, 10-1 to 10-39... Sense amplifier type D flip-flop, 11, 11-5, 11-10, 11-15, 11-20, 11-25, 11-30, 11-35. Stage latch, 12, 12-1 to 12-39, ... Second stage latch, PT111 to PT123, PT212 to PT213 ... PMOS transistor, NT111 to NT120, NT211 to NT219, ... NMOS transistor, SP211 ... First signal path, SP212: second signal path, NA121, NA122, NA121-2 to NA124-37 ... NAND gate, INV121-1 to INV124-39 ... inverter, 111, 200, 210, 215, 220, 225, 230, 235 ... latch Part, 112... Pre-setting part.

Claims (27)

A first-stage latch that captures data input when a synchronization signal that takes the first and second potential levels is at the second potential level, and a second-stage latch that latches latch data of the first-stage latch A flip-flop including
The first stage latch is
A first output node;
A second output node;
A first intermediate node;
A second intermediate node;
A third intermediate node;
Pre-setting means capable of charging the first output node and the second output node to a second potential level by charging the first output node and the second output node when the synchronization signal is at a first potential level;
Conducting when the second output node is at the first potential level, connecting the first output node to a potential source at the second potential level, and being kept non-conductive when at the second potential level. First switching means to be performed;
Conducting when the first output node is at the first potential level and connecting the second output node to the potential source at the second potential level, and being non-conductive when at the second potential level. A second switching means held;
Connected between the first output node and the first intermediate node, held in a non-conductive state when the second output node is at the first potential level, and when at the second potential level A third switching means for conducting;
The second output node is connected between the second output node and the second intermediate node. When the first output node is at a first potential level, the non-conductive state is maintained. When the first output node is at a second potential level, A fourth switching means for conducting;
The first intermediate node is connected between the first intermediate node and the third intermediate node, and is held in a non-conductive state when the data input signal is at the first potential level and is conductive when the data input signal is at the second potential level. 5 switching means;
The second intermediate node is connected between the second intermediate node and the third intermediate node, and is kept nonconductive when the inverted signal of the data input signal is at the first potential level, and is at the second potential level. Sixth switching means for conducting;
Seventh switching means connected between the third intermediate node and a reference potential, held in a non-conductive state when the synchronization signal is at the first potential level, and conductive when at the second potential level. When,
Connection means including a resistance component and connecting the first intermediate node and the second intermediate node;
The pre-setting means is
An output terminal of a first NAND circuit which is supplied with the data input signal and a signal from the second output terminal of the second latch and performs a logical operation; an inverted signal of the data input signal; and the second latch The first NAND circuit is connected in parallel to the output terminal of the second NAND circuit which is supplied with a signal from the first output terminal and logically operated, and the parallel connection point is driven through the first switching circuit driven by the synchronization signal. The data input signal and the signal from the first output terminal of the second latch are connected to the output terminal of the third NAND circuit that performs a logical operation, and the output terminal of the third NAND circuit is connected to the first NAND terminal. Connected to one output node,
An output terminal of a fourth NAND circuit which is supplied with the data input signal and a signal from the second output terminal of the second latch and logically operates; an inverted signal of the data input signal; and the second latch Is connected in parallel to the output terminal of the fifth NAND circuit which is supplied with a signal from the first output terminal and logically operated, and the parallel connection point is driven via the second switching circuit driven by the synchronization signal. The data input signal and the signal from the first output terminal of the second latch are connected to the output terminal of a sixth NAND circuit that performs a logical operation, and the output terminal of the sixth NAND circuit is connected to the first terminal. A flip-flop connected to two output nodes . The second stage latch holds normal data and inversion data that complementarily take the first potential level and the second potential level in the first node and the second node,
The pre-setting means is
Eighth and ninth switching elements that are conductive when the synchronization signal is at the first potential level and are kept non-conductive when the second potential level;
Tenth and eleventh switching elements that are conductive when the data input signal is at a first potential level and are held non-conductive when the second potential level;
Twelfth and thirteenth switching elements that are conductive when the inverted signal of the data input signal is at the first potential level and are held non-conductive when the second potential level;
Fourteenth and fifteenth switching elements that are conductive when the first node of the second-stage latch is at a first potential level and are kept nonconductive when the second potential level;
Sixteenth and seventeenth switching elements that are conductive when the second node of the second-stage latch is at a first potential level and are kept nonconductive when the second potential level;
An eighteenth switching element that is conductive when the data input signal is at the second potential level and is held nonconductive when the data input signal is at the first potential level;
A nineteenth switching element that conducts when the inverted signal of the data input signal is at a second potential level and is held in a non-conducting state when the signal is at the first potential level;
A twentieth switching element that is conductive when the first node of the second-stage latch is at a second potential level and is held in a non-conductive state when the first node is at the first potential level;
A twenty-first switching element that is conductive when the second node of the second-stage latch is at a second potential level and is held non-conductive when the first potential level;
The eighth switching element is connected to the first output node, and the tenth and sixteenth switching elements are connected in series between the eighth switching element and the potential source at the second potential level. And the twelfth and fourteenth switching elements are connected in parallel to the tenth and sixteenth switching elements between the eighth switching element and the potential source of the second potential level , The eighteenth and twentieth switching elements are connected in series between the first output node and the reference potential,
The ninth switching element is connected to the second output node, and the thirteenth and fifteenth switching elements are connected in series between the ninth switching element and the potential source at the second potential level. The eleventh and seventeenth switching elements are connected in parallel to the thirteenth and fifteenth switching elements between the ninth switching element and the second potential level potential source, The flip-flop according to claim 1, wherein the nineteenth and twenty-first switching elements are connected in series between the second output node and a reference potential. 2. The flip-flop according to claim 1, wherein the second stage latch includes a circuit that outputs a data signal to be latched by the first stage latch in parallel with a latch process. When the output signal level of the first stage latch changes and a signal opposite to the second stage latch is held, the second stage latch simultaneously changes the output signal of the first stage latch. The flip-flop according to claim 3, further comprising a circuit that invalidates the reciprocal signal held in the stage latch and transmits the signal to the final output signal. A first-stage latch that captures data input when the synchronization signal that takes the first and second potential levels is at the second potential level, and a second-stage latch that latches the latch data of the first-stage latch A flip-flop including
The first stage latch is
A first output node;
A second output node;
First and second intermediate nodes formed in order toward the reference potential in a first signal path between the first output node and the reference potential;
A third and a fourth intermediate node formed in order toward the reference potential in a second signal path between the second output node and the reference potential;
Pre-setting means for setting the first output node and the second output node to a second potential level when the synchronization signal is at a first potential level;
Conducting when the second output node is at the first potential level, connecting the first output node to a potential source at the second potential level, and being kept non-conductive when at the second potential level. First switching means to be performed;
Conducting when the first output node is at the first potential level and connecting the second output node to the potential source at the second potential level, and being non-conductive when at the second potential level. A second switching means held;
Third and fourth switching means which are held in a non-conductive state when the synchronization signal is at the first potential level and are conductive when at the second potential level;
Fifth switching means which is held in a non-conductive state when the data input signal is at the first potential level and is conductive when at the second potential level;
Sixth switching means which is held in a non-conductive state when the inverted signal of the data input signal is at a first potential level and is conductive when at a second potential level;
Seventh switching means which is held in a non-conductive state when the first output node is at a first potential level and is conductive when at a second potential level;
An eighth switching means which is held in a non-conductive state when the second output node is at the first potential level and is conductive when at the second potential level;
Have
The third, fifth and seventh switching means are connected in series to the first signal path, and at least the third switching means includes the first output node and the first intermediate node. Or between the first intermediate node and the second intermediate node,
The fourth, sixth, and eighth switching means are connected in series to the second signal path, and at least the fourth switching means includes the second output node and the third intermediate node. Or between the third intermediate node and the fourth intermediate node,
The pre-setting means is
An output terminal of a first NAND circuit which is supplied with the data input signal and a signal from the second output terminal of the second latch and performs a logical operation; an inverted signal of the data input signal; and the second latch The first NAND circuit is connected in parallel to the output terminal of the second NAND circuit which is supplied with a signal from the first output terminal and logically operated, and the parallel connection point is driven through the first switching circuit driven by the synchronization signal. The data input signal and the signal from the first output terminal of the second latch are connected to the output terminal of the third NAND circuit that performs a logical operation, and the output terminal of the third NAND circuit is connected to the first NAND terminal. Connected to one output node,
An output terminal of a fourth NAND circuit which is supplied with the data input signal and a signal from the second output terminal of the second latch and logically operates; an inverted signal of the data input signal; and the second latch Is connected in parallel to the output terminal of the fifth NAND circuit that is logically operated by the signal supplied from the first output terminal, and the parallel connection point is connected via the second switching circuit driven by the synchronization signal. The data input signal and the signal from the first output terminal of the second latch are connected to the output terminal of a sixth NAND circuit that performs a logical operation, and the output terminal of the sixth NAND circuit is connected to the first NAND terminal. A flip-flop connected to two output nodes . The second stage latch holds normal data and inversion data that complementarily take the first potential level and the second potential level in the first node and the second node,
The pre-setting means is
Ninth and tenth switching elements that are conductive when the synchronization signal is at the first potential level and are kept nonconductive when the synchronization signal is at the second potential level;
Eleventh and twelfth switching elements that are conductive when the data input signal is at a first potential level and are kept non-conductive when the data input signal is at the second potential level;
Thirteenth and fourteenth switching elements that are turned on when the inverted signal of the data input signal is at a first potential level and are held in a non-conductive state at the second potential level;
Fifteenth and sixteenth switching elements that are conductive when the first node of the second-stage latch is at a first potential level and are kept nonconductive when the second potential level;
Seventeenth and eighteenth switching elements that are conductive when the second node of the second-stage latch is at a first potential level and are kept nonconductive when the second potential level;
A nineteenth switching element that conducts when the data input signal is at the second potential level and is held in a non-conducting state when the data input signal is at the first potential level;
A twentieth switching element that conducts when the inverted signal of the data input signal is at the second potential level and is held in a non-conducting state when the signal is at the first potential level;
A twenty-first switching element that is conductive when the first node of the second-stage latch is at a second potential level and is held non-conductive when the first potential level;
A 22nd switching element that is conductive when the second node of the second stage latch is at the second potential level and is kept nonconductive when the first potential level;
The ninth switching element is connected to the first output node, and the eleventh and seventeenth switching elements are connected in series between the ninth switching element and the potential source at the second potential level. The thirteenth and fifteenth switching elements are connected in parallel to the eleventh and seventeenth switching elements between the ninth switching element and the potential source of the second potential level , The nineteenth and twenty-first switching elements are connected in series between the first output node and the reference potential,
The tenth switching element is connected to the second output node, and the fourteenth and sixteenth switching elements are connected in series between the tenth switching element and the potential source at the second potential level. The twelfth and eighteenth switching elements are connected in parallel to the fourteenth and sixteenth switching elements between the tenth switching element and the second potential level potential source, and The flip-flop according to claim 5, wherein the twentieth and twenty-second switching elements are connected in series between the second output node and a reference potential. The third switching means is connected between the first output node and the first intermediate node, and the fifth switching means is between the first intermediate node and the second intermediate node. The seventh switching means is connected between the second intermediate node and the reference potential;
The fourth switching means is connected between the second output node and the third intermediate node, and the sixth switching means is between the third intermediate node and the fourth intermediate node. The eighth switching means is connected between the fourth intermediate node and the reference potential;
The first stage latch further includes:
The second output node conducts when the second potential level is at the second potential level, connects the first intermediate node to the reference potential, and is kept non-conductive when the first potential level is at the ninth potential level. Switching means;
When the first output node is at the second potential level, the first intermediate node is connected to the reference potential, and when the first output node is at the first potential level, a tenth state is maintained. The flip-flop according to claim 5, further comprising switching means. 8. The flip-flop according to claim 7, wherein the second stage latch includes a circuit that outputs a data signal to be latched by the first stage latch in parallel with the latch process. When the output signal level of the first stage latch changes and a signal opposite to the second stage latch is held, the second stage latch simultaneously changes the output signal of the first stage latch. The flip-flop according to claim 8, further comprising a circuit that invalidates the reciprocal signal held in the stage latch and transmits the signal to the final output signal. The third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is between the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential;
The fourth switching means is connected between the second output node and the third intermediate node, and the eighth switching means is between the third intermediate node and the fourth intermediate node. The sixth switching means is connected between the fourth intermediate node and the reference potential;
The first stage latch further includes:
The second output node is conductive when it is at the second potential level, connects the second intermediate node to the reference potential, and is held in the non-conductive state when it is at the first potential level. Switching means;
When the first output node is at the second potential level, the fourth intermediate node is connected to the reference potential, and when the first output node is at the first potential level, the tenth state is maintained in the non-conductive state. The flip-flop according to claim 5, further comprising switching means. The flip-flop according to claim 10, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first stage latch changes and a signal opposite to the second stage latch is held, the second stage latch simultaneously changes the output signal of the first stage latch. The flip-flop according to claim 11, further comprising a circuit that invalidates the reciprocal signal held in the stage latch and transmits the signal to the final output signal. The third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is between the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential;
The fourth switching means is connected between the second output node and the third intermediate node, and the eighth switching means is between the third intermediate node and the fourth intermediate node. The sixth switching means is connected between the fourth intermediate node and the reference potential;
The first stage latch further includes:
The second output node conducts when the second potential level is at the second potential level, connects the first intermediate node to the reference potential, and is kept non-conductive when the first potential level is at the ninth potential level. Switching means;
When the first output node is at the second potential level, the first intermediate node is connected to the reference potential, and when the first output node is at the first potential level, a tenth state is maintained. The flip-flop according to claim 5, further comprising switching means. 14. The flip-flop according to claim 13, wherein the second stage latch includes a circuit that outputs a data signal to be latched by the first stage latch in parallel with the latch process. When the output signal level of the first stage latch changes and a signal opposite to the second stage latch is held, the second stage latch simultaneously changes the output signal of the first stage latch. The flip-flop according to claim 14, further comprising a circuit that invalidates a reciprocal signal held in the stage latch and transmits the signal to a final output signal. The third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is between the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential;
The fourth switching means is connected between the second output node and the third intermediate node, and the eighth switching means is between the third intermediate node and the fourth intermediate node. The sixth switching means is connected between the fourth intermediate node and the reference potential;
The first stage latch further includes:
Conducting when the second output node is at the second potential level, connecting the second intermediate node and the fourth intermediate node, and being kept in the non-conducting state when at the first potential level. A ninth switching means;
Conducting when the first output node is at the second potential level, connecting the second intermediate node and the fourth intermediate node, and being kept in the non-conducting state when the first output node is at the first potential level. The flip-flop according to claim 5, further comprising tenth switching means. The flip-flop according to claim 16, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first stage latch changes and a signal opposite to the second stage latch is held, the second stage latch simultaneously changes the output signal of the first stage latch. The flip-flop according to claim 17, further comprising a circuit that invalidates a reciprocal signal held in the stage latch and transmits the signal to a final output signal. The third switching means is connected between the first output node and the first intermediate node, and the seventh switching means is between the first intermediate node and the second intermediate node. The fifth switching means is connected between the second intermediate node and the reference potential;
The fourth switching means is connected between the second output node and the third intermediate node, and the eighth switching means is between the third intermediate node and the fourth intermediate node. The sixth switching means is connected between the fourth intermediate node and the reference potential;
The first stage latch further includes:
The flip-flop according to claim 5, further comprising a connection unit that includes a resistance component and connects the second intermediate node and the fourth intermediate node. The flip-flop according to claim 19, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first stage latch changes and a signal opposite to the second stage latch is held, the second stage latch simultaneously changes the output signal of the first stage latch. 21. The flip-flop according to claim 20, further comprising a circuit that invalidates the reciprocal signal held in the stage latch and transmits the signal to the final output signal. The fifth switching means is connected between the first output node and the first intermediate node, and the third switching means is between the first intermediate node and the second intermediate node. The seventh switching means is connected between the second intermediate node and the reference potential;
The sixth switching means is connected between the second output node and the third intermediate node, and the fourth switching means is between the third intermediate node and the fourth intermediate node. The eighth switching means is connected between the fourth intermediate node and the reference potential;
The first stage latch further includes:
Conducting when the second output node is at the second potential level, connecting the first output node and the first intermediate node, and being kept non-conductive when at the first potential level. A ninth switching means;
Conducting when the first output node is at the second potential level, connecting the second output node and the third intermediate node, and being kept non-conductive when at the first potential level. The flip-flop according to claim 5, further comprising tenth switching means. The flip-flop according to claim 22, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first stage latch changes and a signal opposite to the second stage latch is held, the second stage latch simultaneously changes the output signal of the first stage latch. 24. The flip-flop according to claim 23, further comprising a circuit that invalidates the reciprocal signal held in the stage latch and transmits the signal to the final output signal. The fifth switching means is connected between the first output node and the first intermediate node, and the third switching means is between the first intermediate node and the second intermediate node. The seventh switching means is connected between the second intermediate node and the reference potential;
The sixth switching means is connected between the second output node and the third intermediate node, and the fourth switching means is between the third intermediate node and the fourth intermediate node. The eighth switching means is connected between the fourth intermediate node and the reference potential;
The first stage latch further includes:
The flip-flop according to claim 5, further comprising a connection unit that includes a resistance component and connects the second intermediate node and the fourth intermediate node. 26. The flip-flop according to claim 25, wherein the second-stage latch includes a circuit that outputs a data signal to be latched by the first-stage latch in parallel with a latch process. When the output signal level of the first stage latch changes and a signal opposite to the second stage latch is held, the second stage latch simultaneously changes the output signal of the first stage latch. 27. The flip-flop according to claim 26, further comprising a circuit that invalidates the reciprocal signal held in the stage latch and transmits the signal to the final output signal.

Images