JP2013110441A - Component built-in wiring board manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a component built-in wiring board manufacturing method which can achieve high productivity and low cost even when a plurality of types of components are loaded, buried and mounted together.SOLUTION: A component built-in wiring board manufacturing method comprises: forming on a first insulating plate, a first land for mounting a semiconductor element including a semiconductor chip having terminal pads and terminals for surface mounting which are electrically connected to the terminal pads and arranged in a grid-shape, and a second land for mounting a chip component for surface mounting; applying cream solder on the first and second lands to mount the semiconductor element and the chip component on the first and second lands via the cream solder, respectively; heating the cream solder for reflow soldering to connect the semiconductor element and the chip component to the first and second lands, respectively; and integrating a second insulating plate with the first insulating plate in a laminated fashion so as to bury the semiconductor element and the chip component respectively connected to the first and second lands in the second insulating plate apart from the first insulating plate.

Description

  The present invention relates to a method of manufacturing a component built-in wiring board in which components are embedded and mounted in an insulating plate, and more particularly to a method of manufacturing a component built-in wiring board in which a plurality of types of components are embedded and mounted in a mixed manner.

  An example of a component built-in wiring board in which a plurality of types of components are embedded and mounted in a mixed manner is disclosed in Japanese Patent Application Laid-Open No. 2003-197849. In the wiring board disclosed in this document, in addition to passive components such as a chip capacitor (chip capacitor), a semiconductor chip is a target component to be embedded. By embedding a semiconductor component such as a semiconductor chip, the added value as a component built-in wiring board is remarkably increased as compared with a case where only a passive component is provided.

  When embedding and mounting a semiconductor component in a wiring board, the wiring board itself is not so thick even in recent years even if it is a multi-layer board, and inevitably usually has as little thickness as a bare chip, for example. The form will be used. In the case of using a bare chip, as shown in the above-mentioned document, it is advantageous in terms of saving thickness that a face-down mounting is performed on the inner layer wiring pattern of the wiring board. In general, a technique for mounting a semiconductor chip face down on a wiring pattern is known as flip chip connection, and this technique can be used.

  Flip chip connection includes a technique for aligning fine-pitch connection pads formed on a semiconductor chip with respect to lands formed by a wiring pattern. To ensure positional accuracy, the size of a work having a wiring pattern is reduced. It can't be too big. On the other hand, a technique for mounting a passive component such as a chip capacitor on a wiring pattern is a so-called surface mounting technique that uses solder or a conductive adhesive as a connection member between the component and the wiring pattern. In this case, the positioning accuracy of the parts with respect to the wiring pattern may be coarser than that in the case of flip-chip connection, and therefore, the production equipment corresponding to a relatively large work can be used in consideration of productivity.

  In a wiring board with a built-in component in which multiple types of components such as passive components and semiconductor components are embedded and mounted in a wiring board, surface mounting technology is used for mounting passive components. For this purpose, flip-chip connection technology is used. Therefore, separate steps are necessary, and one problem arises in improving productivity. Also, flip chip connection is disadvantageous in improving productivity because it cannot handle large workpieces.

JP 2003-197849 A

  The present invention has been made in consideration of the above circumstances, and in a method of manufacturing a component built-in wiring board in which components are embedded and mounted in an insulating plate, a plurality of types of components are embedded and mounted in a mixed manner. Even so, an object of the present invention is to provide a method for manufacturing a component built-in wiring board capable of realizing high productivity and low cost.

  In order to solve the above problems, a method of manufacturing a component built-in wiring board according to one aspect of the present invention includes a semiconductor chip having a terminal pad by patterning a metal foil laminated on a first insulating plate, and the terminal A first land, which is a land for mounting a semiconductor element having a grid-like array of surface mounting terminals electrically connected to a pad, and a land for mounting a chip component for surface mounting. Forming a wiring pattern including a second land, applying a cream solder or an uncured conductive composition on the first and second lands on the first insulating plate, and Placing the semiconductor element on the first land of the first insulating plate via cream solder or the conductive composition; and the first via the cream solder or the conductive composition. End of A step of placing the chip component on the second land of the plate, and a state in which the semiconductor element is placed on the first land and the chip component is placed on the second land. Heating the solder solder to reflow or curing the conductive composition to connect the semiconductor element to the first land and the chip component to the second land; The semiconductor element connected to the first land and the chip component connected to the second land are embedded in a second insulating plate which is an insulating plate different from the one insulating plate. Integrating the second insulating plate with the first insulating plate in a laminated manner.

  According to the present invention, in a method of manufacturing a component built-in wiring board in which components are embedded and mounted in an insulating plate, large productivity and low cost can be achieved even when multiple types of components are embedded and mounted in a mixed manner. Can be realized.

Sectional drawing which shows typically the structure of the component built-in wiring board by the manufacturing method which is one Embodiment of this invention. The bottom view and sectional drawing which show the semiconductor element 42 used for the component built-in wiring board shown in FIG. Process drawing which shows the example of a manufacturing process about the semiconductor element 42 used for the component built-in wiring board shown in FIG. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. Process drawing which shows another part of manufacturing process of the component built-in wiring board shown in FIG. FIG. 9 is a process diagram schematically showing still another part of the manufacturing process of the component built-in wiring board shown in FIG. 1.

  As an embodiment of the present invention, the cream solder may be a cream solder in which copper particles are dispersed in a flux in addition to solder particles. According to this, even if the solder for the built-in component remelts due to heat when the component is mounted on the main surface of the wiring board, it is possible to effectively prevent the occurrence of a failure such as a connection failure. .

  Further, as an embodiment, the electrical connection between the surface mounting terminal and the terminal pad in the semiconductor element can be made by a rewiring layer formed on the semiconductor chip. When such a rewiring layer is used, a portion corresponding to the package of the semiconductor element can be made to have a slight thickness and volume, and is suitable by being incorporated in the wiring board.

  As an embodiment, the thickness of the semiconductor element may be thinner than the height of the chip component. According to this, as a manufacturing process, the force in the stacking direction applied to the semiconductor element at the time of stacking is suppressed by the electric / electronic component, so that it is possible to effectively prevent defects such as the breakdown of the semiconductor element at the time of manufacturing. .

  As an embodiment, the surface mounting terminal of the semiconductor element can be an LGA terminal. In surface mounting using LGA, it is possible to mount on a wiring board without using bumps such as solder balls, and the size in the height direction can be suppressed.

  Further, as an embodiment, the surface mounting terminal of the semiconductor element has either a Ni / Au plating layer as a surface layer, a tin plating layer as a surface layer, or Cu as a surface layer. can do. Since the surface mounting terminal has such a Ni / Au plating layer as a surface layer, good soldering and high reliability of the connection can be obtained. Moreover, although it is cheaper according to the tin plating layer, good soldering and high reliability of the connection can be obtained. Further, even Cu can be soldered, and in this case, there is a high possibility that the structure as a semiconductor element becomes simpler, and the manufacturing can be made at a lower cost.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to a manufacturing method according to an embodiment of the present invention. As shown in FIG. 1, this component built-in wiring board includes an insulating layer 11 (first insulating layer), 12, 12, 13, 14, and 15 (12, 13, 14, 15 second insulating layer). ), Wiring layers (wiring patterns) 21, 22, 23 (second wiring patterns), 24, 25, 26 (= 6 layers in total), interlayer connectors 31, 32, 34, 35, through-hole conductor 33, chip component 41 (electric / electronic component), semiconductor element (by wafer level / chip scale package) 42, connection members (solder) 51, 52, and solder resists 61, 62.

  That is, this wiring board has chip components 41 and semiconductor elements 42 which are different components from each other as built-in components. The chip component 41 is a so-called surface mounting chip component, and is, for example, a chip capacitor here. The planar size is, for example, 0.6 mm × 0.3 mm. Terminals 41 a are provided at both ends, and the lower side thereof is opposed to the mounting land formed by the wiring layer 22. The terminal 41 a of the chip component 41 and the mounting land are electrically and mechanically connected by the connecting member 51.

  The semiconductor element 42 is an element based on a wafer level / chip scale package, and includes at least a semiconductor chip and a grid-like array of surface mounting terminals 42a formed on the semiconductor chip. Details of the structural example and the manufacturing process example will be described later (FIGS. 2 and 3). The surface mounting terminal 42a is a terminal provided by rearranging its position while being electrically conducted through a rewiring layer from a terminal pad that the semiconductor chip originally has. By such rearrangement, the arrangement density as a terminal is coarser than that of the terminal pad on the semiconductor chip. Thereby, the semiconductor element 42 can be mounted on the mounting land by the wiring layer 22 via the connection member (solder) 52 by the surface mounting technique similar to that of the chip component 41.

  Describing another structure as a component built-in wiring board, the wiring layers 21 and 26 are wiring layers on both main surfaces as a wiring board, and various components (not shown) can be mounted thereon. Solder resist 61 is provided on both main surfaces except for the land portions of the wiring layers 21 and 26 on which solder (not shown) is to be mounted in mounting, so that the solder melted at the time of solder connection is held on the land portions and thereafter functions as a protective layer. , 62 (thickness is about 20 μm, for example). An Ni / Au plating layer (not shown) with high corrosion resistance may be formed on the surface layer of the land portion.

  The wiring layers 22, 23, 24, and 25 are inner wiring layers, and the insulating layer 11 is insulated between the wiring layer 21 and the wiring layer 22, and the wiring layer 22 and the wiring layer 23 are insulated in this order. The insulating layer 13 is provided between the wiring layer 23 and the wiring layer 24, the insulating layer 14 is provided between the wiring layer 24 and the wiring layer 25, and the insulating layer 15 is provided between the wiring layer 25 and the wiring layer 26. However, the wiring layers 21 to 26 are separated from each other. Each of the wiring layers 21 to 26 is made of, for example, a metal (copper) foil having a thickness of 18 μm.

  Each of the insulating layers 11 to 15 is a rigid material made of, for example, a glass epoxy resin, each having a thickness of 100 μm, for example, only the insulating layer 13 has a thickness of, for example, 300 μm, excluding the insulating layer 13. In particular, the insulating layer 13 has an opening at a position corresponding to the built-in chip component 41 and the semiconductor element 42, and provides a space for embedding the chip component 41 and the semiconductor element 42. The insulating layers 12 and 14 are deformed so as to fill the space inside the through-hole conductor 33 of the insulating layer 13 and the insulating layer 13 for the built-in chip component 41 and the semiconductor element 42, and the inside. There is no space for voids.

  The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted by a through-hole conductor 33 provided through the insulating layer 13. The wiring layer 24 and the wiring layer 25 can be conducted by an interlayer insulator 34 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted by an interlayer connector 25 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15.

  The interlayer connectors 31, 32, 34, and 35 are derived from conductive bumps formed by screen printing of a conductive composition, respectively, and depend on the manufacturing process in the axial direction (shown in FIG. 1). The diameter changes in the upper and lower stacking directions). The diameter is, for example, 200 μm on the thick side.

  The structure of the component built-in wiring board according to this embodiment has been described above. Next, the configuration of the semiconductor element 42 used in this component built-in wiring board will be described in some detail with reference to FIG. FIG. 2 is a bottom view (FIG. 2 (a)) and a cross-sectional view (FIG. 2 (b)) schematically showing the semiconductor element 42 used in the component built-in wiring board shown in FIG. FIG. 2B is a cross-sectional view in the arrow direction at the position A-Aa in FIG. In FIG. 2, the same components as those shown in FIG.

  As shown in FIG. 2A, the semiconductor element 42 has surface mounting terminals 42a arranged in a grid. The arrangement pitch of the terminals 42a is, for example, 0.2 mm to 1.0 mm. In the vicinity of the center of the surface on which the terminal 42a is disposed, when the number of terminals necessary for the semiconductor element 42 is small, the terminal 42a may not be disposed.

  The semiconductor element 42 is in the form of a so-called LGA (land grid array) in which there is no solder ball on the terminal 42a as a form before being mounted because it is built in the wiring board. By adopting such a configuration without solder balls, the mounting size in the height direction is suppressed and the suitability for incorporation is further improved. If the thickness of the built-in wiring board allows, a so-called BGA (ball grid array) in which solder balls are mounted on the terminals 42a can also be used.

  In the cross-sectional direction of the semiconductor element 42, as shown in FIG. 2B, the surface mounting terminal 42a is in contact with the rewiring layer 42b on the insulating layer 42e and through the portion penetrating the insulating layer 42e. It is formed to do. Further, the redistribution layer 42b is in contact with the terminal pad 42c on the semiconductor chip on the insulating layer 42d provided between the insulating layer 42e and the semiconductor chip and through a portion penetrating the insulating layer 42d. Is formed.

  Since the terminal pads 42c are usually arranged in a line along each side of the semiconductor chip, the arrangement pitch is relatively narrow. That is, the rewiring layer 42b is provided in order to mediate conduction between the arrangement pitch and the arrangement pitch of the surface mounting terminals 42a that are arranged in a grid and have a relatively large arrangement pitch. With this configuration, the semiconductor element 42 has a surface area that is the same as that of the semiconductor chip in spite of being capable of being mounted on the surface, and is slightly thicker than the semiconductor chip itself in the thickness direction. It has become. In order to make the semiconductor element 42 thinner, the back surface of the semiconductor chip may be ground by providing a grinding step. For example, the total thickness can be about 0.3 mm or less.

  Next, an example of a manufacturing process of such a semiconductor element 42 will be described with reference to FIG. FIG. 3 is a process diagram schematically showing a manufacturing process example of the semiconductor element 42 used in the component built-in wiring board shown in FIG. In FIG. 3, the same reference numerals are given to the same components as those already shown in the drawings.

  First, as shown in FIG. 3A, a semiconductor wafer 42w having a plurality of semiconductor devices already formed on its surface is prepared. On the surface of the semiconductor wafer 42w, terminal pads 42c are formed as external connection portions of the respective semiconductor devices. The terminal pads 42c usually have an area necessary for wire bonding and are provided along the four sides of each semiconductor device with an arrangement pitch that does not hinder wire bonding. ing. This arrangement pitch is narrower than the arrangement pitch of terminals for general surface mounting.

  Next, as shown in FIG. 3B, an insulating layer 42d is formed on the entire surface of the semiconductor wafer 42w so as to cover the pad 42c. As a forming method, a known method may be used. For example, a polyimide which is an insulating material is dropped on the semiconductor wafer 42w and spin-coated, and the thickness can be formed to about 1 μm, for example.

  Next, as shown in FIG. 3C, the insulating layer 42d on the pad 42c is selectively removed by etching to form an opening 71 leading to the pad 42c in the insulating layer 42d. For selective etching, a known method such as photolithography can be applied. Instead of the method shown in FIGS. 3B and 3C, a method of selectively forming the insulating layer 42d except on the pad 42c may be used. The insulating layer 42d can be selectively formed by a well-known method.

  After the opening 71 is formed, next, as shown in FIG. 3D, a rewiring layer 42b is formed on the insulating layer 42d with a conductive material so as to fill the opening 71 and have a necessary pattern. . For the rewiring layer 42b, for example, Al, Au, Cu, or the like can be used. As a formation method, an appropriate one can be selected in consideration of a material to be used among sputtering, vapor deposition, plating, and the like. For patterning, in consideration of the material to be used, unnecessary portions are etched away after being formed on the entire surface of the insulating layer 42d, or a resist mask having a predetermined pattern is formed on the insulating layer 42d and then re-applied. This can be done by forming a layer to be the wiring layer 42b. The thickness of the rewiring layer 42b can be set to about 1 μm, for example.

  After forming the rewiring layer 42b, next, as shown in FIG. 3E, an insulating layer 42e is formed so as to cover the rewiring layer 42b, and the insulating layer 42e is selectively removed by etching. An opening 72 leading to the rewiring layer 42b is formed in 42e. The step shown in FIG. 3E can be performed in the same manner as in FIG. 3B and FIG. 3C, which are steps for forming and processing the insulating layer 42d. The same applies when a method for selectively forming the insulating layer 42e is selected.

  After the opening 72 is formed, next, as shown in FIG. 3 (f), the surface mounting terminal 42a is made of a conductive material so as to fill the opening 72 and occupy a predetermined arrangement position on the insulating layer 42e. Form. For example, Al, Au, Cu, or the like can be used as the conductive material. As a formation method, an appropriate one can be selected in consideration of a material to be used among sputtering, vapor deposition, plating, and the like. In order to form it selectively, in consideration of the material to be used, an unnecessary portion is etched away after being formed on the entire surface of the insulating layer 42e, or a resist mask having a predetermined pattern is formed on the insulating layer 42d. This can be done by forming a layer to be the surface mounting terminal 42a. The layer of the surface mounting terminal 42a can have a thickness of about 1 μm, for example.

  If the conductive material is Cu or Al, the surface mounting terminal 42a may be further processed so that its surface layer is covered with a Ni / Au plating layer or a Sn (tin) plating layer. For example, an electroless plating process can be used to perform such plating. By having a plating layer of a predetermined material, it is possible to obtain good soldering and connection reliability in surface mounting for incorporation in a wiring board.

  When the surface mounting terminals 42a are formed, finally, as shown in FIG. 3G, the semiconductor wafer 42w is diced to obtain individual semiconductor elements 42. The semiconductor element 42 obtained in this way can be subjected to a surface mounting process in the same manner as the chip component as described above by the surface mounting terminal 42a.

  In FIG. 3, the method of forming the surface mounting terminals 42a using the wafer 42w before dicing has been described. However, this shows an example in which the surface mounting terminals 42a are formed with higher productivity. On the other hand, the surface mounting terminals 42a can be formed in the same manner on the individual semiconductor chips after dicing.

  As a modification of the semiconductor element 42 as shown in FIG. 3, an example in which the rewiring layer 42b and the surface mounting terminal 42a are formed as the same layer can be given. In this case, a layer of a conductive material is formed on the insulating layer 42d so as to have a pattern necessary for rewiring and to have a pattern of the surface mounting terminals 42a in contact with this pattern. This conductive material layer fills the opening 71 formed in the insulating layer 42d. Then, the conductive material layer is formed so as to cover the entire surface with the insulating layer 42e except for the portion of the surface mounting terminal 42a. This also makes it possible to obtain a semiconductor element having the surface mounting terminals 42a in which the terminal pads 42c of the semiconductor device are rearranged.

  As described above, the component built-in wiring board according to this embodiment includes the semiconductor element 42 as one of a plurality of types of components and the chip component 41 as another one embedded at the same time. Here, the semiconductor element 42 has a semiconductor chip and a surface mounting terminal 42a arranged in a grid. Therefore, when the semiconductor element 42 is mounted because it is built in the wiring board, the same surface mounting technology as that of the chip component 41 can be applied at the same time. Therefore, it is possible to use a surface mounting technique for mounting a plurality of types of components at the same time, and it is possible to use a relatively large workpiece in consideration of productivity. Accordingly, the component built-in wiring board achieves high productivity and low cost.

  In addition, since the surface mounting terminals 42a are particularly arranged in a grid, that is, in a plane arrangement, the plane area of the semiconductor element 42 can be minimized. Further, since the electrical connection between the surface mounting terminal 42a and the terminal pad 42c on the semiconductor chip is made by the rewiring layer 42b formed on the semiconductor chip, the thickness of the semiconductor element 42 is also different from that of the semiconductor chip itself. Not so thick compared. That is, in terms of the area and thickness of the semiconductor element 42, the ease of incorporation similar to that of the semiconductor chip is ensured. On the other hand, it does not require a highly accurate alignment process as required for flip chip connection when a semiconductor chip is incorporated. Therefore, this also contributes to improvement of productivity and cost reduction.

  The semiconductor element 42 to be embedded or buried is not a wafer level chip scale package as described above, but another package product (for example, an interpose substrate is provided between the semiconductor chip and the surface mounting terminal 42a). Form). In this case, the area and thickness of the element are inevitably larger than those of the wafer level / chip scale package, but this can be dealt with depending on the specifications of the board side used for component incorporation. Also in this case, the advantage that the surface mounting technology similar to that of the chip component 41 can be simultaneously applied to the semiconductor element 42 is maintained.

  Next, the manufacturing process of the component built-in wiring board shown in FIG. 1 will be described with reference to FIGS. 4 to 6 are process diagrams schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. In these figures, the same or equivalent components as those shown in FIG.

  It demonstrates from FIG. FIG. 4 shows a manufacturing process of a portion centering on the insulating layer 11 in each configuration shown in FIG. First, as shown in FIG. 4A, a paste-like conductive composition to be the interlayer connection body 31 is formed on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm, for example, by screen printing, for example, in a substantially conical shape. It is formed in a bump shape (bottom diameter, for example, 200 μm, height, for example, 160 μm). This conductive composition is obtained by dispersing fine metal particles such as silver, gold and copper or fine carbon particles in a paste-like resin. For convenience of explanation, printing is performed on the lower surface of the metal foil 22A, but it may be printed on the upper surface (the following drawings are also the same). After the interlayer connector 31 is printed, it is dried and cured.

  Next, as shown in FIG. 4B, an FR-4 prepreg 11A having a thickness of, for example, 100 μm is laminated on the metal foil 22A to penetrate the interlayer connector 31 so that the head is exposed. To do. At the time of exposure or thereafter, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connection body 31 has an axis that coincides with the stacking direction, and the diameter changes in the axial direction). Subsequently, as shown in FIG. 4C, a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 11A, and the whole is integrated by pressing and heating. At this time, the metal foil 21A is in electrical continuity with the interlayer connector 31, and the prepreg 11A is completely cured to become the insulating layer 11.

  Next, as shown in FIG. 4D, patterning by, for example, well-known photolithography is performed on the metal foil 22A on one side, and this is processed into a wiring pattern 22 including mounting lands. Then, as shown in FIG. 4E, cream solders 51A and 52A are printed and applied on the mounting lands obtained by processing, for example, by screen printing. The cream solders 51A and 52A can be easily printed in a predetermined pattern by using screen printing. A dispenser can be used instead of screen printing.

  The cream solders 51 </ b> A and 52 </ b> A may use a conductive composition before curing instead of these. When the conductive composition is used, heat resistance after curing is high, and it is possible to effectively prevent poor connection due to heat applied during component mounting as a wiring board after completion.

  Next, the chip component 41 and the semiconductor element 42 are respectively mounted on the mounting lands through the cream solders 51A and 52A, for example, with a mounter, and then heated to reflow the cream solders 51A and 52A (for example, from 220 ° C. to 250 ° C. ° C). As a result, as shown in FIG. 4 (f), the wiring board material 1 in a state where the chip component 41 and the semiconductor element 42 are connected to the mounting land of the wiring layer 22 through the connecting members 51 and 52 is obtained. . A subsequent process using the wiring board material 1 will be described with reference to FIG.

As a composition of the solder grains dispersed in the cream solders 51A and 52A, for example, a lead-free composition (Sn-3Ag-0.5Cu) containing tin as a main component can be used. Moreover, in order to make it hard to remelt, the thing of the structure which disperse | distributed the copper grain in the flux in addition to a solder grain can also be used. In such a configuration, the solder grains melt at, for example, 217 ° C. to 221 ° C. to cover the surfaces of the copper grains. At this time, the tin component of the solder covering the surface of the copper grains forms a compound Cu ₆ Sn ₅ with copper. As a result, the tin component in the portion excluding the copper grains is reduced. The copper grains whose surfaces are covered with a copper-tin compound may be partially connected to each other by the compound Cu ₆ Sn ₅ .

According to the connection members 51 and 52 formed in this way, when this component built-in wiring board is used for component mounting, reliability deterioration due to remelting can be effectively prevented. That is, the compound Cu ₆ Sn ₅ has a high melting point of 600 ° C. or higher, and does not melt during component mounting. Furthermore, the tin of the portion excluding the copper grains is reduced compared to that of the original solder grains, and even if remelted, the volume change is small and the influence on the surroundings is suppressed. Therefore, reliability as a component built-in wiring board is unlikely to decrease.

  The copper particles in the cream solders 51A and 52A may be other metals such as silver, gold, aluminum, and copper-tin alloy. In addition, solder particles having a composition of, for example, Sn-3Ag-0.5Cu can have a particle size of, for example, 10 μm to 20 μm. Further, the particle size of the copper particles whose surfaces are covered with the copper-tin compound in the connection members 51 and 52 can be set to 3 μm to 40 μm, for example. Further, the proportion of the copper grains in the connection members 51 and 52 can be set to 5 wt% to 50 wt%, for example.

  Next, a description will be given with reference to FIG. FIG. 5 shows a manufacturing process of a part centering on the insulating layers 13 and 12 in each configuration shown in FIG. First, as shown in FIG. 5A, for example, an FR-4 insulating layer 13 having a thickness of, for example, 300 μm in which metal foils (electrolytic copper foils) 23A and 24A having a thickness of 18 μm are laminated on both surfaces is prepared. A through-hole 83 for forming a through-hole conductor is formed at a predetermined position, and component openings 81 and 82 are formed in portions corresponding to the chip component 41 and the semiconductor element 42 incorporated therein.

  Next, electroless plating and electrolytic plating are performed to form a through-hole conductor 33 on the inner wall of the through-hole 83 as shown in FIG. At this time, a conductor is also formed on the inner walls of the openings 81 and 82. Further, as shown in FIG. 5C, the metal foils 23A and 24A are patterned in a predetermined manner using well-known photolithography to form the wiring layers 23 and 24. By patterning the wiring layers 23 and 24, the conductor formed on the inner walls of the openings 81 and 82 is also removed.

  Next, as shown in FIG. 5 (d), conductive bumps (bottom diameter: 200 μm, height: 160 μm, for example) that become interlayer connectors 32 are formed at predetermined positions on the wiring layer 23 of the paste-like conductive composition. It is formed by screen printing. Subsequently, as shown in FIG. 5E, the FR-4 prepreg 12A (nominal thickness, for example, 100 μm) to be the insulating layer 12 is laminated on the wiring layer 23 side using a press. In the prepreg 12 </ b> A, openings similar to the insulating layer 13 are provided in advance corresponding to the built-in chip component 41 and the semiconductor element 42.

  In the stacking step of FIG. 5 (e), the head of the interlayer connector 32 is made to penetrate the prepreg 12A. In addition, the broken line of the head part of the interlayer connection body 32 in FIG. 5E indicates that there are both cases where the head part is plastically deformed and crushed at this stage and where it is not plastically deformed. The wiring board material obtained as described above is referred to as a wiring board material 2.

  The process shown in FIG. 5 can be performed as follows. In the stage of FIG. 5A, only the through hole 83 is formed, and the subsequent steps from FIG. 5B to FIG. 5D are performed without forming the openings 81 and 82 for the built-in components. Next, as a step corresponding to FIG. 5E, prepreg 12A (without opening) is laminated. And it is the process of forming simultaneously the opening part for components incorporation in the insulating layer 13 and the prepreg 12A.

  Next, a description will be given with reference to FIG. FIG. 6 is a diagram showing an arrangement relationship in which the wiring board materials 1 and 2 obtained as described above are stacked. Here, the upper wiring board material 3 shown in the figure applies the same process as that of the lower wiring board material 1, and thereafter, the interlayer connector 34 and the prepreg 14A are connected to the interlayer connector in the intermediate wiring board material 2 shown in the figure. 32 and the prepreg 12A.

  However, the wiring board material 3 is configured without a component (chip component 41 and semiconductor element 42) and a portion (mounting land) for connecting the component, and the prepreg 14A has an opening for the chip component 41, An opening for the semiconductor element 42 is not provided. Other than that, the metal foil (electrolytic copper foil) 26A, the insulating layer 15, the interlayer connection body 35, the wiring layer 25, the prepreg 14A, and the interlayer connection body 34 are the metal foil 21A of the wiring board material 1, the insulating layer 11, and the interlayer connection, respectively. The same as the body 31, the wiring layer 22, the prepreg 12 </ b> A of the wiring board material 2, and the interlayer connection body 32.

  The respective wiring board materials 1, 2, and 3 are laminated and arranged in the arrangement as shown in FIG. Thereby, the prepregs 12A and 14A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12A and 14A obtained by heating, the prepregs 12A and 14A are deformed into the space around the chip component 41 and the semiconductor element 42 and the space inside the through-hole conductor 33, and no gap is generated. . The wiring layers 22 and 24 are electrically connected to the interlayer connectors 32 and 34, respectively.

  In this pressing process, in order to relieve the pressing force applied to the semiconductor element 42 and suppress the occurrence of defects such as breakage, the height of the semiconductor element 42 is slightly lower than the height of the chip component 41. It is preferable. This is because in many applications, the number of the semiconductor elements 42 is small (for example, one), and the chip components 41 are often arranged so as to surround them. The chip component 41 disposed in such a manner bears more pressing force and the pressing force applied to the semiconductor element 42 becomes smaller.

  After the laminating process shown in FIG. 6, the metal foils 26A and 21A on the upper and lower surfaces are patterned in a predetermined manner using well-known photolithography, and further, layers of solder resists 61 and 62 are formed, as shown in FIG. Such a component built-in wiring board can be obtained.

  As a modification, the through-hole conductor 33 provided in the intermediate insulating layer 13 can naturally have a configuration similar to the interlayer connector 31 or 32. Further, for the interlayer connectors 31, 32, 34, and 35, in addition to those derived from the conductive bumps printed by the conductive composition described above, for example, metal bumps formed by metal plate etching, conductive composition filling It is also possible to appropriately select and employ a connection body obtained from the above, a conductor bump formed by plating, or the like. In addition, the outer wiring layers 21 and 26 are formed at the stage of each wiring board material 1 and 3 (for example, at the stage of FIG. 4D) other than patterning after the final lamination process. May be.

  In the laminating process shown in FIG. 6, for the wiring board materials 1 and 2, the prepreg 12 </ b> A and the interlayer connector 32 are provided not on the wiring board material 2 side but on the wiring board material 1 side. May be. That is, the formation of the interlayer connector 32 and the lamination of the prepreg 12A are performed in advance on the wiring layer 22 (on the insulating layer 11) of the wiring board material 1. In this case, the mounted chip component 41 and the semiconductor element 42 seem to be an interference factor when the interlayer connection body 32 is formed by screen printing at first glance, but the chip component 41 and the semiconductor element 42 are sufficiently thin components. The case is not actually an interference factor. In the step of laminating the prepreg 12A, the prepreg 12A can be uniformly laminated in the in-plane direction by pressing and heating with a cushioning material that can absorb the thickness of the chip component 41 and the semiconductor element 42 interposed therebetween.

  DESCRIPTION OF SYMBOLS 1 ... Wiring board material, 2 ... Wiring board material, 3 ... Wiring board material, 11 ... Insulating layer, 11A ... Prepreg, 12 ... Insulating layer, 12A ... Prepreg, 13 ... Insulating layer, 13A ... Prepreg, 14 ... Insulating layer, 14A ... Prepreg, 15 ... Insulating layer, 21 ... Wiring layer (wiring pattern), 21A ... Metal foil (copper foil), 22 ... Wiring layer (wiring pattern), 22A ... Metal foil (copper foil), 23 ... Wiring layer ( Wiring pattern), 23A ... Metal foil (copper foil), 24 ... Wiring layer (wiring pattern), 24A ... Metal foil (copper foil), 25 ... Wiring layer (wiring pattern), 26 ... Wiring layer (wiring pattern), 26A ... Metal foil (copper foil), 31, 32, 34, 35 ... Interlayer connection body (conductive bump by conductive composition printing), 33 ... Through-hole conductor, 41 ... Chip component (electric / electronic component), 41a ... Terminal, 42 ... Semiconductor element ( 42a ... terminal for surface mounting, 42b ... redistribution layer, 42c ... terminal pad, 42d, 42e ... insulating layer, 42w ... semiconductor wafer, 51,52 ... connecting member (solder or conductive composition) ), 51A, 51B ... Cream solder or pre-curing conductive composition, 61, 62 ... solder resist, 71, 72 ... opening, 81, 82 ... opening for parts, 83 ... through hole.

Claims (6)

A metal element laminated on a first insulating plate is patterned to mount a semiconductor element including a semiconductor chip having terminal pads and a grid-like array of surface mounting terminals electrically connected to the terminal pads. Forming a wiring pattern including a first land that is a land for mounting and a second land that is a land for mounting a chip component for surface mounting;
Applying cream solder or an uncured conductive composition on the first and second lands on the first insulating plate;
Placing the semiconductor element on the first land of the first insulating plate via the cream solder or the conductive composition;
Placing the chip component on the second land of the first insulating plate via the cream solder or the conductive composition;
In a state where the semiconductor element is placed on the first land and the chip component is placed on the second land, heating is performed to reflow the cream solder or to cure the conductive composition. Connecting the semiconductor element to the first land and the chip component to the second land;
The semiconductor element connected to the first land and the chip component connected to the second land are embedded in a second insulating plate which is an insulating plate different from the first insulating plate. And a step of integrating the second insulating plate in a laminated form with the first insulating plate.   The method of manufacturing a component built-in wiring board according to claim 1, wherein the cream solder is cream solder in which copper particles are dispersed in a flux in addition to solder particles.   The method of manufacturing a component built-in wiring board according to claim 1, wherein electrical connection between the surface mounting terminal and the terminal pad in the semiconductor element is made by a rewiring layer formed on the semiconductor chip.   The method of manufacturing a component built-in wiring board according to claim 1, wherein a thickness of the semiconductor element is thinner than a height of the chip component.   The method of manufacturing a component built-in wiring board according to claim 1, wherein the surface mounting terminal of the semiconductor element is an LGA terminal.   The component built-in wiring according to claim 1, wherein the surface mounting terminal of the semiconductor element has a Ni / Au plating layer as a surface layer, a tin plating layer as a surface layer, or Cu as a surface layer. A manufacturing method of a board.

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