JP2013098369A - Method of manufacturing semiconductor device, semiconductor device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a through electrode inside a through hole by metal plating even if the through hole included in a semiconductor device is miniaturized.SOLUTION: A method of manufacturing a semiconductor device 100 includes: a seed layer formation step of forming a seed layer 30 on a first surface 10a side of a substrate 10; a wiring layer formation step of forming a wiring layer 40 on the seed layer 30 after the seed layer formation step; a through hole formation step of forming a through hole 10c reaching the seed layer 30 from a second surface 10b of the substrate 10 after the wiring layer formation step; a through electrode formation step of forming a through electrode 60 inside the through hole 10c by metal plating after the through hole formation step; and a dividing step of dividing the seed layer 30 into a plurality of parts after the through electrode formation step.

Description

  The present invention relates to a semiconductor device manufacturing method, a semiconductor device, and an electronic apparatus.

2. Description of the Related Art In recent years, in a sensor package that has been reduced in size and increased in accuracy, a form in which TSV (Through Silicon Vias) is applied when wiring is desired is desired. In TSV, connection wiring is required to be miniaturized, and through holes tend to be miniaturized accordingly.
By the way, when a penetration electrode is formed in a penetration hole formed in a semiconductor substrate using an electrolytic plating method, a diffusion prevention layer (for example, a film containing titanium tungsten (TiW) or titanium (Ti)) is formed inside the penetration hole. It is already known to form a seed layer (for example, see Patent Document 1). It is also known that the seed layer is formed by sputtering copper (Cu), gold (Au), or the like, for example.

  Hereinafter, the manufacturing method of the through electrode described in Patent Document 1 will be briefly described with reference to FIG. In the manufacturing method, as shown in FIG. 5A, first, the first insulating film 20 is formed on one surface 10 a of the semiconductor substrate 10. Then, a patterned wiring layer 40 is formed on the first insulating film 20. Thereafter, a through hole 10c reaching the wiring layer 40 from the other surface 10b side of the semiconductor substrate 10 is formed. Next, as shown in FIG. 5B, the second insulating film is formed on the wall surface of the semiconductor substrate 10 and the first insulating film 20 exposed through the through-hole 10 c and on the other surface 10 b of the semiconductor substrate 10. 50 is formed. Then, the seed layer 30 is formed so as to cover the second insulating film 50 and the wiring layer 40. Finally, as shown in FIG. 5C, electrolytic plating is performed to form the through electrode 60 in the through hole 10c. The through electrode 60 is formed by filling the inside of the through hole 10 c with the second insulating film 50 and the seed layer 30 interposed therebetween. The reason why the plating can be filled is that the plating grows from the surface of the seed layer 30 when the electrolytic plating is performed.

JP 2008-218689 A

By the way, with the recent miniaturization of semiconductor devices, the terminal pitch is narrowed, and the through-hole 10c tends to be miniaturized accordingly. When the above-described method for manufacturing a through electrode is used for the miniaturized through hole 10c, the following method is used.
First, as shown in FIG. 6A, a second insulating film 50 is formed inside the miniaturized through hole 10c. Thereafter, when the seed layer 50 is formed, for example, by using a sputtering method, the seed layer 50 is formed on the other surface 10b of the semiconductor substrate 10 and in the vicinity of the opening of the through hole 10c as shown in FIG. It is formed.

  However, it may be difficult to form the seed layer 50 near the wiring layer 40 (so-called via bottom). For this reason, when an electrode is formed using the electrolytic plating method, the electrode may not be formed in the vicinity of the via bottom. Therefore, when the through hole 10c is miniaturized, there is a problem that it is difficult to form the through electrode 60 inside the through hole 10c using an electrolytic plating method.

  Therefore, the present invention has been made in view of such circumstances, and even when the through hole is miniaturized, a semiconductor device in which a through electrode can be formed inside the through hole by plating. It is an object to provide a manufacturing method, a semiconductor device manufactured by the manufacturing method, and an electronic apparatus using the semiconductor device.

  One embodiment of the present invention for solving the above problems is a seed layer forming step of forming a seed layer on one surface side of a semiconductor substrate, and a wiring layer is formed on the seed layer after the seed layer forming step. A wiring layer forming step; a through hole forming step for forming a through hole reaching the seed layer from the other surface of the semiconductor substrate after the wiring layer forming step; and a plating in the through hole after the through hole forming step. And a through electrode forming step for forming a through electrode, and a dividing step for dividing the seed layer into a plurality of pieces after the through electrode forming step.

  The manufacturing method of the above aspect includes a step of forming a wiring layer on the seed layer and a step of forming a through hole reaching the seed layer from the other surface of the semiconductor substrate. That is, since the seed layer is formed in advance on one surface side of the semiconductor substrate and then the through hole is formed, when the through electrode is formed by plating in the through hole, the seed layer at the bottom of the via Is exposed. For this reason, even when the through hole is miniaturized, plating can be grown from the seed layer at the bottom of the via, so that the inside of the through hole can be filled with plating. Therefore, the through electrode can be formed inside the through hole, and as a result, the through electrode and the wiring layer can be electrically connected.

In another aspect of the present invention, the dividing step may be performed by dicing a seed layer that is conductive on the dicing line along the dicing line.
The manufacturing method of the said aspect includes the process of dicing the seed layer electrically connected on a dicing line along a dicing line. For this reason, since the seed layer can be electrically insulated without using a method such as etching, for example, the manufacture of the semiconductor device can be facilitated.

According to another aspect of the present invention, there is provided a semiconductor substrate, a seed layer formed on one surface side of the semiconductor substrate, a wiring layer formed on the seed layer, and the other surface of the semiconductor substrate. A semiconductor device comprising: a through electrode penetrating through the semiconductor substrate and connected to the seed layer.
The semiconductor device of the above aspect includes a wiring layer formed on the seed layer and a through electrode that penetrates the semiconductor substrate and the first insulating film from the other surface of the semiconductor substrate and connects to the seed layer. For this reason, even if the through hole is miniaturized, the through electrode and the wiring layer can be electrically connected. Therefore, even when the semiconductor device is downsized (that is, when the terminal pitch is reduced), the semiconductor device can be operated.

Another embodiment of the present invention is an electronic device including the semiconductor device of the above embodiment.
The electronic device according to the above aspect includes the semiconductor device according to the above aspect. Therefore, the semiconductor device can be operated even when the electronic device is downsized. Therefore, the electronic device can be operated.

Sectional drawing which shows the semiconductor device which concerns on embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. The top view seen from the active surface side after a wiring layer formation process. The figure which shows the division | segmentation of the seed layer by dicing. Sectional drawing which shows the manufacturing method of the conventional semiconductor device (the 1). Sectional drawing which shows the manufacturing method of the conventional semiconductor device (the 2).

Hereinafter, a semiconductor device according to an embodiment of the present invention, a manufacturing method thereof, and an electronic apparatus including the semiconductor device will be described in this order with reference to the drawings.
(1) Configuration of Semiconductor Device First, the configuration of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 according to the present embodiment includes a semiconductor substrate 10 (hereinafter also simply referred to as “substrate 10”). For example, a silicon (Si) substrate or the like is used as the substrate 10. The substrate 10 has one surface 10a (hereinafter also simply referred to as “front surface 10a”) and the other surface 10b on the opposite side of the one surface 10a (hereinafter also simply referred to as “back surface 10b”). have.

A first insulating film 20 is formed on the surface 10 a of the substrate 10. For example, a silicon oxide film (SiO ₂ film) or the like is used as the first insulating film 20.
In the substrate 10 and the first insulating film 20, a through hole 10 c that penetrates the substrate 10 and the first insulating film 20 is formed. Here, the inner diameter of the through hole 10 c formed in the substrate 10 is larger than the inner diameter of the through hole 10 c formed in the first insulating film 20.

On the first insulating film 20, an electroplating seed layer 30 (hereinafter also simply referred to as "seed layer 30") is formed at a position corresponding to the through hole 10c. As a material of the seed layer 30, for example, Cu or Au is used. As shown in FIG. 1, when a plurality of through holes 10c are formed, the seed layer 30 is electrically divided.
A wiring layer 40 is formed on the seed layer 30. The material of the wiring layer 40 may be a conductive material, such as aluminum (Al). The wiring layer 40 functions as a pad electrode when mounted. Similarly to the seed layer 30, when the plurality of through holes 10 c are formed, the wiring layers 40 are electrically divided.

A second insulating film 50 is formed on the wall surface of the substrate 10 and the first insulating film 20 in which the through hole 10 c is formed and on the back surface 10 b of the substrate 10. As the second insulating film 50, for example, a SiO ₂ film or the like is used.
A through electrode 60 is formed in the through hole 10 c via the second insulating film 50. The through electrode 60 is also continuously formed on a part of the second insulating film 50 formed on the back surface 10 b of the substrate 10. As a material of the through electrode 60, for example, Cu or the like is used.
The through electrode 60 is electrically connected to the wiring layer 40 through the seed layer 30.

Further, as shown in FIG. 1, when a plurality of through electrodes 60 are formed, each through electrode 60 is electrically divided.
Further, a diffusion prevention layer (that is, a barrier layer) may be formed between the through electrode 60 and the second insulating film 50 for the purpose of preventing the material of the through electrode 60 from diffusing into the substrate 10. By forming this diffusion prevention layer, it is possible to prevent leakage of current and the like caused by the diffusion of the material of the through electrode 60 into the substrate 10. As the diffusion preventing layer, for example, a film containing TiW, Ti or the like is used.

  As described above, in the case of the above aspect, the wiring layer 40 formed on the seed layer 30 and the penetration that penetrates the substrate 10 and the first insulating film 20 from the back surface 10 b side of the substrate 10 and connects to the seed layer 30. Electrode 60. For this reason, even when the terminal pitch is narrow, conduction can be established between the through electrode 60 and the wiring layer 40. Therefore, even when the semiconductor device 100 is downsized, the semiconductor device can be operated.

(2) Manufacturing Method of Semiconductor Device Next, a manufacturing method of the semiconductor device 100 will be described with reference to FIG. 2A to 2H are schematic cross-sectional views showing each manufacturing process included in the method for manufacturing the semiconductor device 100. FIG.
Hereinafter, each manufacturing process will be described. FIG. 2A is a cross-sectional view showing a first insulating film forming step, a seed layer forming step, and a wiring layer forming step. FIG. 3 is a plan view seen from the active surface side after the wiring layer forming step.

(2.1) First Insulating Film Forming Step First, a first insulating film forming step for forming the first insulating film 20 on the surface 10a of the substrate 10 is performed. The first insulating film 20 is formed by using a normal semiconductor process such as oxidizing the surface 10a of the substrate 10, for example. In the present embodiment, for example, a SiO ₂ film is formed on the surface 10 a of the substrate 10 using a normal semiconductor process, and this is used as the first insulating film 20.

(2.2) Seed Layer Formation Step Next, a seed layer formation step for forming the seed layer 30 on the first insulating film 20 is performed. In the present embodiment, a Cu layer or an Au layer is formed on the first insulating film 20 by, for example, sputtering of Cu or Au or chemical vapor deposition (CVD), and this is used as the seed layer 30. Note that the seed layer 30 is electrically separated after formation of a through electrode 60 described later. For this reason, as shown in FIG. 3, it is desirable to form the seed layer 30 on the first insulating film 20 in advance so as to be easily divided. However, if the seed layer 30 can be divided in a later step, the seed layer 30 may be formed on the entire surface of the first insulating film 20 (so-called solid surface formation). In addition, the part shown with the broken line in FIG. 3 has shown the position 60a (namely, position where the through-hole 10c is formed) in which the penetration electrode 60 is formed.

(2.3) Wiring Layer Forming Step Next, a wiring layer forming step for forming the wiring layer 40 on the seed layer 30 is performed. In the present embodiment, the wiring layer 40 is formed using, for example, Al. When forming the wiring layer 40, a normal semiconductor process can be used. Note that the wiring layer 40 is electrically connected to the through electrode 60 formed in the through electrode forming process described later via the seed layer 30.

(2.4) Through-hole formation process Next, the through-hole formation process which forms the through-hole 10c in the board | substrate 10 and the 1st insulating film 20 is implemented. In the through-hole forming step, as shown in FIG. 2B, a dry etching mask 200 (hereinafter also simply referred to as “mask 200”) is formed of a photoresist on the back surface 10b side of the substrate 10. The mask 200 is provided with an opening 200a corresponding to the planar cross-sectional shape of the through hole 10c. Then, by dry etching the substrate 10 and the first insulating film 20 from the opening 200a (that is, from the back surface 10b side), the through hole 10c that penetrates the substrate 10 and the first insulating film 20 and reaches the seed layer 30 is formed. It forms (refer FIG.2 (c)).
In the present embodiment, the opening diameter of the substrate 10 (that is, the inner diameter of the through hole 10c) is about 10 μm to 30 μm.

As a gas used for this dry etching, when the substrate 10 is a Si substrate and the first insulating film 20 is a SiO ₂ film, for example, a mixed gas of SF ₆ and O ₂ (SF ₆ + O _2). ), A mixed gas of C ₄ F ₈ and O ₂ (C ₄ F ₈ + O ₂ ), or the like can be used.
Further, when the substrate 10 and the first insulating film 20 are dry-etched with one kind of gas, due to the difference in etching rate between the substrate 10 and the first insulating film 20, The inner diameter is larger than the inner diameter of the through hole 10c formed in the first insulating film 20 (see FIG. 2C).

(2.5) Second Insulating Film Forming Step Next, a second insulating film forming step for forming a second insulating film inside the through hole 10c is performed. In the second insulating film forming step, as shown in FIG. 2D, the second insulating film is formed on the wall surface of the substrate 10 and the wall surface of the first insulating film 20 exposed by the formation of the through hole 10c and the back surface 10b of the substrate 10. A film 50 is formed. That is, the second insulating film 50 is not formed on the seed layer 30, and the second insulating film 50 is exposed inside the through hole 10c. In the present embodiment, a SiO ₂ film is formed by, for example, a CVD method, and the SiO ₂ film is used as the second insulating film 50. As shown in FIG. 2C, the mask 200 formed in the through hole forming step is removed before the second insulating film forming step is performed.
The seed layer 30 exposed in the through hole forming step may be covered again with the second insulating film 50 by performing the second insulating film forming step. In this case, the seed layer 30 is used in the through hole forming step. By performing dry etching again, the surface of the seed layer 30 covered with the second insulating film 50 can be exposed.

(2.6) Through Electrode Forming Step Next, a through electrode forming step for forming the through electrode 60 through the second insulating film 50 in the through hole 10c is performed. In the through electrode forming step, as shown in FIG. 2E, an electroplating mask 300 (hereinafter also simply referred to as “mask 300”) is formed on the second insulating film 50 formed on the back surface 10b side of the substrate 10. Is formed of a photoresist. At this time, the mask 300 is formed so as not to block the opening of the through hole 10 c with the mask 300. The mask 300 is provided with an opening 300a having a diameter larger than the inner diameter of the through hole 10c.

Next, the through electrode 60 is formed inside the through hole 10c by electrolytic plating. When the seed layer 30 is formed of, for example, a Cu layer, Cu plating grows from the exposed surface of the Cu layer when electrolytic plating is performed. As a result, the inside of the through hole 10 c is filled with Cu plating, and this filled Cu plating becomes the through electrode 60.
Note that the plating time is that until the plating fills the inside of the through hole 10c and further grows on the back surface 10b side by about 10 μm to 20 μm. Thereafter, the electrolytic plating mask 300 is removed, and the through electrode 60 including the back surface terminal 60b is formed (see FIG. 2F).

(2.7) Dividing Step Next, a dividing step of electrically dividing the seed layer 30 is performed. In the dividing step, as shown in FIG. 2G, a wet etching mask 400 (hereinafter also simply referred to as “mask 400”) is formed of a photoresist so as to cover the seed layer 30 and the wiring layer 40. Next, the seed layer 30 is wet-etched with, for example, an ammonium persulfate aqueous solution or a sodium persulfate aqueous solution. Thereby, the seed layer 30 other than the portion covered with the mask 400 is etched. Thus, the seed layer 30 is electrically separated.
Finally, the mask 400 is removed, and the semiconductor device 100 in which the through electrode 60 is formed inside the through hole 10c is completed as shown in FIG.

  As described above, in the above aspect, the through hole 10 c is formed so as to reach the seed layer 30 from the back surface 10 b side of the substrate 10. For this reason, even when the through hole 10c is miniaturized, the seed layer 30 can be exposed at the via bottom. As a result, when electrolytic plating is performed, the plating can be grown from the surface of the seed layer 30 at the bottom of the via, and the inside of the through hole 10c can be filled. As a result, the through electrode 60 can be formed inside the through hole 10c. Therefore, the shape of the conductive electrode corresponding to a fine pitch and a fine diameter is possible, and the semiconductor device can be made high definition and small.

In addition, as other functions and effects, it is possible to cope with a high aspect ratio, so that the risk of thinning can be avoided.
In the present embodiment, as a method for dividing the seed layer 50, the method for dividing by the wet etching has been described. However, the method is not limited to this. Instead of wet etching, the seed layer 50 may be selectively divided using, for example, a laser, or may be divided when dicing into pieces using dicing or the like.

Therefore, the division of the seed layer 50 by dicing will be described below. FIG. 4 is a diagram illustrating a process of dividing the seed layer 50 by dicing. 4A and 4B show the seed layer 50 before dicing and the seed layer 50 after dicing, respectively.
As shown in FIG. 4A, the seed layer 50 is electrically connected on the dicing line 500 before dicing. Then, by dicing along the dicing line 500, as shown in FIG. 4B, the seed layer 30 is electrically divided.
If it is the said aspect, since the seed layer 50 currently connected on the dicing line 500 is diced along the dicing line 500, the seed layer 50 can be electrically insulated without using methods, such as wet etching, for example. it can. Therefore, the manufacture of the semiconductor device 100 can be facilitated.

In the present embodiment, the formation of the SiO ₂ film as the second insulating film has been described. However, the present invention is not limited to this. The second insulating film may be any material as long as the insulating property can be ensured, and may be an inorganic material or an organic material.
Moreover, although this embodiment demonstrated performing the penetration electrode formation process after the 2nd insulating film formation process, it is not limited to this. For example, after the second insulating film forming step, a diffusion preventing layer forming step for forming a diffusion preventing layer that prevents the material of the through electrode 60 from diffusing into the substrate 10 may be performed. By forming this diffusion prevention layer, it is possible to prevent leakage of current and the like caused by the diffusion of the material of the through electrode 60 into the substrate 10. As the diffusion preventing layer, for example, a film containing TiW, Ti or the like is used.

(3) Electronic Device The electronic device according to the present embodiment includes the semiconductor device 100 of the above aspect. For this reason, the semiconductor device 100 can be operated even when the electronic apparatus is downsized. Therefore, the electronic device can be operated.
In addition, the manufacturing method of the said aspect, the semiconductor device of the said aspect, and the electronic device of the said aspect are applicable to various sensors, such as CMOS and CCD, and its manufacturing method, for example.

  DESCRIPTION OF SYMBOLS 10 Semiconductor substrate, 10a surface, 10b back surface, 10c through-hole, 20 1st insulating film, 30 seed layer, 40 wiring layer, 50 2nd insulating film, 60 through electrode, position where 60a through electrode is formed, 60b back surface terminal , 100 semiconductor device, 200 mask, 200a opening, 300 mask, 300a opening, 400 mask, 500 dicing line

Claims (4)

A seed layer forming step of forming a seed layer on one surface side of the semiconductor substrate;
A wiring layer forming step of forming a wiring layer on the seed layer after the seed layer forming step;
A through hole forming step for forming a through hole reaching the seed layer from the other surface of the semiconductor substrate after the wiring layer forming step;
After the through hole forming step, a through electrode forming step of forming a through electrode by plating in the through hole;
A method for manufacturing a semiconductor device, comprising: a step of dividing the seed layer into a plurality of portions after the through electrode forming step.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the dividing step, the seed layer that is conductive on the dicing line is diced along the dicing line. 3. A semiconductor substrate;
A seed layer formed on one side of the semiconductor substrate;
A wiring layer formed on the seed layer;
A semiconductor device comprising: a through electrode that penetrates the semiconductor substrate from the other surface of the semiconductor substrate and connects to the seed layer.   An electronic apparatus comprising the semiconductor device according to claim 3.

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