JP2013098274A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that allows preventing the tendency of cracking of a semiconductor element and improving the formation yield of the element even if VIA holes are formed in high density.SOLUTION: A semiconductor device includes: a substrate 110; a gate electrode 124, a source electrode 120, and a drain electrode 122 that are disposed on a first surface of the substrate and each have a plurality of fingers; VIA holes SC that are disposed at under portions of each source electrode 120; and a ground electrode that is disposed on a second surface of the substrate opposite to the first surface and is connected to the source electrode through the VIA holes. The VIA holes SC are disposed along a different direction from a cleavage direction of a compound semiconductor crystal forming the substrate 110.

Description

  Embodiments described herein relate generally to a semiconductor device.

  For example, a field effect transistor (FET) using a compound semiconductor has excellent high-frequency characteristics and operates in a microwave / millimeter wave / submillimeter wave band (for example, a power amplification device or a switching device). ) Is widely put into practical use. In such a power amplifying device or switching device, a contact hole called a VIA hole (via hole (through hole)) is formed under the source electrode.

JP-A-9-186501 JP 2000-294568 A

  However, since the VIA holes formed in such a semiconductor device have a narrow hole interval, the VIA holes are formed side by side with high density. At this time, if the direction in which the VIA holes are aligned and the cleaved facets direction of the compound semiconductor (GaAs, SiC, etc.) crystal coincide with each other, the device is easily broken, and as a result, the device formation yield is lowered. There was a problem.

  The problem to be solved by the present embodiment is to provide a semiconductor device capable of preventing the semiconductor element from being easily broken even if the VIA holes are formed at a high density and improving the formation yield of the element. is there.

  The semiconductor device according to the present embodiment includes a substrate, a gate electrode, a source electrode and a drain electrode, a VIA hole, and a ground electrode. The gate electrode, the source electrode, and the drain electrode are disposed on the first surface of the substrate and each have a plurality of fingers. The VIA hole is disposed below the source electrode. The ground electrode is disposed on the second surface opposite to the first surface of the substrate, and is connected to the source electrode through the VIA hole. Here, the VIA holes are arranged along a direction different from the cleavage direction of the compound semiconductor crystal forming the substrate.

(A) An enlarged view of a schematic planar pattern configuration of the semiconductor device according to the embodiment, (b) an enlarged view of a portion J in FIG. 1 (a), and (c) formed in the semiconductor device shown in FIG. 1 (a). The figure which illustrates the formation pattern of VIA hole. 1 is a configuration example 1 of a semiconductor device according to an embodiment, in which (a) a schematic cross-sectional structure diagram taken along line II in FIG. 1B and (b) a line II-II in FIG. FIG. FIG. 3 is a configuration example 2 of the semiconductor device according to the embodiment, in which (a) is a schematic cross-sectional structure diagram taken along the line II in FIG. 1B, and FIG. 1B is a line II-II in FIG. FIG. FIG. 4 is a configuration example 3 of the semiconductor device according to the embodiment, in which (a) is a schematic cross-sectional structure diagram taken along line II in FIG. 1B, and FIG. 1B is taken along line II-II in FIG. FIG. FIG. 4 is a configuration example 4 of the semiconductor device according to the embodiment, in which (a) is a schematic cross-sectional structure diagram taken along line II in FIG. 1B, and FIG. 1B is taken along line II-II in FIG. FIG. FIG. 6 is a configuration example 5 of the semiconductor device according to the embodiment, in which (a) is a schematic cross-sectional structure diagram taken along line II in FIG. 1B, and FIG. 1B is taken along line II-II in FIG. FIG. FIG. 8A is an enlarged view of a schematic planar pattern configuration of a semiconductor device according to a comparative example, and FIG. 7B is a diagram illustrating a VIA hole formation pattern formed in the semiconductor device shown in FIG. The schematic diagram which shows the example of the cleavage surface direction of the compound semiconductor crystal (GaN, SiC) used with the semiconductor device which concerns on embodiment, and the semiconductor device which concerns on a comparative example. FIG. 6 is a schematic view illustrating the upper surface of a semiconductor substrate wafer (GaN, SiC) used in the semiconductor device according to the embodiment and the semiconductor device according to the comparative example. (A) It is a schematic diagram which illustrates the surface orientation of the semiconductor substrate (GaAs, Si) used with the semiconductor device which concerns on embodiment, and the semiconductor device which concerns on a comparative example, Comprising: (a) The example of (100) surface, b) Example of (001) plane. (A) The enlarged view of the modification 1 of the typical plane pattern structure of the semiconductor device which concerns on embodiment, (b) The figure which illustrates the formation pattern of the VIA hole formed in the semiconductor device shown to Fig.11 (a). (A) The enlarged view of the modification 2 of the typical plane pattern structure of the semiconductor device which concerns on embodiment, (b) The figure which illustrates the formation pattern of the VIA hole formed in the semiconductor device shown to Fig.12 (a). (A) The enlarged view of the modification 3 of the typical plane pattern structure of the semiconductor device which concerns on embodiment, (b) The figure which illustrates the formation pattern of the VIA hole formed in the semiconductor device shown to Fig.13 (a). (A) The enlarged view of the modification 4 of the typical plane pattern structure of the semiconductor device which concerns on embodiment, (b) The figure which illustrates the formation pattern of the VIA hole formed in the semiconductor device shown to Fig.14 (a). (A) The enlarged view of the modification 5 of the typical plane pattern structure of the semiconductor device which concerns on embodiment, (b) The figure which illustrates the formation pattern of the VIA hole formed in the semiconductor device shown to Fig.15 (a).

  Next, embodiments will be described with reference to the drawings. In the following, the same elements are denoted by the same reference numerals to avoid duplication of explanation and to simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and the embodiment does not specify the arrangement of each component as described below. This embodiment can be modified in various ways within the scope of the claims.

(Semiconductor element structure)
An enlarged view of a schematic planar pattern configuration of the semiconductor device according to the embodiment is represented as shown in FIG. 1A, and an enlarged view of a portion J in FIG. 1A is shown in FIG. The formation pattern of the VIA hole formed in the semiconductor device shown in FIG. 1A is illustrated in FIG. Further, Configuration Examples 1 to 5 of the semiconductor device according to the embodiment are represented as shown in FIGS. In each of FIGS. 3 to 6, (a) is a schematic cross-sectional structure diagram taken along line II in FIG. 1B, and (b) is taken along line II-II in FIG. 1B. It is a typical section structure figure.

  The semiconductor device according to the embodiment includes a semi-insulating substrate 110, a gate finger electrode 124, a source finger electrode 120, and a drain finger electrode 122 that are disposed on the first surface of the semi-insulating substrate 110 and each have a plurality of fingers. A plurality of gate terminal electrodes G1, G2,..., G6 disposed on the first surface of the semi-insulating substrate 110 and formed by bundling a plurality of fingers for each of the gate finger electrode 124 and the drain finger electrode 122; Electrodes D1, D2,..., D6, VIA holes SC11, SC12, SC21, SC22,..., SC61, SC62, SC71 disposed below each source finger electrode 120, and the first surface of the semi-insulating substrate 110 Arranged on the second surface on the opposite side, VIA holes SC11, S 12, SC21, SC22, ..., and a ground electrode 125 connected to a source finger electrode 120 through the SC61, SC62, SC71.

  A VIA hole SC11, SC12, SC21, SC22,..., SC61, SC62, SC71 formed on the inner wall of the source finger electrode 120 and a VIA hole formed on the barrier metal layer. The source finger electrode 120 is connected to the ground electrode 125 through the filling metal layer 132 filling the.

  The semi-insulating substrate 110 is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or One of the diamond substrates.

  Here, once turning to FIG. 7, FIG. 7A is an enlarged view of a schematic planar pattern configuration of a semiconductor device according to a comparative example, and FIG. 7B is shown in FIG. 2 illustrates a VIA hole formation pattern formed in the semiconductor device according to the comparative example. Also in the semiconductor device according to the comparative example, VIA holes SC11, SC12, SC21, SC22,..., SC61, SC62, SC71 are arranged below the source finger electrode 120, and VIA holes SC11, SC12, SC21, SC22,. , SC61, SC62, SC71, the source finger electrode 120 is grounded via a barrier metal layer (not shown) formed on the inner wall and a filling metal layer (not shown) formed on the barrier metal layer and filling the VIA hole. It is connected to an electrode (not shown).

  In FIG. 7, line D indicates the cleavage plane direction of the compound semiconductor crystal forming the semiconductor device according to the comparative example. Examples of the semiconductor crystal include a gallium arsenide (GaAs) substrate crystal, a silicon carbide (SiC) substrate crystal, and a nitride compound semiconductor (eg, gallium nitride (GaN)) crystal formed on the substrate. . The cleavage plane of the compound semiconductor crystal is, for example, a (011) plane for a GaAs crystal substrate and a (01-10) plane for a SiC crystal substrate.

  An example of the cleavage plane direction of the compound semiconductor crystal (GaN, SiC) used in the semiconductor device according to the embodiment and the semiconductor device according to the comparative example is schematically represented as shown in FIG. As shown in FIG. 8, the cleavage plane of the compound semiconductor crystal (GaN, SiC) is, for example, (10-10), (1-100), (01-10), (-1010), (-1100), (0-110).

  FIG. 9 illustrates the upper surface of a semiconductor substrate wafer (GaN, SiC) used in the semiconductor device according to the embodiment and the semiconductor device according to the comparative example. The orientation flat (OF) is formed for recognizing a cleavage plane (for example, (01-01) plane), and is used as a reference for adjusting the angle with respect to the cleavage plane orientation when a device is formed on the upper surface of the wafer 1. . In FIG. 9, six target directions AA, BB, and CC in the cleavage plane direction of the compound semiconductor crystal (GaN, SiC) are illustrated.

  On the other hand, FIG. 10A is a schematic view illustrating the plane orientation of a semiconductor substrate (GaAs, Si) used in the semiconductor device according to the embodiment and the semiconductor device according to the comparative example, and an example of the (100) plane is shown in FIG. An example of (001 plane) is expressed as shown in FIG. In the example of FIG. 10A, the <011> direction perpendicular to the orientation flat (OF) or the <011> direction parallel to the orientation flat (OF) is the cleavage plane direction. In the example of FIG. The <110> direction perpendicular to the orientation flat (OF) or the <01-1> direction parallel to the orientation flat (OF) is the cleavage plane direction.

  VIA holes SC11, SC12, SC21, SC22,..., SC61, SC62, SC71 formed in the semiconductor device as shown in FIG. 7 have a narrow hole interval (for example, the hole interval in the D-line direction is about 200 μm). VIA holes SC11, SC12, SC21, SC22,..., SC61, SC62, and SC71 are formed side by side with a high density because the hole width in the D-line direction is about 20 to 30 μm. Then, as in the semiconductor device according to the comparative example of FIG. 7, the alignment direction of the VIA holes SC11, SC12, SC21, SC22,..., SC61, SC62, SC71 and the cleavage plane direction (D line) of the compound semiconductor crystal. If they coincide with each other, the semiconductor element is easily broken, and as a result, the yield of the element is lowered.

  Returning to FIG. 1 again, according to the semiconductor device of the embodiment, the VIA holes SC11, SC21, SC31,..., SC61, SC71 are formed in the lower part of one side (first position) of the source finger electrode 120. The VIA holes SC12, SC22, SC32,..., SC52, SC62 are formed and arranged below the other side (second position) of the source finger electrode 120. That is, the VIA holes SC adjacent to each other (for example, the VIA hole SC11 and the VIA hole SC12) are alternately formed and arranged at the first position and the second position (alternately along different lines). Formed and arranged).

  Thereby, the VIA holes SC11, SC12, SC21, SC22,..., SC61, SC62, and SC71 formed and arranged in the semiconductor device according to the embodiment are in a direction different from the cleavage direction as compared with the VIA hole of the comparative example. They are arranged with variation, and are not formed side by side with high density (close proximity) in the cleavage plane direction of the compound semiconductor crystal. Therefore, it is possible to avoid the problem that the semiconductor element is hardly broken and the formation yield of the element is lowered.

(Structural example 1)
As shown in FIG. 2A, the configuration example 1 of the semiconductor device according to the embodiment includes a p ⁺ -type semiconductor substrate 110 a and a p-type disposed on the first surface of the p ⁺ -type semiconductor substrate 110 a. Epitaxial growth layer 112a, n ⁺ -type source region 126 and drain region 128 disposed on p-type epitaxial growth layer 112a, and p ⁺ -type semiconductor substrate 110a between source region 126 and drain region 128. A gate finger electrode 120 disposed on the source region 126, a gate finger electrode 124 disposed on the gate insulating film 123, and a drain finger electrode 122 disposed on the drain region 128.

As shown in FIG. 2B, a VIA hole SC is disposed below the source finger electrode 120, and a ground electrode 125 is disposed on the second surface opposite to the first surface of the p ⁺ type semiconductor substrate 110a. Is done. The source finger electrode 120 includes a barrier metal layer (not shown) formed on the inner wall of the VIA hole SC formed below the source finger electrode 120 and a filling metal layer 132 formed on the barrier metal layer and filling the VIA hole. And is connected to the ground electrode 125. In the configuration example 1 shown in FIG. 2, a SiC-based MOS transistor (Metal-Oxide-Semiconductor Transistor) is shown.

(Structural example 2)
Configuration example 2 of the semiconductor device according to the embodiment includes a semi-insulating substrate 110 and a nitride-based compound semiconductor layer disposed on the first surface of the semi-insulating substrate 110 as shown in FIG. 112, an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on the nitride-based compound semiconductor layer 112, and an aluminum gallium nitride layer (Al _x Ga _1- a source finger electrode (S) 120, a gate finger electrode (G) 124, and a drain finger electrode (D) 122 disposed on _x N) (0.1 ≦ x ≦ 1) 118. A two-dimensional electron gas (2DEG) layer is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. 116 is formed.

  As shown in FIG. 3B, the VIA hole SC is disposed below the source finger electrode 120, and the ground electrode 125 is disposed on the second surface opposite to the first surface of the semi-insulating substrate 110. . The source finger electrode 120 includes a barrier metal layer (not shown) formed on the inner wall of the VIA hole SC formed below the source finger electrode 120 and a filling metal layer 132 formed on the barrier metal layer and filling the VIA hole. And is connected to the ground electrode 125. In the configuration example 2 shown in FIG. 3, a GaN-based high electron mobility transistor (HEMT) is shown.

(Structural example 3)
Configuration example 3 of the semiconductor device according to the embodiment includes a semi-insulating substrate 110 and a nitride-based compound semiconductor layer disposed on the first surface of the semi-insulating substrate 110 as shown in FIG. 112, a source region 126 and a drain region 128 disposed on the nitride compound semiconductor layer 112, a source finger electrode (S) 120 disposed on the source region 126, and a nitride compound semiconductor layer 112. Gate finger electrode (G) 124 and drain finger electrode (D) 122 disposed on drain region 128. A Schottky contact is formed at the interface between the nitride-based compound semiconductor layer 112 and the gate finger electrode (G) 124.

  As shown in FIG. 4B, the VIA hole SC is disposed below the source finger electrode 120, and the ground electrode 125 is disposed on the second surface opposite to the first surface of the semi-insulating substrate 110. . The source finger electrode 120 includes a barrier metal layer (not shown) formed on the inner wall of the VIA hole SC formed below the source finger electrode 120 and a filling metal layer 132 formed on the barrier metal layer and filling the VIA hole. And is connected to the ground electrode 125. In the configuration example 3 shown in FIG. 4, a GaN-based metal-semiconductor field effect transistor (MESFET) is shown.

  Alternatively, a GaAs semi-insulating substrate may be used as the semi-insulating substrate 110, and a GaAs compound semiconductor layer may be applied instead of the nitride compound semiconductor layer 112. In that case, the configuration example 3 shown in FIG. 4 shows a GaAs-based MESFET.

(Structural example 4)
Configuration example 4 of the semiconductor device according to the embodiment includes a semi-insulating substrate 110 and a nitride-based compound semiconductor layer disposed on the first surface of the semi-insulating substrate 110 as shown in FIG. 112, an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on the nitride-based compound semiconductor layer 112, and an aluminum gallium nitride layer (Al _x Ga _1- source finger electrode (S) 120 and drain finger electrode (D) 122 disposed on _x N) (0.1 ≦ x ≦ 1) 118, and an aluminum gallium nitride layer (Al _x Ga _1-x N) (0 1 ≦ x ≦ 1) 118, and a gate finger electrode (G) 124 disposed in a recess portion. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118.

  As shown in FIG. 5B, the VIA hole SC is disposed below the source finger electrode 120, and the ground electrode 125 is disposed on the second surface opposite to the first surface of the semi-insulating substrate 110. . The source finger electrode 120 includes a barrier metal layer (not shown) formed on the inner wall of the VIA hole SC formed below the source finger electrode 120 and a filling metal layer 132 formed on the barrier metal layer and filling the VIA hole. And is connected to the ground electrode 125. In the configuration example 4 illustrated in FIG. 5, the HEMT is illustrated.

(Structural example 5)
Configuration example 5 of the semiconductor device according to the embodiment includes a semi-insulating substrate 110 and a nitride-based compound semiconductor layer disposed on the first surface of the semi-insulating substrate 110 as shown in FIG. 112, an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on the nitride-based compound semiconductor layer 112, and an aluminum gallium nitride layer (Al _x Ga _1- source finger electrode (S) 120 and drain finger electrode (D) 122 disposed on _x N) (0.1 ≦ x ≦ 1) 118, and an aluminum gallium nitride layer (Al _x Ga _1-x N) (0 1 ≦ x ≦ 1) 118 and a gate finger electrode 124 disposed in a two-stage recess portion. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118.

  As shown in FIG. 6B, a VIA hole SC is disposed below the source finger electrode 120, and a ground electrode 125 is disposed on the second surface opposite to the first surface of the semi-insulating substrate 110. . The source finger electrode 120 includes a barrier metal layer (not shown) formed on the inner wall of the VIA hole SC formed below the source finger electrode 120 and a filling metal layer 132 formed on the barrier metal layer and filling the VIA hole. And is connected to the ground electrode 125. In the configuration example 5 illustrated in FIG. 6, the HEMT is illustrated.

  The source finger electrode 120 and the drain finger electrode 122 are made of, for example, Ti / Al. The gate finger electrode 124 can be formed of, for example, Ni / Au.

  In the semiconductor device 140, the pattern lengths in the longitudinal direction of the gate finger electrode 124, the source finger electrode 120, and the drain finger electrode 122 are set shorter as the operating frequency increases. For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  The width of the source finger electrode 120 is, for example, about 40 to 50 μm, and the length (size in the longitudinal direction) of the source finger electrode 120 is, for example, about 70 μm. The width of the VIA hole SC is, for example, about 20 to 30 μm, and the length (size in the longitudinal direction) of the VIA hole SC is, for example, about 50 μm. Of the source finger electrode 120, the size of the blank portion where the VIA hole SC is not formed is about 10 μm in each of the upper, lower, left, and right sides. The VIA hole SC can be formed in a rectangular shape as shown in FIG. 1 or the like, for example, in a square shape.

(Modification 1)
FIG. 11A is an enlarged view of Modification 1 of the schematic planar pattern configuration of the semiconductor device according to the embodiment, and FIG. 11B is formed in the semiconductor device shown in FIG. The formation pattern of a VIA hole is illustrated.

  As shown in FIG. 11, according to the first modification of the semiconductor device according to the embodiment, the VIA hole SC11 is formed and arranged below the one side (first position) of the source finger electrode 120, and the VIA hole SC12 is formed. Is formed and arranged at the lower part of the center part (third position) of the source finger electrode 120, the VIA hole SC21 is formed and arranged at the lower part of the other side (second position) of the source finger electrode 120, and the VIA hole SC22 is formed. A VIA hole SC131 is formed and arranged at the lower part of one side (first position) of the source finger electrode 120, and is arranged at the lower part of the center part (third position) of the source finger electrode 120,. Is formed and arranged on the lower side of the other side (second position) of the source finger electrode 120, and the VIA hole SC 62 is connected to the source finger electrode 12. The central portion is formed and arranged in the lower part of the (third position), and the VIA holes SC71 formed arranged in the lower part of one side of the source finger electrode 120 (the first position). That is, adjacent VIA holes SC (for example, VIA hole SC11, VIA hole SC12, and VIA hole SC21) are alternately formed at the first position, the third position, and the second position (different from each other). Each is staggered along the line).

(Modification 2)
12A is an enlarged view of a second modification of the schematic planar pattern configuration of the semiconductor device according to the embodiment, and FIG. 12B is formed in the semiconductor device shown in FIG. The formation pattern of a VIA hole is illustrated.

  As shown in FIG. 12, according to the second modification of the semiconductor device according to the embodiment, the VIA holes SC11 and SC12 are formed and arranged below the one side (first position) of the source finger electrode 120, and the VIA Holes SC21 and SC22 are formed and arranged below the other side (second position) of source finger electrode 120, and VIA holes SC31 and SC32 are formed below one side (first position) of source finger electrode 120. And VIA holes SC61 and SC62 are formed and arranged below the other side (second position) of the source finger electrode 120, and the VIA holes SC71 (and SC72) are arranged on one side of the source finger electrode 120 (first side). (Position 1). That is, adjacent VIA holes SC (for example, VIA holes SC11 and SC12 and VIA holes SC21 and SC22) are formed and arranged alternately in the first position and the second position (two sets each). , Each of which is staggered along different lines).

(Modification 3)
FIG. 13A is an enlarged view of Modification 3 of the schematic planar pattern configuration of the semiconductor device according to the embodiment, and FIG. 13B is formed in the semiconductor device shown in FIG. The formation pattern of a VIA hole is illustrated.

  As shown in FIG. 13, according to the third modification of the semiconductor device according to the embodiment, two sets of VIA holes SC <b> 11 are arranged on the lower side on one side (first position) of the source finger electrode 120 and the other side ( The first VIA hole SC12 is formed and arranged at the lower part of the second position), and one set of VIA holes SC12 is formed and arranged at the lower part of the center part (third position) of the source finger electrode 120. 120 is formed and arranged at the lower part of one side (first position) and the lower part of the other side (second position), respectively, and one set of VIA holes SC22 is arranged at the center part of the source finger electrode 120 (third position). ), One set of VIA holes SC62 is formed and arranged in the lower part of the central part (third position) of the source finger electrode 120, and two sets of VIA holes SC71 are formed The bottom of one side of the Nga electrode 120 under the other side of the (first position) (second position) are formed arranged. That is, adjacent VIA holes SC (for example, two sets of VIA holes SC11 and one set of VIA holes SC12) are alternately formed at the first position, the second position, and the third position, respectively. (Two sets of VIA holes SC11 and one set of VIA holes SC12 are alternately formed along different lines).

(Modification 4)
FIG. 14A is an enlarged view of Modification 4 of the schematic planar pattern configuration of the semiconductor device according to the embodiment, and FIG. 14B is formed in the semiconductor device shown in FIG. The formation pattern of a VIA hole is illustrated.

  As shown in FIG. 14, according to the fourth modification of the semiconductor device according to the embodiment, two sets of VIA holes SC <b> 11 are arranged on the lower side and the central part (first side) of one side (first position) of the source finger electrode 120. 3 positions), and two sets of VIA holes SC12 are formed and arranged on the other side (second position) of the source finger electrode 120 and the lower part of the central portion (third position), respectively. Two sets of VIA holes SC21 are formed and arranged at the lower part of one side (first position) and the lower part of the other side (second position) of the source finger electrode 120, respectively. SC61 is formed and arranged at the lower part of the other side (second position) and the lower part of the central part (third position) of the source finger electrode 120, respectively, and two sets of VIA holes SC62 are formed as one part of the source finger electrode 120. The two VIA holes SC71 are formed on one side (first position) of the source finger electrode 120 by forming and disposing them on the lower side of the first side (first position) and the lower side of the other side (second position), respectively. They are formed and arranged at the lower part of the lower part and the central part (third position), respectively. That is, adjacent VIA holes SC (for example, two sets of VIA holes SC11, two sets of VIA holes SC12, and two sets of VIA holes SC21) are alternately arranged in the first position and the second position, Each of the first position and the second position is formed and arranged (at least one of the two adjacent VIA holes is located on a different line). Formed and arranged).

(Modification 5)
FIG. 15A is an enlarged view of Modification 5 of the schematic planar pattern configuration of the semiconductor device according to the embodiment, and FIG. 15B is formed in the semiconductor device shown in FIG. The formation pattern of a VIA hole is illustrated.

  As shown in FIG. 15, according to the fifth modification of the semiconductor device according to the embodiment, two sets of VIA holes SC <b> 11 are arranged at the lower part and the central part (first part) on one side (first position) of the source finger electrode 120. The two VIA holes SC12 are formed at the lower part on one side (first position) and the lower part on the other side (second position) of the source finger electrode 120, respectively. Two pairs of VIA holes SC21 are formed and arranged at the lower part of the center part (third position) and the lower part of the other side (second position) of the source finger electrode 120, respectively. SC61 is formed and arranged at the lower part of the other side (second position) and the lower part of the central part (third position) of the source finger electrode 120, respectively, and two sets of VIA holes SC62 are formed as one part of the source finger electrode 120. The two VIA holes SC71 are formed on one side (first position) of the source finger electrode 120 by forming and disposing them on the lower side of the first side (first position) and the lower side of the other side (second position), respectively. They are formed and arranged at the lower part of the lower part and the central part (third position), respectively. That is, adjacent VIA holes SC (for example, two sets of VIA holes SC11, two sets of VIA holes SC12, and two sets of VIA holes SC21) are staggered between the first position and the third position, The position, the second position, and the second position and the third position are respectively formed and arranged (at least one of the two pairs of VIA holes adjacent to each other is on a different line. Formed and arranged).

  Thus, the VIA holes SC11, SC12, SC21, SC22,..., SC61, SC62, SC71 formed and arranged in the first to fifth modifications of the semiconductor device according to the embodiment are compared with the VIA holes of the comparative example. They are arranged with a variation in a direction different from the cleavage direction, and are not formed side by side with high density (closely) in the cleavage plane direction of the compound semiconductor crystal. Therefore, it is possible to avoid the problem that the semiconductor element is hardly broken and the formation yield of the element is lowered.

  According to the embodiment described above, it is possible to provide a semiconductor device capable of preventing the semiconductor element from being easily broken even if the VIA holes are formed at a high density, and improving the formation yield of the element.

[Other embodiments]
Although the semiconductor device according to the embodiment and its modifications 1 to 5 has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  In the semiconductor device according to the embodiment and its modifications 1 to 5, the n-type and p-type conductivity types of the semiconductor may be reversed.

  The semiconductor device according to the embodiment is not limited to an FET or HEMT, but an amplifying element such as a Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor (LDMOS) or a heterojunction bipolar transistor (HBT). Needless to say, the above can also be applied.

  As described above, various embodiments that are not described herein are included.

DESCRIPTION OF SYMBOLS 1 ... Wafer 110 ... Semi-insulating substrate 110a ... Semiconductor substrate 112 ... Nitride type compound semiconductor layer (GaN epitaxial growth layer)
112a ... epitaxial layer 116 ... two-dimensional electron gas (2DEG) layer 118 ... aluminum gallium nitride layer _{(Al x Ga 1-x N} ) (0.1 ≦ x ≦ 1)
120 ... Source finger electrode 122 ... Drain finger electrode 124 ... Gate finger electrode 125 ... Ground electrode 126 ... Source region 128 ... Drain region 132 ... Filling metal layer G (G1, G2, ..., G10) ... Gate terminal electrode D (D1, D1) D2,..., D10) Drain terminal electrodes SC (SC11, SC12, SC21, SC22,..., SC61, SC62, SC71) ... VIA holes S ... Source terminal electrodes OF ... Orientation flat

Claims (5)

A substrate,
A gate electrode, a source electrode and a drain electrode, each disposed on a first surface of the substrate, each having a plurality of fingers;
A VIA hole disposed under the source electrode;
A ground electrode disposed on a second surface opposite to the first surface of the substrate and connected to the source electrode through the VIA hole;
The VIA hole is arranged along a direction different from the cleavage direction of the compound semiconductor crystal forming the substrate. The semiconductor device further includes a nitride compound semiconductor layer disposed on the substrate,
2. The semiconductor device according to claim 1, wherein the VIA hole is arranged along a direction different from a cleavage direction of the compound semiconductor crystal forming the nitride-based compound semiconductor layer.   The semiconductor device according to claim 1, wherein the adjacent VIA holes are alternately arranged along different lines.   3. The semiconductor device according to claim 1, wherein the adjacent VIA holes are alternately arranged in a lower portion of the first position and a lower portion of the second position of the source electrode, respectively.   The semiconductor device according to claim 1, wherein the compound semiconductor crystal forming the substrate is GaAs, SiC, or GaN.

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