JP2013055233A - Method of detecting chip arrangement on wafer in prober - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an array detection method capable of detecting chip array even on a wafer of large chip in a prober, with reduced burden on an operator.SOLUTION: In a prober, each terminal of a tester is connected to an electrode of a chip for electrically inspecting operation of the chip formed regularly on a wafer W. A method of detecting chip array on a wafer loaded on a wafer stage includes the steps of :(S13) detecting a center position of a wafer; (S15) imaging a surface image of the wafer by a plurality of times using a wafer alignment camera while changing a relative position, and compositing the imaged images to generate a surface image within a predetermined range from the center position of the wafer; (S16) displaying a composite wafer surface image so that the entire predetermined range is displayed; (S17) registering an intersection of an instructed street; (S19) registering an alignment mark in the chip that is instructed; and detecting an alignment mark of a different chip and calculating chip array from positional relationship.

Description

  In the present invention, in order to perform electrical inspection of a plurality of semiconductor chips (dies) (hereinafter simply referred to as chips) formed on a semiconductor wafer (hereinafter simply referred to as wafers), terminals of a tester are provided. The present invention relates to a prober connected to an electrode pad of a chip, and more particularly to a method of detecting a chip arrangement in the prober without data on the arrangement of chips formed on a wafer.

  In the semiconductor manufacturing process, various processes are performed on a thin disk-shaped semiconductor wafer to form a plurality of chips (dies) each having a semiconductor device (device). Each chip is inspected for electrical characteristics, then separated by a dicer, and then fixed to a lead frame and assembled. The inspection of the electrical characteristics is performed by a wafer test system that combines a prober and a tester. The prober fixes the wafer to the wafer stage and brings the probe into contact with the electrode pad of each chip. The tester supplies power and various test signals from the terminals connected to the probe, and analyzes the signals output to the electrodes of the chip with the tester to check whether it operates normally.

  The prober has a wafer stage for holding a wafer, a moving / rotating part of the wafer stage, a probe position detection camera for detecting the position of the probe, a wafer alignment camera, and a card holder to which a probe card is attached. The probe card has a probe arranged according to the electrode arrangement of the device to be inspected, and is exchanged according to the device to be inspected. The probe position detection camera detects the arrangement and height position of the probe, and the wafer alignment camera detects the position of the electrode pad of the semiconductor chip (die) on the wafer W. The coordinate system indicating the position of the image detected by the wafer alignment camera is associated with the coordinate system of the prober wafer stage moving / rotating mechanism. Here, the coordinate system of the wafer alignment camera and the coordinate system of the moving / rotating mechanism are collectively referred to as a prober coordinate system.

  The prober inspection sequence is set every time the probe card is replaced in accordance with the device to be inspected. At this time, generally, information such as a wafer size and a chip size (index) is provided, but information such as a chip arrangement is not provided. Therefore, the prober picks up a wafer sample with the wafer alignment camera, displays the image on the monitor screen, and the operator recognizes the part called the street between the chips and indicates the intersection of the streets on the screen. In addition, it is necessary to perform a registration operation for specifying an alignment mark in the chip. The prober control unit registers the intersection of the specified street and the alignment mark, detects the alignment mark of a different chip, and detects the chip arrangement in the prober coordinate system from the positional relationship of the two alignment marks. To do.

  In general, the wafer alignment camera can switch the photographing magnification to a plurality of stages. When displaying a wide range, the magnification is low, and when displaying / detecting a circuit pattern, the magnification is high. Take a picture. In Patent Document 1, a wafer alignment camera is moved relative to a wafer based on the street position that has already been detected, a plurality of high-magnification images are taken, and a plurality of images are combined to obtain a high-level overall chip. The generation of a magnification image is described.

  In the registration operation, when an operator captures a sample of a wafer with the wafer alignment camera so as to recognize the street, the wafer alignment camera captures a low-magnification image and displays the image to display as wide a range as possible. Display on the screen. If there is no street intersection in the displayed screen, the operator moves the wafer stage to change the relative position between the wafer alignment camera and the wafer and searches for the street intersection.

  After detecting the chip arrangement in the prober coordinate system as described above, the chip arrangement direction matches the prober coordinate system, that is, the street direction on the wafer is the X-axis and Y-axis of the prober coordinate system. After adjusting so as to coincide with the axial direction, the intersection of the street and the position of the alignment mark are re-registered. The prober is provided with a function of detecting the thickness of the wafer placed on the wafer stage and the center of the circular wafer, and registers the intersection of the streets from the center of the wafer.

  When the registration process as described above is completed, if the wafer is the same device, the intersection of the street and the alignment mark can be automatically detected by image processing if the center of the wafer is detected from the second time onward. Measurement can be performed fully automatically.

JP 2004-241686 A JP 2003-97930 A

  Up to now, the maximum chip size is generally about 20 mm × 20 mm. The image size captured by the wafer alignment camera at a low magnification is about 10 mm, and if the image of the wafer is captured, the entire chip may not be captured, but there is a possibility that a street exists in the displayed image. It was quite expensive. Therefore, the operator can easily recognize streets and street intersections. Even when there are no streets in the image, the street and street intersections appear on the screen and can be easily recognized by moving the wafer stage a little and changing the position on the wafer to be imaged. .

  However, in recent years, large chips with a size of 50 mm × 50 mm or more may be made. In the case of such a large chip, the possibility that a street exists in the displayed image is very small. If there are no street intersections in the image, move the wafer stage to change the position on the wafer to be imaged, and look for the appearance of street intersections in the displayed image. In some cases, there are street intersections in the displayed image, and it takes a long time to recognize them.

  In general, an image obtained by imaging a wafer surface, in particular, a low-magnification image is an image that is difficult to recognize because of a pattern or the like formed on the wafer surface. For this reason, as described above, the operation of searching for a street intersection is very complicated, and is a burdensome operation for the operator, and there is a problem that the operation time becomes long.

  An object of the present invention is to solve such a problem, and it is an object of the present invention to detect a chip arrangement on a wafer with a reduced burden on an operator even in the case of a large chip.

  In order to achieve the above object, according to the method for detecting a chip arrangement on a wafer of the present invention, a wafer alignment camera synthesizes a plurality of images taken while changing the relative position with respect to the wafer to obtain a surface image of the wafer within a predetermined range. And the synthetic wafer surface image is displayed so that the entire predetermined range is displayed, so that the operator can easily recognize the street.

  That is, the prober of the present invention is a prober for connecting each terminal of the tester to the electrode of the chip in order to electrically inspect the operation of the chip regularly formed on the wafer. A method for detecting the arrangement of chips on a wafer, wherein the center position of the wafer is detected, and a wafer alignment camera is used to capture a surface image of the wafer multiple times while changing the relative position with respect to the wafer. The synthesized wafer surface image is generated from the center position of the wafer, and the synthesized wafer surface image is displayed so that the entire predetermined range is displayed, and the street between the instructed chips is displayed. Register the intersection point, register the alignment mark in the indicated chip for the street intersection point, and differ from the chip containing the registered alignment mark. By detecting the alignment mark of the chip, from the positional relationship of the two alignment marks, it computes a sequence of chips on a wafer, characterized in that.

  The predetermined range is determined so as to always include a street intersection from the chip size.

According to the present invention, a surface image of a wafer within a predetermined range from the center position of the wafer is synthesized and displayed. If the predetermined range is equal to or larger than the size of the chip, the composite image always includes a street, so that the operator can easily recognize the street intersection in the displayed composite image.
A series of operations in the prober is performed by a control unit configured by a computer.

  According to the present invention, there is an effect that it is possible to reduce the burden on the operator when registering the street intersection of the wafer to which information such as the chip arrangement is not provided and the alignment mark in the chip.

It is a figure which shows the basic composition of the wafer test system which test | inspects the chip | tip on a wafer with a prober and a tester. It is a figure which shows the example of arrangement | sequence of the big chip | tip formed on the wafer. It is a figure which shows the registration operation | movement flow of the street intersection of a wafer and the alignment mark in a chip | tip in embodiment. It is a figure which shows the example of a synthesized image.

  FIG. 1 is a diagram illustrating a schematic configuration of a wafer test system according to an embodiment. The wafer test system includes a prober 10 and a tester 30. As illustrated, the prober 10 includes a wafer stage 16 that holds the wafer W, a Z-axis moving / rotating unit 15 that moves the wafer stage 16 in the Z-axis direction and rotates about the Z-axis, and a probe position. The probe position detection camera 18 to be detected, the camera movement mechanism 17 for moving the probe position detection camera 18 in the Z-axis direction, the Z-axis movement / rotation unit 15 and the camera movement mechanism 17 are supported and moved in the X-axis direction ( X-axis) moving table 14, a Y-axis moving table 13 that supports the X-axis moving table 14 and moves in the Y-axis direction, a moving base 12 that supports the Y-axis moving table 13, and a base that supports the moving base 12 A base 11, a support 19 and 20 supported by the base 11, a head stage 21 supported by the support 19 and 20, a wafer alignment camera 22 provided on a support (not shown), Having a card holder 23 provided on the Ddosuteji 21, a probe card 24 attached to the card holder 23, a. Since the moving / rotating mechanism is widely known, the description thereof is omitted here. The prober 10 includes a control unit, a display, and a control panel (not shown). The control unit is configured by a computer, for example. The display also displays images taken by the wafer alignment camera 22 and the probe position detection camera 18, instructions / information to the operator, and the like. The operator gives instructions to the wafer test system via the control panel while watching the display. The control unit has a function of reading the position on the screen designated by the operator with a direction key, a mouse, or the like as the position of the prober coordinate system.

  The probe card 24 has a probe 25 arranged according to the electrode arrangement of the device to be inspected, and is exchanged according to the device to be inspected. The probe position detection camera 18 detects the arrangement and height position of the probe, and the wafer alignment camera 22 detects the position of the electrode pad of the semiconductor chip (die) on the wafer W.

  The tester 30 includes a tester body 31 and a contact ring 32 provided on the tester body 31. The probe card 25 is provided with a terminal connected to each probe, and the contact ring 32 has a spring probe arranged so as to contact the terminal. The tester body 31 is held with respect to the prober 10 by a support mechanism (not shown).

  The wafer W to be inspected is transferred from the cassette outside the prober 10 to the wafer stage 16 by a wafer loading mechanism (not shown), and the wafer that has been inspected is transferred to the cassette outside the prober 10 by the wafer unloading mechanism. Be transported. In some cases, wafer loading and wafer unloading are performed by the same mechanism.

  The wafer loading mechanism detects the outer periphery and notch or orientation flat of the wafer W, and conveys the wafer onto the wafer stage 16 with a certain degree of positional accuracy. Accordingly, the wafer W chucked on the wafer stage 16 is arranged with a certain degree of positional accuracy with respect to the prober coordinate system, and the street is also placed with a certain degree of directional accuracy with respect to the prober coordinate system. As described above, the image detected by the wafer alignment camera 22 is associated with the prober coordinate system.

  When the probe card is exchanged according to the device to be inspected, it is necessary to register street intersections and alignment marks in the chips in order to define the arrangement of chips on the wafer.

  FIG. 2 is a diagram illustrating an arrangement example of large chips formed on the wafer W on which street intersections and alignment marks in the chips are registered in the embodiment. In this example, nine chips C are formed on the wafer W in a 3 × 3 array, a portion between the chips C is a street S, and an intersection of the streets S is a street intersection S ′. In FIG. 2, A indicates an imaging range when imaging is performed with the wafer alignment camera 22 at a low magnification. When the magnification is high, the imaging range is further reduced.

  As shown in FIG. 2, it can be seen that the imaging range A of the wafer alignment camera 22 at a low magnification is smaller than the size of the chip C, and it is not easy to find the street S and the street intersection S ′.

  FIG. 3 is a diagram illustrating a registration operation flow of the wafer street intersection and the alignment mark in the chip in the embodiment. A series of operations is controlled by the control unit.

  In step S11, the notch or orientation flat and the outer periphery of the wafer W are detected by the wafer loading mechanism.

  In step S12, the wafer W is transferred (loaded) onto the wafer stage 16 by the wafer loading mechanism. The wafer W, which has been transferred onto the wafer stage 16 and fixed by the chuck, is positioned on the wafer stage 16 with a certain degree of positional accuracy. Therefore, the center of the wafer W deserves the vicinity of the center on the wafer stage 16, and the street of the wafer W extends in a direction approximate to the X-axis and Y-axis directions of the prober moving mechanism. In other words, the chucked wafer W is arranged with a certain degree of positional accuracy with respect to the prober coordinate system. However, it is not sufficient to perform an inspection by bringing the probe into contact with the electrode pad.

  In step S13, the thickness and center position of the wafer W are detected. The thickness of the wafer W can be measured by using a dedicated thickness measuring device or by detecting the focal position of the surface of the wafer W with the wafer alignment camera 22. The thickness and the center position of the wafer W can be calculated, for example, by detecting the edge of the circular wafer W at three or more points, for example, four points by the wafer alignment camera 22.

  In step S14, the wafer stage 16 is moved so that the wafer alignment camera 22 images the center position of the wafer W.

  In step S <b> 15, the wafer W is moved with respect to the wafer alignment camera by the imaging range of the wafer alignment camera 22 to capture a plurality of images, and a composite image in a predetermined range with respect to the center position of the wafer W is generated. Such an operation is generally called scanning. The predetermined range is, for example, a range slightly larger than the size of the chip C. In this case, the street intersection S ′ is always included in the composite image of the predetermined range.

  In general, when changing a device to be inspected, an index indicating a chip size is instructed from the outside as information on a wafer. When the chip is rectangular, an index XI in the X direction and an index YI in the Y direction are instructed. When the size of the imaging range of the wafer alignment camera 22 is XS × YS, m and n are determined so that mXS> XI and nYS> YI, and m × n images are synthesized.

  In step S16, the composite image is displayed on the display so that the entire predetermined range is displayed. At this time, at least one street intersection S 'is displayed on the screen. Since the number of pixels of the composite image is larger than the number of pixels of the display, the composite image is compressed or thinned out to display the same number of pixels.

FIG. 4 is a diagram illustrating a display example of a composite image.
FIG. 4A shows an example in which images are synthesized by performing scanning so that the center of the wafer W is positioned at the center of a predetermined range in FIG. 2, and the synthesized image has 15 × 15 imaging ranges. The image A is synthesized, and four street intersections S ′ are displayed on the screen D. The street S is inclined with respect to the X axis and the Y axis of the screen.

  4B is a composite image of the image A in the 15 × 15 imaging range, and one street intersection S ′ is displayed on the screen D. FIG.

  As described above, there are various arrangements of the chips C on the wafer W, and information relating to them is not supplied. Further, it is arbitrary how to set the predetermined range with respect to the center position of the wafer W, and it is not known until a composite image is generated what composite image is generated. For example, unlike FIG. 2, there may be a street intersection S ′ near the center position of the wafer W. Further, when scanning a range of ± (predetermined range) / 2 in the X-axis direction and the Y-axis direction with respect to the center position of the wafer W, the X-axis direction and the Y-axis direction are one from the center position of the wafer W. There is a case of scanning in the direction.

In any case, if a composite image of a predetermined range is generated as described above, at least one street intersection S ′ is included in the composite image and displayed on the display.
The operator observes the composite image displayed on the display, and inputs the position of the street intersection S ′ on the screen via the controller.

  In step S <b> 17, the position of the designated street intersection S ′ is registered in the coordinate system of the prober 10.

  In step S18, the direction of the street S is detected. The inclined street S is detected by the method described in Patent Document 2, for example. Note that the operator is requested to indicate a position on the street S other than the street intersection S ′ on the composite image displayed on the display, and the position on the street S and the street intersection S ′ already specified are instructed. The direction of the street S may be detected.

  The operator observes the composite image displayed on the display and instructs an alignment mark. It is desirable that there is only one alignment mark in the chip and the pattern is easy to identify. For example, an electrode pad or the like can be easily identified, but is not preferable as an alignment mark because there are others having the same shape. The operator instructs a pattern that satisfies such conditions.

  In step S19, the wafer alignment camera 22 images the alignment mark instructed by the operator at a high magnification, and registers the image including the positional relationship with the street intersection S '.

  In step S20, an alignment mark of a chip different from the chip including the registered alignment mark is detected. When moving from the registered alignment mark by the index (chip size) in the street direction calculated in step S18, another chip alignment mark is reached. If it moves by a plurality of indexes, it reaches an alignment mark further away. In this way, alignment marks on other chips can be easily detected.

  The control unit performs the above operation, images the alignment marks of different chips at high magnification, and precisely calculates the chip arrangement direction θ, that is, the street direction, from the positional relationship with the registered alignment marks. .

  In step S21, the rotational position of the wafer stage 16 is corrected so that the calculated chip arrangement direction θ coincides with the X-axis and Y-axis of the prober coordinate system. After that, the street intersection and the alignment mark position are automatically re-registered.

  This completes the registration operation of the wafer street intersection and the alignment mark in the chip.

  When the registration process as described above is completed, if the wafer is the same device, the intersection of the street and the alignment mark can be automatically detected by image processing if the center of the wafer is detected from the second time onward. Measurement can be performed fully automatically.

  In order to perform the inspection, it is further necessary to match the arrangement of the electrode pads of the chip with the arrangement of the probes detected by the probe position detection camera. Therefore, the wafer stage is rotated to match the arrangement of the electrode pads of the chip with the arrangement of the probes, and the arrangement of the probes in the prober coordinate system is registered. Subsequent movement operations are performed based on the probe arrangement in the registered prober coordinate system. For example, if the probe array is rotated by a small amount relative to the prober's coordinate system, the error will increase if the probe is moved a long distance ignoring this small amount of rotation, and the probe will come out of contact with the electrode pad. Occurs. Therefore, the wafer stage is rotated by a small amount, and the prober is moved in the coordinate system while correcting the minute amount. Further, in order to accurately measure the probe arrangement, a contact trace (needle trace) when the probe is actually brought into contact with the electrode pad may be detected by a wafer alignment camera.

When the above operation is completed, the chip on the wafer W can be inspected. When inspection is performed, the wafer W having the notch or orientation flat and the outer periphery detected is transferred and fixed (loaded) on the wafer stage 16 by the wafer loading mechanism. Further, the thickness and center position of the wafer W fixed on the wafer stage 16 are detected, the alignment marks of different chips are detected, θ is accurately detected, the wafer stage 16 is rotated, and the probe array and The θ correction is performed including the relationship. Then, after detecting or calculating the position of the electrode pad in which the positional relationship with the alignment mark or the street intersection is defined and moving the wafer stage 16 so that the electrode pad is located immediately below the corresponding probe, the wafer stage 16 is raised to bring the probe 25 into contact with the electrode pad. Thus, the tester 30 can be inspected.
The embodiment has been described above, but it goes without saying that various modifications are possible.

DESCRIPTION OF SYMBOLS 12 Movement base 14 X-axis movement stand 15 Z-axis movement and rotation part 16 Wafer stage 18 Probe position detection camera 22 Wafer alignment camera 24 Probe card 26 Probe

Claims (2)

An array of the chips on the wafer loaded on the wafer stage in a prober for connecting each terminal of the tester to the electrodes of the chip to electrically inspect the operation of the chips regularly formed on the wafer. A method of detecting
Detecting the center position of the wafer;
Using the wafer alignment camera, the surface image of the wafer is captured a plurality of times while changing the relative position with the wafer, and the captured images are combined to generate a surface image of the wafer within a predetermined range from the center position of the wafer. And
Display the synthetic wafer surface image so that the entire predetermined range is displayed,
Register the street intersection that is the part between the indicated chips,
Register the alignment mark in the designated chip for the intersection of the streets,
Detecting the alignment mark of a chip different from the chip including the registered alignment mark, and calculating the arrangement of the chips on the wafer from the positional relationship of the two alignment marks. .   The method according to claim 1, wherein the predetermined range is determined from the size of the chip so as to include an intersection of the streets.

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