JP2013053898A - Semiconductor testing jig and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing jig capable of shortening a test time by improving workability in testing multiple vertical semiconductor devices, and also to provide a manufacturing method of the same.SOLUTION: The semiconductor testing jig is used for testing multiple vertical semiconductor devices 5 each of which has a lower surface electrode 3 and an upper surface electrode 4. A conductive base table 1 has multiple arrangement parts 6. The multiple vertical semiconductor devices 5 are respectively individually arranged in the arrangement parts 6 while the lower surface electrodes 3 have contact with the arrangement parts. Grid shape insulating frames 2 are arranged on the base table 1. The frames 2 respectively enclose the multiple arrangement parts 6.

Description

  The present invention relates to a semiconductor test jig for testing a plurality of vertical semiconductor devices having a lower surface electrode and an upper surface electrode, and a method for manufacturing the same.

  When testing the electrical characteristics of a plurality of semiconductor devices cut into chips, each semiconductor device was individually positioned and tested. For this reason, workability | operativity was bad and the test time was long. On the other hand, an insulating transport tray that can position a plurality of semiconductor devices such as an IC package in a lump, and a test apparatus using the same have been proposed (for example, see Patent Document 1). Thereby, workability | operativity can be improved and test time can be shortened.

JP 2006-292727 A

  In the vertical semiconductor device, a current flows between the upper electrode and the lower electrode of the device. When testing this vertical semiconductor device, the stage with which the lower electrode of the semiconductor device contacts is one of the measurement electrodes. Therefore, the vertical semiconductor device cannot be tested with the vertical semiconductor device installed on the conventional insulating transfer tray.

  The present invention has been made to solve the above-described problems, and its object is to improve the workability when testing a plurality of vertical semiconductor devices and reduce the test time. A tool and its manufacturing method are obtained.

  A semiconductor test jig according to the present invention is a semiconductor test jig for testing a plurality of vertical semiconductor devices having a bottom electrode and a top electrode, and the plurality of vertical semiconductors in a state in which the bottom electrode is in contact with the semiconductor test jig. A conductive base having a plurality of installation portions on which the apparatus is individually installed; and a grid-like insulating frame provided on the base and surrounding each of the plurality of installation portions. Features.

  According to the present invention, workability when testing a plurality of vertical semiconductor devices can be improved, and the test time can be shortened.

It is a top view which shows the semiconductor test jig | tool which concerns on Embodiment 1 of this invention. It is sectional drawing in alignment with I-II of FIG. It is sectional drawing which shows the semiconductor test jig | tool which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the semiconductor test jig | tool which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the semiconductor test jig | tool which concerns on Embodiment 4 of this invention. It is a top view which shows the semiconductor test jig | tool which concerns on Embodiment 5 of this invention. It is sectional drawing along I-II of FIG.

  A semiconductor test jig and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a top view showing a semiconductor test jig according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view taken along the line I-II in FIG. In FIG. 1, only the transport tray including the base 1 and the frame portion 2 is shown for simplification of description. This semiconductor test jig is used for testing a plurality of vertical semiconductor devices 5 having the lower surface electrode 3 and the upper surface electrode 4. The vertical semiconductor device 5 is, for example, a semiconductor chip, but is not limited thereto, and may be a substrate on which a semiconductor chip is temporarily assembled.

  The base 1 is made of a plate-like metal having conductivity such as aluminum. The base 1 has 16 installation parts 6. A plurality of vertical semiconductor devices 5 are individually installed in the installation unit 6 with the lower surface electrode 3 in contact therewith. The installation portion 6 is preferably a flat surface from which burrs and protrusions have been removed by a cleaning and polishing process so as not to damage the lower surface electrode 3 of the vertical semiconductor device 5. The number of the installation units 6 is not limited to 16, and may be increased or decreased according to the size of the test apparatus or the vertical semiconductor device 5.

  A grid-like frame portion 2 is provided on the base 1. The frame part 2 surrounds the plurality of installation parts 6. A side surface of the frame portion 2 facing the vertical semiconductor device 5 is an inclined surface. The frame portion 2 is made of an insulating material such as PPS resin so that adjacent vertical semiconductor devices 5 do not conduct each other.

  Positioning portions 7 and 8 are provided on the base 1 by machining. The positioning part 7 is a notch provided in at least one corner of the base 1. The four positioning portions 8 are through holes provided in the base 1 and are fitted with the convex portions of the stage 9. However, the positioning part 8 is not limited to this, and the number is not limited to four.

  The base 1 is installed in a state where the back surface of the base 1 is in contact with the conductive stage 9. The conductive probe 10 contacts the upper surface electrode 4 of the vertical semiconductor device 5. The test apparatus 11 tests the vertical semiconductor device 5 through the base 1, the stage 9, and the probe 10 in a state where the vertical semiconductor device 5 is installed in the installation unit 6.

  Then, the test method using said semiconductor test jig is demonstrated. First, the vertical semiconductor device 5 is installed on the installation part 6 of the base 1 surrounded by the frame part 2 so as to slide the inclined surface of the frame part 2. At this time, the lower surface electrode 3 of the vertical semiconductor device 5 contacts the installation portion 6 of the base 1. The installation directions of the plurality of vertical semiconductor devices 5 are all made the same.

  Next, a transport tray on which a plurality of vertical semiconductor devices 5 are installed is installed on the stage 9. At this time, the direction of the transport tray is confirmed using the positioning unit 7.

  Next, the position of the upper surface electrode 4 of each vertical semiconductor device 5 is determined using the positioning unit 8, and the probe 10 is brought into contact with the upper surface electrode 4 of the vertical semiconductor device 5. Then, the vertical semiconductor device 5 is tested by the test apparatus 11.

  Then, the manufacturing method of said semiconductor test jig is demonstrated. First, a porous shape is formed on the surface of the base 1. Next, the frame portion 2 is formed by filling the porous shape of the base 1 with a crystalline insulating resin. Further, before forming the frame part 2, a medium dissolved in a supercritical medium (ethyl alcohol, carbon dioxide, water, etc.) may be applied as a pretreatment in the porous shape.

  As described above, the plurality of vertical semiconductor devices 5 can be collectively positioned by the transport tray including the base 1 and the frame portion 2. And since the base 1 is electroconductive, the base 1 itself can be functioned as a measurement electrode. Therefore, the test of the vertical semiconductor device 5 can be performed while being installed on the transfer tray. Therefore, workability at the time of testing a plurality of vertical semiconductor devices 5 can be improved, and the test time can be shortened.

  Moreover, since the side surface of the frame part 2 is an inclined surface, the vertical semiconductor device 5 can be easily installed. Further, since the base 1 has at least one positioning portion 7 or 8, the positioning time can be shortened and the positioning accuracy can be improved.

  Further, a porous shape is formed on the surface of the base 1, and the porous portion is filled with a crystalline insulating resin to form the frame portion 2. Thereby, the adhesive force of the base 1 and the frame part 2 increases. Along with this, shape changes such as deformation and peeling of the frame portion 2 can be suppressed in tests at high and low temperatures, so that the vertical semiconductor device 5 can be stably held.

Embodiment 2. FIG.
FIG. 3 is a cross-sectional view showing a semiconductor test jig according to Embodiment 2 of the present invention. For simplification of explanation, only the transport tray including the base 1 and the frame portion 2 is shown.

  When the vertical semiconductor device 5 is, for example, a semiconductor chip manufactured by dicing from a silicon wafer, foreign matters such as silicon scraps are likely to be generated from the end of the vertical semiconductor device 5. Further, when the vertical semiconductor device 5 is installed so as to slide the inclined surface of the frame portion 2, it is easy to cause the fall of the attached silicon dust or the like or new foreign matter such as silicon scrap due to friction or the like. Therefore, in the jig of FIG. 3, the groove portion 12 is provided in the base 1 in the vicinity of the inclined surface of the frame portion 2. Other configurations are the same as those of the first embodiment.

  By containing foreign matter in the groove 12 disposed below the end of the vertical semiconductor device 5, foreign matter is prevented from entering between the lower surface electrode 3 of the vertical semiconductor device 5 and the base 1, resulting in a defect. Generation can be reduced.

Embodiment 3 FIG.
FIG. 4 is a sectional view showing a semiconductor test jig according to Embodiment 3 of the present invention. For simplification of explanation, only the transport tray including the base 1 and the frame portion 2 is shown.

  The frame portion 2 includes a frame main body 13 whose side surface facing the vertical semiconductor device 5 is an inclined surface, and a base portion 14 that is provided under the frame main body 13 and has a wider width than the frame main body 13. The cross section of the frame part 2 is substantially L-shaped. A recess 15 is provided in the base 1. The base portion 14 of the frame portion 2 is installed in the concave portion 15 of the base 1. Other configurations are the same as those of the first embodiment.

  Thereby, since the contact area of the base 1 and the frame part 2 increases, both adhesive force increases. Along with this, shape changes such as deformation and peeling of the frame portion 2 can be suppressed in tests at high and low temperatures, so that the vertical semiconductor device 5 can be stably held. In addition, since the creepage distance with the adjacent vertical semiconductor device 5 can be increased to suppress discharge, the measurement accuracy can be improved.

Embodiment 4 FIG.
FIG. 5 is a cross-sectional view showing a semiconductor test jig according to Embodiment 4 of the present invention. For simplification of explanation, only the transport tray including the base 1 and the frame portion 2 is shown.

  A groove portion 16 is provided in the base portion 14 of the frame portion 2 in the vicinity of the inclined surface of the frame portion 2. Other configurations are the same as those of the second modification. Thereby, not only the effect similar to the modification 2 can be obtained but also the occurrence of defects can be reduced.

Embodiment 5 FIG.
FIG. 6 is a top view showing a semiconductor test jig according to Embodiment 5 of the present invention. FIG. 7 is a cross-sectional view taken along the line I-II in FIG. Only a configuration different from the first embodiment will be described.

  Openings 17 are respectively provided in the plurality of installation portions 6. The opening 17 exposes at least a part of the lower surface electrode 3 of the vertical semiconductor device 5 installed in the installation unit 6. A temperature sensor 18 such as a thermocouple is provided on the base 1.

  The conductive probe 19 contacts the lower surface electrode 3 of the vertical semiconductor device 5 installed in the installation unit 6 through the opening 17. The conductive probe 10 contacts the upper surface electrode 4 of the vertical semiconductor device 5. With the vertical semiconductor device 5 installed on the installation unit 6, the test apparatus 11 tests the vertical semiconductor device 5 via the probes 10 and 19.

  Since direct contact is made with the lower surface electrode 3 of the vertical semiconductor device 5 through the opening 17 penetrating the base 1, it is not necessary to consider the contact resistance between the base 1 and the vertical semiconductor device 5. Therefore, the test accuracy is improved as compared with the first embodiment.

  Further, by installing the temperature sensor 18 on the base 1, it is possible to obtain accurate test temperatures in the high temperature and low temperature tests. In addition, when positioning and installing a conveyance tray, although the output part of the temperature sensor 18 is connected to the test apparatus 11 and temperature information is obtained, it is not restricted to this. You may add the temperature sensor 18 to the structure of Embodiment 1-4.

DESCRIPTION OF SYMBOLS 1 Base 2 Frame part 3 Lower surface electrode 4 Upper surface electrode 5 Vertical semiconductor device 6 Installation part 7, 8 Positioning part 9 Stage 10 Probe (2nd probe)
DESCRIPTION OF SYMBOLS 11 Test apparatus 12, 16 Groove part 13 Frame main body 14 Base part 15 Recessed part 17 Opening part 18 Temperature sensor 19 Probe (1st probe)

Claims (12)

A semiconductor test jig for testing a plurality of vertical semiconductor devices having a bottom electrode and a top electrode,
A conductive base having a plurality of installation portions in which the plurality of vertical semiconductor devices are individually installed in a state where the lower surface electrodes are in contact with each other;
A semiconductor test jig comprising a grid-like insulating frame portion provided on the base and surrounding each of the plurality of installation portions. A conductive stage on which the base is installed with the back surface of the base in contact;
A conductive probe in contact with the upper surface electrode of the vertical semiconductor device;
The test apparatus further comprises a test apparatus for testing the vertical semiconductor device through the base, the stage, and the probe in a state where the vertical semiconductor device is installed in the installation section. The semiconductor test jig according to 1. A semiconductor test jig for testing a plurality of vertical semiconductor devices having a bottom electrode and a top electrode,
A plurality of installation parts in which the plurality of vertical semiconductor devices are individually installed, and at least a part of the lower surface electrode of the vertical semiconductor device provided in each of the plurality of installation parts and installed in the installation part A base having an opening for exposing
A semiconductor test jig comprising a grid-like insulating frame portion provided on the base and surrounding each of the plurality of installation portions. A conductive first probe that is in contact with the lower surface electrode of the vertical semiconductor device installed in the installation unit via the opening;
A conductive second probe in contact with the upper surface electrode of the vertical semiconductor device;
4. The apparatus according to claim 3, further comprising a test apparatus that tests the vertical semiconductor device through the first and second probes in a state where the vertical semiconductor device is installed in the installation section. The semiconductor test jig described in 1.   The semiconductor test jig according to claim 1, wherein a side surface of the frame portion facing the vertical semiconductor device is an inclined surface.   The semiconductor test jig according to claim 5, wherein a groove portion is provided in the base near the inclined surface of the frame portion. The frame part has a frame body whose side surface facing the vertical semiconductor device is an inclined surface, and a base part that is provided under the frame body and has a width wider than the frame body,
A recess is provided in the base,
The semiconductor test jig according to claim 1, wherein the base portion of the frame portion is installed in the concave portion of the base.   The semiconductor test jig according to claim 7, wherein a groove portion is provided in the base portion of the frame portion in the vicinity of the inclined surface of the frame portion.   The semiconductor test jig according to claim 1, wherein the base has at least one positioning portion.   The semiconductor test jig according to claim 1, further comprising a temperature sensor provided on the base. A method of manufacturing the semiconductor test jig according to claim 1,
Forming a porous shape on the surface of the base;
And a step of filling the porous shape of the base with a crystalline insulating resin to form the frame portion.   The method for manufacturing a semiconductor test jig according to claim 11, further comprising a step of applying a medium dissolved in a supercritical medium into the porous shape before forming the frame portion.

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