JP2013048525A - Constant current power supply unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a constant current power supply unit capable of immediately executing a rise in an output voltage V0 even when the quantity of light is reduced in starting a power supply and a duty ratio of a PWM signal is small.SOLUTION: An LED current IL running through an LED array 2 by a voltage drop across a resistor R2 is detected, and the voltage drop across the resistor R2 corresponding to the LED current IL and a second reference voltage Vref2 are compared by a comparator CP1. As a result, electric power is supplied from the primary side to the secondary side for a long supplement period Ts to a PWM signal until the LED current IL reaches the second reference voltage Vref2 in starting and, after the LED current IL reaches the second reference voltage Vref2, electric power is supplied to a load for a short supplement period Tn.

Description

  The present invention relates to a constant current power supply device that drives a load with a constant current, and more particularly to a constant current power supply device that drives a load with a pulse signal (hereinafter referred to as a PWM signal) based on PWM control (Pulse Width Modulation).

  An LED (light emitting diode) has a characteristic that the color tone changes in accordance with the magnitude of current. Therefore, the LED is generally driven with a constant current. When dimming control is performed, the LED is turned on / off with a PWM signal, and the light amount is adjusted by the duty ratio of the PWM signal.

  On the other hand, when a switching power supply is used as a constant current power supply device that drives a load with a constant current, it is necessary to detect the output current and perform feedback control. When the LED is driven by the PWM signal as described above, the LED repeats the lighting period and the extinguishing period. Naturally, no current flows through the LED during the extinguishing period, and the output current is fed back as zero. In this way, when the output current is fed back as zero, excessive power is supplied too much, so it is proposed to prevent excessive power supply by limiting the feedback control during the lighting period of the LED. (For example, refer to Patent Document 1).

  Patent Document 1 discloses a non-insulated step-up chopper type switching power supply, and an ON period in which an LED is turned on is an OFF period in which an operating current is supplied based on an LED operating current instruction value and the LED is turned off. The LED and the supply voltage are separated by an n-type MOS transistor, and the switching operation of the switching power supply as the LED supply voltage source is also turned off in synchronization. As described above, in Patent Document 1, power consumption during standby is reduced by turning on / off the switching power supply in synchronization with the PWM signal.

JP 2004-147435 A

FIG. 4 shows a circuit configuration diagram of a conventional constant current power supply device.
FIG. 5 is a waveform diagram for explaining the operation of the conventional constant current power supply device of FIG. 4, wherein (a) is a PWM signal, (b) is an output voltage of the power supply line, and (c) is an LED. The LED current flowing through the array 2, (d) indicates the LED drive signal, and (e) indicates the error signal FB.
Referring to FIG. 5, when a PWM signal is input at time t0, an LED drive signal synchronized with the PWM signal is also output, power is supplied from the primary side to the secondary side, and the output voltage rises. When the output voltage reaches the forward voltage drop VF at which the output voltage starts to flow through the LED array 2 at time t1, the LED current starts to flow. After the output voltage reaches a predetermined voltage at time t2, the LED array 2 is driven with a constant current.

However, in the prior art, since the switching power supply is turned on / off in synchronization with the PWM signal, the switching power supply is turned on only during the ON period in which the LED whose driving signal is at the H level is lit even in the startup sequence at the time of power activation. Thus, power is supplied from the primary side to the secondary side.
Therefore, as shown in FIG. 5, when the light amount is reduced at the time of starting the power supply and the duty ratio of the PWM signal is small, the switching power supply has a short ON period, so that the rise time of the output voltage is delayed and the prescribed LED There is a problem that it takes time until the LED emits light when current flows.
Note that, as disclosed in Patent Document 1, in a non-insulated step-up chopper type switching power supply, an output voltage is obtained by raising an input voltage, and therefore a delay in rise time is short due to a difference between the input voltage and the output voltage. However, in the switching power supply of the insulation type DC-DC converter, the output voltage always rises from 0V, so that the delay of the rise time of the output voltage becomes remarkable.

  Further, since the ON period of the switching power supply changes according to the duty ratio of the PWM signal, the output voltage rise time is not determined, and the time until the LED emits light due to the specified LED current flowing varies.

  The object of the present invention is to solve the problems of the prior art in view of the above problems, and to quickly raise the output voltage even when the light amount is reduced and the duty ratio of the PWM signal is small at power-on. An object of the present invention is to provide a constant current power supply device that can be used.

The constant current power supply device according to the present invention supplies power to the load in synchronization with an external pulse signal for driving the load on / off, and at a constant current in which the load is set using the power supplied to the secondary side. A constant current power supply device for driving,
Load current detection means for detecting the current flowing through the load;
An error signal generating means for comparing the load current detected by the load current detecting means with a preset second reference value and outputting a difference signal;
During startup, until the load current reaches the second reference value, the load is supplied with power based on the difference signal from the error signal generating means during the first replenishment period, regardless of the external pulse signal,
After the load current reaches the second reference value, power is supplied to the load based on the difference signal from the load current comparison means for a second replenishment period shorter than the first replenishment period regardless of the external pulse signal. A replenishment period generation unit is provided.
In the constant current power supply device of the present invention, the replenishment period is a predetermined period generated by using the end timing of the ON period of the pulse signal as a trigger.

It is a circuit block diagram which shows the circuit structure of embodiment of the constant current power supply device which concerns on this invention. 2 is a circuit configuration diagram showing an ON generation circuit 5. FIG. FIG. 2 is a waveform diagram illustrating signal waveforms and operation waveforms of respective units during the steady operation of FIG. 1. It is a circuit block diagram of the constant current power supply device of a prior art. It is a wave form diagram which shows the signal waveform of each part of FIG. 4, and an operation | movement waveform.

Next, embodiments of the present invention will be specifically described with reference to the drawings.

(Embodiment)
FIG. 1 is a circuit configuration diagram showing a circuit configuration of an embodiment of a constant current power supply device according to the present invention.
As shown in FIG. 1, the constant current power supply according to the first embodiment includes a rectifier circuit DB, a smoothing capacitor C1, a controller 1, an N-type MOSFET (hereinafter referred to as NMOS) Q1, and a resistor R1. , Transformer T, rectifier diode D1, smoothing capacitor C2, resistor R2, NMOS Q2, differential amplifier OTA, sample and hold circuit SH2, reference voltage Vref1, reference voltage Vref2, and shunt regulator Z1 , An ON generation circuit 5, a comparator CP, an OR circuit OR, an inverter INV1, a P-type MOSFET (hereinafter referred to as PMOS) Q3, a photo diode PCD and a photo transistor PCTR. A coupler, and is configured to drive the LED array 2 with a constant current Is.
In the constant current power supply device of the first embodiment, the same components as those of the conventional constant current power supply device shown in FIG.

  A commercial AC power supply AC is connected to the AC input terminals ACin1 and ACin2 of the rectifier circuit DB, and the AC voltage input from the commercial AC power supply AC is full-wave rectified and output from the rectifier circuit DB. The negative terminal of the rectifier output DB of the rectifier circuit DB is connected to the source terminal of an N-type MOSFET (hereinafter referred to as NMOS) Q1, which is a switching element, and the drain terminal of the NMOS Q1 is connected to the rectifier circuit via the primary winding P of the transformer T. It is connected to the rectified output positive terminal of DB. The gate terminal of the NMOS Q1 is connected to the primary side control circuit Cont1, and the NMOS Q1 is controlled to be turned on / off by the primary side control circuit Cont1. A DC power source rectified and smoothed by the rectifier circuit DB and the smoothing capacitor C1 is applied to the primary winding P of the transformer T by the on / off control of the NMOS Q1.

  The transformer T stores magnetic energy when the NMOS Q1 is turned on, and the magnetic energy stored when the NMOS Q1 is turned off is released as electric power from the secondary winding S of the transformer T. A smoothing capacitor C2 is connected between both terminals of the secondary winding S of the transformer T via a rectifier diode D1, and the electric power discharged from the secondary winding S of the transformer T is supplied to the rectifier diode D1 and the smoothing capacitor C2. Is rectified and smoothed. The line connected to the positive terminal of the smoothing capacitor C2 is a power supply line for the output voltage V0, and the line connected to the negative terminal of the smoothing capacitor C2 is a GND line connected to the ground terminal.

  An LED array 2 in which n (n is an arbitrary natural number) LEDs 21 to 2n are connected in series is used as a load to be driven that is dimmed from an external device. The LED array 2, the NMOS Q2, and the resistor R2 are connected in series between the power supply line and the GND line. The anode side terminal of the LED array 2 is connected to the power supply line, the drain terminal of the NMOS Q2 is connected to the cathode side terminal of the LED array 2, and the source terminal of the NMOS Q2 is connected to the GND line via the resistor R2.

The resistor R2, the differential amplifier OTA, the sample and hold circuit SH2, the reference voltage Vref1, the capacitor C3, and the shunt regulator Z1 function as an error signal generation circuit that generates an error signal FB corresponding to the output current IL flowing through the LED array 2. To do. The photocoupler including the photodiode PCD and the phototransistor PCTR functions as a feedback circuit that feeds back the error signal FB generated by the error signal generation circuit from the secondary side to the primary side controller 1.
Furthermore, the controller 1 functions as a control circuit that controls power supply from the primary side to the secondary side based on the error signal FB fed back via the feedback circuit. By inputting the error signal FB to the Fb terminal of the controller 1, the controller 1 starts supplying power from the primary side to the secondary side load, and the error signal FB received by the phototransistor PCTR disappears. The controller stops power supply from the primary side to the secondary side load.
Further, the ON generation circuit 5, the OR circuit OR, the inverters INV1, the PMOS Q3, the voltage comparator CP, the reference voltage Vref2, and the resistor R2 limit the period during which the error signal FB is fed back to the primary side. Functions as a power supply period limiting circuit.
Further, the voltage comparator CP functions as a circuit that switches the replenishment period generated by the ON generation circuit 5 between a long period ts and a short period tn. This is because, when the current IL flowing through the LED array 2 does not reach a predetermined current, the power supplied from the primary side to the secondary side is increased by switching the replenished period to a long period ts. Thus, the rise time of the output voltage VO at the start-up can be shortened. Therefore, the power supply period limiting circuit can be rephrased as a supplement period generation means.

As shown in FIG. 1, the connection point between the source terminal of the NMOS Q2 and the resistor R2 is connected to the inverting input terminal of the differential amplifier OTA, and the non-inverting input terminal of the differential amplifier OTA is connected to the positive terminal of the reference voltage Vref1. It is connected. The differential amplifier OTA converts the difference voltage between the reference voltage Vref1 input to the non-inverting input terminal and the voltage generated at the resistor R2 input to the inverting input terminal into a current and outputs the current. As a result, a current proportional to the output current IL flowing through the LED array 2 is output from the differential amplifier OTA.
The output terminal of the differential amplifier OTA is connected to the control terminal a of the shunt regulator Z1 via the sample and hold circuit SH2. The on / off terminal of the sample and hold circuit SH2 is connected to the PWM signal terminal from the outside together with the gate terminal of the NMOS Q2.

Further, the PWM signal terminal is connected to one input terminal of an OR circuit OR and is also connected to the ON generation circuit 5, and the other of the OR circuit OR is connected via the output of the ON generation circuit 5. Connected to the input terminal. The output terminal of the OR circuit OR is connected to the gate terminal of the PMOS Q3 via the inverter INV1.
Here, the on generation circuit 5 is a circuit for generating a replenishment period based on the down edge of the PWM signal, and is based on a logical sum of the ON period of the PWM signal and the replenishment period generated by the on generation circuit 5. The PMOS Q3 is on / off controlled.

  The anode of the shunt regulator Z1 is connected to the GND line, and the cathode of the shunt regulator Z1 is connected to the drain terminal of the PMOS Q3. The source terminal of the PMOS Q3 is connected to the cathode of the photodiode PCD constituting the photocoupler, and the anode of the photodiode PCD is connected to the external auxiliary power supply Vcc.

The connection point between the source terminal of the NMOS Q2 and the resistor R2 is connected to the inverting input terminal of the voltage comparator CP, and the non-inverting input terminal of the voltage comparator CP is connected to the positive terminal of the reference voltage Vref2. ing. The reference voltage Vref2 is set to a voltage lower than the reference voltage Vref1.
The voltage comparator CP compares the reference voltage Vref2 input to the non-inverting input terminal with the voltage generated at the resistor R2 input to the inverting input terminal, and the resistance R2 corresponding to the output current IL flowing through the LED array 2 is compared. Whether the voltage drop is equal to or higher than the reference voltage Vref2 is output to the D flip-flop logic circuit DFF of the ON generation circuit 5. This means that the voltage comparator CP outputs an L level signal when the value of the output current IL flowing through the LED array 2 reaches the reference voltage Vref2.
The on-generation circuit 5 switches the replenishment period from the long period ts to the short period tn according to the output voltage signal of the voltage comparator CP, but the replenishment period is shortened when the value of the output current IL reaches a current corresponding to the reference voltage Vref2. Switch to tn.

FIG. 2 is a circuit configuration diagram showing the ON generation circuit 5. The ON generation circuit 5 includes a D flip-flop logic circuit DFF, an NMOS Q4, an inverter INV2, a capacitor C3, resistors R3 and R4, and a PMOS Q5.
The gate of the NMOS Q4 is connected to the clock input terminal of the D flip-flop logic circuit DFF, and receives the PWM signal. The D input terminal of the D flip-flop logic circuit DFF is connected to the output terminal of the voltage comparator CP, and the output terminal Q is connected to the gate terminal of the PMOS Q5.
Further, the source terminal of the PMOS Q5 and one terminal of the resistor R3 are connected to another power source + Vcc, and a series circuit of the resistor Q4 connected to the drain terminal of the PMOS Q5 and the PMOS Q5 is connected in parallel to the resistor R3. The drain of the NMOS Q4 and the input terminal of the inverter INV2 are connected, the resistor R3 and the other terminal of the resistor R4 are connected to the connection point, and one terminal of the capacitor C3 is connected. The other terminal of the capacitor C3 is grounded to GND. The output terminal of the inverter INV2 becomes the output terminal of the on generation circuit 5 and is connected to one terminal of the OR circuit OR.

  The ON generation circuit 5 has a function of generating an ON signal at the down edge of the PWM signal and extending the pulse width of the input PWM signal. The detailed operation of the ON generation circuit 5 is as follows.

When the down edge of the pulse waveform of the PWM signal is input to the clock terminal of the D flip-flop logic circuit DFF, the D input terminal voltage level is output from the output terminal Q.
When the D input terminal voltage level is H level, the PMOS Q5 is turned off. Here, since the PWM signal is at the L level because of the down edge, the NMOS Q4 is in the OFF state, the capacitor C3 is charged with the power supply voltage + Vcc via the resistor R3, and the time constant between the capacitor C3 and the resistor R3 is reached. The H level signal is output from the output of the inverter INV2. That is, an H level signal is output from the output of the inverter INV2 during the time constant (ts) of the capacitor C3 and the resistor R3 from the down edge of the PWM signal.

When the D input terminal voltage level of the D flip-flop logic circuit DFF is L level, when the PWM signal down edge is input to the clock terminal of the D flip-flop logic circuit DFF, the output Q becomes L level and the PMOS Q5 is turned on. It becomes a state. The NMOS Q4 is turned off by the down edge of the PWM signal.
Accordingly, the resistor R4 is connected in parallel with the resistor R3, and starts charging the capacitor C3 with the combined resistance of the resistor R3 and the resistor R4 with the power supply voltage + Vcc. That is, from the down edge of the PWM signal, the time constant (t by the combined resistance of the capacitor C3, the resistor R3, and the resistor R4)
In the period n), an H level signal is output from the output of the inverter INV2.

Here, since the D input terminal of the D flip-flop logic circuit DFF is connected to the output of the voltage comparator CP, an H level signal is input when the LED current IL is less than a predetermined value. It will be.
In this case, since the Q output voltage of the D flip-flop logic circuit DFF is the same H level as the input when the PWM signal is at the down edge, the PMOS Q5 is turned off. That is, a time constant circuit is formed by the resistor 3 and the capacitor C4, and a long time constant (ts) is formed.
When the LED current IL is greater than or equal to a predetermined value, an L level signal is input, so that a time constant circuit is formed by the combined resistance of the resistor 3 and the resistor R4 and the capacitor C4. A constant (tn) is formed.
As described above, a long pulse (ts) and a short pulse (tn) are switched and output from the ON generation circuit 5 according to the output of the voltage comparator CP.

The output of the ON generation circuit 5 is connected to the other terminal of the OR circuit OR, and the PWM signal is input to one terminal of the OR circuit OR. Accordingly, since the output of the OR circuit OR becomes the OR of the signals at both terminals, the output is made by supplementing the period of the time constant (ts) or (tn) with respect to the pulse width of the PWM signal. .
That is, the time constant period (ts) or (tn) generated by the ON generation circuit 5 can be rephrased as a supplement period.

According to the above configuration, the sample and hold circuit SH2 is turned on during the H level period of the PWM signal, and a current corresponding to the difference voltage between the reference voltage Vref1 and the voltage generated in the resistor R2 is output from the differential amplifier OTA. An error signal voltage corresponding to the output current IL is input to the control terminal a of the shunt regulator Z1.
Further, since the PMOS Q3 is in the ON state, a current corresponding to the voltage of the control terminal a of the shunt regulator Z1, that is, a current IF corresponding to the output current IL flows through the photodiode PCD, and the current is used as the error signal FB. To the phototransistor PCTR. The PMOS Q3 is turned on because the output of the inverter INV1 is at the L level, that is, the OR circuit OR output is at the H level, and the error signal FB is fed back during the PWM signal on period, The logical sum with the replenishment period generated by the ON generation circuit 5 is limited.

  The collector terminal of the phototransistor PCTR is connected to the feedback input terminal Fb of the controller 1, and the emitter terminal of the phototransistor PCTR is connected to the ground terminal. In the phototransistor PCTR, when the error signal FB from the photodiode PCD is received, a current corresponding to the received error signal FB flows and is transmitted to the controller 1. As a result, the controller 1 generates a PWM signal having a pulse width corresponding to the error signal FB, thereby controlling the NMOS Q1 on / off to supply necessary power from the primary side to the secondary side load. The LED array 2 is configured to be driven with a constant current Is.

FIG. 3 shows a rising sequence when the constant current power supply device according to the first embodiment is started. (A) is a PWM signal for driving the NMOS Q2, and (a ′) is output from the on-generation circuit 5. (B) is an output current IL flowing through the LED array 2, (c) is an error signal FB fed back from the secondary side to the primary side, and (d) is both terminals of the smoothing capacitor C2. The output voltage VO, (e) between them indicates the output current IDP flowing through the NMOS Q1.
The PWM signal indicates a period in which dimming is set to be dark and the ON period of the PWM signal is relatively short.

As shown in FIG. 3A, when the PWM signal rises at time T1, the PMOS Q3 is turned on and the sample and hold circuit SH2 is turned on. As a result, the current corresponding to the output current IL is fed back as the error signal FB from the secondary side to the primary side. However, due to the time delay of the feedback control, as shown in FIG. Until the error signal FB is not fed back from the secondary side to the primary side.
The error signal FB is fed back from time T2, and the NMOS Q1 starts a switching operation via the primary side control circuit Cont1.
In addition, the PWM signal in FIG. 3A includes a period of the error signal FB from which the ON signal shown in FIG. 3A ′ is output from the ON generation circuit 5 and fed back from the secondary side to the primary side. Replenish for ts period of T4 period.

  When the switching operation of the NMOS Q1 is started, electric power is supplied from the primary side to the secondary side, electric charges are accumulated in the smoothing capacitor C2, and the output voltage VO rises as shown in FIG. When the output voltage VO that has risen reaches the forward drop voltage VF at which current starts to flow in the LED array 2 at time T5, as shown in FIG. 3C, the LED current IL starts to flow in synchronization with the PWM signal. The constant current Is is reached at T9.

Here, as shown in FIG. 3 (a ′), the pulse width Ts of the ON signal in the period from time T1 to T7 is longer than the pulse width Tn of the ON signal after time T8. . This is because the output current IL flowing through the LED array 2 during the period of time T5 to T6 does not reach the constant current Is, so that the output voltage VO is sharply raised regardless of the pulse width of the PWM signal.
This detailed operation is performed when the voltage drop of the resistor R2 for detecting the current flowing through the LED array 2 is compared with the reference voltage Vref2 by the voltage comparator CP, and the voltage drop of the resistor R2 is lower than the reference voltage Vref2. Outputs an H level signal to the on generation circuit 5 via the switch Std, and generates a long replenishment period Ts from the on generation circuit 5.
The reference voltage Vref2 is preferably set to a value around 90% of the reference voltage Vref1.

  At time T8, the output current IL flowing through the LED array 2 shown in FIG. 3B exceeds the current corresponding to the reference voltage Vref2, so the output of the voltage comparator CP becomes L level, and the switch Std is switched to the ts side. From the ON generation circuit 5 to generate a short replenishment period Tn. Accordingly, as shown in FIG. 3E, the switching operation period of the NMOS Q1 is shortened, but the output current IL reaches the constant current Is at time T9.

  In the steady operation state after time T9, the replenishment period Tn is generated from the ON generation circuit 5, and the error signal FB is output for the replenishment period Tn with respect to the pulse width of the PWM signal (time T13 to T14, etc.). By this replenishment period Tn operation, the output voltage VO during the OFF period of the PWM signal maintains a voltage slightly higher than the rated voltage.

The on-generation circuit 5 is a circuit that generates a one-shot pulse having a preset pulse width with respect to an input trigger, and as shown in FIG. An ON signal for generating a pulse having a preset pulse width (ts or tn) serving as a replenishment period is output using the end timing of the ON period as a trigger. As a result, the PMOS Q3 is turned on during the ON period of the PWM signal and the pulse width supplement period following the ON period of the PWM signal.
Therefore, as shown in FIG. 3A, when the PWM signal falls at time T9 or time T13, the sample and hold circuit SH2 is in the hold state, but the PMOS Q3 is in the period of the pulse width Tn, that is, from time T9 to time T9. The period of time T10 and times T13 to T14 is maintained in the ON state. During this period, since the sample and hold circuit SH2 is in the hold state, the voltage at the down edge of the PWM signal is maintained, and the error signal FB from the secondary side to the primary side as shown in FIG. Will be returned.
As a result, power is supplied to the smoothing capacitor C2 from the primary side. However, since the PWM signal falls and the LED array 2 is not driven, the supplied power is accumulated in the smoothing capacitor C2. .
As shown in FIG. 3 (d), the output voltage VO (solid line) is the rated voltage at the time T9 or the time T14 by the electric power stored in the smoothing capacitor C2 during the time T9 to T10 or the time T13 to T14. It is configured to be higher by ΔV than (dotted line).
In other words, during the period of the pulse width Tn following the on-time of the PWM signal, the power consumed to drive the LED array 2 during the period of time delay of feedback control at the next rise of the PWM signal is 1 in the smoothing capacitor C2. Supplied from the next side.
Therefore, in the on-time of the PWM signal, the output voltage VO is maintained at approximately the rated voltage and the output current IL is maintained at approximately the constant current Is, and the circuit configuration of the embodiment in which time delay occurs in feedback control. Even if it exists, there exists an effect that the LED array 2 which is load can be driven with the constant current Is.

  The power supplied to the smoothing capacitor C2 during the period of the pulse width Tn following the on-time of the PWM signal, and the power consumed for driving the LED array 2 during the time delay of feedback control at the rise of the PWM signal. Are substantially the same, but even if they are slightly different, the effect of preventing the output current IL from decreasing at the rise of the PWM signal can be obtained.

  As described above, according to the embodiment, the LED current IL flowing through the LED array 2 is detected by the voltage drop due to the resistor R1, and the second voltage drop of the resistor R1 corresponding to the LED current IL detected by the comparator CP1 is detected. By comparing with the reference voltage Vref2, a long replenishment period Ts from the ON generation circuit 5 is synchronized with the PWM signal until the voltage drop of the resistor R1 corresponding to the LED current IL reaches the second reference voltage Vref2 at the time of startup. And power is supplied from the primary side to the secondary side. With this configuration, the embodiment has an effect that the output voltage V0 can be quickly raised even when the amount of light is reduced when the power is turned on and the duty ratio of the PWM signal is small.

  In the above-described embodiment, an example has been described in which the LED array 2 in which n (n represents an arbitrary natural number) LEDs 21 to 2n are connected in series is driven as a load, but one LED may be used. . Further, the load is not limited to the LED as long as it can be driven with a direct current.

  Note that the present invention is not limited to the above-described embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention. In addition, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to a suitable number, position, shape, and the like in practicing the present invention. In each figure, the same numerals are given to the same component.

1 controller 2 LED array 21-2n LED
C1, C2 Smoothing capacitor C3 Capacitor CP Comparator DB Rectifier circuit INV1, INV2 Inverter circuit FF1 Flip-flop circuit D1 Rectifier diode OR OR circuit OTA Differential amplifier PCD Photodiode coupler PCTR Phototransistor coupler Q1, Q2, Q4 MOSFET (NMOS) )
Q3, Q5 MOSFET (PMOS)
R1, R2, R3, R4 Resistors SH1, SH2 Sample and hold circuit T Transformer Vref1 First reference voltage Vref2 Second reference voltage (second reference value)
Z1 shunt regulator DFF D flip-flop logic circuit

Claims (2)

A constant current power supply device that supplies power to a load in synchronization with an external pulse signal that drives the load on / off, and that drives the load with a set constant current using the supplied power,
Load current detecting means for detecting a current flowing through the load;
An error signal generating means for comparing the load current detected by the load current detecting means with a preset second reference value and outputting a difference signal;
At start-up, power is supplied to the load based on the difference signal from the error signal generator during the first replenishment period, regardless of the external pulse signal, until the load current reaches the second reference value. Supply
After the load current reaches the second reference value, based on the difference signal from the load current comparing means during a second replenishment period shorter than the first replenishment period regardless of the external pulse signal. A constant current power supply apparatus comprising a replenishment period generating means for supplying power to a load.   The constant current power supply device according to claim 1, wherein the replenishment period is a predetermined period generated using a timing of ending the ON period of the pulse signal as a trigger.

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