JP2007135277A - Switching power supply device - Google Patents

Switching power supply device Download PDF

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JP2007135277A
JP2007135277A JP2005324025A JP2005324025A JP2007135277A JP 2007135277 A JP2007135277 A JP 2007135277A JP 2005324025 A JP2005324025 A JP 2005324025A JP 2005324025 A JP2005324025 A JP 2005324025A JP 2007135277 A JP2007135277 A JP 2007135277A
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circuit
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output
current
voltage
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JP4862362B2 (en
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Kengo Koike
憲吾 小池
Mitsutaka Kawamoto
光隆 川本
Takashi Okada
敬 岡田
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption at standby without making the switching operation of a switching power supply device unstable. <P>SOLUTION: This switching power supply device is provided with: an output voltage adjustment circuit (33) that imparts a control signal to a control circuit (10) by receiving a detection signal of an output voltage detection circuit (8) at normal operation, shortens an on-period of a MOSFET (3) when an output voltage is high, and extends the on-period of the MOSFET (3) when the output voltage is low; a current adjustment circuit (41) that controls the impedance of a current that drives the output voltage adjustment circuit (33); and a standby-state detection circuit (34) that detects the standby operation of a load (7), and generates a standby signal. Since the impedance is increased by the current adjustment circuit (41) when the standby signal is generated by the standby-state detection circuit (34), not only the power consumption of the output voltage adjustment circuit (33) is reduced but also the power consumption of the switching power supply device itself is reduced by extending an off-period of the MOSFET (3) by using the output voltage adjustment circuit (33). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、電力変換効率の改善、特に待機時の消費電力を低減させるスイッチング電源装置に関する。   The present invention relates to a switching power supply device that improves power conversion efficiency, and in particular, reduces power consumption during standby.

スイッチング電源装置の電力変換効率の改善には、最近では特に待機時の消費電力の低減が重要になってきた。待機時にスイッチング周波数を低下させるか又は間欠動作(バースト動作)でスイッチングを行ってスイッチング損失を低減し、駆動電力を削減する目的に対して、待機時の検出、周波数の低下及び間欠動作の方法等に各種の方法が提案されている。   In order to improve the power conversion efficiency of a switching power supply device, it has recently become important to reduce power consumption during standby. For the purpose of reducing switching loss by reducing the switching frequency during standby, or switching by intermittent operation (burst operation), and reducing driving power, detection during standby, frequency reduction and intermittent operation methods, etc. Various methods have been proposed.

例えば、下記の特許文献1は、負荷待機時等の軽負荷時に消費電力を低減して変換効率を向上するスイッチング電源装置を示す。図4に示すように、このスイッチング電源装置は、交流電源(1a)に接続される整流平滑回路(1b)で構成された直流電源(1)と、1次巻線(2a)、2次巻線(2b)及び補助巻線(2c)を有するトランス(2)と、スイッチング素子としてのMOSFET(MOS型電界効果トランジスタ)(3)と、出力整流ダイオード(4)及び出力平滑コンデンサ(5)から成る整流平滑回路(6)と、負荷(7)の電圧VOを検出する出力電圧検出回路(8)と、MOSFET(3)をオン・オフ制御する制御回路(10)とを備えている。 For example, Patent Document 1 below shows a switching power supply device that reduces power consumption and improves conversion efficiency during light loads such as when waiting for a load. As shown in FIG. 4, this switching power supply device includes a DC power source (1) composed of a rectifying / smoothing circuit (1b) connected to an AC power source (1a), a primary winding (2a), and a secondary winding. Transformer (2) having line (2b) and auxiliary winding (2c), MOSFET (MOS field effect transistor) (3) as a switching element, output rectifier diode (4) and output smoothing capacitor (5) a rectifying and smoothing circuit (6) comprising, a load (7) the output voltage detection circuit (8) for detecting the voltage V O of, and a MOSFET (3) the on-off control to the control circuit (10).

トランス(2)の1次巻線(2a)及びMOSFET(3)は、直流電源(1)に対して直列に接続される。整流平滑回路(6)は、トランス(2)の2次巻線(2b)に接続され、電圧VOの直流電力を負荷(7)に供給する。補助巻線(2c)は、補助整流ダイオード(11)及び補助平滑コンデンサ(12)を介して制御回路(10)の電源端子(VCC)に接続される。制御回路(10)は、補助巻線(2c)から電源端子(VCC)に印加される電圧により駆動され且つ駆動回路(14)を介してMOSFET(3)のゲート端子にオン・オフ信号VGを付与する信号発生回路(13)と、出力電圧検出回路(8)の検出信号により信号発生回路(13)から出力されるオン・オフ信号VGのパルス幅を制御するオン期間制御回路(18)とを備えている。 The primary winding (2a) of the transformer (2) and the MOSFET (3) are connected in series to the DC power supply (1). The rectifying / smoothing circuit (6) is connected to the secondary winding (2b) of the transformer (2) and supplies DC power of voltage V O to the load (7). The auxiliary winding (2c) is connected to the power supply terminal (V CC ) of the control circuit (10) via the auxiliary rectifier diode (11) and the auxiliary smoothing capacitor (12). The control circuit (10) is driven by a voltage applied from the auxiliary winding (2c) to the power supply terminal (V CC ), and is connected to the gate terminal of the MOSFET (3) via the drive circuit (14). a signal generating circuit for applying a G (13), the output voltage detection circuit (8) of the detection signal by the on-period control circuit for controlling the pulse width of the on-off signal V G that are output from the signal generating circuit (13) ( 18).

オン期間制御回路(18)は、出力電圧検出回路(8)の検出電圧が目標値より低いとき、信号発生回路(13)から出力されるオン・オフ信号VGのパルス幅を延長し、逆に目標値より高いとき、信号発生回路(13)から出力されるオン・オフ信号VGのパルス幅を短縮して、トランス(2)の2次巻線(2b)から整流平滑回路(6)を介して負荷(7)に印加される直流出力電圧VOのレベルを一定に保持する。また、直流電源(1)の正側端子と制御回路(10)の電源端子(VCC)との間に接続された起動抵抗(16)を介して、起動時に直流電源(1)から流れる電流により補助平滑コンデンサ(12)を充電することにより、制御回路(10)の電源端子(VCC)に印加される電圧により制御回路(10)を起動し、MOSFET(3)のゲート端子にオン・オフ信号VGを付与する。 ON period control circuit (18), when the detection voltage of the output voltage detection circuit (8) is lower than the target value, by extending the pulse width of the on-off signal V G that are output from the signal generating circuit (13), opposite when higher than the target value, to shorten the pulse width of the on-off signal V G that are output from the signal generating circuit (13), the transformer rectifier smoothing circuit from the secondary winding of the (2) (2b) (6) The level of the DC output voltage V O applied to the load (7) via the is maintained constant. In addition, the current flowing from the DC power supply (1) during startup via the startup resistor (16) connected between the positive terminal of the DC power supply (1) and the power supply terminal (V CC ) of the control circuit (10) By charging the auxiliary smoothing capacitor (12) using the voltage, the control circuit (10) is activated by the voltage applied to the power supply terminal (V CC ) of the control circuit (10), and the gate terminal of the MOSFET (3) is turned on / off. An off signal V G is applied.

図5に示すように、制御回路(10)は、信号発生手段としての信号発生回路(13)と、負荷(7)が軽くなるにつれて出力電圧検出回路(8)から出力される検出信号により信号発生回路(13)の出力信号V4の周波数を低下させる周波数制御手段としての周波数制御回路(17)と、オン期間制御手段としてのオン期間制御回路(18)と、最小オン期間出力手段としての最小オン期間出力回路(19)と、Dフリップフロップで構成されるオン期間比較手段としてのオン期間比較回路(20)と、オン期間比較回路(20)の出力信号により周波数制御回路(17)を駆動状態又は停止状態に切り換える切換手段(26)と、駆動回路(14)とを備えている。 As shown in FIG. 5, the control circuit (10) has a signal generation circuit (13) as a signal generation means and a detection signal output from the output voltage detection circuit (8) as the load (7) becomes lighter. a frequency control circuit (17) as frequency control means for reducing the frequency of the output signal V 4 generation circuit (13), and on-period control circuit for an on period control means (18), as the minimum oN period output means A minimum on-period output circuit (19), an on-period comparison circuit (20) as an on-period comparison means constituted by a D flip-flop, and a frequency control circuit (17) by an output signal of the on-period comparison circuit (20) A switching means (26) for switching to a driving state or a stopping state and a driving circuit (14) are provided.

信号発生回路(13)は、電源端子(VCC)に印加される電圧により駆動され且つ出力電圧検出回路(8)が負荷(7)の低電圧VOを検出したとき長いパルス幅の出力信号V4を発生し、出力電圧検出回路(8)が負荷(7)の高電圧VOを検出したとき短いパルス幅の出力信号V4を発生する。オン期間制御回路(18)は、軽負荷より重い負荷(7)の状態のときに軽負荷時より信号発生回路(13)の出力信号V4の周波数が高い状態で出力電圧検出回路(8)の検出信号により信号発生回路(13)の出力信号V4のパルス幅を制御する。最小オン期間出力回路(19)は、軽負荷状態又は軽負荷より重い負荷状態に対応して第1の最小オン期間T1又は第2の最小オン期間T2のパルス信号V1,V2を出力する。オン期間比較回路(20)は、最小オン期間出力回路(19)から出力されるパルス信号V1,V2の第1の最小オン期間T1又は第2の最小オン期間T2と信号発生回路(13)の出力信号V4のオン期間とを比較して軽負荷状態か又は軽負荷より重い負荷状態かを判定する。駆動回路(14)は、最小オン期間出力回路(19)のパルス信号V1,V2と信号発生回路(13)の出力信号V4との論理和信号を出力するORゲート(14a)と、ORゲート(14a)の出力信号をオン・オフ信号VGとしてMOSFET(3)のゲート端子に付与するドライバ(14b)とを有する。最小オン期間出力回路(19)及びオン期間比較回路(20)は、信号発生回路(13)の出力信号V4のパルス幅により軽負荷状態か又は軽負荷より重い負荷状態かを判定する負荷状態判定手段を構成する。 The signal generation circuit (13) is driven by a voltage applied to the power supply terminal (V CC ), and an output signal having a long pulse width when the output voltage detection circuit (8) detects the low voltage V O of the load (7). When V 4 is generated and the output voltage detection circuit (8) detects the high voltage V O of the load (7), an output signal V 4 having a short pulse width is generated. ON period control circuit (18), the output voltage detection circuit in a state in which there is a high frequency of the output signal V 4 of the signal generator from the light load (13) when the state heavier load than the light load (7) (8) The pulse width of the output signal V 4 of the signal generation circuit 13 is controlled by the detection signal. The minimum on-period output circuit 19 outputs the pulse signals V 1 and V 2 of the first minimum on-period T 1 or the second minimum on-period T 2 corresponding to a light load state or a load state heavier than a light load. Output. ON period comparison circuit (20) the minimum ON period output circuit (19) a pulse signal V 1, the first minimum on period of the V 2 T 1 or second minimum ON period T 2 and a signal generating circuit which is output from the Compared with the ON period of the output signal V 4 in (13), it is determined whether the load is light or heavier than the light load. The drive circuit (14) includes an OR gate (14a) that outputs a logical sum signal of the pulse signals V 1 and V 2 of the minimum on-period output circuit (19) and the output signal V 4 of the signal generation circuit (13); and a driver (14b) to be applied to the gate terminal of the MOSFET (3) an output signal of the OR gate (14a) as the on-off signal V G. Minimum ON period output circuit (19) and the on-period comparison circuit (20), the signal generating circuit (13) load state determines heavier load conditions than either light load or light load by pulse width of the output signal V 4 of A determination unit is configured.

最小オン期間出力回路(19)は、第1のパルス発生回路(23)と、第2のパルス発生回路(24)と、最小オン期間切換回路(25)とを有する。第1のパルス発生回路(23)は、第1の最小オン期間T1を規定する第1のパルス信号V1を出力する。第2のパルス発生回路(24)は、第1の最小オン期間T1よりも短い第2の最小オン期間T2を規定する第2のパルス信号V2を出力する。最小オン期間切換回路(25)は、負荷(7)が軽負荷状態のときオン期間比較回路(20)の出力信号により第1のパルス信号V1を出力し、負荷(7)が軽負荷より重い負荷状態のときオン期間比較回路(20)の出力信号により第2のパルス信号V2を出力する。即ち、最小オン期間出力回路(19)は、信号発生回路(13)の出力信号V4のオン期間が第2の最小オン期間T2より短いときに第2の最小オン期間T2より長い第1の最小オン期間T1を有する第1のパルス信号V1を出力し、信号発生回路(13)の出力信号V4のオン期間が第1の最小オン期間T1より長いときに第1の最小オン期間T1より短い第2の最小オン期間T2を有する第2のパルス信号V2を出力するヒステリシス特性を有する。 The minimum on-period output circuit (19) includes a first pulse generation circuit (23), a second pulse generation circuit (24), and a minimum on-period switching circuit (25). The first pulse generation circuit (23) outputs a first pulse signal V 1 that defines a first minimum on-period T 1 . The second pulse generation circuit (24) outputs a second pulse signal V 2 that defines a second minimum on-period T 2 shorter than the first minimum on-period T 1 . When the load (7) is in a light load state, the minimum on-period switching circuit (25) outputs the first pulse signal V 1 by the output signal of the on-period comparison circuit (20), and the load (7) is less than the light load. outputting a second pulse signal V 2 by the output signal of the oN period comparison circuit (20) when the heavy load state. That is, the minimum ON period output circuit (19) is longer than the signal generating circuit (13) minimum ON period T 2 output ON period of the signal V 4 is a second when the second shorter than the minimum ON period T 2 of the of the outputting a first pulse signal V 1 having a minimum oN period T 1 of the 1, the oN period of the output signal V 4 of the signal generating circuit (13) is first when longer than the minimum on-period T 1 first It has a hysteresis characteristic that outputs a second pulse signal V 2 having a second minimum on-period T 2 shorter than the minimum on-period T 1 .

第1のパルス発生回路(23)から出力される第1のパルス信号V1の第1の最小オン期間T1は、軽負荷時にオン・オフ信号VGの周波数が可聴領域まで低下してもトランス(2)の磁歪音が聞こえない値に設定される。オン期間比較回路(20)は、信号発生回路(13)の出力信号V4のオン期間が最小オン期間出力回路(19)から出力される第2のパルス信号V2の第2の最小オン期間T2よりも短いとき、軽負荷状態を示す出力信号を最小オン期間出力回路(19)内の最小オン期間切換回路(25)に付与すると共に、切換手段(26)に付与して周波数制御回路(17)を駆動状態に切り換え、信号発生回路(13)の出力信号V4のオン期間が最小オン期間出力回路(19)から出力される第1のパルス信号V1の第1の最小オン期間T1よりも長いとき、軽負荷よりも重い負荷状態を示す出力信号を最小オン期間出力回路(19)内の最小オン期間切換回路(25)に付与すると共に切換手段(26)に付与して周波数制御回路(17)を停止状態にする。 First minimum ON period T 1 of the first pulse signal V 1 output from the first pulse generation circuit (23), even if the frequency of the on-off signal V G at light load is lowered to the audible region The value is set so that the magnetostrictive sound of the transformer (2) cannot be heard. ON period comparison circuit (20), second second minimum on period of the pulse signal V 2 that the ON period of the output signal V 4 is outputted from the minimum ON period output circuit (19) of the signal generating circuit (13) when less than T 2, together with imparting an output signal indicative of the light load state to minimize the minimum oN period switching circuit oN period output circuit (19) in (25), the frequency control circuit by applying to the switching means (26) (17) switching the drive state, the first first minimum oN period of the pulse signal V 1 to the oN period of the output signal V 4 of the signal generating circuit (13) is outputted from the minimum oN period output circuit (19) when longer than T 1, and applied to the switching means (26) while applying an output signal indicating a heavy load condition than the light load to the minimum oN period switching circuit of the minimum oN period output circuit (19) in (25) Stop the frequency control circuit (17).

図5に示すように、信号発生回路(13)は、発振周波数設定用コンデンサ(21)と、発振周波数設定用コンデンサ(21)の充電時間、即ち発振周波数設定用コンデンサ(21)の充電電圧VCFが最小値から最大値に達するまでの時間により決定される周波数のパルス信号を出力する発振手段としての発振回路(22)と、オン期間制御回路(18)の出力信号により発振回路(22)のパルス信号をPWM(パルス幅変調)制御して出力信号V4を発生するPWM制御回路(27)とを有する。PWM制御回路(27)は、発振回路(22)のパルス信号によりセット状態となり、オン期間制御回路(18)の出力信号によりリセット状態となるRS-FF(RSフリップフロップ)(27a)と、発振回路(22)のパルス信号とRS-FF(27a)の出力信号との論理和の反転信号V4を出力するNORゲート(27b)とから構成される。オン期間比較回路(20)は、クロック信号入力端子(CLK)に入力される最小オン期間出力回路(19)の出力信号V3の立ち下りに同期して制御信号入力端子(D)に入力される信号発生回路(13)の出力信号V4の電圧レベルの信号及びその反転信号を出力するDフリップフロップにより構成される。 As shown in FIG. 5, the signal generating circuit (13) includes the oscillation frequency setting capacitor (21) and the charging time of the oscillation frequency setting capacitor (21), that is, the charging voltage V of the oscillation frequency setting capacitor (21). An oscillation circuit (22) as an oscillating means for outputting a pulse signal having a frequency determined by the time until CF reaches the maximum value from the minimum value, and an oscillation circuit (22) by the output signal of the on-period control circuit (18) a pulse signal having a PWM (pulse width modulation) control to generate an output signal V 4 PWM control circuit (27). The PWM control circuit (27) is set by the pulse signal of the oscillation circuit (22), and is reset by the output signal of the ON period control circuit (18), and the RS-FF (RS flip-flop) (27a) constructed from a NOR gate (27b) for outputting an inverted signal V 4 of the logical sum of the pulse signal and the output signal of the RS-FF (27a) of the circuit (22). ON period comparison circuit (20) is inputted in synchronism with the falling of the output signal V 3 of the minimum ON period output circuit (19) which is input to the control signal input terminal (D) to the clock signal input terminal (CLK) And a D flip-flop that outputs a voltage level signal of the output signal V 4 of the signal generation circuit 13 and its inverted signal.

最小オン期間切換回路(25)は、第1のパルス発生回路(23)から出力される第1のパルス信号V1とオン期間比較回路(20)の反転信号出力端子の出力信号V5との論理積信号を出力する第1のANDゲート(25a)と、第2のパルス発生回路(24)から出力される第2のパルス信号V2とオン期間比較回路(20)の非反転信号出力端子の出力信号V6との論理積信号を出力する第2のANDゲート(25b)と、第1のANDゲート(25a)の出力信号と第2のANDゲート(25b)の出力信号との論理和信号V3を出力するORゲート(25c)とを備えている。周波数制御回路(17)は、出力電圧検出回路(8)の検出信号に比例する電流信号で信号発生回路(13)内の発振周波数設定用コンデンサ(21)の電荷を直接放電させるカレントミラー回路により構成される。周波数制御回路(17)の制御端子と接地端子との間に接続されたMOSFETで構成される切換手段(26)は、軽負荷状態のときにオン期間比較回路(20)の非反転出力端子から出力される低電圧(L)レベルの信号V6によりオフ状態となり周波数制御回路(17)を駆動状態に切り換え、軽負荷より重い負荷状態のときにオン期間比較回路(20)の非反転出力端子から出力される高電圧(H)レベルの信号V6によりオン状態となり周波数制御回路(17)を停止状態に切り換える。 The minimum on time switching circuit (25), the output signal V 5 of the inverted signal output terminal of the first pulse signal V 1 and the ON period comparison circuit output from the first pulse generator (23) (20) first aND gate (25a), the non-inverted signal output terminal of the second pulse signal V 2 and the oN period comparison circuit output from the second pulse generating circuit (24) (20) for outputting a logical product signal logical sum of the second aND gate for outputting a logical product signal (25b), and the output signal of the output signal of the first aND gate (25a) and a second aND gate (25b) between the output signal V 6 of and an OR gate (25c) for outputting a signal V 3. The frequency control circuit (17) is a current mirror circuit that directly discharges the charge of the oscillation frequency setting capacitor (21) in the signal generation circuit (13) with a current signal proportional to the detection signal of the output voltage detection circuit (8). Composed. The switching means (26) composed of a MOSFET connected between the control terminal of the frequency control circuit (17) and the ground terminal is connected to the non-inverting output terminal of the on-period comparison circuit (20) in a light load state. The low voltage (L) level signal V 6 is turned off to switch the frequency control circuit (17) to the driving state. When the load is heavier than a light load, the non-inverted output terminal of the on period comparison circuit (20) Is turned on by a high voltage (H) level signal V 6 output from the frequency control circuit 17 to switch the frequency control circuit 17 to a stopped state.

図4及び図5に示すスイッチング電源装置が動作する際に、直流電源(1)から起動抵抗(16)を介して制御回路(10)の電源端子(VCC)に電圧が印加されると、制御回路(10)が起動して信号発生回路(13)から高電圧(H)レベルのオン・オフ信号VGが出力され、MOSFET(3)が導通状態となる。これにより、トランス(2)の1次巻線(2a)に直流電源(1)の電圧Eが印加されると共に、補助巻線(2c)に電圧が発生する。補助巻線(2c)に発生した電圧は、補助整流ダイオード(11)及び補助平滑コンデンサ(12)を介して制御回路(10)の電源端子(VCC)に印加され、起動時以降は補助巻線(2c)に発生する電圧により制御回路(10)が駆動される。 When the switching power supply shown in FIGS. 4 and 5 is operated, if a voltage is applied from the DC power supply (1) to the power supply terminal (V CC ) of the control circuit (10) via the starting resistor (16), control circuit (10) is activated the signal generating circuit a high voltage from the (13) (H) level of the on-off signal V G is output, MOSFET (3) becomes conductive. As a result, the voltage E of the DC power source (1) is applied to the primary winding (2a) of the transformer (2), and a voltage is generated in the auxiliary winding (2c). The voltage generated in the auxiliary winding (2c) is applied to the power supply terminal (V CC ) of the control circuit (10) via the auxiliary rectifier diode (11) and the auxiliary smoothing capacitor (12). The control circuit (10) is driven by the voltage generated on the line (2c).

制御回路(10)内の信号発生回路(13)から駆動回路(14)を介してMOSFET(3)のゲート端子に高電圧(H)レベルのオン・オフ信号VGが付与され、MOSFET(3)がオン状態になると、直流電源(1)からトランス(2)の1次巻線(2a)及びMOSFET(3)を介して電流が流れ、トランス(2)にエネルギが蓄積される。このとき、整流平滑回路(6)を構成する出力整流ダイオード(4)に逆方向の電圧が印加されて非導通状態となるから、出力整流ダイオード(4)には電流が流れず、トランス(2)の2次巻線(2b)へのエネルギの伝達は行われない。これと同時に、トランス(2)の補助巻線(2c)に接続された補助整流ダイオード(11)にも逆方向の電圧が印加されて非導通状態となるので、MOSFET(3)のオン期間中は補助平滑コンデンサ(12)の充電電圧が制御回路(10)の電源端子(VCC)に印加される。 A high voltage (H) level of the on-off signal V G is applied through the drive circuit (14) from the signal generating circuit of the control circuit (10) in (13) to the gate terminal of the MOSFET (3), MOSFET (3 ) Is turned on, current flows from the DC power source (1) through the primary winding (2a) of the transformer (2) and the MOSFET (3), and energy is stored in the transformer (2). At this time, since a reverse voltage is applied to the output rectifying diode (4) constituting the rectifying / smoothing circuit (6) and a non-conducting state is established, no current flows through the output rectifying diode (4), and the transformer (2 ) Is not transmitted to the secondary winding (2b). At the same time, a reverse voltage is applied to the auxiliary rectifier diode (11) connected to the auxiliary winding (2c) of the transformer (2), and the non-conducting state is applied. The charging voltage of the auxiliary smoothing capacitor (12) is applied to the power supply terminal (V CC ) of the control circuit (10).

次に、制御回路(10)からMOSFET(3)のゲート端子に付与されるオン・オフ信号VGが高電圧(H)レベルから低電圧(L)レベルとなり、MOSFET(3)がオンからオフになると、トランス(2)の2次巻線(2b)から整流平滑回路(6)の出力整流ダイオード(4)に順方向の電圧が印加されて導通状態となるので、トランス(2)に蓄積されたエネルギが2次巻線(2b)から整流平滑回路(6)を介して負荷(7)に供給され、トランス(2)がリセットされる。これと同時に、トランス(2)の補助巻線(2c)に接続された補助整流ダイオード(11)にも順方向の電圧が印加されて導通状態となるので、MOSFET(3)のオフ期間中は補助巻線(2c)から補助整流ダイオード(11)及び補助平滑コンデンサ(12)を介して制御回路(10)の電源端子(VCC)に電圧が印加される。そして、所定の時間が経過すると、制御回路(10)内の信号発生回路(13)から駆動回路(14)を介してMOSFET(3)のゲート端子に高電圧(H)レベルのオン・オフ信号VGが付与され、再びMOSFET(3)がオン状態となる。 Next, the on / off signal V G applied from the control circuit (10) to the gate terminal of the MOSFET (3) changes from the high voltage (H) level to the low voltage (L) level, and the MOSFET (3) turns from on to off. Then, a forward voltage is applied from the secondary winding (2b) of the transformer (2) to the output rectifier diode (4) of the rectifying / smoothing circuit (6) and becomes conductive, so that it accumulates in the transformer (2). The energy thus supplied is supplied from the secondary winding (2b) to the load (7) via the rectifying and smoothing circuit (6), and the transformer (2) is reset. At the same time, since a forward voltage is applied to the auxiliary rectifier diode (11) connected to the auxiliary winding (2c) of the transformer (2) to be in a conductive state, during the off period of the MOSFET (3) A voltage is applied from the auxiliary winding (2c) to the power supply terminal (V CC ) of the control circuit (10) through the auxiliary rectifier diode (11) and the auxiliary smoothing capacitor (12). When a predetermined time elapses, a high voltage (H) level on / off signal is sent from the signal generation circuit (13) in the control circuit (10) to the gate terminal of the MOSFET (3) via the drive circuit (14). V G is applied, and the MOSFET (3) is turned on again.

負荷(7)のインピーダンスが高い軽負荷状態のときは、出力電圧検出回路(8)の検出電圧が目標値より高くなるので、制御回路(10)内のオン期間制御回路(18)により信号発生回路(13)から駆動回路(14)を介して出力されるオン・オフ信号VGのパルス幅が狭くなるように制御され、MOSFET(3)のオン期間が短くなる。逆に、負荷(7)のインピーダンスが低い重負荷状態のときは、出力電圧検出回路(8)の検出電圧が目標値より低くなるので、制御回路(10)内のオン期間制御回路(18)により信号発生回路(13)から駆動回路(14)を介して出力されるオン・オフ信号VGのパルス幅が広くなるように制御され、MOSFET(3)のオン期間が長くなる。 When the load (7) has a high impedance and a light load, the output voltage detection circuit (8) detection voltage is higher than the target value, so the on-period control circuit (18) in the control circuit (10) generates a signal. It is controlled so that the pulse width of the on-off signal V G which is output through the circuit (13) from the drive circuit (14) is narrowed, the oN period of the MOSFET (3) is shortened. Conversely, when the load (7) impedance is low and the load is heavy, the detection voltage of the output voltage detection circuit (8) is lower than the target value, so the on-period control circuit (18) in the control circuit (10) the pulse width of the signal generating circuit (13) on-off signal is output via the drive circuit (14) from the V G is controlled to become wide, the oN period of the MOSFET (3) is prolonged.

負荷(7)が軽負荷より重い負荷状態(図6に示す時刻t1〜t7)のときは、図6(B)に示す信号発生回路(13)の出力信号V4のパルス幅は、図6(C)に示す最小オン期間出力回路(19)の出力信号V3のパルス幅よりも長いため、駆動回路(14)からMOSFET(3)に付与されるオン・オフ信号VGは、図6(H)に示すように、図6(C)に示す最小オン期間出力回路(19)の出力信号V3よりもパルス幅の長い図6(B)に示す信号発生回路(13)の出力信号V4と略同様の波形となる。一方、図6(F)に示す高電圧(H)レベルの信号V6がオン期間比較回路(20)の非反転出力端子から出力され、図6(G)に示す低電圧(L)レベルの信号V5が反転出力端子から出力されるので、図6(D)に示す第2のパルス発生回路(24)の第2のパルス信号V2が、最小オン期間出力回路(19)の最小オン期間切換回路(25)から図6(C)に示す出力信号V3として出力される。 When the load (7) is heavier load condition than the light load (time t 1 ~t 7 shown in FIG. 6), the pulse width of the signal generating circuit (13) of the output signal V 4 shown in FIG. 6 (B), longer than the pulse width of the output signal V 3 of the minimum oN period output circuit (19) shown in FIG. 6 (C), the on-off signal V G applied from the drive circuit (14) to the MOSFET (3) is, as shown in FIG. 6 (H), the signal generating circuit shown in long Figure 6 pulse width than the output signal V 3 of the minimum oN period output circuit (19) shown in FIG. 6 (C) (B) (13) The waveform is substantially the same as that of the output signal V 4 . On the other hand, the high voltage (H) level signal V 6 shown in FIG. 6 (F) is output from the non-inverting output terminal of the on period comparison circuit (20), and the low voltage (L) level shown in FIG. 6 (G). Since the signal V 5 is output from the inverting output terminal, the second pulse signal V 2 of the second pulse generation circuit (24) shown in FIG. 6 (D) becomes the minimum ON period output circuit (19) minimum ON. output period switching circuit from (25) as an output signal V 3 shown in FIG. 6 (C).

また、オン期間比較回路(20)の非反転出力端子の出力信号V6が高電圧(H)レベルのため、切換手段(26)がオン状態となり、周波数制御回路(17)は、駆動されないため、発振周波数設定用コンデンサ(21)の充電時間、即ち充電電圧VCFが最小値から最大値に達するまでの時間が一定となる。したがって、信号発生回路(13)の発振周波数設定用コンデンサ(21)の電圧VCFの周波数が図6(A)に示すように一定となり、オン期間制御回路(18)の出力信号により信号発生回路(13)内のPWM制御回路(27)から出力される信号V4のパルス幅が、図6(B)に示すように制御される。 Further, since the output signal V 6 of the non-inverting output terminal of the on period comparison circuit (20) is at a high voltage (H) level, the switching means (26) is turned on and the frequency control circuit (17) is not driven. The charging time of the oscillation frequency setting capacitor (21), that is, the time until the charging voltage VCF reaches the maximum value is constant. Therefore, the frequency of the voltage V CF of the oscillation frequency setting capacitor (21) of the signal generation circuit (13) becomes constant as shown in FIG. 6 (A), and the signal generation circuit is determined by the output signal of the ON period control circuit (18). The pulse width of the signal V 4 output from the PWM control circuit (27) in (13) is controlled as shown in FIG. 6 (B).

時刻t7にて負荷(7)が軽負荷状態になると、信号発生回路(13)の図6(B)に示す出力信号V4のパルス幅が最小オン期間出力回路(19)の出力信号V3の図6(C)に示すパルス幅よりも短くなるため、駆動回路(14)からMOSFET(3)に付与される図6(H)に示すオン・オフ信号VGは、信号発生回路(13)の図6(B)に示す出力信号V4よりパルス幅の長い最小オン期間出力回路(19)の図6(C)に示す出力信号V3と略同様の波形となる。一方、時刻t7から第2の最小オン期間T2が経過した後の時刻t8に、オン期間比較回路(20)は、第2のパルス発生回路(24)の第2のパルス信号V2のパルス幅より短い信号発生回路(13)の出力信号V4を検出するので、オン期間比較回路(20)の出力信号V5及びV6は、それぞれ図6(G)及び図6(F)に示すように低電圧(L)レベルから高電圧(H)レベル及び高電圧(H)レベルから低電圧(L)レベルに変換される。 When the load at time t 7 (7) is a light load state, the output signal V of the signal generating circuit (13) FIG. 6 (B) the pulse width of the output signal V 4 shown in the minimum ON period output circuit (19) since shorter than the pulse width shown in 3 of FIG. 6 (C), the on-off signal V G shown in FIG. 6 (H) applied from the drive circuit (14) to the MOSFET (3), the signal generating circuit ( The waveform is substantially the same as that of the output signal V 3 shown in FIG. 6C of the minimum on-period output circuit 19 having a longer pulse width than the output signal V 4 shown in FIG. On the other hand, at the time t 8 after the second minimum on-period T 2 has elapsed from the time t 7 , the on-period comparison circuit (20) outputs the second pulse signal V 2 of the second pulse generation circuit (24). Since the output signal V 4 of the signal generation circuit 13 shorter than the pulse width of the output signal V 4 is detected, the output signals V 5 and V 6 of the on-period comparison circuit 20 are respectively shown in FIGS. 6G and 6F. As shown in FIG. 4, the low voltage (L) level is converted to the high voltage (H) level, and the high voltage (H) level is converted to the low voltage (L) level.

このため、時刻t8以降には、図6(E)に示す第1のパルス発生回路(23)の第1のパルス信号V1は、図6(C)に示す出力信号V3として最小オン期間切換回路(25)から出力されると同時に、オン期間比較回路(20)の出力信号V6が低電圧(L)レベルのため、切換手段(26)がオンからオフとなり、周波数制御回路(17)が駆動される。これにより、出力電圧検出回路(8)の検出信号に比例する電流信号により発振周波数設定用コンデンサ(21)の電荷が直接放電されるので、負荷(7)が軽くなる程、発振周波数設定用コンデンサ(21)の充電時間が延長される。このように、時刻t7以降に、負荷(7)が軽くなる程、図6(A)に示すように、発振周波数設定用コンデンサ(21)の電圧VCFが低下するため、図6(B)に示すように、PWM制御回路(27)の出力信号V4の周波数が制御される。 For this reason, after time t 8 , the first pulse signal V 1 of the first pulse generation circuit (23) shown in FIG. 6 (E) is minimum on as the output signal V 3 shown in FIG. 6 (C). simultaneously output from the period switching circuit (25), the output signal V 6 of the oN period comparison circuit (20) is a low voltage (L) level, the switching means (26) is turned off from on, the frequency control circuit ( 17) is driven. As a result, since the electric charge of the oscillation frequency setting capacitor (21) is directly discharged by the current signal proportional to the detection signal of the output voltage detection circuit (8), the lighter the load (7), the lower the oscillation frequency setting capacitor. (21) Charging time is extended. Thus, after time t 7, the load (7) enough to become lighter, as shown in FIG. 6 (A), since the voltage V CF oscillation frequency setting capacitor (21) is reduced, FIG. 6 (B ), The frequency of the output signal V 4 of the PWM control circuit (27) is controlled.

その後、時刻t12にて負荷(7)が軽負荷状態からある程度重くなると、信号発生回路(13)の図6(B)に示す出力信号V4のパルス幅が最小オン期間出力回路(19)の図6(C)に示す出力信号V3のパルス幅よりも長くなるため、駆動回路(14)からMOSFET(3)に付与される図6(H)に示すオン・オフ信号VGのパルス幅は、図6(C)に示す最小オン期間出力回路(19)の出力信号V3よりも長くなり、信号発生回路(13)の図6(B)に示す出力信号V4と略同様の波形となる。一方、時刻t12から第1の最小オン期間T1が経過した時刻t14に、オン期間比較回路(20)は、第1のパルス発生回路(23)の第1のパルス信号V1のパルス幅より長い信号発生回路(13)の出力信号V4を検出するので、オン期間比較回路(20)の出力信号V5及びV6は、それぞれ図6(G)及び図6(F)に示すように、高電圧(H)レベルから低電圧(L)レベル及び低電圧(L)レベルから高電圧(H)レベルになる。 Thereafter, when the load at time t 12 (7) is made somewhat heavier a light load state, the signal generating circuit (13) FIG. 6 (B) are shown the output signal V 4 of the pulse width is the minimum ON period output circuit (19) 6 for longer than the pulse width of the output signal V 3 of (C), the pulse of FIG. 6 (H) to indicate on-off signal V G applied to the MOSFET (3) from the drive circuit (14) The width is longer than the output signal V 3 of the minimum on-period output circuit (19) shown in FIG. 6 (C) and is substantially the same as the output signal V 4 shown in FIG. 6 (B) of the signal generation circuit (13). It becomes a waveform. On the other hand, the time t 14 from the time t 12 minimum ON period T 1 first has elapsed, the ON period comparison circuit (20), the first of the first pulse signal V 1 of the pulse of the pulse generating circuit (23) Since the output signal V 4 of the signal generation circuit 13 longer than the width is detected, the output signals V 5 and V 6 of the on period comparison circuit 20 are shown in FIGS. 6G and 6F, respectively. As described above, the high voltage (H) level changes to the low voltage (L) level, and the low voltage (L) level changes to the high voltage (H) level.

このため、時刻t14以降に、第2のパルス発生回路(24)の図6(D)に示す第2のパルス信号V2は、最小オン期間切換回路(25)から図6(C)に示す出力信号V3として出力される。また、オン期間比較回路(20)の出力信号V6は、時刻t14以降に高電圧(H)レベルとなるため、切換手段(26)がオフからオン状態となり、周波数制御回路(17)の動作が停止する。このように、時刻t12以降に発振周波数設定用コンデンサ(21)の図6(A)に示す電圧VCFの周波数が一定になるため、オン期間制御回路(18)の出力信号によりPWM制御回路(27)からの出力信号V4のパルス幅は、図6(B)に示すように制御される。 Therefore, after time t 14 , the second pulse signal V 2 shown in FIG. 6D of the second pulse generation circuit 24 is transferred from the minimum ON period switching circuit 25 to FIG. 6C. Is output as the output signal V 3 shown. The output signal V 6 of the ON period comparison circuit (20), because after time t 14 becomes a high voltage (H) level, the switching means (26) is turned on from off, the frequency control circuit (17) Operation stops. Since the frequency of the voltage V CF shown in FIG. 6 (A) of the capacitor oscillation frequency set to the time t 12 after (21) is constant, PWM control circuit by an output signal of the on-period control circuit (18) The pulse width of the output signal V 4 from (27) is controlled as shown in FIG. 6 (B).

負荷(7)がある程度重い状態となる期間t1〜t7及び時刻t12以降は、周波数制御回路(17)が停止状態となるため、PWM制御回路(27)の図6(B)に示す出力信号V4のパルス幅は、オン期間制御回路(18)の出力信号により制御される。また、負荷(7)が軽負荷となる期間t7〜t12では、周波数制御回路(17)は、出力電圧検出回路(8)の検出信号により信号発生回路(13)の出力信号V4の周波数を低下させるが、同時に出力電圧検出回路(8)の検出信号がオン期間制御回路(18)にも入力されるため、信号発生回路(13)の出力信号V4のパルス幅もオン期間制御回路(18)の出力信号により図6(B)に示すように制御される。但し、軽負荷時に、第1の最小オン期間T1を有する第1のパルス信号V1が第1のパルス発生回路(23)から出力されて、最小オン期間出力回路(19)の出力信号V3としてORゲート(14a)に信号発生回路(13)の出力信号V4と共に入力されるため、MOSFET(3)のゲート端子に付与される図6(H)に示すオン・オフ信号VGのオン期間は、第1の最小オン期間T1に等しくなる。このため、必要以上に長い期間、強制的にMOSFET(3)がオン状態に維持されるので、出力電圧検出回路(8)の検出信号の帰還量が増加して、信号発生回路(13)の図6(B)に示す出力信号V4のパルス幅は、オン期間制御から周波数制御に制御方式が切り換わる直前の第2の最小オン期間T2よりも更に短くなる。 Load (7) the period t 1 ~t 7 and time t 12 after serving as the somewhat heavier state, the frequency control circuit (17) is stopped, shown in Figure of the PWM control circuit (27) 6 (B) The pulse width of the output signal V 4 is controlled by the output signal of the ON period control circuit (18). The load during the period t 7 ~t 12 (7) is a light load, frequency control circuit (17), the signal generating circuit by the detection signal of the output voltage detection circuit (8) of the output signal V 4 (13) While lowering the frequency, the detection signal of the output voltage detection circuit (8) is also input to the on-period control circuit (18) at the same time, the pulse width of the output signal V 4 is also on-period control signal generating circuit (13) Control is performed as shown in FIG. 6B by the output signal of the circuit (18). However, when the load is light, the first pulse signal V 1 having the first minimum on-period T 1 is output from the first pulse generation circuit (23), and the output signal V of the minimum on-period output circuit (19). to be input together with the output signal V 4 of the signal generating circuit to the OR gate (14a) (13) as 3, MOSFET on and off signal V G shown in FIG. 6 (H) applied to the gate terminal of the (3) The on period is equal to the first minimum on period T 1 . For this reason, the MOSFET (3) is forcibly maintained in an on state for a longer period than necessary, so that the feedback amount of the detection signal of the output voltage detection circuit (8) increases, and the signal generation circuit (13) The pulse width of the output signal V 4 shown in FIG. 6B is further shorter than the second minimum on-period T 2 immediately before the control method is switched from on-period control to frequency control.

このように、負荷待機時等の軽負荷時にオン・オフ信号VGのオン期間が第1の最小オン期間T1以下に短縮されないようにオン・オフ信号VGのオン期間を一定としてオン・オフ信号VGの周波数を低下させるので、MOSFET(3)のスイッチング損失を減少して、変換効率を向上できる。また、負荷(7)がある程度重くなると、最小オン期間出力回路(19)の出力信号V3が第1の最小オン期間T1より短い第2の最小オン期間T2を有する第2のパルス信号V2に切り換えられ、軽負荷時よりもオン・オフ信号VGの周波数が高い状態でオン期間が制御されるので、トランス(2)等を大型化せずに通常負荷時から重負荷時まで高い変換効率を実現できる。また、最小オン期間出力回路(19)は、ヒステリシス特性を有するので、制御回路(10)からMOSFET(3)のゲート端子に付与するオン・オフ信号VGの周波数制御とオン期間制御とを円滑に切り換えることができる。更に、軽負荷時にオン・オフ信号VGの周波数が可聴領域まで低下してもトランス(2)に流れる電流ピークが抑えられるので、トランス(2)の磁歪音等の騒音を防止できる。 Thus, on the ON period of the light load to the on-off signal V G is the ON period of the on-off signal V G so as not to be shortened to a first minimum on period T 1 of the following isochronous load stand as constant because lowering the frequency of the off signal V G, and reducing the switching losses of the MOSFET (3), it can improve the conversion efficiency. Further, when the load (7) is somewhat heavier, a second pulse signal having a minimum ON period output circuit (19) the minimum ON period T 2 output signal V 3 is a second shorter than the minimum ON period T 1 first of It is switched to V 2, the on-period is in a state of high frequency of the light load on-off signal V G than is controlled, to heavy load from the normal load without upsizing the transformer (2), etc. High conversion efficiency can be realized. The minimum ON period output circuit (19), because it has a hysteresis characteristic, the control circuit (10) facilitates the frequency control and the on period control of the on-off signal V G to be applied to the gate terminal of the MOSFET (3) from Can be switched to. Furthermore, since the current peaks flowing through the transformer (2) even at light loads the frequency of the on-off signal V G decreases to audible range can be suppressed, thereby preventing noise etc. magnetostrictive sound transformer (2).

ところで、特許文献1に示されるスイッチング電源装置では、制御回路(10)を構成するコントローラICも、バイポーラプロセスからC-MOSプロセスが主流になり、消費電流が大幅に低減された。20mA程度の電流を消費するバイポーラICの代わりに、C-MOS型ICを使用すると1mA程度になる。また、コントローラICを15Vで駆動すると、バイポーラICでは0.3W程度の電力を消費するのに対し、最近のC-MOS型ICでは0.015W程度まで低減される。   By the way, in the switching power supply device shown in Patent Document 1, the controller IC constituting the control circuit (10) has been changed from the bipolar process to the C-MOS process, and the current consumption has been greatly reduced. If a C-MOS type IC is used instead of a bipolar IC that consumes a current of about 20 mA, the current becomes about 1 mA. Further, when the controller IC is driven at 15 V, the power consumption of about 0.3 W is consumed in the bipolar IC, whereas it is reduced to about 0.015 W in the recent C-MOS type IC.

殆どの方式の絶縁型スイッチング電源装置では、出力電圧を基準電圧と比較して得られる出力電圧検出回路からの誤差信号をフォトカプラを介して1次側に伝達し、抵抗で制御電圧に変換して制御回路に伝達する。この方法では、負荷が変動しても安定に動作するため、例えば、最大負荷時にフォトカプラの受光部に流れる電流を0.1mAに設定すると、待機時に1mA程度の電流が制御回路に流れる。このとき、制御回路を15Vで駆動すると、待機時に0.015Wの電力が消費される。これは制御回路に使用するコントローラICの消費電力に匹敵する。同様に、フォトカプラの発光部でも待機時に最大電流が流れる。フォトカプラの電流伝達率及びスイッチング電源装置の変換効率等を考慮すると、消費電力は更に増大する。   In most types of isolated switching power supply devices, an error signal from an output voltage detection circuit obtained by comparing an output voltage with a reference voltage is transmitted to the primary side via a photocoupler and converted into a control voltage by a resistor. To the control circuit. Since this method operates stably even when the load fluctuates, for example, if the current flowing through the light receiving portion of the photocoupler at the maximum load is set to 0.1 mA, a current of about 1 mA flows through the control circuit during standby. At this time, if the control circuit is driven at 15 V, 0.015 W of power is consumed during standby. This is comparable to the power consumption of the controller IC used for the control circuit. Similarly, the maximum current flows in the light emitting portion of the photocoupler during standby. Considering the current transfer rate of the photocoupler and the conversion efficiency of the switching power supply, the power consumption further increases.

例えば、視聴時に80〜100W程度の消費電力となる21インチクラスのカラーテレビでも、0.1〜0.2Wまで低下する待機時の低消費電力が要求される。待機時に負荷で消費される電力は、0.01〜0.05W程度であるから、フォトカプラの受光部と抵抗とで消費される電力は、負荷で消費される電力に匹敵する。   For example, even a 21-inch color television that consumes about 80 to 100 W during viewing requires low power consumption during standby, which is reduced to 0.1 to 0.2 W. Since the power consumed by the load during standby is about 0.01 to 0.05 W, the power consumed by the light receiving unit and the resistor of the photocoupler is comparable to the power consumed by the load.

特許第3525436号公報Japanese Patent No. 3525436

ところで、待機時の消費電力0.1〜0.2Wを実現するには、スイッチング電源装置の待機時にスイッチング周波数を低下させるか又はバースト動作させても1つのスイッチング電源装置では困難であり、待機時用に別のスイッチング電源装置を備える必要があった。また、フォトカプラ及び抵抗で消費される電力は、待機時に要求される消費電力に対して無視できないレベルに達する。この消費電力を低減するため、フォトカプラに流れる電流を減少させると、出力電圧の検出から制御回路の動作に至る制御系を高い利得で動作させることになるため、最大負荷時に流れる電流が少なくなり、スイッチング動作が不安定になる問題が生ずる。   By the way, in order to realize standby power consumption of 0.1 to 0.2 W, it is difficult to use one switching power supply device even if the switching frequency is lowered or the burst operation is performed at the standby time of the switching power supply device. Therefore, it was necessary to provide another switching power supply device. Further, the power consumed by the photocoupler and the resistor reaches a level that cannot be ignored with respect to the power consumption required during standby. In order to reduce this power consumption, if the current flowing through the photocoupler is reduced, the control system from the detection of the output voltage to the operation of the control circuit is operated with a high gain, so that the current flowing at the maximum load is reduced. This causes a problem that the switching operation becomes unstable.

そこで、本発明は、スイッチング動作を不安定にさせずに、待機時の消費電力を低減できるスイッチング電源装置を提供することを目的とする。   Therefore, an object of the present invention is to provide a switching power supply device that can reduce power consumption during standby without making the switching operation unstable.

本発明のスイッチング電源装置は、直流電源(1)と、直流電源(1)に直列に接続されたトランス(2)の1次巻線(2a)及びスイッチング素子(3)と、スイッチング素子(3)の制御端子に駆動信号を付与する制御回路(10)と、トランス(2)の2次巻線(2b)に接続されて負荷(7)に直流電力を供給する整流平滑回路(6)と、負荷(7)に供給される直流電力の電圧を検出して検出信号を発生する出力電圧検出回路(8)と、通常動作時に出力電圧検出回路(8)の検出信号を受信して制御回路(10)に制御信号を付与し、直流電力の電圧が高いときはスイッチング素子(3)のオン期間を短縮し、直流電力の電圧が低いときはスイッチング素子(3)のオン期間を延長する出力電圧調整回路(33)とを備えている。このスイッチング電源装置は、出力電圧調整回路(33)を駆動する電流のインピーダンスを制御する電流調整回路(41)と、負荷(7)の待機動作を検出して待機信号を発生する待機状態検出回路(34)とを備えている。待機状態検出回路(34)が待機信号を発生したとき、電流調整回路(41)は、インピーダンスを増加させるので、出力電圧調整回路(33)にて消費される電力を低減するのみならず、出力電圧調整回路(33)によりスイッチング素子(3)のオフ期間を延長することにより、スイッチング電源装置自体の消費電力を低減することができる。また、待機時にのみ電流調整回路(41)のインピーダンスを増加させるので、負荷(7)が増大しても、小電力で確実にスイッチング素子(3)にスイッチング動作を行わせることができる。   The switching power supply device of the present invention includes a DC power supply (1), a primary winding (2a) and a switching element (3) of a transformer (2) connected in series to the DC power supply (1), and a switching element (3 ) A control circuit (10) for applying a drive signal to the control terminal of), a rectifying / smoothing circuit (6) connected to the secondary winding (2b) of the transformer (2) and supplying DC power to the load (7); The output voltage detection circuit (8) that detects the voltage of the DC power supplied to the load (7) and generates a detection signal, and the control circuit that receives the detection signal of the output voltage detection circuit (8) during normal operation An output that gives a control signal to (10) and shortens the ON period of the switching element (3) when the DC power voltage is high, and extends the ON period of the switching element (3) when the DC power voltage is low And a voltage adjustment circuit (33). This switching power supply includes a current adjustment circuit (41) that controls the impedance of the current that drives the output voltage adjustment circuit (33), and a standby state detection circuit that detects a standby operation of the load (7) and generates a standby signal (34). When the standby state detection circuit (34) generates a standby signal, the current adjustment circuit (41) increases the impedance, so not only the power consumed by the output voltage adjustment circuit (33) is reduced, but also the output By extending the OFF period of the switching element (3) by the voltage adjustment circuit (33), the power consumption of the switching power supply device itself can be reduced. Further, since the impedance of the current adjustment circuit (41) is increased only during standby, even if the load (7) increases, the switching element (3) can be reliably switched with low power.

本発明によるスイッチング電源装置では、待機時の消費電力を低減して、スイッチング電源装置のランニングコスト及び発生する熱量を抑制することができる。   In the switching power supply according to the present invention, power consumption during standby can be reduced, and the running cost of the switching power supply and the amount of heat generated can be suppressed.

以下、本発明によるスイッチング電源装置の実施の形態を図1〜図3について説明する。図1及び図3では、図4に示す箇所と同一の部分には同一の符号を付して説明を省略する。   Embodiments of a switching power supply device according to the present invention will be described below with reference to FIGS. In FIG. 1 and FIG. 3, the same parts as those shown in FIG.

図1に示すように、直流電源(1)は、交流電源(1a)にラインフィルタ(1c)を介して接続された整流平滑回路(1b)を備え、整流平滑回路(1b)は、ラインフィルタ(1c)の後段に接続された全波整流回路(1d)と、一端が突入電流制限抵抗(28)を介して全波整流回路(1d)の正側出力端子に接続され且つ他端が全波整流回路(1d)の負側端子に接続された入力平滑コンデンサ(29)とを備えている。全波整流回路(1d)の正側出力端子は、突入電流制限抵抗(28)、トランス(2)の1次巻線(2a)、MOSFET(3)及び電流検出抵抗(9)を通じて全波整流回路(1d)の負側端子に接続される。電源を投入すると、交流電源(1a)からの交流電圧がラインフィルタ(1c)を介して全波整流回路(1d)で全波整流され、入力平滑コンデンサ(29)で平滑化されて直流電圧に変換される。突入電流制限抵抗(28)は、電源投入時に入力平滑コンデンサ(29)に流れる突入電流を制限する。   As shown in FIG. 1, a DC power source (1) includes a rectifying / smoothing circuit (1b) connected to an AC power source (1a) via a line filter (1c). The rectifying / smoothing circuit (1b) (1c) Full-wave rectifier circuit (1d) connected to the latter stage, one end is connected to the positive output terminal of full-wave rectifier circuit (1d) via inrush current limiting resistor (28), and the other end is all And an input smoothing capacitor (29) connected to the negative terminal of the wave rectifier circuit (1d). The positive output terminal of the full-wave rectifier circuit (1d) is full-wave rectified through the inrush current limiting resistor (28), the primary winding (2a) of the transformer (2), the MOSFET (3), and the current detection resistor (9). Connected to the negative terminal of the circuit (1d). When the power is turned on, the AC voltage from the AC power source (1a) is full-wave rectified by the full-wave rectifier circuit (1d) via the line filter (1c), smoothed by the input smoothing capacitor (29), and converted to a DC voltage. Converted. The inrush current limiting resistor (28) limits the inrush current flowing through the input smoothing capacitor (29) when the power is turned on.

トランス(2)の2次巻線(2b)の一端は、整流平滑回路(6)を構成する出力整流ダイオード(4)を介して負荷(7)の正側入力端子に接続され、2次巻線(2b)の他端は、負荷(7)の負側端子に接続される。出力整流ダイオード(4)のカソード端子と2次巻線(2b)の他端との間に整流平滑回路(6)を構成する出力平滑コンデンサ(5)が接続され、出力平滑コンデンサ(5)と負荷(7)との間に並列に出力電圧検出回路(8)が接続される。出力電圧検出回路(8)は、出力平滑コンデンサ(5)と並列に接続された分圧抵抗(54,55)と、分圧抵抗(54,55)の分圧点に接続されたベース端子を有するトランジスタ(誤差増幅回路)(52)と、トランジスタ(52)のエミッタ端子(一方の主端子)と2次巻線(2b)の他端との間に接続されたツェナダイオード(閾値設定回路)(53)と、出力整流ダイオード(4)とツェナダイオード(53)との間に接続された抵抗(51)とを備えている。トランジスタ(52)のコレクタ端子(他方の主端子)は、フォトカプラ(30)を構成する発光部(発光ダイオード)(31)及び抵抗(56)を介して出力整流ダイオード(4)に接続される。   One end of the secondary winding (2b) of the transformer (2) is connected to the positive input terminal of the load (7) via the output rectifier diode (4) constituting the rectifying and smoothing circuit (6). The other end of the line (2b) is connected to the negative terminal of the load (7). An output smoothing capacitor (5) constituting a rectifying / smoothing circuit (6) is connected between the cathode terminal of the output rectifier diode (4) and the other end of the secondary winding (2b). An output voltage detection circuit (8) is connected in parallel with the load (7). The output voltage detection circuit (8) has a voltage dividing resistor (54, 55) connected in parallel with the output smoothing capacitor (5) and a base terminal connected to the voltage dividing point of the voltage dividing resistor (54, 55). Transistor (error amplification circuit) (52), and a Zener diode (threshold setting circuit) connected between the emitter terminal (one main terminal) of the transistor (52) and the other end of the secondary winding (2b) (53) and a resistor (51) connected between the output rectifier diode (4) and the Zener diode (53). The collector terminal (the other main terminal) of the transistor (52) is connected to the output rectifier diode (4) via the light emitting part (light emitting diode) (31) and the resistor (56) constituting the photocoupler (30). .

トランス(2)の補助巻線(2c)の一端は、電流制限抵抗(15)及び補助整流ダイオード(11)を介してレギュレータ(50)の入力端子に接続される。レギュレータ(50)は、制御回路(10)内の各デバイスに一定電圧VREGの直流電力を供給する。制御回路(10)を起動するため、レギュレータ(50)の入力端子は、起動抵抗(16)を介して全波整流回路(1d)に接続される。補助整流ダイオード(11)とレギュレータ(50)との間と補助巻線(2c)の他端との間に補助平滑コンデンサ(12)が接続される。フォトカプラ(30)の受光部(32)を構成するフォトトランジスタのコレクタ端子は補助整流ダイオード(11)に接続され、エミッタ端子は比較器(37)の非反転入力端子に接続され、ベース端子はフォトカプラ(30)の発光部(31)からの光を受光する。受光部(32)のフォトトランジスタのエミッタ端子と補助巻線(2c)の他端との間には、一対の調整抵抗(35,36)が並列に接続される。 One end of the auxiliary winding (2c) of the transformer (2) is connected to the input terminal of the regulator (50) via the current limiting resistor (15) and the auxiliary rectifier diode (11). The regulator (50) supplies DC power of a constant voltage V REG to each device in the control circuit (10). In order to activate the control circuit (10), the input terminal of the regulator (50) is connected to the full-wave rectifier circuit (1d) via the activation resistor (16). An auxiliary smoothing capacitor (12) is connected between the auxiliary rectifier diode (11) and the regulator (50) and between the other end of the auxiliary winding (2c). The collector terminal of the phototransistor constituting the light receiving section (32) of the photocoupler (30) is connected to the auxiliary rectifier diode (11), the emitter terminal is connected to the non-inverting input terminal of the comparator (37), and the base terminal is Light from the light emitting part (31) of the photocoupler (30) is received. A pair of adjustment resistors (35, 36) are connected in parallel between the emitter terminal of the phototransistor of the light receiving unit (32) and the other end of the auxiliary winding (2c).

フォトカプラ(30)の受光部(32)と調整抵抗(35,36)は、出力電圧検出回路(8)の検出信号を受信する受信手段として機能し、出力電圧検出回路(8)からの誤差信号に基づく電流がフォトカプラ(30)の受光部(32)に流れ、調整抵抗(35,36)には誤差信号に基づく制御電圧VFBが発生する。この制御電圧VFBは、比較器(37)の非反転入力端子に入力される。即ち、フォトカプラ(30)及び調整抵抗(35,36)は伝達手段として機能する。比較器(37)の反転入力端子は、分圧抵抗(42,43)の分圧点に接続され、一方の分圧抵抗(42)の一端はレギュレータ(50)に接続されて例えば8Vで一定の直流電圧VREGが印加され、他方の分圧抵抗(43)の他端は全波整流回路(1d)の負側端子に接続される。よって、比較器(37)の反転入力端子には、レギュレータ(50)の出力電圧VREGを分圧抵抗(42,43)で分圧した分圧電圧VDTが入力される。比較器(37)の出力端子は、RS-FF(38)のリセット端子に接続され、RS-FF(38)の出力端子は、MOSFET(3)のゲート端子(制御端子)に接続される。出力電圧検出回路(8)、フォトカプラ(30)及び比較器(37)は、出力電圧調整回路(33)を構成する。 The light receiving section (32) and adjustment resistor (35, 36) of the photocoupler (30) function as a receiving means for receiving the detection signal of the output voltage detection circuit (8), and errors from the output voltage detection circuit (8). A current based on the signal flows to the light receiving section (32) of the photocoupler (30), and a control voltage V FB based on the error signal is generated in the adjustment resistors (35, 36). This control voltage V FB is input to the non-inverting input terminal of the comparator (37). That is, the photocoupler (30) and the adjustment resistors (35, 36) function as transmission means. The inverting input terminal of the comparator (37) is connected to the voltage dividing point of the voltage dividing resistor (42, 43), and one end of one voltage dividing resistor (42) is connected to the regulator (50) and is constant at 8V, for example. The other voltage- dividing resistor (43) is connected to the negative terminal of the full-wave rectifier circuit (1d). Therefore, the divided voltage V DT obtained by dividing the output voltage V REG of the regulator (50) by the voltage dividing resistors (42, 43) is input to the inverting input terminal of the comparator (37). The output terminal of the comparator (37) is connected to the reset terminal of the RS-FF (38), and the output terminal of the RS-FF (38) is connected to the gate terminal (control terminal) of the MOSFET (3). The output voltage detection circuit (8), the photocoupler (30), and the comparator (37) constitute an output voltage adjustment circuit (33).

電流調整回路(41)は、受光部(32)と比較器(37)との間に並列に接続された一対の調整抵抗(35,36)と、一方の調整抵抗(35)に直列に接続された切換スイッチ(44)と、第1及び第2の発振器(39,40)と、第1及び第2の発振器(39,40)を選択的にRS-FF(38)のセット端子に接続する出力端子を有する選択スイッチ(45)とを備えている。調整抵抗(35,36)の一端はフォトカプラ(30)の受光部(32)に接続され、一方の調整抵抗(35)の他端は切換スイッチ(44)を介して補助巻線(2c)の他端に接続され、他方の調整抵抗(36)の他端は直に補助巻線(2c)の他端に接続される。補助巻線(2c)の他端は、MOSFET(3)と電流検出抵抗(9)との接続点に接続され、1次側回路の基準電位(図1では接地電位)となる。第1及び第2の発振器(39,40)の入力端子はRS-FF(38)の出力端子に接続され、第1及び第2の発振器(39,40)の出力端子は選択スイッチ(45)の第1及び第2の入力端子にそれぞれ接続される。このため、選択スイッチ(45)は、待機状態検出回路(34)からの出力信号によって第1の発振器(39)からの入力信号及び第2の発振器(40)の入力信号の何れかを選択してRS-FF(38)のセット端子に出力し、RS-FF(38)をセットしてMOSFET(3)をオンする。これと同時に、切換スイッチ(44)も待機状態検出回路(34)からの出力信号により開閉され、調整抵抗(35,36)のレンジを切り換える。第1及び第2の発振器(39,40)は、RS-FF(38)からの出力信号を受信すると、所定の期間経過後にそれぞれパルスを発生するが、第2の発振器(40)の発振周波数は第1の発振器(39)の発振周波数よりも低いため、第2の発振器(40)から発生するパルスの間隔は第1の発振器(39)から発生するパルスの間隔よりも長くなる。したがって、選択スイッチ(45)により第2の発振器(40)からのパルス出力が選択されると、RS-FF(38)がセットされる期間が長くなり、MOSFET(3)のオフ期間が長くなる。待機状態検出回路(34)、切換スイッチ(44)及び選択スイッチ(45)は、モード切換回路(46)を構成する。   The current adjustment circuit (41) is connected in series with a pair of adjustment resistors (35, 36) connected in parallel between the light receiver (32) and the comparator (37), and one adjustment resistor (35). Switch 44, first and second oscillators 39 and 40, and first and second oscillators 39 and 40 are selectively connected to the set terminal of RS-FF 38. And a selection switch (45) having an output terminal. One end of the adjusting resistor (35, 36) is connected to the light receiving part (32) of the photocoupler (30), and the other end of one adjusting resistor (35) is connected to the auxiliary winding (2c) via the changeover switch (44). The other end of the other adjustment resistor (36) is directly connected to the other end of the auxiliary winding (2c). The other end of the auxiliary winding (2c) is connected to a connection point between the MOSFET (3) and the current detection resistor (9), and becomes a reference potential of the primary circuit (ground potential in FIG. 1). The input terminals of the first and second oscillators (39, 40) are connected to the output terminal of the RS-FF (38), and the output terminals of the first and second oscillators (39, 40) are the selection switch (45). Are connected to the first and second input terminals, respectively. Therefore, the selection switch (45) selects either the input signal from the first oscillator (39) or the input signal from the second oscillator (40) according to the output signal from the standby state detection circuit (34). Output to the set terminal of the RS-FF (38), set the RS-FF (38), and turn on the MOSFET (3). At the same time, the changeover switch (44) is also opened / closed by the output signal from the standby state detection circuit (34) to switch the range of the adjustment resistors (35, 36). When the first and second oscillators (39, 40) receive the output signal from the RS-FF (38), the first and second oscillators (39, 40) each generate a pulse after a predetermined period of time, but the oscillation frequency of the second oscillator (40) Is lower than the oscillation frequency of the first oscillator (39), the interval between pulses generated from the second oscillator (40) is longer than the interval between pulses generated from the first oscillator (39). Therefore, when the pulse output from the second oscillator (40) is selected by the selection switch (45), the period during which the RS-FF (38) is set becomes longer and the off period of the MOSFET (3) becomes longer. . The standby state detection circuit (34), the changeover switch (44), and the selection switch (45) constitute a mode changeover circuit (46).

図1に示すスイッチング電源装置に電源を投入すると、交流電源(1a)からラインフィルタ(1c)、全波整流回路(1d)及び突入電流制限抵抗(28)を介して入力平滑コンデンサ(29)が充電されると共に、起動抵抗(16)を介して補助平滑コンデンサ(12)が充電される。これと同時に、起動抵抗(16)を介して制御回路(10)内のレギュレータ(50)に直流電力が供給される。補助平滑コンデンサ(12)の充電電圧が集積回路により構成される制御回路(10)の起動電圧に達すると、レギュレータ(50)が起動電圧を検出して、制御回路(10)の動作が開始される。制御回路(10)内のレギュレータ(50)は、制御回路(10)の電源端子に印加される電圧VCCを検出して、内部の各デバイスの起動又は停止を行うと共に、常に安定な電圧を制御回路(10)内の各デバイスに印加する。 When the switching power supply shown in FIG. 1 is turned on, the input smoothing capacitor (29) is switched from the AC power supply (1a) through the line filter (1c), the full-wave rectifier circuit (1d), and the inrush current limiting resistor (28). In addition to being charged, the auxiliary smoothing capacitor (12) is charged via the starting resistor (16). At the same time, DC power is supplied to the regulator (50) in the control circuit (10) via the starting resistor (16). When the charging voltage of the auxiliary smoothing capacitor (12) reaches the starting voltage of the control circuit (10) configured by the integrated circuit, the regulator (50) detects the starting voltage and the operation of the control circuit (10) is started. The The regulator (50) in the control circuit (10) detects the voltage V CC applied to the power supply terminal of the control circuit (10), starts or stops each internal device, and constantly supplies a stable voltage. Applied to each device in the control circuit (10).

図1に示す状態で、制御回路(10)が動作を開始すると、第1の発振器(39)からのパルス出力によりRS-FF(38)が駆動信号を発生して、MOSFET(3)がオンに切り換えられる。MOSFET(3)がオンすると、直流電源(1)の入力平滑コンデンサ(29)からトランス(2)の1次巻線(2a)、MOSFET(3)、電流検出抵抗(9)及び直流電源(1)の全波整流回路(1d)の経路で電流IDが流れる。このとき、図2に示すように、MOSFET(3)に流れる電流IDは、入力平滑コンデンサ(29)の電圧とトランス(2)の1次巻線(2a)のインダクタンスで決まる所定の傾きで増加し、この電流IDに対応して、レギュレータ(50)の出力電圧VREGを分圧抵抗(42,43)で分圧した電圧(例えば1.5V)から分圧電圧VDTは、所定の傾きで減少する。このとき、MOSFET(3)に流れる電流IDに対応するレベルの電圧が電流検出抵抗(9)に発生すると共に、トランス(2)の1次巻線(2a)に流れる電流IDによりトランス(2)にエネルギが蓄積されるが、出力整流ダイオード(4)は逆方向にバイアスされるため、2次巻線(2b)には電流が流れない。 When the control circuit (10) starts operating in the state shown in FIG. 1, the RS-FF (38) generates a drive signal by the pulse output from the first oscillator (39), and the MOSFET (3) is turned on. Can be switched to. When the MOSFET (3) is turned on, the primary winding (2a) of the transformer (2) from the input smoothing capacitor (29) of the DC power source (1), the MOSFET (3), the current detection resistor (9) and the DC power source (1 ) Current I D flows through the full-wave rectifier circuit (1d). At this time, as shown in FIG. 2, the current ID flowing in the MOSFET (3) has a predetermined slope determined by the voltage of the input smoothing capacitor (29) and the inductance of the primary winding (2a) of the transformer (2). Corresponding to this current ID , the divided voltage V DT is a predetermined voltage from a voltage (eg, 1.5 V) obtained by dividing the output voltage V REG of the regulator (50) by the voltage dividing resistors (42, 43). Decrease with the slope of. At this time, the voltage of the level corresponding to the current I D flowing through the MOSFET (3) is generated in the current detecting resistor (9), trans by the current I D flowing through the primary winding of the transformer (2) (2a) ( Although energy is stored in 2), no current flows through the secondary winding (2b) because the output rectifier diode (4) is biased in the reverse direction.

出力電圧検出回路(8)は、負荷(7)に印加される出力電圧を分圧抵抗(54,55)で分圧して、分圧された電圧がトランジスタ(52)のベース端子に印加されると、トランジスタ(52)のベース−エミッタ間電圧とツェナダイオード(53)の閾値との差に相当する誤差信号がフォトカプラ(30)の発光部(31)に流れる。したがって、トランジスタ(52)のベース端子に印加される出力電圧が高いときは、トランジスタ(52)のエミッタ−コレクタ間に多量の電流が流れて発光部(31)の発光量が増加し、逆にトランジスタ(52)のベース端子に印加される出力電圧が低いときは、トランジスタ(52)のエミッタ−コレクタ間に少量の電流が流れて発光部(31)の発光量が減少する。   The output voltage detection circuit (8) divides the output voltage applied to the load (7) by the voltage dividing resistor (54, 55), and the divided voltage is applied to the base terminal of the transistor (52). Then, an error signal corresponding to the difference between the base-emitter voltage of the transistor (52) and the threshold value of the Zener diode (53) flows to the light emitting section (31) of the photocoupler (30). Therefore, when the output voltage applied to the base terminal of the transistor (52) is high, a large amount of current flows between the emitter and collector of the transistor (52), increasing the amount of light emitted from the light emitting unit (31). When the output voltage applied to the base terminal of the transistor (52) is low, a small amount of current flows between the emitter and collector of the transistor (52), and the light emission amount of the light emitting section (31) decreases.

一方、補助平滑コンデンサ(12)に充電された電圧により、補助平滑コンデンサ(12)、フォトカプラ(30)の受光部(32)、調整抵抗(35,36)及び補助平滑コンデンサ(12)の経路で電流が流れるが、この電流が調整抵抗(35,36)に流れることにより、制御電圧VFBが比較器(37)の非反転入力端子に印加される。比較器(37)は、反転入力端子に印加される分圧抵抗(42,43)の分圧電圧VDTと制御電圧VFBとを比較して、分圧電圧VDTが制御電圧VFBに達するか又はこれより低下すると、高電圧(H)レベルの出力を発生する。 On the other hand, depending on the voltage charged in the auxiliary smoothing capacitor (12), the path of the auxiliary smoothing capacitor (12), the light receiving part (32) of the photocoupler (30), the adjusting resistor (35, 36), and the auxiliary smoothing capacitor (12) The current flows through the adjustment resistor (35, 36), whereby the control voltage V FB is applied to the non-inverting input terminal of the comparator (37). The comparator (37) compares the divided voltage V DT of the voltage dividing resistor (42, 43) applied to the inverting input terminal with the control voltage V FB, and the divided voltage V DT becomes the control voltage V FB . When it reaches or falls below, it produces a high voltage (H) level output.

図2に示すように、分圧電圧VDTの最小電圧は、調整抵抗(35,36)に印加される制御電圧VFBにより決定される。分圧電圧VDTが比較器(37)の非反転入力端子に印加される制御電圧VFBに達するか又はこれより低下すると、比較器(37)の出力は高電圧(H)レベルに反転するので、比較器(37)の高電圧(H)レベルの出力により、RS-FF(38)がリセットされる。このため、RS-FF(38)の出力(Q)が低電圧(L)レベルになり、MOSFET(3)はオフに切り換えられ、同時に第1の発振器(39)にリセット信号が送出される。このとき、トランス(2)に蓄積されたエネルギが2次巻線(2b)から出力整流ダイオード(4)及び出力平滑コンデンサ(5)を介して負荷(7)に供給される。また、電流IDの急激な減少に対応して、分圧電圧VDTも急激に増加する。リセット信号を受けた第1の発振器(39)は、所定の時間が経過した後に起動パルスを出力し、この起動パルスによりRS-FF(38)がセットされる。したがって、RS-FF(38)の出力信号が高電圧(H)レベルになり、MOSFET(3)がオンする。前記の動作を反復して、所定の電圧レベルに安定するように負荷(7)への出力電圧が制御される。 As shown in FIG. 2, the minimum voltage of the divided voltage V DT is determined by the control voltage V FB applied to the adjustment resistors (35, 36). When the divided voltage V DT reaches or falls below the control voltage V FB applied to the non-inverting input terminal of the comparator (37), the output of the comparator (37) is inverted to the high voltage (H) level. Therefore, the RS-FF (38) is reset by the high voltage (H) level output of the comparator (37). For this reason, the output (Q) of the RS-FF (38) becomes a low voltage (L) level, the MOSFET (3) is switched off, and simultaneously, a reset signal is sent to the first oscillator (39). At this time, the energy stored in the transformer (2) is supplied from the secondary winding (2b) to the load (7) via the output rectifier diode (4) and the output smoothing capacitor (5). Corresponding to the rapid decrease in current ID, the divided voltage VDT also increases rapidly. The first oscillator (39) that has received the reset signal outputs a start pulse after a predetermined time has elapsed, and the RS-FF (38) is set by this start pulse. Therefore, the output signal of the RS-FF (38) becomes a high voltage (H) level, and the MOSFET (3) is turned on. By repeating the above operation, the output voltage to the load (7) is controlled so as to be stabilized at a predetermined voltage level.

2次巻線(2b)からの出力電圧が上昇すると、発光部(31)に流れる電流が増加するため、受光部(32)に流れる電流も増加する。このため、調整抵抗(35,36)に発生する制御電圧VFBが図2の右側に示すように、1.5Vに接近して上昇する。このため、MOSFET(3)がオンに切り換えられても、分圧電圧VDTが短時間で制御電圧VFBに達するため、MOSFET(3)が短時間でオンからオフに切り換えられて、MOSFET(3)のオン期間が短縮され、出力電圧が低下する。逆に、2次巻線(2b)からの出力電圧が低下すると、発光部(31)に流れる電流が減少するため、受光部(32)に流れる電流も減少する。このため、調整抵抗(35,36)に発生する制御電圧VFBが1.5Vから離間して低下する。このため、MOSFET(3)がオンに切り換えられたとき、分圧電圧VDTが制御電圧VFBに達するのに時間を要するため、MOSFET(3)が長時間でオンからオフに切り換えられて、MOSFET(3)のオン期間が延長され、負荷(7)への出力電圧が上昇する。 When the output voltage from the secondary winding (2b) rises, the current flowing through the light emitting unit (31) increases, so the current flowing through the light receiving unit (32) also increases. For this reason, the control voltage V FB generated in the adjustment resistor (35, 36) rises close to 1.5V as shown on the right side of FIG. Therefore, even if the MOSFET (3) is switched on, the divided voltage V DT reaches the control voltage V FB in a short time, so that the MOSFET (3) is switched from on to off in a short time, and the MOSFET ( The on period of 3) is shortened and the output voltage is lowered. Conversely, when the output voltage from the secondary winding (2b) decreases, the current flowing through the light emitting section (31) decreases, and the current flowing through the light receiving section (32) also decreases. For this reason, the control voltage V FB generated in the adjustment resistor (35, 36) decreases away from 1.5V. For this reason, when the MOSFET (3) is switched on, it takes time for the divided voltage V DT to reach the control voltage V FB. Therefore, the MOSFET (3) is switched from on to off in a long time, The on period of the MOSFET (3) is extended, and the output voltage to the load (7) increases.

待機時には、負荷(7)及びトランス(2)の1次巻線(2a)並びに2次巻線(2b)に流れる電流が減少するので、待機状態検出回路(34)は、負荷(7)又は1次巻線(2a)若しくは2次巻線(2b)に電流検出抵抗(図示せず)等の電流検出センサを接続して、減少する電流の量を測定することにより、待機時の減少電流を検出することができる。例えば、負荷(7)へ流れる電流IOのレベルを検出して待機時を決定すればよい。また、電流検出抵抗(9)を流れる電流IDのレベルを検出して待機時を決定してもよい。待機時以外では、負荷(7)に流れる電流が大きくなり、これに対応して、トランス(2)の1次巻線(2a)及び2次巻線(2b)に流れる電流が増加する。したがって、待機状態検出回路(34)は、待機時に負荷(7)及び1次巻線(2a)並びに2次巻線(2b)の何れかに流れる減少電流を電流検出センサにより検出して、待機信号を発生すればよい。 During standby, the current flowing through the primary winding (2a) and secondary winding (2b) of the load (7) and transformer (2) decreases, so that the standby state detection circuit (34) By connecting a current detection sensor such as a current detection resistor (not shown) to the primary winding (2a) or secondary winding (2b) and measuring the amount of current that decreases, the current that decreases during standby is reduced. Can be detected. For example, the standby time may be determined by detecting the level of the current IO flowing to the load (7). Further, the standby time may be determined by detecting the level of the current ID flowing through the current detection resistor (9). Except during standby, the current flowing through the load (7) increases, and the current flowing through the primary winding (2a) and the secondary winding (2b) of the transformer (2) increases correspondingly. Therefore, the standby state detection circuit (34) detects the reduced current flowing in any of the load (7), the primary winding (2a) and the secondary winding (2b) by the current detection sensor during standby, A signal may be generated.

負荷(7)が待機動作になると、待機状態検出回路(34)は待機信号を発生して、切換スイッチ(44)をオンからオフに切り換える。これにより、通常時には調整抵抗(35,36)を通じて受光部(32)の電流が流れるのに対して、待機時には調整抵抗(36)のみを通じて受光部(32)の電流が流れるため、待機時には出力電圧調整回路(33)のインピーダンスが増加して、制御電圧VFBが上昇する。これと同時に、待機状態検出回路(34)は、選択スイッチ(45)を図示する第1の入力端子から第2の入力端子に切り換える。選択スイッチ(45)の切り換えにより、第1の発振器(39)がRS-FF(38)から切り離されて、第2の発振器(40)がRS-FF(38)のセット端子に接続される。第2の発振器(40)から発生するパルスの間隔は、第1の発振器(39)から発生するパルスの間隔より長く、それ故MOSFET(3)のオフ期間が長くなるため、MOSFET(3)のスイッチング周波数が低下し、待機時の電力変換効率を改善することができる。また、フォトカプラ(30)の受光部(32)を流れる電流は、他方の調整抵抗(36)のみに流れ、切り離された一方の調整抵抗(35)には電流が流れない。通常時には、フォトカプラ(30)の受光部(32)から調整抵抗(35,36)を通じて電流が流れるときに、調整抵抗(35,36)に発生する電圧VFBのレベルによりMOSFET(3)のオン期間幅を決定して、負荷(7)への出力電圧を一定レベルに制御するが、待機時には、他方の調整抵抗(36)のみを通じて電流が流れるので、通常時に比べフォトカプラ(30)の受光部(32)を流れる電流を減少させることができる。このように、出力電圧調整回路(33)により消費される電力を低減するのみならず、出力電圧調整回路(33)によりスイッチング素子(3)のオフ期間を延長することにより、スイッチング電源装置自体の消費電力を低減することができる。 When the load (7) enters the standby operation, the standby state detection circuit (34) generates a standby signal and switches the changeover switch (44) from on to off. As a result, the current of the light receiving unit (32) flows through the adjustment resistor (35, 36) during normal operation, whereas the current of the light receiving unit (32) flows through only the adjustment resistor (36) during standby, so that the output is output during standby. The impedance of the voltage adjustment circuit (33) increases and the control voltage V FB rises. At the same time, the standby state detection circuit (34) switches the selection switch (45) from the first input terminal shown in the figure to the second input terminal. By switching the selection switch (45), the first oscillator (39) is disconnected from the RS-FF (38), and the second oscillator (40) is connected to the set terminal of the RS-FF (38). The interval between pulses generated from the second oscillator (40) is longer than the interval between pulses generated from the first oscillator (39), and therefore the off period of the MOSFET (3) becomes longer. The switching frequency is lowered, and the power conversion efficiency during standby can be improved. Further, the current flowing through the light receiving part (32) of the photocoupler (30) flows only through the other adjustment resistor (36), and no current flows through the separated adjustment resistor (35). Normally, when a current flows from the light receiving part (32) of the photocoupler (30) through the adjusting resistor (35, 36), the level of the voltage V FB generated in the adjusting resistor (35, 36) depends on the level of the MOSFET (3). The ON period width is determined and the output voltage to the load (7) is controlled to a constant level.However, during standby, current flows only through the other adjustment resistor (36), so the photocoupler (30) The current flowing through the light receiving unit (32) can be reduced. In this way, not only the power consumed by the output voltage adjustment circuit (33) is reduced, but also by extending the off period of the switching element (3) by the output voltage adjustment circuit (33), the switching power supply device itself Power consumption can be reduced.

負荷(7)が通常動作になると、待機状態検出回路(34)は待機信号を発生しないため、切換スイッチ(44)がオフからオンに切り換えられると共に、選択スイッチ(45)が第2の入力端子から第1の入力端子に切り換えられて、図示の状態に復帰する。   When the load (7) is in normal operation, the standby state detection circuit (34) does not generate a standby signal, so that the changeover switch (44) is switched from off to on and the selection switch (45) is the second input terminal. Is switched to the first input terminal to return to the state shown in the figure.

図1に示す実施の形態では、待機時ではMOSFET(3)のオン期間が短いので、制御電圧VFBは略1.5Vまで上昇する。このとき、調整抵抗(35,36)を同時に使用する通常時のモードでフォトカプラ(30)の受光部(32)には1mAの電流が必要となるのに対して、本実施の形態では、他方の調整抵抗(36)のみを使用すると、フォトカプラ(30)の受光部(32)に流れる電流が減少するので、待機時の電流は300μAでよく、フォトカプラ(30)の受光部(32)の電流を1/3以下に低減することができる。 In the embodiment shown in FIG. 1, since the ON period of the MOSFET (3) is short during standby, the control voltage V FB rises to approximately 1.5V. At this time, a current of 1 mA is required for the light receiving portion (32) of the photocoupler (30) in the normal mode in which the adjustment resistors (35, 36) are used simultaneously. If only the other adjustment resistor (36) is used, the current flowing through the light receiving section (32) of the photocoupler (30) decreases, so that the standby current may be 300 μA, and the light receiving section (32 of the photocoupler (30) may be used. ) Current can be reduced to 1/3 or less.

待機時を脱して負荷(7)に流れる電流が大きくなると、フォトカプラ(30)の受光部(32)に流れる電流は減少するので、比較器(37)が不安定動作になることがあるが、モード切換回路(46)によって両調整抵抗(35,36)を使用するため、出力電圧調整回路(33)のインピーダンスが小さくなり、フォトカプラ(30)の受光部(32)を流れる電流が増加するので、比較器(37)の動作及びMOSFET(3)のスイッチング動作を安定化させることができる。フォトカプラ(30)の受光部(32)の電流を電圧に変換する調整抵抗(35,36)の抵抗値を変えると、スイッチング電源装置の出力電圧を安定化動作させる制御系の利得が変化するが、待機時は負荷電流が極めて少なく、負荷変動も殆どないため、動作上は問題にならない。   If the current that flows to the load (7) increases from the standby state, the current that flows to the light receiver (32) of the photocoupler (30) decreases, so the comparator (37) may become unstable. Because both adjustment resistors (35, 36) are used by the mode switching circuit (46), the impedance of the output voltage adjustment circuit (33) is reduced and the current flowing through the light receiving part (32) of the photocoupler (30) is increased. Therefore, the operation of the comparator (37) and the switching operation of the MOSFET (3) can be stabilized. Changing the resistance value of the adjustment resistor (35, 36) that converts the current of the light receiving part (32) of the photocoupler (30) into a voltage changes the gain of the control system that stabilizes the output voltage of the switching power supply. However, since the load current is very small and there is almost no load fluctuation during standby, there is no problem in operation.

制御回路(10)を15Vで動作させる場合、フォトカプラ(30)の受光部(32)と直列に接続された調整抵抗(35,36)で消費される電力は、通常時では0.015Wであるが、本発明の待機時では1/3以下の0.0045Wに低減される。これは、フォトカプラ(30)の発光部(31)でも同様であり、フォトカプラ(30)の電流伝達率(CTR)を50、出力電圧を15Vとすると、通常時では0.03Wになるが、本発明の待機時では0.009Wとなる。フォトカプラ(30)の発光部(31)での消費電力は2次側で消費されるので、消費電力のトランス(2)による電力変換効率を考慮する必要がある。待機時、即ち軽負荷時の電力変換効率を50%と仮定すると、フォトカプラ(30)の発光部(31)に流れる電流に起因する消費電力(入力電力)は、通常動作時では0.06Wであるが、待機動作時では0.018Wである。フォトカプラ(30)の受光部(32)及び発光部(31)に流れる電流に起因する消費電力(入力電力)を合計すると、通常動作時の消費電力は0.075Wであるのに対し、待機動作時の消費電力は0.0225Wになる。本発明による待機動作時では、0.05Wに消費電力を低減できる。スイッチング電源装置の待機時に要する消費電力は、0.1〜0.2Wであるから、この効果は大きい。ただし、発光部(31)の電流が減少する程、フォトカプラ(30)の電流伝達率は低下する傾向があるので、実際に得られる効果は若干少ないこともある。   When the control circuit (10) is operated at 15V, the power consumed by the adjusting resistors (35, 36) connected in series with the light receiving section (32) of the photocoupler (30) is 0.015 W in normal times. However, it is reduced to 0.0045 W which is 1/3 or less in the standby mode of the present invention. The same applies to the light emitting section (31) of the photocoupler (30). When the current transfer rate (CTR) of the photocoupler (30) is 50 and the output voltage is 15 V, the output voltage is normally 0.03 W. The standby time of the present invention is 0.009W. Since power consumption in the light emitting section (31) of the photocoupler (30) is consumed on the secondary side, it is necessary to consider the power conversion efficiency of the power consumption transformer (2). Assuming that the power conversion efficiency during standby, that is, during light load, is 50%, the power consumption (input power) caused by the current flowing through the light emitting section (31) of the photocoupler (30) is 0.06 W during normal operation. However, it is 0.018 W during the standby operation. The total power consumption (input power) due to the current flowing through the light receiving part (32) and light emitting part (31) of the photocoupler (30) is 0.075W during normal operation, while waiting. The power consumption during operation is 0.0225W. During standby operation according to the present invention, power consumption can be reduced to 0.05 W. Since the power consumption required when the switching power supply is on standby is 0.1 to 0.2 W, this effect is significant. However, since the current transfer rate of the photocoupler (30) tends to decrease as the current of the light emitting unit (31) decreases, the actually obtained effect may be slightly less.

図1に示す本発明の実施の形態は変更が可能である。例えば、切換スイッチ(44)をトランジスタ等の半導体スイッチに変更することもできる。この場合に、図3に示すように、切換スイッチ(44)をトランジスタ(47)に置き換え、待機状態検出回路(34)からの待機信号をトランジスタ(47)のベース端子に付与し、トランジスタ(47)のベース電流の大きさに応じてトランジスタ(47)のエミッタ−コレクタ間を流れる電流を調整することにより、受光部(32)に流れる電流、即ち制御電圧VFBを連続的に調整することもできる。また、第1の発振器(39)とグランドとの間に放電用抵抗(48)と、放電用抵抗(48)に並列に発振周波数調整用コンデンサ(49)を接続して、待機状態検出回路(34)からの待機信号を発振周波数調整用コンデンサ(49)に付与して、発振周波数調整用コンデンサ(49)の充電電圧レベルを調整することにより、第1の発振器(39)の発振周波数を連続的に変更して、種々の発振周波数でMOSFET(3)をオフに切り換えることも可能である。また、フォトカプラ(30)を省略して、出力電圧検出回路(8)の出力信号をレベル変更するか又はレベル変更せずに、比較器(37)の非反転入力端子に付与してもよい。また、MOSFET(3)の代わりにバイポーラトランジスタ、IGBT(絶縁ゲート型バイポーラトランジスタ)等の他の半導体スイッチング素子も使用可能である。 The embodiment of the present invention shown in FIG. 1 can be modified. For example, the changeover switch (44) can be changed to a semiconductor switch such as a transistor. In this case, as shown in FIG. 3, the changeover switch (44) is replaced with a transistor (47), a standby signal from the standby state detection circuit (34) is applied to the base terminal of the transistor (47), and the transistor (47 The current flowing between the emitter and the collector of the transistor (47) is adjusted according to the magnitude of the base current of the transistor (47), so that the current flowing through the light receiving section (32), that is, the control voltage V FB can be continuously adjusted. it can. Further, a discharge resistor (48) is connected between the first oscillator (39) and the ground, and an oscillation frequency adjusting capacitor (49) is connected in parallel to the discharge resistor (48), so that a standby state detection circuit ( 34) Apply the standby signal from the oscillation frequency adjustment capacitor (49) to the oscillation frequency adjustment capacitor (49), and adjust the charging voltage level of the oscillation frequency adjustment capacitor (49), thereby making the oscillation frequency of the first oscillator (39) continuous. The MOSFET (3) can be switched off at various oscillation frequencies. Further, the photocoupler (30) may be omitted, and the output signal of the output voltage detection circuit (8) may be applied to the non-inverting input terminal of the comparator (37) without changing the level or without changing the level. . Other semiconductor switching elements such as bipolar transistors and IGBTs (insulated gate bipolar transistors) can be used instead of the MOSFET (3).

上記の実施の形態では、フライバック型で他励式のスイッチング電源装置に本発明を適用したが、フォワード型又は共振型或いは自励式のスイッチング電源装置にも本発明を適用することができる。   In the above embodiment, the present invention is applied to a flyback type separately excited switching power supply, but the present invention can also be applied to a forward type, resonant type, or self-excited type switching power supply.

本発明によるスイッチング電源装置の実施の形態を示す電気回路図Electrical circuit diagram showing an embodiment of a switching power supply device according to the present invention 図1に示す電気回路図のスイッチング電流、分圧電圧及び制御電圧の特性を示すグラフThe graph which shows the characteristic of the switching current of the electric circuit diagram shown in FIG. 1, a divided voltage, and a control voltage 本発明の他の実施の形態を示す電気回路図Electric circuit diagram showing another embodiment of the present invention 従来のスイッチング電源装置を示す電気回路図Electric circuit diagram showing a conventional switching power supply 図4に示す制御回路の内部構成の詳細を示す電気回路図Electrical circuit diagram showing details of internal configuration of control circuit shown in FIG. 従来のスイッチング電源装置の各部作動信号のタイミングチャートTiming chart of operation signal of each part of conventional switching power supply

符号の説明Explanation of symbols

(1)・・直流電源、 (1a)・・交流電源、 (1b)・・整流平滑回路、 (1c)・・ラインフィルタ、 (1d)・・全波整流回路、 (2)・・トランス、 (2a)・・1次巻線、 (2b)・・2次巻線、 (2c)・・補助巻線、 (3)・・MOSFET(スイッチング素子)、 (4)・・出力整流ダイオード、 (5)・・出力平滑コンデンサ、 (6)・・整流平滑回路、 (7)・・負荷、 (8)・・出力電圧検出回路、 (9)・・電流検出抵抗、 (10)・・制御回路、 (11)・・補助整流ダイオード、 (12)・・補助平滑コンデンサ、 (13)・・信号発生回路、 (14)・・駆動回路、 (14a)・・ORゲート、 (14b)・・ドライバ、 (15)・・電流制限抵抗、 (16)・・起動抵抗、 (17)・・周波数制御回路、 (18)・・オン期間制御回路、 (19)・・最小オン期間出力回路、 (20)・・オン期間比較回路(Dフリップフロップ)、 (21)・・発振周波数設定用コンデンサ、 (22)・・発振回路、 (23)・・第1のパルス発生回路、 (24)・・第2のパルス発生回路、 (25)・・最小オン期間切換回路、 (25a)・・第1のANDゲート、 (25b)・・第2のANDゲート、 (25c)・・ORゲート、 (26)・・切換手段、 (27)・・PWM制御回路、 (27a)・・RS-FF(RSフリップフロップ)、 (27b)・・NORゲート、 (28)・・突入電流制限抵抗、 (29)・・入力平滑コンデンサ、 (30)・・フォトカプラ、 (31)・・発光部、 (32)・・受光部、 (33)・・出力電圧調整回路、 (34)・・待機状態検出回路、 (35,36)・・調整抵抗、 (37)・・比較器、 (38)・・RS-FF、 (39)・・第1の発振器、 (40)・・第2の発振器、 (41)・・電流調整回路、 (42,43)・・分圧抵抗、 (44)・・切換スイッチ、 (45)・・選択スイッチ、 (46)・・モード切換回路、 (47)・・トランジスタ(半導体スイッチ)、 (48)・・放電用抵抗、 (49)・・発振周波数調整用コンデンサ、 (50)・・レギュレータ、 (51)・・抵抗、 (52)・・トランジスタ、 (53)・・ツェナダイオード、 (54,55)・・分圧抵抗、 (56)・・抵抗、   (1) ・ ・ DC power supply, (1a) ・ ・ AC power supply, (1b) ・ ・ Rectification smoothing circuit, (1c) ・ ・ Line filter, (1d) ・ ・ Full wave rectification circuit, (2) ・ Transformer, (2a) ・ ・ Primary winding, (2b) ・ ・ Secondary winding, (2c) ・ ・ Auxiliary winding, (3) ・ ・ MOSFET (switching element), (4) ・ ・ Output rectifier diode, ( 5) ... Output smoothing capacitor, (6) ... Rectifier smoothing circuit, (7) ... Load, (8) ... Output voltage detection circuit, (9) ... Current detection resistor, (10) ... Control circuit (11) ・ ・ Auxiliary rectifier diode, (12) ・ ・ Auxiliary smoothing capacitor, (13) ・ ・ Signal generation circuit, (14) ・ ・ Drive circuit, (14a) ・ ・ OR gate, (14b) ・ ・ Driver (15) ... Current limiting resistor, (16) ... Starting resistor, (17) ... Frequency control circuit, (18) ... On period control circuit, (19) ... Minimum on period output circuit, (20 .. ON period comparison circuit (D flip-flop ), (21) ... Oscillation frequency setting capacitor, (22) ... Oscillation circuit, (23) ... First pulse generation circuit, (24) ... Second pulse generation circuit, (25) ... (25a) .. first AND gate, (25b) .. second AND gate, (25c) .. OR gate, (26) .. switching means, (27) .. PWM Control circuit, (27a) ・ ・ RS-FF (RS flip-flop), (27b) ・ ・ NOR gate, (28) ・ ・ Inrush current limiting resistor, (29) ・ ・ Input smoothing capacitor, (30) ・ ・ Photo Coupler, (31) ... Light emitting part, (32) ... Light receiving part, (33) ... Output voltage adjustment circuit, (34) ... Standby detection circuit, (35,36) ... Adjustment resistor, (37・ ・ Comparator, (38) ・ ・ RS-FF, (39) ・ ・ First oscillator, (40) ・ ・ Second oscillator, (41) ・ ・ Current adjustment circuit, (42,43) ・・ Partial resistance, (44) ・ ・ Switch, (45) ・ ・Selection switch, (46) ... mode switching circuit, (47) ... transistor (semiconductor switch), (48) ... discharge resistor, (49) ... oscillation frequency adjusting capacitor, (50) ... regulator, (51) ... Resistance, (52) ... Transistor, (53) ... Zener diode, (54, 55) ... Voltage divider resistor, (56) ... Resistance,

Claims (5)

直流電源と、該直流電源に直列に接続されたトランスの1次巻線及びスイッチング素子と、該スイッチング素子の制御端子に駆動信号を付与する制御回路と、前記トランスの2次巻線に接続されて負荷に直流電力を供給する整流平滑回路と、前記負荷に供給される直流電力の電圧を検出して検出信号を発生する出力電圧検出回路と、通常動作時に前記出力電圧検出回路の検出信号を受信して前記制御回路に制御信号を付与し、前記直流電力の電圧が高いときは前記スイッチング素子のオン期間を短縮し、前記直流電力の電圧が低いときは前記スイッチング素子のオン期間を延長する出力電圧調整回路とを備えたスイッチング電源装置において、
前記出力電圧調整回路を駆動する電流のインピーダンスを制御する電流調整回路と、
前記負荷の待機動作を検出して待機信号を発生する待機状態検出回路とを備え、
該待機状態検出回路が待機信号を発生したとき、前記電流調整回路はインピーダンスを増加させることを特徴とするスイッチング電源装置。
A DC power supply, a primary winding and a switching element of a transformer connected in series to the DC power supply, a control circuit for applying a drive signal to a control terminal of the switching element, and a secondary winding of the transformer A rectifying / smoothing circuit that supplies DC power to the load, an output voltage detection circuit that detects a voltage of the DC power supplied to the load and generates a detection signal, and a detection signal of the output voltage detection circuit during normal operation. Receive and apply a control signal to the control circuit, shorten the on-period of the switching element when the voltage of the DC power is high, and extend the on-period of the switching element when the voltage of the DC power is low In a switching power supply device comprising an output voltage adjustment circuit,
A current adjusting circuit for controlling an impedance of a current for driving the output voltage adjusting circuit;
A standby state detection circuit that detects a standby operation of the load and generates a standby signal;
The switching power supply device according to claim 1, wherein when the standby state detection circuit generates a standby signal, the current adjustment circuit increases impedance.
前記電流調整回路は、前記出力電圧調整回路に流れる電流の電流値を決定する複数の調整抵抗と、該調整抵抗の作動を選択する切換スイッチとを備え、
前記待機状態検出回路が待機信号を発生したとき、前記切換スイッチにより前記調整抵抗を選択して前記電流調整回路のインピーダンスを調整する請求項1に記載のスイッチング電源装置。
The current adjustment circuit includes a plurality of adjustment resistors for determining a current value of a current flowing through the output voltage adjustment circuit, and a changeover switch for selecting an operation of the adjustment resistor,
2. The switching power supply device according to claim 1, wherein when the standby state detection circuit generates a standby signal, the adjustment resistor is selected by the changeover switch to adjust the impedance of the current adjustment circuit.
前記電流調整回路は、前記スイッチング素子のオンのタイミングを決定する発振周波数の異なる複数の発振器を備え、
前記待機状態検出回路が待機信号を発生したとき、前記複数の発振器の中でより低い発振周波数を有する発振器の出力により前記スイッチング素子をオンに切り換える請求項1又は2に記載のスイッチング電源装置。
The current adjustment circuit includes a plurality of oscillators having different oscillation frequencies that determine the ON timing of the switching element,
3. The switching power supply device according to claim 1, wherein when the standby state detection circuit generates a standby signal, the switching element is switched on by an output of an oscillator having a lower oscillation frequency among the plurality of oscillators.
前記電流調整回路は、前記出力電圧調整回路に流れる電流の電流値を調整する調整抵抗と、半導体スイッチにより構成され且つ該半導体スイッチに流れる電流を調整して前記調整抵抗に流れる電流を制御する切換スイッチとを備え、
該切換スイッチは、前記待機状態検出回路が待機信号を発生したときに、前記電流調整回路のインピーダンスを連続的に変化させる請求項1に記載のスイッチング電源装置。
The current adjustment circuit includes a regulation resistor that regulates a current value of a current that flows through the output voltage regulation circuit, and a switch that controls a current that flows through the regulation resistor by regulating a current that flows through the semiconductor switch. With a switch,
2. The switching power supply device according to claim 1, wherein the change-over switch continuously changes the impedance of the current adjustment circuit when the standby state detection circuit generates a standby signal.
前記電流調整回路は、前記スイッチング素子のオンのタイミングを決定する発振器を備え、
該発振器は、前記待機状態検出回路の待機信号により発振周波数が連続的に変化して、異なるタイミングで前記スイッチング素子をオンに切り換える請求項1又は2に記載のスイッチング電源装置。
The current adjustment circuit includes an oscillator that determines the ON timing of the switching element,
3. The switching power supply device according to claim 1, wherein an oscillation frequency of the oscillator is continuously changed by a standby signal of the standby state detection circuit, and the switching element is turned on at different timings.
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JP2010206949A (en) * 2009-03-04 2010-09-16 Shindengen Electric Mfg Co Ltd Switching power supply
CN101854119A (en) * 2009-04-03 2010-10-06 通嘉科技股份有限公司 Control method, power supply control integrated circuit and power supply
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