JP2013012634A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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JP2013012634A
JP2013012634A JP2011145276A JP2011145276A JP2013012634A JP 2013012634 A JP2013012634 A JP 2013012634A JP 2011145276 A JP2011145276 A JP 2011145276A JP 2011145276 A JP2011145276 A JP 2011145276A JP 2013012634 A JP2013012634 A JP 2013012634A
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JP5554293B2 (en
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Tetsuyuki Furui
哲之 古井
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Tokai Rika Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of securing identity of alignment marks without depending on the index of reflection of a substrate, and a method for manufacturing the same.SOLUTION: A semiconductor device 1 comprises: a silicon substrate 24; a circuit part 3 formed by having at least NiCo pattern 31 and an aluminium electrode 30 formed on the silicon substrate 24; a NiCo pattern 22 formed on the silicon substrate 24 as a low reflective pattern formed by the same step as the NiCo pattern 31 of the circuit part 3; and an aluminium pattern 20 formed on the NiCo pattern 22 as a high reflective pattern formed by the same step as the aluminium electrode 30 of the circuit part 3.

Description

本発明は、半導体装置及び半導体装置の製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

従来の技術として、アライメントマークを有する半導体装置がある（例えば、特許文献１参照）。   As a conventional technique, there is a semiconductor device having an alignment mark (see, for example, Patent Document 1).

この半導体装置は、半導体基板上に形成される任意の回路と、回路上にその保護膜として形成されるＳｉＯ２等の酸化膜と、酸化膜上に形成されるアルミニウム層による高反射率パターンとを有し、高反射率パターンと下地の酸化膜層を露出させた低反射率パターンとでＸ方向、Ｙ方向に略十字形状にアライメントマークを形成する。 This semiconductor device includes an arbitrary circuit formed on a semiconductor substrate, an oxide film such as SiO 2 formed as a protective film on the circuit, and a high reflectance pattern by an aluminum layer formed on the oxide film. The alignment mark is formed in a substantially cross shape in the X direction and the Y direction with the high reflectance pattern and the low reflectance pattern with the underlying oxide film layer exposed.

この半導体装置によれば、反射率の異なる高反射パターンと低反射パターンとをアライメントマークに用いたため、高反射パターンのみでアライメントマークを形成した場合に比べてコントラストが向上し、位置合わせを確実にすることができる。   According to this semiconductor device, since the high reflection pattern and the low reflection pattern having different reflectivities are used for the alignment mark, the contrast is improved as compared with the case where the alignment mark is formed only by the high reflection pattern, and the alignment is ensured. can do.

特開平７−２２１１６６号公報Japanese Patent Laid-Open No. 7-221166

しかし、特許文献１に示す半導体装置は、低反射率パターンとして酸化膜層を用いることで照射される光が基板に達するために低反射パターンの反射率が基板の反射率にも依存し、さらにはウエハ上において基板の反射率のばらつきがある場合には、高反射率パターンと低反射率パターンのコントラストが十分でないものが製造され、識別性が確保できない場合があった。   However, in the semiconductor device disclosed in Patent Document 1, since the irradiated light reaches the substrate by using the oxide film layer as the low reflectance pattern, the reflectance of the low reflectance pattern also depends on the reflectance of the substrate. In the case where there is a variation in the reflectance of the substrate on the wafer, a high-reflectance pattern and a low-reflectance pattern with insufficient contrast may be manufactured, and discrimination may not be ensured.

従って、本発明の目的は、基板の反射率に依存せず、アライメントマークの識別性を確保することができる半導体装置及び半導体装置の製造方法を提供することにある。   Accordingly, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device that can ensure the identification of the alignment mark without depending on the reflectance of the substrate.

本発明の一態様は、半導体基板と、前記半導体基板上に少なくとも第１の層と第２の層とを含んで形成される回路部と、前記半導体基板上に前記回路部の前記第１の層と同工程において形成される低反射パターンと、前記低反射パターン上に形成され、前記回路部の前記第２の層と同工程において形成される高反射パターンとを有する半導体装置を提供する。   One embodiment of the present invention includes a semiconductor substrate, a circuit portion formed including at least a first layer and a second layer on the semiconductor substrate, and the first portion of the circuit portion formed on the semiconductor substrate. There is provided a semiconductor device having a low reflection pattern formed in the same process as a layer, and a high reflection pattern formed on the low reflection pattern and formed in the same process as the second layer of the circuit portion.

上記半導体装置の前記第１の層は、磁気抵抗膜であってもよく、前記第２の層は、磁気抵抗膜と電気的に接続される電極であってもよい。   The first layer of the semiconductor device may be a magnetoresistive film, and the second layer may be an electrode electrically connected to the magnetoresistive film.

また、本発明の一態様は、半導体基板上に回路部用のパターンと低反射パターンとを含む第１の層を形成する工程と、前記第１の層上に前記回路部用のパターンと高反射パターンとを含む第２の層を形成する工程とを有する半導体装置の製造方法を提供する。   According to one embodiment of the present invention, a step of forming a first layer including a circuit portion pattern and a low-reflection pattern over a semiconductor substrate, and a step of forming the circuit portion pattern and the height over the first layer are performed. A method for manufacturing a semiconductor device is provided that includes a step of forming a second layer including a reflective pattern.

本発明によれば、基板の反射率に依存せず、アライメントマークの識別性を確保することができる。   According to the present invention, it is possible to ensure the identification of the alignment mark without depending on the reflectance of the substrate.

図１Ａは、実施の形態に係る半導体装置の構成の一例を示す概略平面図である。FIG. 1A is a schematic plan view illustrating an example of the configuration of the semiconductor device according to the embodiment. 図１Ｂは、実施の形態に係る半導体装置の構成の一例を示す概略断面図である。FIG. 1B is a schematic cross-sectional view illustrating an example of the configuration of the semiconductor device according to the embodiment. 図２は、本発明の実施の形態に係る半導体装置の構成の一例を示す概略平面図である。FIG. 2 is a schematic plan view showing an example of the configuration of the semiconductor device according to the embodiment of the present invention. 図３（ａ）は、本実施の形態に係る半導体装置のアライメントマーク付近を拡大した断面図であり、図３（ｂ）は、従来用いられてきた半導体装置のアライメントマーク付近を拡大した断面図である。3A is an enlarged cross-sectional view of the vicinity of the alignment mark of the semiconductor device according to the present embodiment, and FIG. 3B is an enlarged cross-sectional view of the vicinity of the alignment mark of a conventionally used semiconductor device. It is. 図４（ａ）及び（ｂ）は、本実施の形態に係る半導体装置及び従来の半導体装置のアライメントマーク全体を走査した場合（測定Ｌ）の反射強度を示すグラフ図である。4A and 4B are graphs showing the reflection intensity when the entire alignment mark of the semiconductor device according to the present embodiment and the conventional semiconductor device is scanned (measurement L). 図５（ａ）及び（ｂ）は、本実施の形態に係る半導体装置及び従来の半導体装置のアルミパターンを走査した場合（測定Ｍ）の反射強度を示すグラフ図である。FIGS. 5A and 5B are graphs showing the reflection intensity when the aluminum pattern of the semiconductor device according to the present embodiment and the conventional semiconductor device is scanned (measurement M). 図６（ａ）及び（ｂ）は、本実施の形態に係る半導体装置及び従来の半導体装置のアルミパターン以外を走査した場合（測定Ｎ）の反射強度を示すグラフ図である。6 (a) and 6 (b) are graphs showing the reflection intensity when scanning a portion other than the aluminum pattern of the semiconductor device according to the present embodiment and the conventional semiconductor device (measurement N). 図７（ａ）〜（ｅ）は、本実施の形態に係る半導体装置の製造工程の一例を示す断面図である。7A to 7E are cross-sectional views illustrating an example of the manufacturing process of the semiconductor device according to the present embodiment.

（半導体装置の構成）
図１Ａは、実施の形態に係る半導体装置の構成の一例を示す概略平面図である。また、図１Ｂは、実施の形態に係る半導体装置の構成の一例を示す概略断面図である。 (Configuration of semiconductor device)
FIG. 1A is a schematic plan view illustrating an example of the configuration of the semiconductor device according to the embodiment. FIG. 1B is a schematic cross-sectional view illustrating an example of the configuration of the semiconductor device according to the embodiment.

この半導体装置１は、半導体プロセスによって作製された、位置合わせ用のアライメントマーク２と、磁気抵抗素子３Ａ及びバイポーラトランジスタ３Ｂを含む回路部３とを有する。   The semiconductor device 1 includes an alignment mark 2 for alignment, which is manufactured by a semiconductor process, and a circuit unit 3 including a magnetoresistive element 3A and a bipolar transistor 3B.

アライメントマーク２は、シリコン基板２４上に形成された酸化膜２３と、酸化膜２３上に形成された低反射パターンとしてのＮｉＣｏパターン２２と、ＮｉＣｏパターン２２上に形成された窒化膜２１と、窒化膜２１上に形成された高反射パターンとしてのアルミパターン２０とを有する。   The alignment mark 2 includes an oxide film 23 formed on the silicon substrate 24, a NiCo pattern 22 as a low reflection pattern formed on the oxide film 23, a nitride film 21 formed on the NiCo pattern 22, and a nitride film And an aluminum pattern 20 as a highly reflective pattern formed on the film 21.

磁気抵抗素子３Ａは、シリコン基板２４上に形成された酸化膜２３と、酸化膜２３上に形成された磁気抵抗膜としてのＮｉＣｏパターン３１と、ＮｉＣｏパターン３１上に形成された窒化膜２１と、窒化膜２１に開口部を設けてＮｉＣｏパターン３１上に形成されたアルミ電極３０とを有する。   The magnetoresistive element 3A includes an oxide film 23 formed on the silicon substrate 24, a NiCo pattern 31 as a magnetoresistive film formed on the oxide film 23, a nitride film 21 formed on the NiCo pattern 31, The nitride film 21 is provided with an opening and an aluminum electrode 30 formed on the NiCo pattern 31.

バイポーラトランジスタ３Ｂは、シリコン基板２４に形成されたコレクタ３５、エミッタ３６及びベース３７と、シリコン基板２４上に形成された酸化膜２３と、酸化膜２３上に形成された窒化膜２１と、酸化膜２３及び窒化膜２１に開口を設けてコレクタ３５上に形成されたアルミ電極３２と、エミッタ３６上に形成されたアルミ電極３３と、ベース３７上に形成されたアルミ電極３４とを有する。   The bipolar transistor 3B includes a collector 35, an emitter 36 and a base 37 formed on the silicon substrate 24, an oxide film 23 formed on the silicon substrate 24, a nitride film 21 formed on the oxide film 23, and an oxide film. 23 and the nitride film 21 are provided with an aluminum electrode 32 formed on the collector 35, an aluminum electrode 33 formed on the emitter 36, and an aluminum electrode 34 formed on the base 37.

図２は、本発明の実施の形態に係る半導体装置の構成の一例を示す概略平面図である。   FIG. 2 is a schematic plan view showing an example of the configuration of the semiconductor device according to the embodiment of the present invention.

半導体装置１は、直径４インチのシリコンウエハ１０上に複数作製される。ここで、シリコンウエハ１０は、裏面の荒さが各領域で均一ではないため、アライメントマーク２が作製される前は、裏面の荒さが影響してシリコンウエハ１０自体の反射率が各領域において異なる値となる。   A plurality of semiconductor devices 1 are manufactured on a silicon wafer 10 having a diameter of 4 inches. Here, since the roughness of the back surface of the silicon wafer 10 is not uniform in each region, the reflectance of the silicon wafer 10 itself is different in each region due to the roughness of the back surface before the alignment mark 2 is produced. It becomes.

一例として、シリコンウエハ１０の領域を「ＣＥＮＴＥＲ」、「ＬＥＦＴ」、「ＲＩＧＨＴ」、「ＴＯＰ」、「ＢＯＴＴＯＭ」と分けたとき、後述する図６（ｂ）に示すように各領域の半導体装置１Ｃｅｎｔｅｒ、１Ｌｅｆｔ、１Ｒｉｇｈｔ、１Ｔｏｐ、１Ｂｏｔｔｏｍの反射率がばらつく。 As an example, when the region of the silicon wafer 10 is divided into “CENTER”, “LEFT”, “RIGHT”, “TOP”, and “BOTTOM”, the semiconductor device 1 in each region as shown in FIG. The reflectance of Center , 1 Left , 1 Right , 1 Top , and 1 Bottom varies.

（反射率の測定）
アライメントマークの反射率を測定するため、図３（ａ）及び（ｂ）に示す２つの例を比較した。 (Measurement of reflectance)
In order to measure the reflectance of the alignment mark, two examples shown in FIGS. 3A and 3B were compared.

図３（ａ）は、本実施の形態に係る半導体装置のアライメントマーク付近を拡大した断面図であり、図３（ｂ）は、従来用いられてきた半導体装置のアライメントマーク付近を拡大した断面図である。   3A is an enlarged cross-sectional view of the vicinity of the alignment mark of the semiconductor device according to the present embodiment, and FIG. 3B is an enlarged cross-sectional view of the vicinity of the alignment mark of a conventionally used semiconductor device. It is.

図３（ａ）に示すように、半導体装置１の上方からアライメントマーク２全体を走査する場合を測定Ｌ、アルミパターン２０を走査する場合を測定Ｍ、ＮｉＣｏパターン２２を走査する場合を測定Ｎとする。なお、各測定は、波長１３００ｎｍのレーザー光を照射して、その反射光の強度を測定し、照射光と反射光の強度比から反射率を算出することで行う。   As shown in FIG. 3A, the measurement L is the case where the entire alignment mark 2 is scanned from above the semiconductor device 1, the measurement M is the case where the aluminum pattern 20 is scanned, and the measurement N is the case where the NiCo pattern 22 is scanned. To do. Each measurement is performed by irradiating a laser beam having a wavelength of 1300 nm, measuring the intensity of the reflected light, and calculating the reflectance from the intensity ratio of the irradiated light and the reflected light.

また、図３（ｂ）に示すように、従来のアライメントマーク４全体を走査する場合を測定Ｌ、アルミパターン２０を走査する場合を測定Ｍ、アルミパターン２０以外の低反射パターンを走査する場合を測定Ｎとする。   Further, as shown in FIG. 3B, when the entire conventional alignment mark 4 is scanned, the measurement L, when the aluminum pattern 20 is scanned, the measurement M, and when the low reflection pattern other than the aluminum pattern 20 is scanned. Let it be measurement N.

図４（ａ）及び（ｂ）は、本実施の形態に係る半導体装置及び従来の半導体装置のアライメントマーク全体を走査した場合（測定Ｌ）の反射強度を示すグラフ図である。また、図５（ａ）及び（ｂ）は、本実施の形態に係る半導体装置及び従来の半導体装置のアルミパターンを走査した場合（測定Ｍ）の反射強度を示すグラフ図である。また、図６（ａ）及び（ｂ）は、本実施の形態に係る半導体装置及び従来の半導体装置のアルミパターン以外を走査した場合（測定Ｎ）の反射強度を示すグラフ図である。   4A and 4B are graphs showing the reflection intensity when the entire alignment mark of the semiconductor device according to the present embodiment and the conventional semiconductor device is scanned (measurement L). 5A and 5B are graphs showing the reflection intensity when the aluminum pattern of the semiconductor device according to the present embodiment and the conventional semiconductor device is scanned (measurement M). 6 (a) and 6 (b) are graphs showing the reflection intensity when scanning a region other than the aluminum pattern of the semiconductor device according to the present embodiment and the conventional semiconductor device (measurement N).

シリコンウエハ１０の各領域における半導体装置１Ｃｅｎｔｅｒ、１Ｌｅｆｔ、１Ｒｉｇｈｔ、１Ｔｏｐ、１Ｂｏｔｔｏｍのいずれにおいても、図５（ａ）に示すように、アルミパターン２０の反射率のばらつきが少ない。また、図６（ａ）に示すように、ＮｉＣｏパターン２２の反射率のばらつきが少ない。さらに、図４（ａ）に示すように、アルミパターン２０の反射率とＮｉＣｏパターン２２の反射率との差が２５％程度である。 In any of the semiconductor devices 1 Center , 1 Left , 1 Right , 1 Top , and Bottom in each region of the silicon wafer 10, there is little variation in the reflectance of the aluminum pattern 20 as shown in FIG. Further, as shown in FIG. 6A, the variation in the reflectance of the NiCo pattern 22 is small. Further, as shown in FIG. 4A, the difference between the reflectance of the aluminum pattern 20 and the reflectance of the NiCo pattern 22 is about 25%.

一方、シリコンウエハ１０の各領域における従来の半導体装置１Ｃｅｎｔｅｒ、１Ｌｅｆｔ、１Ｒｉｇｈｔ、１Ｔｏｐ、１Ｂｏｔｔｏｍにおいて、図５（ｂ）に示すように、アルミパターン２０の反射率が多少ばらつき、かつ図５（ａ）の場合に比べて反射率が劣る。また、図６（ｂ）に示すように、アルミパターン２０以外の領域の反射率がばらつき、最大１０％程度の差がある。さらに、図４（ｂ）に示すように、アルミパターン２０の反射率とアルミパターン２０以外の領域の反射率との差が最大でも１０％程度、最小では数％であり、本実施の形態の半導体装置１に比べてコントラストが低い。 On the other hand, in the conventional semiconductor devices 1 Center , 1 Left , 1 Right , 1 Top , and 1 Bottom in each region of the silicon wafer 10, the reflectivity of the aluminum pattern 20 varies somewhat as shown in FIG. The reflectance is inferior compared to the case of FIG. Further, as shown in FIG. 6B, the reflectance of the region other than the aluminum pattern 20 varies, and there is a difference of about 10% at the maximum. Further, as shown in FIG. 4B, the difference between the reflectance of the aluminum pattern 20 and the reflectance of the region other than the aluminum pattern 20 is about 10% at the maximum and several% at the minimum. The contrast is lower than that of the semiconductor device 1.

（製造工程）
図７（ａ）〜（ｅ）は、本実施の形態に係る半導体装置の製造工程の一例を示す断面図である。 (Manufacturing process)
7A to 7E are cross-sectional views illustrating an example of the manufacturing process of the semiconductor device according to the present embodiment.

まず、図７（ａ）に示すように、シリコン基板２４にバイポーラトランジスタ３Ｂのコレクタ３５、エミッタ３６及びベース３７を形成する。   First, as shown in FIG. 7A, the collector 35, the emitter 36, and the base 37 of the bipolar transistor 3B are formed on the silicon substrate 24.

次に、図７（ｂ）に示すように、シリコン基板２４上にＳｉＯ２等の酸化膜２３をプラズマＣＶＤ法又は熱酸化法等により形成する。なお、適宜マスクの形成やエッチング等により酸化膜２３に開口を設ける。 Next, as shown in FIG. 7B, an oxide film 23 such as SiO 2 is formed on the silicon substrate 24 by a plasma CVD method or a thermal oxidation method. Note that an opening is provided in the oxide film 23 by appropriately forming a mask, etching, or the like.

次に、図７（ｃ）に示すように、酸化膜２３上にＮｉＣｏパターン２２及びＮｉＣｏパターン３１を同時にプラズマＣＶＤ法又はスパッタリング等により形成する。   Next, as shown in FIG. 7C, a NiCo pattern 22 and a NiCo pattern 31 are simultaneously formed on the oxide film 23 by plasma CVD or sputtering.

次に、図７（ｄ）に示すように、ＮｉＣｏパターン２２、３１、酸化膜２３上にＳｉＮｘ等のプラズマＣＶＤ法により窒化膜２１を形成する。 Next, as shown in FIG. 7D, a nitride film 21 is formed on the NiCo patterns 22 and 31 and the oxide film 23 by plasma CVD using SiN x or the like.

次に、図７（ｅ）に示すように、アルミパターン２０、アルミ電極３０、３２、３３を同時にスパッタリング等により形成する。   Next, as shown in FIG. 7E, an aluminum pattern 20 and aluminum electrodes 30, 32, and 33 are simultaneously formed by sputtering or the like.

（実施の形態の効果）
上記した実施の形態によると、アライメントマーク２の低反射パターンにＮｉＣｏパターン２２を用いたため、低反射パターンの反射率がシリコン基板２４の裏面の荒さの影響を受けず、シリコンウエハ１０のいずれの領域から半導体装置１を作製したとしても低反射パターンの反射率のばらつきが少なくなる。これにより、高反射パターンであるアルミパターン２０と低反射パターンであるＮｉＣｏパターン２２との反射率の差のばらつきも少なくなり、アライメントマーク２の識別性を確保できる。 (Effect of embodiment)
According to the above-described embodiment, since the NiCo pattern 22 is used for the low reflection pattern of the alignment mark 2, the reflectance of the low reflection pattern is not affected by the roughness of the back surface of the silicon substrate 24, and any region of the silicon wafer 10 is used. Even if the semiconductor device 1 is manufactured from the above, the variation in the reflectance of the low reflection pattern is reduced. Thereby, the dispersion | variation in the difference of the reflectance of the aluminum pattern 20 which is a high reflection pattern, and the NiCo pattern 22 which is a low reflection pattern also decreases, and the identification property of the alignment mark 2 is securable.

また、ＮｉＣｏパターン２２は、磁気抵抗素子３ＡのＮｉＣｏパターン３１の作製工程において同時に作製し、アルミパターン２０は、アルミ電極３０、３２、３３、３４の作製工程において同時に作製するため、半導体装置１の製造工程を増加させることがない。   Further, since the NiCo pattern 22 is simultaneously formed in the manufacturing process of the NiCo pattern 31 of the magnetoresistive element 3A, and the aluminum pattern 20 is simultaneously manufactured in the manufacturing process of the aluminum electrodes 30, 32, 33, and 34, the semiconductor device 1 The manufacturing process is not increased.

なお、本発明は、上記した実施の形態に限定されず、本発明の技術思想を逸脱あるいは調整しない範囲内で種々の変形が可能である。例えば、低反射パターン及び高反射パターンの材料は、ＮｉＣｏ及びＡｌに限らず低反射パターンと高反射パターンの反射率の差がアライメントマークを識別する装置又は利用者の識別能力内にあれば他の材料を用いることができる。   The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from or adjusting the technical idea of the present invention. For example, the material of the low-reflection pattern and the high-reflection pattern is not limited to NiCo and Al, and other materials may be used as long as the difference in reflectance between the low-reflection pattern and the high-reflection pattern is within the identification ability of the apparatus or user that identifies the alignment mark. Materials can be used.

１ 半導体装置
２ アライメントマーク
３ 回路部
３Ａ 磁気抵抗素子
３Ｂ バイポーラトランジスタ
４ アライメントマーク
１０ シリコンウエハ
２０ アルミパターン
２１ 窒化膜
２２ ＮｉＣｏパターン
２３ 酸化膜
２４ シリコン基板
３０、３２、３３、３４ アルミ電極
３１ ＮｉＣｏパターン
３５ コレクタ
３６ エミッタ
３７ ベース

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Alignment mark 3 Circuit part 3A Magnetoresistive element 3B Bipolar transistor 4 Alignment mark 10 Silicon wafer 20 Aluminum pattern 21 Nitride film 22 NiCo pattern 23 Oxide film 24 Silicon substrates 30, 32, 33, 34 Aluminum electrode 31 NiCo pattern 35 Collector 36 Emitter 37 Base

Claims (3)

半導体基板と、
前記半導体基板上に少なくとも第１の層と第２の層とを含んで形成される回路部と、
前記半導体基板上に前記回路部の前記第１の層と同工程において形成される低反射パターンと、
前記低反射パターン上に形成され、前記回路部の前記第２の層と同工程において形成される高反射パターンとを有する半導体装置。 A semiconductor substrate;
A circuit unit formed on the semiconductor substrate including at least a first layer and a second layer;
A low reflection pattern formed on the semiconductor substrate in the same step as the first layer of the circuit unit;
A semiconductor device having a high reflection pattern formed on the low reflection pattern and formed in the same step as the second layer of the circuit portion. 前記第１の層は、磁気抵抗膜であり、
前記第２の層は、磁気抵抗膜と電気的に接続される電極である請求項１に記載の半導体装置。 The first layer is a magnetoresistive film;
The semiconductor device according to claim 1, wherein the second layer is an electrode electrically connected to the magnetoresistive film. 半導体基板上に回路部用のパターンと低反射パターンとを含む第１の層を形成する工程と、
前記第１の層上に前記回路部用のパターンと高反射パターンとを含む第２の層を形成する工程とを有する半導体装置の製造方法。 Forming a first layer including a circuit portion pattern and a low reflection pattern on a semiconductor substrate;
Forming a second layer including the circuit portion pattern and the highly reflective pattern on the first layer.
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