JP2012514808A - メモリシステムコントローラ - Google Patents
メモリシステムコントローラ Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
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- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1056—Simplification
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
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- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
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- Human Computer Interaction (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
Description
本開示は、メモリシステムコントローラのための方法およびデバイスを含む。1つ以上の実施形態において、メモリシステムコントローラは、システムコントローラに通信可能に結合されたホストインターフェースを含む。システムコントローラは多数のメモリインターフェースを有し、多数のメモリインターフェースに通信可能に結合された複数のインテリジェント記憶ノードを制御するように構成される。システムコントローラは、物理メモリアドレスと論理メモリアドレスとの間をマップするように構成される論理、および複数のインテリジェント記憶ノードにわたりウェアレベルを管理するように構成される論理を含む。
Claims (42)
- メモリシステムコントローラであって、
ホストインターフェースと、
前記ホストインターフェースに通信可能に結合され、多数のメモリインターフェースを有する、システムコントローラと、を備え、
前記システムコントローラは、前記多数のメモリインターフェースに通信可能に結合された複数のインテリジェントNAND記憶ノード(INSN)を制御するように構成され、前記システムコントローラは、物理メモリアドレスと論理メモリアドレスとの間をマップするように構成される論理を含み、論理は前記複数のINSNにわたりウェアレベルを管理するように構成される、メモリシステムコントローラ。 - 前記メモリインターフェースは、同期メモリインターフェースである、請求項1に記載のメモリシステムコントローラ。
- 前記INSNの第1の部分は、前記多数の同期メモリインターフェースのうちの1つと並列に通信可能に結合される、請求項2に記載のメモリシステムコントローラ。
- 前記INSNの第2の部分は、前記多数の同期メモリインターフェースのうちの異なる1つと並列に通信可能に結合される、請求項3に記載のメモリシステムコントローラ。
- 前記メモリインターフェースは、シリアルメモリインターフェースである、請求項1に記載のメモリシステムコントローラ。
- 前記システムコントローラは、論理ブロック情報なしで、物理ページメモリアクセスリクエストを生成するように構成される、請求項5に記載のメモリシステムコントローラ。
- 前記多数のシリアルメモリインターフェースのそれぞれは、それらに通信可能に結合される少なくとも2つのINSNと通信するように構成される、請求項5に記載のメモリシステムコントローラ。
- 前記システムコントローラは、前記INSNの全てにわたりウェアレベルを管理するように構成される論理を含む、請求項5に記載のメモリシステムコントローラ。
- 前記INSNはそれぞれ、多数のメモリデバイスを有する、請求項1〜8のいずれか1つに記載されるメモリシステムコントローラ。
- 前記多数のINSNにわたりウェアレベルを管理するように構成される前記論理は、特定のINSNの前記多数のメモリデバイスにわたりウェアレベリングを管理するための論理を含む、請求項9に記載のメモリシステムコントローラ。
- 前記多数のINSNにわたりウェアレベルを管理するように構成される前記論理は、複数のINSNの前記多数のメモリデバイスにわたりウェアレベリングを管理するように構成される論理を含む、請求項9に記載のメモリシステムコントローラ。
- 前記多数のINSNにわたりウェアレベルを管理するように構成される前記論理は、全てのINSNの全てのメモリデバイスにわたりウェアレベリングを管理するように構成される論理を含む、請求項11に記載のメモリシステムコントローラ。
- メモリシステムであって、
システムコントローラおよびホストインターフェース(SCHI)であって、
ホストインターフェースと、
前記ホストインターフェースに通信可能に結合され、少なくとも2つのシリアルメモリインターフェースを有する、メモリシステムコントローラと、
前記少なくとも2つのシリアルメモリインターフェースに通信可能に結合される複数の記憶ノードと、を含む、システムコントローラおよびホストインターフェース(SCHI)を備え、
前記メモリシステムコントローラは、前記複数の記憶ノードのために中央管理された物理アドレスから論理アドレスへの変換を提供することと、前記複数の記憶ノードにわたりウェアレベリングを管理することと、を含む、前記複数の記憶ノードを制御するように構成される、メモリシステム。 - 前記複数の記憶ノードは、インテリジェントNAND記憶ノード(INSN)である、請求項13に記載のメモリシステム。
- 前記複数の記憶ノードは、多数のメモリデバイスを含む、請求項13に記載のメモリシステム。
- 前記複数の記憶ノードは、それぞれ、前記多数のメモリデバイスに通信可能に結合されたノードメモリコントローラを含む、請求項15に記載のメモリシステム。
- 前記多数のメモリデバイスは、NANDフラッシュメモリデバイスである、請求項16に記載のメモリシステム。
- 各ノードメモリコントローラは、オープンNANDフラッシュインターフェース(ONFi)によって前記多数のNANDフラッシュメモリデバイスに通信可能に結合される、請求項17に記載のメモリシステム。
- 前記複数の記憶ノードは、それぞれ、マルチチップパッケージで構成される、請求項13〜18のいずれか1つに記載される前記メモリシステム。
- 前記マルチチップパッケージは、20未満のピンを有する、請求項19に記載のメモリシステム。
- 前記マルチチップパッケージは、データおよび制御信号のための3つ以下のピンを有する、請求項20に記載のメモリシステム。
- 前記複数の記憶ノードは固体ドライブである、請求項13〜15のいずれかに記載のメモリシステム。
- メモリシステムであって、
複数のインテリジェントNAND記憶ノード(INSN)と、
第1のシリアルインターフェースを介して前記複数のINSNの第1の部分に通信可能に結合され、第2のシリアルインターフェースを通して前記複数のINSNの第2の部分に通信可能に結合されたメモリシステムコントローラと、を備えるメモリシステムであって
前記メモリシステムコントローラは、ホストシステムによって利用される論理アドレスと前記複数のINSNによって利用される物理アドレスとの間をマップするように構成され、前記メモリシステムコントローラは、前記複数のINSNにわたりウェアレベリングを管理するように構成される、メモリシステム。 - 前記複数のINSNの前記第1の部分は、複数のINSNを含む、請求項23に記載のメモリシステム。
- 前記複数のINSNの前記第2の部分は、複数のINSNを含む、請求項23〜24のいずれか1つに記載のメモリシステム。
- 前記第1および第2のシリアルインターフェースはシリアル通信バスであり、前記複数のINSNの前記第1の部分は前記第1のシリアル通信バスへのデイジーチェーンで配列されており、前記複数のINSNの前記第2の部分は前記第2のシリアル通信バスへのデイジーチェーンで配列されている、請求項23〜24のいずれか1つに記載のメモリシステム。
- 前記INSNのそれぞれは、バス管理モジュールを含む、請求項26に記載のメモリシステム。
- 各バス管理モジュールは、前記ノードメモリコントローラに通信可能に結合され、前記メモリシステムコントローラにデータを伝送するためにシリアル通信バスを制御するように構成される、請求項27に記載のメモリシステム。
- 前記複数のINSNは、それぞれ、多数のNANDフラッシュメモリデバイスを含み、ノードコントローラは、その上の前記NANDフラッシュメモリデバイスと前記ノードコントローラとの間に通信可能に結合される、請求項27に記載のメモリシステム。
- 各ノードコントローラは、NANDフラッシュメモリデバイスアクセスを制御し、NANDフラッシュメモリデバイスの不具合を管理するように構成される、請求項29に記載のメモリシステム。
- 各ノードコントローラは、前記NANDフラッシュメモリデバイスに記憶されるデータ内のエラーを検出および修正するように構成される、請求項29に記載のメモリシステム。
- メモリシステムの動作方法であって、
多数のシリアル通信インターフェースを使用して、複数の記憶ノードとメモリシステムコントローラとの間の通信を確立することであって、前記複数の記憶ノードのそれぞれは、特定のシリアル通信インターフェースと多数のメモリデバイスとの間に通信可能に結合されるノードコントローラを有する、通信を確立することと、
前記メモリシステムコントローラにおいて前記複数の記憶ノードの間のウェアレベリングを管理することと、
前記メモリシステムコントローラにおいて前記複数の記憶ノードのために論理アドレスおよび物理アドレスの間を変換することと、を含む、方法。 - 前記メモリシステムコントローラにおいて特定の記憶ノードの前記多数のメモリデバイスの間のウェアレベリングを管理することを含む、請求項32に記載の方法。
- 特定の記憶ノードに関連付けられた前記ノードコントローラにおいて、前記特定の記憶ノードの前記多数のメモリデバイスの間のエラー修正を管理することを含む、請求項33に記載の方法。
- 前記メモリシステムコントローラにおいて、複数の記憶ノードの前記多数のメモリデバイスの間のウェアレベリングを管理することを含む、請求項34に記載の方法。
- 複数の記憶ノードの前記多数のメモリデバイスの間のウェアレベリングを管理することは、前記多数のメモリデバイスの間のウェアの差異を検出することを含む、請求項35に記載の方法。
- 複数の記憶ノードの前記多数のメモリデバイスの間のウェアレベリングを管理することは、個別のメモリデバイス内の制限を越えるウェアを検出することを含む、請求項35〜36のいずれか1つに記載の方法。
- 前記制限は事前設定された固定の制限である、請求項37に記載の方法。
- 前記制限は動的な制限である、請求項37に記載の方法。
- メモリシステムを動作するための方法であって、
ホストシステムからの論理アドレスの範囲に対応して、書き込みコマンドおよび関連付けられたデータを受信することと、
メモリシステムコントローラにおいて、多数の記憶ノードの間のウェアレベリングに基づき、前記関連付けられたデータを記憶する前記多数の記憶ノードの特定の記憶ノードを決定することと、
論理アドレスの範囲を前記特定の記憶ノードの物理アドレスにマップすることと、
記憶ノードのデイジーチェーンを通して、前記特定の記憶ノードへ逐次的に前記データを伝送することと、を含む、方法。 - 前記多数の記憶ノードはインテリジェントNAND記憶ノード(INSN)であり、前記方法は、論理ブロックを参照せずに、前記INSNへ、前記メモリシステムコントローラによって物理ページアクセスリクエストを通信することを含む、請求項40に記載の方法。
- 記憶ノードのデイジーチェーンを通して、逐次的に前記データを伝送する前に、前記メモリシステムコントローラ上で、生NANDコマンドにディスクドライブプロトコルを変換することを含む、請求項40〜41のいずれかに記載の方法。
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US12/350,686 US8412880B2 (en) | 2009-01-08 | 2009-01-08 | Memory system controller to manage wear leveling across a plurality of storage nodes |
US12/350,686 | 2009-01-08 | ||
PCT/US2009/006740 WO2010080141A2 (en) | 2009-01-08 | 2009-12-30 | Memory system controller |
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JP5453661B2 JP5453661B2 (ja) | 2014-03-26 |
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US (2) | US8412880B2 (ja) |
EP (1) | EP2377027B1 (ja) |
JP (1) | JP5453661B2 (ja) |
KR (1) | KR101274306B1 (ja) |
CN (1) | CN102272745B (ja) |
TW (2) | TWI484341B (ja) |
WO (1) | WO2010080141A2 (ja) |
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