JP2012512490A5 - - Google Patents

Download PDF

Info

Publication number
JP2012512490A5
JP2012512490A5 JP2011542254A JP2011542254A JP2012512490A5 JP 2012512490 A5 JP2012512490 A5 JP 2012512490A5 JP 2011542254 A JP2011542254 A JP 2011542254A JP 2011542254 A JP2011542254 A JP 2011542254A JP 2012512490 A5 JP2012512490 A5 JP 2012512490A5
Authority
JP
Japan
Prior art keywords
unit
coprocessor
series
processor
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011542254A
Other languages
English (en)
Japanese (ja)
Other versions
JP5676470B2 (ja
JP2012512490A (ja
Filing date
Publication date
Priority claimed from US12/337,159 external-priority patent/US7930519B2/en
Application filed filed Critical
Publication of JP2012512490A publication Critical patent/JP2012512490A/ja
Publication of JP2012512490A5 publication Critical patent/JP2012512490A5/ja
Application granted granted Critical
Publication of JP5676470B2 publication Critical patent/JP5676470B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2011542254A 2008-12-17 2009-12-10 共有された命令ストリームを伴うコプロセッサユニット Active JP5676470B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/337,159 2008-12-17
US12/337,159 US7930519B2 (en) 2008-12-17 2008-12-17 Processor with coprocessor interfacing functional unit for forwarding result from coprocessor to retirement unit
PCT/US2009/067409 WO2010077751A2 (en) 2008-12-17 2009-12-10 Coprocessor unit with shared instruction stream

Publications (3)

Publication Number Publication Date
JP2012512490A JP2012512490A (ja) 2012-05-31
JP2012512490A5 true JP2012512490A5 (enExample) 2013-01-17
JP5676470B2 JP5676470B2 (ja) 2015-02-25

Family

ID=41820594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011542254A Active JP5676470B2 (ja) 2008-12-17 2009-12-10 共有された命令ストリームを伴うコプロセッサユニット

Country Status (6)

Country Link
US (1) US7930519B2 (enExample)
EP (1) EP2374060B1 (enExample)
JP (1) JP5676470B2 (enExample)
KR (1) KR101507096B1 (enExample)
CN (1) CN102282540B (enExample)
WO (1) WO2010077751A2 (enExample)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7391865B2 (en) 1999-09-20 2008-06-24 Security First Corporation Secure data parser method and system
CN101375284B (zh) 2004-10-25 2012-02-22 安全第一公司 安全数据分析方法和系统
CN101401341B (zh) 2005-11-18 2016-06-01 安全第一公司 安全数据解析方法和系统
US8538015B2 (en) * 2007-03-28 2013-09-17 Intel Corporation Flexible architecture and instruction for advanced encryption standard (AES)
JP4868012B2 (ja) * 2009-03-09 2012-02-01 日本電気株式会社 コンピュータシステム、コンピュータシステムの制御方法、及びプログラム
US8745372B2 (en) 2009-11-25 2014-06-03 Security First Corp. Systems and methods for securing data in motion
JP4809497B2 (ja) 2010-02-25 2011-11-09 ファナック株式会社 複数の独立したシーケンスプログラムを並列実行するプログラマブルコントローラ
AU2011235068B2 (en) * 2010-03-31 2015-10-01 Security First Corp. Systems and methods for securing data in motion
EP2577936A2 (en) 2010-05-28 2013-04-10 Lawrence A. Laurich Accelerator system for use with secure data storage
US9304774B2 (en) 2011-02-04 2016-04-05 Qualcomm Incorporated Processor with a coprocessor having early access to not-yet issued instructions
US20120236010A1 (en) * 2011-03-15 2012-09-20 Boris Ginzburg Page Fault Handling Mechanism
US8683175B2 (en) * 2011-03-15 2014-03-25 International Business Machines Corporation Seamless interface for multi-threaded core accelerators
US9405550B2 (en) * 2011-03-31 2016-08-02 International Business Machines Corporation Methods for the transmission of accelerator commands and corresponding command structure to remote hardware accelerator engines over an interconnect link
US9633407B2 (en) * 2011-07-29 2017-04-25 Intel Corporation CPU/GPU synchronization mechanism
SE537552C2 (sv) * 2011-12-21 2015-06-09 Mediatek Sweden Ab Digital signalprocessor
CN104137060B (zh) * 2011-12-30 2018-03-06 英特尔公司 高速缓存协处理单元
US9075623B2 (en) * 2012-01-18 2015-07-07 International Business Machines Corporation External auxiliary execution unit interface for format conversion of instruction from issue unit to off-chip auxiliary execution unit
EP3373105B1 (en) 2012-03-30 2020-03-18 Intel Corporation Apparatus and method for accelerating operations in a processor which uses shared virtual memory
WO2014031495A2 (en) * 2012-08-18 2014-02-27 Arteris SAS System translation look-aside buffer with request-based allocation and prefetching
US9582287B2 (en) * 2012-09-27 2017-02-28 Intel Corporation Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
US9594594B2 (en) * 2012-10-18 2017-03-14 Advanced Micro Devices, Inc. Media hardware resource allocation
US20140189333A1 (en) * 2012-12-28 2014-07-03 Oren Ben-Kiki Apparatus and method for task-switchable synchronous hardware accelerators
US9361116B2 (en) * 2012-12-28 2016-06-07 Intel Corporation Apparatus and method for low-latency invocation of accelerators
TWI477121B (zh) * 2012-12-28 2015-03-11 Askey Computer Corp 多級模組擴充系統及多級模組通訊方法
US10140129B2 (en) 2012-12-28 2018-11-27 Intel Corporation Processing core having shared front end unit
US9417873B2 (en) 2012-12-28 2016-08-16 Intel Corporation Apparatus and method for a hybrid latency-throughput processor
US10346195B2 (en) 2012-12-29 2019-07-09 Intel Corporation Apparatus and method for invocation of a multi threaded accelerator
US20140201408A1 (en) * 2013-01-17 2014-07-17 Xockets IP, LLC Offload processor modules for connection to system memory, and corresponding methods and systems
US10203958B2 (en) * 2013-07-15 2019-02-12 Texas Instruments Incorporated Streaming engine with stream metadata saving for context switching
USRE49652E1 (en) 2013-12-16 2023-09-12 Qualcomm Incorporated Power saving techniques in computing devices
US9535490B2 (en) * 2013-12-16 2017-01-03 Qualcomm Incorporated Power saving techniques in computing devices
CN104301253A (zh) * 2014-10-21 2015-01-21 合肥星服信息科技有限责任公司 线程池和共享池组合优化大负荷通讯服务器
US11449452B2 (en) * 2015-05-21 2022-09-20 Goldman Sachs & Co. LLC General-purpose parallel computing architecture
CN106325819B (zh) * 2015-06-17 2019-08-02 华为技术有限公司 计算机指令处理方法、协处理器和系统
US9727944B2 (en) 2015-06-22 2017-08-08 Apple Inc. GPU instruction storage
GB2544994A (en) * 2015-12-02 2017-06-07 Swarm64 As Data processing
US10037229B2 (en) * 2016-05-11 2018-07-31 International Business Machines Corporation Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
US11029659B2 (en) 2016-06-30 2021-06-08 Intel Corporation Method and apparatus for remote field programmable gate array processing
US20180150124A1 (en) * 2016-11-28 2018-05-31 Qualcomm Incorporated Wifi memory power minimization
KR102235803B1 (ko) * 2017-03-31 2021-04-06 삼성전자주식회사 반도체 장치
US12299446B2 (en) 2017-06-28 2025-05-13 Texas Instruments Incorporated Streaming engine with stream metadata saving for context switching
US10437739B2 (en) * 2017-09-26 2019-10-08 Intel Corporation Low-latency accelerator
CN108196849A (zh) * 2018-01-12 2018-06-22 江苏华存电子科技有限公司 一种低延迟指令调度器
CN110618833B (zh) * 2018-06-19 2022-01-11 深圳大心电子科技有限公司 指令处理方法及存储控制器
US10776125B2 (en) 2018-12-05 2020-09-15 Apple Inc. Coprocessor memory ordering table
US10909054B2 (en) * 2019-04-26 2021-02-02 Samsung Electronics Co., Ltd. Method for status monitoring of acceleration kernels in a storage device and storage device employing the same
US11816037B2 (en) 2019-12-12 2023-11-14 Advanced Micro Devices, Inc. Enhanced page information co-processor
US11429451B2 (en) * 2020-01-22 2022-08-30 Microsoft Technology Licensing, Llc Managing exceptions on a shared resource
GB2630748A (en) * 2023-06-05 2024-12-11 Advanced Risc Mach Ltd Task delegation

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920004414B1 (ko) * 1990-06-21 1992-06-04 삼성전자 주식회사 프로세서와 코프로세서의 프로세서간 통신방식
JP2987308B2 (ja) * 1995-04-28 1999-12-06 松下電器産業株式会社 情報処理装置
US5764939A (en) 1995-10-06 1998-06-09 Lsi Logic Corporation RISC processor having coprocessor for executing circular mask instruction
DE69717369T2 (de) * 1996-08-27 2003-09-11 Matsushita Electric Ind Co Ltd Vielfadenprozessor zur Verarbeitung von mehreren Befehlsströmen unabhängig von einander durch eine flexible Durchsatzsteuerung in jedem Befehlsstrom
JP3189727B2 (ja) * 1997-04-15 2001-07-16 日本電気株式会社 コプロセッサ内蔵パケット型メモリｌｓｉ、それを用いたメモリシステム及びそれらの制御方法
US5923893A (en) 1997-09-05 1999-07-13 Motorola, Inc. Method and apparatus for interfacing a processor to a coprocessor
US6557065B1 (en) 1999-12-20 2003-04-29 Intel Corporation CPU expandability bus
EP1139222A1 (en) * 2000-03-31 2001-10-04 Texas Instruments Incorporated Prefetch for TLB cache
US20020010848A1 (en) 2000-05-29 2002-01-24 Shoichi Kamano Data processing system
US6754804B1 (en) 2000-12-29 2004-06-22 Mips Technologies, Inc. Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions
US7237090B1 (en) 2000-12-29 2007-06-26 Mips Technologies, Inc. Configurable out-of-order data transfer in a coprocessor interface
US6684305B1 (en) * 2001-04-24 2004-01-27 Advanced Micro Devices, Inc. Multiprocessor system implementing virtual memory using a shared memory, and a page replacement method for maintaining paged memory coherence
GB2378271B (en) * 2001-07-30 2004-12-29 Advanced Risc Mach Ltd Handling of coprocessor instructions in a data processing apparatus
US7260424B2 (en) 2002-05-24 2007-08-21 Schmidt Dominik J Dynamically configured antenna for multiple frequencies and bandwidths
US20030225816A1 (en) * 2002-06-03 2003-12-04 Morrow Michael W. Architecture to support multiple concurrent threads of execution on an arm-compatible processor
US8090928B2 (en) 2002-06-28 2012-01-03 Intellectual Ventures I Llc Methods and apparatus for processing scalar and vector instructions
US7421694B2 (en) * 2003-02-18 2008-09-02 Microsoft Corporation Systems and methods for enhancing performance of a coprocessor
KR101130361B1 (ko) * 2003-02-18 2012-09-18 마이크로소프트 코포레이션 코프로세서 내의 연산을 스트림라인하는 방법
US7079147B2 (en) * 2003-05-14 2006-07-18 Lsi Logic Corporation System and method for cooperative operation of a processor and coprocessor
JP2008538620A (ja) * 2005-01-25 2008-10-30 ルーシッド インフォメイション テクノロジー リミテッド モノリシック構成のシリコン・チップ上に多数のグラフィックス・コアを用いるグラフィック処理及び表示システム
US7647475B2 (en) 2006-09-06 2010-01-12 Mips Technologies, Inc. System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue
DE102007025397B4 (de) * 2007-05-31 2010-07-15 Advanced Micro Devices, Inc., Sunnyvale System mit mehreren Prozessoren und Verfahren zu seinem Betrieb
US8156307B2 (en) * 2007-08-20 2012-04-10 Convey Computer Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set

Similar Documents

Publication Publication Date Title
JP2012512490A5 (enExample)
US10318307B2 (en) Scalarization of vector processing
WO2007107707A3 (en) Computer architecture
JP2016526220A5 (enExample)
JP2012525620A5 (enExample)
WO2006083543A3 (en) Multithreading processor including thread scheduler based on instruction stall likelihood prediction
GB2456775B (en) Apparatus and method for performing permutation operations on data
US20170083329A1 (en) Write nullification
MY168503A (en) Cryptographic support instructions
WO2017048650A1 (en) Debug support for block-based processor
GB2517877A (en) Controlling an order for processing data elements during vector processing
JP2011238266A5 (enExample)
EP2796990A3 (en) Apparatus and method for supporting multi-modes of processor
US20170083322A1 (en) Multimodal targets in a block-based processor
GB2508312A (en) Instruction and logic to provide vector load-op/store-op with stride functionality
CN104583941B (zh) 用于在多线程处理系统中选择性激活恢复检查操作的方法和设备
JP2013518327A5 (enExample)
KR20100032399A (ko) 프로세서에서의 쓰레드 스케쥴링
WO2011087590A3 (en) Synchronizing simd vectors
GB201213316D0 (en) Exploiting an architected last-use operand indication in a computer system operand resource pool
EP3350687B1 (en) Store nullification in the target field
GB2520858A (en) Instruction set for message scheduling of SHA256 algorithm
US20150074353A1 (en) System and Method for an Asynchronous Processor with Multiple Threading
WO2012078735A3 (en) Performing function calls using single instruction multiple data (simd) registers
WO2015119886A1 (en) Method and apparatus for enabling a processor to generate pipeline control signals