JP2012243885A - Reference voltage generation circuit, drive unit, print head and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a reference voltage, having excellent temperature characteristics and a little variation for the variation of power supply voltage, as the reference voltage being applied to the drive unit of a light-emitting element.SOLUTION: The reference voltage generation circuit 100 generating a reference voltage Vref includes a first current mirror circuit 120 having a negative temperature coefficient dependent on the negative temperature coefficient of the base-emitter voltage of a bipolar transistor, and a second current mirror circuit 140 having a positive temperature coefficient dependent on the negative temperature coefficient. A current subtraction circuit 150 generates a current by subtracting the output current of the second current mirror circuit 140 from the output current of the first current mirror circuit 110, and outputs a reference voltage Vref proportional thereto.

Description

  The present invention relates to a reference voltage generating circuit that generates a reference voltage, and an image forming apparatus such as a driving device, a print head, and an electrophotographic printer using the reference voltage generating circuit.

  2. Description of the Related Art Conventionally, there are image forming apparatuses such as printers using an electrophotographic system in which an exposure unit is formed by arranging a large number of light emitting elements. As the light emitting element, a light emitting diode (hereinafter referred to as “LED”), an organic electroluminescence element (hereinafter referred to as “organic EL element”), a light emitting thyristor, and the like are used.

  In general, a light-emitting element as a driven element has temperature dependency and has a characteristic that its light output decreases as the temperature rises. In electrophotographic printers and the like, if the light output of the light emitting element fluctuates, the print density will fluctuate, which is not preferable. It is equipped with the structure which increases.

  For this reason, the drive current of the light emitting element is given to the drive device as being substantially proportional to the reference voltage, and temperature compensation is performed by giving a positive temperature coefficient to the reference voltage.

  In recent years, with the increase in the speed of printers, there has been a demand for an increase in the light output of the print head. The light output directivity of the LED is unidirectional and the light extraction efficiency is improved to increase the light output. For the purpose, for example, a distributed reflection (Distributed Bragg Ref1ector, hereinafter referred to as “DBR”) type LED as described in Patent Document 1 below has been used.

JP 2010-219220 A

  However, the conventional reference voltage generation circuit, drive device, print head, and image forming apparatus have the following problems.

  For example, in the case of adopting a DBR structure having a distributed reflection film as described in Patent Document 1 for the purpose of improving the directivity of light from the LED and thereby improving the light extraction efficiency, the chip temperature Due to the emission wavelength shift caused by, the reflectance by the distributed reflection film changes, and the apparent temperature coefficient of the LED emission output changes. Therefore, a phenomenon in which the light emission output increases due to the temperature rise occurs. To correct this phenomenon, it is necessary to reduce the drive current for driving the LED and to provide a negative temperature coefficient in the reference voltage generation circuit. However, the conventional reference voltage generation circuit has a characteristic with a positive or substantially zero temperature coefficient, and is inconvenient for use in an LED driving device having a DBR structure.

  A reference voltage generation circuit according to a first aspect of the present invention is a reference voltage generation circuit that generates a constant reference voltage when driven by a power supply voltage, and depends on a negative temperature coefficient of a base-emitter voltage of a bipolar transistor. A first current circuit having a first current mirror circuit having a negative temperature coefficient, and a second current having a positive temperature coefficient generated depending on the negative temperature coefficient of the base-emitter voltage of the bipolar transistor. A second current circuit having a current mirror circuit; and subtracting the output current of the second current mirror circuit from the output current of the first current mirror circuit to generate a subtraction current, and the reference voltage proportional to the subtraction current is And a current subtracting circuit for outputting to the output terminal.

  A reference voltage generating circuit according to a second invention is characterized in that a level shift circuit is provided in the reference current generating circuit according to the first invention. The level shift circuit is connected between the output side of the first current circuit, the output side of the second current circuit, and the input side of the current subtraction circuit, and transitions the level of the power supply voltage.

  According to a third aspect of the present invention, there is provided a driving device that receives the reference voltage generation circuit according to the first or second aspect and the reference voltage output from the reference voltage generation circuit, and generates a control voltage corresponding to the reference voltage. A control voltage generation circuit, a logic circuit, and a drive circuit. The logic circuit includes a power supply terminal to which a power supply voltage output from the first power supply is applied, and a ground terminal to which the control voltage is applied, and inputs a strobe signal and a data signal, and the strobe signal This is a circuit for controlling the output of a data signal to output a high level voltage substantially equal to the power supply voltage or a low level voltage substantially equal to the control voltage. Further, the drive circuit is a circuit to which the power supply voltage is applied and a drive current corresponding to the output voltage of the logic circuit is supplied to the driven element.

  According to a fourth aspect of the present invention, there is provided a print head comprising: the driving device according to the third aspect of the invention; and a light emitting element array in which a plurality of light emitting elements as the driven elements are arranged and emits light by the driving current. To do.

  According to a fifth aspect of the present invention, there is provided an image forming apparatus comprising the print head according to the fourth aspect, wherein the print head is exposed to form an image on a recording medium.

  According to the first, third and fourth inventions of the present invention, the current subtracting circuit causes the second current mirror having a positive temperature coefficient from the output current of the first current mirror circuit having the negative temperature coefficient. The output current of the circuit is subtracted, and a reference voltage proportional to the subtracted current is generated. Therefore, the positive temperature coefficient value is subtracted from the negative temperature coefficient value by a predetermined ratio, and a desired temperature coefficient having a relatively large negative value can be obtained. Further, the reference voltage value can be arbitrarily set independently of the temperature coefficient. As a result, it is possible to realize a driving device and a print head that match the temperature characteristics of various driven elements such as light emitting elements.

  According to the second, third, and fourth inventions, since the level shift circuit is provided, the constant current characteristic can be improved, and even if the power supply voltage fluctuates, the fluctuation of the reference voltage can be reduced. As a result, the driven element can be driven more stably.

  According to the image forming apparatus of the fifth invention, since the print head having the reference voltage generation circuit is employed, a high quality image forming apparatus excellent in space efficiency and light extraction efficiency can be realized.

FIG. 1 is a circuit diagram showing a configuration of the reference voltage generating circuit 100 in FIG. 6 according to the first embodiment of the present invention. FIG. 2 is a schematic configuration diagram illustrating the image forming apparatus according to the first exemplary embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing the configuration of the print head 13 in FIG. FIG. 4 is a perspective view showing the substrate unit in FIG. FIG. 5 is a block diagram showing the configuration of the printer control circuit in the image forming apparatus 1 of FIG. FIG. 6 is a circuit configuration diagram showing the print head 13 in FIG. FIG. 7 is a circuit diagram showing the main part of the drive device in FIG. FIG. 8 is a timing chart for explaining the printing operation of the print head 13 of FIG. FIG. 9 is a diagram for explaining the operation of the reference voltage generation circuit 100 of FIG. FIG. 10 is a circuit diagram showing a configuration of a reference voltage generating circuit according to the second embodiment of the present invention. FIG. 11 is a diagram for explaining the operation of the reference voltage generation circuit 100A of FIG.

  Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Image Forming Apparatus of Example 1)
FIG. 2 is a schematic configuration diagram illustrating the image forming apparatus according to the first embodiment of the present invention.
The image forming apparatus 1 is an electrophotographic color printer equipped with a print head using a light emitting element (for example, LED) as a driven element. The image forming apparatus 1 is black (K), yellow (Y), magenta (M), and There are four process units 10-1 to 10-4 for forming cyan (C) images of each color, and these are arranged in order from the upstream side of the conveyance path of the recording medium (for example, paper) 20. Yes. Since the internal configurations of the process units 10-1 to 10-4 are common, for example, the magenta process unit 10-3 will be described as an example.

  In the process unit 10-3, a photoconductor (for example, photoconductor drum) 11 as an image carrier is disposed so as to be rotatable in the arrow direction in FIG. Around the photosensitive drum 11, a charging device 12 that supplies electric charges to the surface of the photosensitive drum 11 and charges the surface of the photosensitive drum 11 in order from the upstream side in the rotation direction, and selectively applies light to the surface of the charged photosensitive drum 11. An exposure device (for example, a print head) 13 that forms an electrostatic latent image by irradiating with a light is disposed. Further, a developing device 14 for generating a visible image by attaching magenta (predetermined color) toner to the surface of the photosensitive drum 11 on which the electrostatic latent image is formed, and a visible image of the toner on the photosensitive drum 11. A cleaning device 15 for removing toner remaining after the transfer to the paper 20 is provided. Note that the drums or rollers used in these devices rotate by receiving power from a drive source (not shown) via a gear or the like.

  A paper cassette 21 for storing the paper 20 in a stacked state is mounted at the bottom of the image forming apparatus 1, and a hopping roller 22 for separating and transporting the paper 20 one by one is disposed above the paper cassette 21. Yes. On the downstream side of the hopping roller 22 in the transport direction of the paper 20, the paper 20 is sandwiched together with the pinch rollers 23 and 24, thereby correcting the skew of the paper 20 and the transport roller 25 for transporting the paper 20. A registration roller 26 to be conveyed to 10-1 is disposed. The hopping roller 22, the conveyance roller 25, and the registration roller 26 are rotated by receiving power from a driving source (not shown) via a gear or the like.

  At the positions facing the respective photosensitive drums 11 of the process units 10-1 to 10-4, transfer units 27 formed of semiconductive rubber or the like are respectively disposed. Each transfer device 27 has a potential difference between the surface potential of each photoconductor drum 11 and the surface potential of each of these transfer devices 27 at the time of transferring the visible image by the toner attached on the photoconductor drum 11 to the paper 20. A potential for applying the voltage is applied.

  A fixing device 28 is disposed downstream of the process unit 10-4. The fixing device 28 includes a heating roller having a built-in heater and a backup roller, and is a device that fixes the toner transferred onto the sheet 20 by pressurizing and heating. 30, pinch rollers 31 and 32 of a discharge unit, and a paper stacker unit 33 are provided. The discharge rollers 29 and 30 sandwich the paper 20 discharged from the fixing device 28 together with the pinch rollers 31 and 32 of the discharge unit and convey the paper 20 to the paper stacker unit 33. The fixing device 28, the discharge roller 29, and the like rotate when power is transmitted from a driving source (not shown) via a gear or the like.

The image forming apparatus 1 configured as described above operates as follows.
First, the sheets 20 stored in a stacked state in the sheet cassette 21 are separated and transported one by one from the top by the hopping roller 22. Subsequently, the sheet 20 is sandwiched between the conveyance roller 25, the registration roller 26, and the pinch rollers 23 and 24, and is conveyed between the photosensitive drum 11 and the transfer unit 27 of the process unit 10-1. Thereafter, the sheet 20 is sandwiched between the photosensitive drum 11 and the transfer unit 27, and the toner image is transferred to the recording surface thereof, and at the same time, the sheet 20 is conveyed by the rotation of the photosensitive drum 11. Similarly, the paper 20 sequentially passes through the process units 10-2 to 10-4, and the toner of each color obtained by developing the electrostatic latent image formed by each print head 13 by each developing device 14 in the process of passing. Images are sequentially transferred and superimposed on the recording surface.

  After the toner images of the respective colors are superimposed on the recording surface in this way, the paper 20 on which the toner image is fixed by the fixing device 28 is sandwiched between the discharge rollers 29 and 30 and the pinch rollers 31 and 32 to form an image. The paper is discharged to a paper stacker unit 33 outside the apparatus 1. Through the above process, a color image is formed on the paper 20.

(Print head of Example 1)
FIG. 3 is a schematic cross-sectional view showing the configuration of the print head 13 in FIG. FIG. 4 is a perspective view showing the substrate unit in FIG.

  The print head 13 shown in FIG. 3 has a base member 13a, and the substrate unit shown in FIG. 4 is fixed on the base member 13a. The board unit includes a printed wiring board 13b fixed on the base member 13a and a plurality of semiconductor composite chips 13c fixed on the printed wiring board 13b with an adhesive or the like. The semiconductor composite chip 13c is a chip formed by combining a light emitting element (for example, LED) and a driver monolithic integrated circuit (hereinafter referred to as “driver IC”). A light emitting element array 60 is arranged on the semiconductor composite chip 13c. A plurality of terminals (not shown) in each semiconductor composite chip 13c and wiring pads (not shown) on the printed wiring board 13b are electrically connected by bonding wires 13h.

  On the light emitting element array 60 in the plurality of semiconductor composite chips 13c, a lens array (for example, a rod lens array) 13d in which a large number of columnar optical elements are arranged is disposed, and the rod lens array 13d is fixed by a holder 13e. ing. The base member 13a, the printed wiring board 13b, and the holder 13e are fixed by clamp members 13f and 13g.

(Printer control circuit)
FIG. 5 is a block diagram showing the configuration of the printer control circuit in the image forming apparatus 1 of FIG.

  The printer control circuit includes a print control unit 40 disposed inside the printing unit in the image forming apparatus 1. The print control unit 40 includes a microprocessor, a read-only memory (ROM), a readable / writable memory (RAM), an input / output port for inputting / outputting signals, a timer, and the like, and a control signal from an image processing unit (not shown). The image forming apparatus has a function of performing a printing operation by controlling the entire image forming apparatus using SG1 and video signals (one-dimensionally arranged dot map data) SG2. The print control unit 40 includes four print heads 13 of the process units 10-1 to 10-4, a heater 28a of the fixing device 28, drivers 41 and 43, a paper suction port sensor 45, a paper discharge port sensor 46, a paper remaining amount. An amount sensor 47, a paper size sensor 48, a fixing device temperature sensor 49, a charging high-voltage power supply 50 that is turned on by a charge signal SGC, a transfer high-voltage power supply 51 that is turned on by a transfer signal SG4, and the like are connected. The driver 41 has a development / transfer process motor (PM) 42, the driver 43 has a paper feed motor (PM) 44, the charging high-voltage power supply 50 has a developing device 14, and the transfer high-voltage power supply 51 has a transfer device 27. Are connected to each other.

The printer control circuit having such a configuration performs the following operation.
When the printing control unit 40 receives a printing instruction in response to a control signal SGl from an image processing unit (not shown), first, the temperature sensor 49 detects whether or not the heater 28a in the fixing device 28 is within a usable temperature range. If not in the temperature range, the heater 28a is energized to heat the fixing device 28 to a usable temperature. Next, the development / transfer process motor 42 is rotated via the driver 41, and at the same time, the charging high-voltage power supply 50 is turned on by the charge signal SGC to charge the developing device 14.

  2 is detected by the remaining paper amount sensor 47 and the paper size sensor 48, and paper feeding suitable for the paper 20 is started. Here, a planetary gear mechanism (not shown) is connected to the paper feed motor 44 and can be rotated in both directions via a driver 43. Therefore, by changing the rotation direction of the paper feed motor 44, different paper feed transport rollers 25 in the image forming apparatus can be selectively driven.

  Each time a page of paper is printed, the paper feed motor 44 is first reversed to feed the set paper 20 by a preset amount until the paper inlet sensor 45 detects it. Subsequently, the sheet 20 is rotated forward and conveyed to a printing mechanism inside the image forming apparatus.

  When the paper 20 reaches a printable position, the print control unit 40 transmits a timing signal SG3 (including a main scanning synchronization signal and a sub scanning synchronization signal) to an image processing unit (not shown), and a video signal. SG2 is received. A video signal SG2 edited for each page in an image processing unit (not shown) and received by the print control unit 40 is transferred to each print head 13 as a print data signal (hereinafter simply referred to as “print data”) HD-DATA. . Each print head 13 is formed by arranging a plurality of light emitting elements (for example, LEDs) provided for printing one dot (pixel) on a line.

  When receiving the video signal SG2 for one line, the print control unit 40 transmits a latch signal HD-LOAD to each print head 13 to hold the print data HD-DATA in each print head 13. Further, the print control unit 40 can print the print data HD-DATA held in each print head 13 even while the next video signal SG2 is being received from an image processing unit (not shown).

  Note that a clock signal (hereinafter simply referred to as “clock”) HD-CLK transmitted from the print control unit 40 to each print head 13 and a strobe signal HD-STB-N (where “ −N ”means a negative logic signal.) Among them, the clock HD-CLK is a signal for transmitting the print data HD-DATA to the print head 13.

  Transmission / reception of the video signal SG2 is performed for each print line. Light emitted from the print head 13 is irradiated onto the photosensitive drum 11 charged to a negative potential. As a result, the information to be printed is converted into a latent image on the photosensitive drum 11 as dots having an increased potential. In the developing unit 14, the toner for image formation charged to a negative potential is sucked to each dot by an electric suction force, and a toner image is developed and formed.

  Thereafter, the toner image is sent to the transfer device 27, and on the other hand, the transfer high voltage power supply 51 is turned on to a positive potential by the transfer signal SG4, and the transfer device 27 passes through the interval between the photosensitive drum 11 and the transfer device 27. A toner image is transferred onto the paper 20. The sheet 20 having the transferred toner image is conveyed in contact with a fixing device 28 including a heater 28 a, and is fixed to the sheet 20 by the heat of the fixing device 28. The sheet 20 having the fixed image is further conveyed and discharged from the printing mechanism of the image forming apparatus 1 through the sheet discharge port sensor 46 to the outside of the image forming apparatus.

  In response to detection by the paper size sensor 48 and the paper inlet sensor 45, the print control unit 40 supplies the voltage from the high-voltage power supply 51 for transfer to the transfer device 27 only while the paper 20 passes through the transfer device 27. Apply. When printing is finished and the paper 20 passes through the paper discharge port sensor 46, the application of voltage to the developing device 14 by the charging high-voltage power supply 50 is finished, and at the same time, the rotation of the development / transfer process motor 42 is stopped. Thereafter, the above operation is repeated.

(Configuration of print head)
FIG. 6 is a circuit configuration diagram showing the print head 13 in FIG.

  For example, the print head 13 is configured to be able to print on A4 size paper at a resolution of 600 dots per inch.

  The print head 13 includes a printed wiring board (not shown). On the printed wiring board, a reference voltage generation circuit 100, a plurality of driver ICs 200 (= 200-1 to 200-n, for example, n = 26), A plurality of light emitting element arrays 60 (= 60-1 to 60-n, for example, n = 26) are mounted. Here, the reference voltage generation circuit 100 and the plurality of driver ICs 200-1 to 200-n constitute the driving device of the first embodiment.

  In the light emitting element array 60, for example, a light emitting layer is formed using an epitaxial film, and this film is pasted on the driver IC 200 to form a semiconductor composite chip 13c configured by combining the light emitting element array 60 and the driver IC 200. doing. In each light emitting element array 60, a plurality of (for example, 192) light emitting elements (for example, LEDs) are arranged substantially linearly. The total number of LEDs is 4992 dots (pieces).

  The reference voltage generation circuit 100 is a circuit that generates a reference voltage Vref based on the potential of the first power supply (for example, the power supply voltage VDD), and a plurality of driver ICs 200 are connected to the output side. Each light emitting element array 60 is connected to the output side of the driver IC 200.

  The plurality of driver ICs 200 that drive the plurality of light emitting element arrays 60 are configured by the same circuit, and adjacent driver ICs 200-1, 200-2,... Are cascade-connected (cascade connection). 192 LEDs can be driven per driver IC chip, 26 of these driver IC chips are cascade-connected, and the print data HD-DATA sent from the print control unit 40 during printing can be transferred serially. .

  Each driver IC 200 receives the control voltage generation circuit 210 that generates a control voltage based on the reference voltage Vref and the clock HD-CLK sent from the print control unit 40 during printing, and performs shift transfer of the print data HD-DATA. A shift register 220, a latch circuit 230 that latches an output signal of the shift register 220 with a latch signal HD-LOAD sent from the print control unit 40 during printing, and a strobe sent from the print control unit 40 during printing An inverter 241 for inverting the signal HD-STB-N, a logic circuit (for example, a NAND circuit, hereinafter referred to as “NAND”) 242 for obtaining the logic of the output signals of the latch circuit 230 and the inverter 241, and the NAND 242 Drive current from power supply voltage VDD according to output signal And a drive circuit 250 supplies to 0. The control voltage generation circuit 210 has a function of generating a control voltage so that the drive current of the drive circuit 250 is constant.

  Note that one reference voltage generation circuit 100 shown in FIG. 6 is provided in the print head 13 and is configured to control the driver ICs 200-1 to 200-n in common, but this is mainly simplified. Therefore, the reference voltage generation circuit 100 may be provided in each driver IC 200. With such a configuration, the light emitting element array 60 and the driver IC 200 are thermally coupled to each other, and the chip temperatures of the light emitting element array 60 and the driver IC 200 can be made substantially equal. It is more preferable from the viewpoint of temperature compensation described later.

(Configuration of reference voltage generation circuit)
FIG. 1 is a circuit diagram showing a configuration of the reference voltage generation circuit 100 in FIG. 6 according to the first embodiment of the present invention.

  The reference voltage generating circuit 100 includes a first current circuit 110, a second current circuit 130, and a current subtracting circuit 150 connected between the first current circuit 110 and the second current circuit 130. This is a circuit that is driven by a voltage (for example, VDD), generates a constant reference voltage Vref, and outputs it from an output terminal VREF.

  The first current circuit 110 includes a first current mirror circuit 120 that generates a current having a negative temperature coefficient generated depending on a negative temperature coefficient of the base-emitter voltage of the bipolar transistor, and a first bipolar transistor (for example, , An NPN transistor, hereinafter simply referred to as “NPN”) 124, and a second resistor 125 (for example, a resistor having a resistance value R 125) 125.

  The first current mirror circuit 120 includes a first conductivity type third MOS transistor (eg, P-channel type MOS transistor, hereinafter referred to as “PMOS”) 121, a first conductivity type second MOS transistor (eg, PMOS) 122, and the like. And a first MOS transistor (for example, PMOS) 123 of the first conductivity type.

  The PMOS 121 has a source connected to the first power supply (for example, VDD power supply), a drain connected to the node N121 on the output terminal VREF side, a gate connected to the node N123, and a negative temperature coefficient from the drain. This is a transistor that outputs a drain current I4 as a second dependent current. The PMOS 122 is a transistor that has a source connected to the VDD power supply, a drain connected to the second node N122, a gate connected to the node N123, and outputs a drain current I5 as a first dependent current from the drain. The PMOS 123 is a transistor that has a source connected to the VDD power supply, a drain connected to the first node N125, a gate connected to the node N123 and the drain, and outputs a drain current I6 as a control-side current from the drain.

  These PMOSs 121, 122, and 123 are set to have the same gate length, and the sources and the gates are connected to each other, the gate-source voltages are set to be equal, and have a current mirror relationship. . The PMOS 123 has a gate and a drain connected, and operates in a saturation region.

  The NPN 124 has a collector and a base connected to the node N122, and an emitter connected to a second power source (for example, the ground GND). Further, the resistor 125 is connected between the node N125 and the ground GND. The node N121 on the output terminal VREF side is connected to the ground GND via a first resistor (for example, a resistor having a resistance value R163) 163.

  The second current circuit 130 includes a second current mirror circuit 140 that generates a current having a positive temperature coefficient depending on a negative temperature coefficient of the base-emitter voltage of the bipolar transistor, a third resistor, A resistor (for example, a resistor having a resistance value R144) 144, a third bipolar transistor (for example, NPN) 145, a third resistor (for example, a resistor having a resistance value R146) 146, and a second bipolar transistor (for example, NPN) 147 And have.

  The second current mirror circuit 140 includes a first conductivity type fifth MOS transistor (for example, PMOS) 141, a first conductivity type fourth MOS transistor (for example, PMOS) 142, and a first conductivity type sixth MOS transistor (for example, PMOS). , PMOS) 143.

  The PMOS 141 has a source connected to the VDD power supply, a drain connected to the fourth node N141, a gate connected to the node N142, and a first dependent side current (for example, a drain current) having a positive temperature characteristic from the drain. It is a transistor that outputs I1. The PMOS 142 is a transistor that has a source connected to the VDD power supply, a drain connected to the third node N142, a gate connected to the node N142 and the drain, and outputs a control-side current (for example, a drain current) I2 from the drain. . Further, the PMOS 143 is a transistor whose source is connected to the VDD power source, drain is connected to the fifth node N143, gate is connected to the node N142, and the second dependent current (for example, drain current) I3 is output from the drain. is there.

  These PMOSs 141, 142, and 143 are set to have the same gate length, the sources are connected to each other, the gates are connected to each other, and the gate-source voltages are set to be equal to each other. The PMOS 142 has a gate and a drain connected, and operates in a saturation region.

  The resistor 144 has one end connected to the node N141 and the other end connected to the collector of the NPN 145. The NPN 145 has an emitter connected to the ground GND and a base connected to the node N141. The base-emitter voltage of this NPN 145 is Vbe145. The resistor 146 has one end connected to the node N142 and the other end connected to the collector of the NPN 147. The NPN 147 has an emitter connected to the ground GND and a base connected to the collector of the NPN 145. The base-emitter voltage of this NPN 147 is Vbe147.

  The emitter area of the NPN 147 is set to N times (N> 1) the emitter area of the NPN 145. As will be described later, the resistor 146 is provided for the purpose of making the collector potential of the NPN 147 substantially equal to the collector potential of the NPN 145. However, if it is not necessary to align the operating points of the NPNs 145 and 147, the resistor 146 is provided. Can be omitted.

  The current subtracting circuit 150 is a current I4B that is proportional to the output current (eg, drain current) I4 of the first current mirror circuit 120 to the output current (eg, drain current as the second dependent current) I3 of the second current mirror circuit 140. Is subtracted to generate a subtraction current (for example, a drain current as a dependent current) I4A, and a reference voltage Vref proportional to the drain current I4A is output to the output terminal RREF, and the third current mirror circuit 160 is Have.

  The third current mirror circuit 160 includes a second conductivity type seventh MOS transistor (eg, N-channel type MOS transistor, hereinafter referred to as “NMOS”) 161, a second conductivity type eighth MOS transistor (eg, NMOS) 162, and It is comprised by. The NMOS 161 is a transistor having a drain and a gate connected to the fifth node N143, a source connected to the ground GND, and a drain current I3 input to the drain and gate as a control-side current. Further, the NMOS 162 is a transistor having a drain connected to the node N121 on the output terminal VREF side, a gate connected to the gate of the NMOS 161, and a drain current I4B as a dependent current flowing through the drain. A drain current I4A (= I4-I4B) flows through the resistor 163 connected between the node N121 on the output terminal VREF side and the ground GND.

  These NMOSs 161 and 162 are set to have the same gate length, the sources are connected to the same gate, the gate-source voltages are set to be equal, and have a current mirror relationship. The NMOS 161 has a gate and a drain connected, and operates in a saturation region.

  In order to simplify the description below, if the gate widths of the PMOSs 141 and 142 are equal, the drain currents I1 and I2 are equal, and the output characteristics are approximately constant current characteristics.

  When the current amplification factor of the NPN 145 is large, the base current is negligible compared to the collector current, so that the drain currents I1 and I2 are substantially equal to the currents flowing through the resistors 144 and 146, respectively, and this is also the collector current of each of the NPNs 145 and 147. Is almost equal.

  Since the drain currents I1 and I2 are set to be equal, by setting the resistance values R144 and R146 of the resistors 144 and 146 to be approximately equal, the potential drops generated at both ends thereof are equal, and the collector potentials of the NPNs 145 and 147 are also approximately equal. can do. This is preferable because the operating conditions of NPN 145 and 147 can be made uniform.

  Further, by setting the gate width of the PMOS 143 to a predetermined ratio with respect to the gate width of the PMOS 142, the drain current I3 can be set to a value having a predetermined ratio with respect to the drain current I2. In order to improve the above characteristics, it is preferable to set the gate lengths of the PMOSs 141, 142, and 143 to be large.

  Similarly, by setting the gate lengths of the PMOSs 161 and 162 to be equal, the operation states can be made uniform, and the drain currents I3 and I4B can be in a proportional relationship.

(Function of the reference voltage generation circuit 100)
The functions (A) and (B) of the reference voltage generation circuit 100 of FIG. 1 will be considered quantitatively.

(A) Function of Second Current Circuit 130 In order to quantitatively consider the function of the reference voltage generation circuit 100, first, the drain current I1 in the second current circuit 130 is obtained.

As is well known from the theory of electronic properties, the relationship of the following formula (1) is established between the emitter current Ie of the bipolar transistor and the base-emitter voltage Vbe.
Ie≈Is * exp (qVbe / (kT)) (1)
Where Is: saturation current (a constant determined in proportion to the element area of the bipolar transistor)
exp (); exponential function
q: electron charge q = 1.6 * 10 ⁻¹⁹ [C]
k; Boltzmann constant k = 1.38 * 10 ⁻²³ [J / K]
T: Absolute temperature About 298 [K] at room temperature of 25 [° C]

Equation (1) is transformed to obtain the following equation (2).
Vbe = (kT / q) * ln (Ie / Is) (2)
Where ln (); natural logarithm function

Here, for NPNs 145 and 147, the base-emitter voltages are Vbe145 and Vbe147, the emitter currents are Ie145 and Ie147, and the saturation currents are Is145 and Is147. In this case, the following expressions (3) and (4) hold for NPNs 145 and 147.
Vbe145 = (kT / q) * ln (Ie145 / Is145) (3)
Vbe147 = (kT / q) * ln (Ie147 / Is147) (4)

In FIG. 1, the potential at one end of the resistor 144 (resistance value R144) is Vbe145, and the potential at the other end is Vbe147. For this reason, the potential difference ΔVbe generated at both ends of the resistor 144 is
ΔVbe = Vbe145−Vbe147 (5)
It is. Substituting the formulas (3) and (4) into the formula (5) and rearranging gives the following formula (6).
ΔVbe = (kT / q) × [ln (Ie145 / Is145) −ln (Ie147 / Is147)]]
= (KT / q) × ln [(Is147 / Is145) * (Ie145 / Ie147)] (6)

As described above, the emitter area ratio of NPN 145 and 147 is set to 1: N (N> 1), and the saturation current is proportional to the element area of the transistor.
Is147 = Is145 × N (7)
It becomes.

As described above, the PMOSs 141 and 142 have a current mirror relationship, and the drain current can be I1 = I2. As a result, the emitter currents Ie145 and Ie147 are substantially equal.
ΔVbe = (kT / q) × ln (N) (8)
The relationship is obtained. The drain current I1 shown in FIG. 1 is substantially equal to the current flowing through the resistor 144 (resistance value R144).
I1 = ΔVbe / R144
= (1 / R144) × (kT / q) × ln (N) (9)
It is.

  As described above, the PMOSs 141, 142, and 143 have a current mirror relationship, and the drain current can be I1 = I2 = I3. It can be seen that the drain current I1 is proportional to the absolute temperature (T) and has a positive temperature coefficient. In general, the temperature coefficient Tc of the reference voltage Vref is defined by the following equation (10).

Therefore, the temperature coefficient Tc of the drain currents Il, I2, and I3 in the second current circuit 130 shown in FIG.
Tc = (1 / T) (11)
Near room temperature (25 ° C)
Tc = 0.33 [% / ° C.]
It can be seen that the temperature coefficient is

(B) Function of First Current Circuit 110 Next, the function of the first current circuit 110 will be considered. As described above, the PMOSs 122 and 123 have a current mirror relationship, and their drain potentials can be made substantially equal by appropriately setting the operating conditions. As a result, the potentials of the node N122 and the node N125 in FIG. 1 are substantially equal.

Since the potential of the node N122 is equal to the base-emitter voltage Vbe124 of the NPN 124 and the node N125 is connected to one end of the resistor 125 (resistance value R125), the drain current I6 is given by the following equation (12).
I6 = Vbe124 / R125 (12)

As is well known from the theory of electronic properties, a typical value of the base-emitter voltage Vbe of a bipolar transistor made of a silicon substrate is about 0.6 V, and its temperature dependency is -2 mV / ° C. Therefore, the temperature coefficient Tc of the base-emitter voltage Vbe124 is
Tc = -2 × 10 ⁻³ /0.6=−0.33 [% / ° C.] (13)
Can be calculated. If the temperature coefficient of the resistor R125 is ignored for the time being, it can be seen that the temperature coefficient of the drain current I6 is also −0.33 [% / ° C.]. In this case, since the drain current is I5 = I6, it can be seen that the temperature coefficient of the current I5 is also −0.33 [% / ° C.].

As described above, since the drain currents I4, I5, and I6 are in a proportional relationship, the temperature coefficient of the drain current I4 is also −0.33 [% / ° C.]. By making the gate width of the PMOS 121 equal to the gate width of the PMOSs 122 and 123, the drain current I4 can be made equal to I5,
I4 = I5 = I6
It can be.

  On the other hand, a current mirror circuit 160 surrounded by a broken line is composed of NMOSs 161 and 162, and the drain current I3 of the PMOS 143 flows into the control side node N143 of the current mirror circuit 160. As a result, an inflow current I4B substantially proportional to the drain current I3 is generated at the subordinate node N121 of the current mirror circuit 160. The ratio of the current flowing into the control side node N143 and the dependent side node N121 of the current mirror circuit 160 can be arbitrarily set by changing the size ratio of the NMOSs 161 and 162.

(Configuration of drive unit)
FIG. 7 is a circuit diagram showing the main part of the drive device in FIG.

  In FIG. 7, a circuit diagram of a driving device for driving one dot (for example, one LED as a driven element) is shown.

  In the driving apparatus according to the first embodiment, a control voltage generation circuit 210 provided for each driver IC 200 is connected to the output terminal VREF of the reference voltage generation circuit 100.

  The control voltage generation circuit 210 includes a feedback control circuit including an operational amplifier (hereinafter referred to as “op-amp”) 211, a resistor 212 having a resistance value Rref, and a PMOS 213. The operational amplifier 211 has an inverting input terminal (−) connected to the output terminal VREF, and a non-inverting input terminal (+) connected to the ground GND via the resistor 212 and also connected to the drain of the PMOS 213, An output terminal for outputting Vcontrol is connected to the gate of the PMOS 213. The source of the PMOS 213 is connected to the VDD power source. In this control voltage generation circuit 210, the reference current Iref flowing through the resistor 212, that is, the current flowing between the source and drain of the PMOS 213, depends on only the input reference voltage Vref and the resistance value Rref of the resistor 212, regardless of the power supply voltage VDD. The configuration is determined.

  A latch element 231 composed of a flip-flop circuit for one dot constituting the latch circuit 230 includes a G terminal for inputting a latch signal HD-LOAD, a D input terminal for inputting print data output from the shift register 220, and a Q terminal. When the latch signal HD-LOAD is input to the G terminal, the print data output from the shift register 220 is input from the D terminal, latched, and output from the Q output terminal. A NAND 242 is connected to the Q output terminal of the latch circuit 230 and the output terminal of the inverter 241 that inverts the negative logic strobe signal HD-STB-N.

  The NAND 242 has a power supply terminal connected to the VDD power supply and a ground terminal connected to the output terminal of the operational amplifier 211. When the output potential of the NAND 242 is at a high level (hereinafter referred to as “H level”), it is substantially equal to the power supply voltage VDD. When a potential is output and the output potential of the NAND 242 is at a low level (hereinafter referred to as “L level”), a potential substantially equal to the control voltage Vcontrol is output.

  The output terminal of the NAND 242 is connected to the gate of a one-dot drive element (for example, PMOS) 251 constituting the drive circuit 250, and the source of the PMOS 251 is connected to the VDD power source. The drain of the PMOS 251 is connected to the anode of the LED 61 for one dot in the light emitting element array 60, and the cathode of the LED 61 is connected to the ground GND.

Here, the PMOS 213 in the control voltage generation circuit 210 is configured to have the same gate length as the PMOS 251 and the like. In the control voltage generation circuit 210, the operation of the operational amplifier 211 controls the potential of the inverting input terminal (−) and the potential of the non-inverting input terminal (+) to be substantially equal. The potential of the terminal (+) becomes substantially equal to the inputted reference voltage Vref. Therefore, the reference current Iref flowing through the resistor 212 is
Iref = Vref / Rref
As given.

  The LED driving PMOS 251 and the PMOS 213 are configured to have the same gate length, and the gate potential is equal to the control voltage Vcontrol when the LED is driven. The PMOS 213 and the LED driving PMOS 251 are in the saturation region. It is operating and has a current mirror relationship. As a result, each drive current value of the LED 61 and the like is proportional to the reference current Iref, and the reference current Iref is proportional to the reference voltage Vref input from the output terminal VREF. Therefore, the LED drive current value is determined by the reference voltage Vref. Can be adjusted at once.

(Print head operation)
FIG. 8 is a timing chart for explaining the printing operation of the print head 13 of FIG.

  With the start of the printing operation, one pulse of the timing signal SG3 is output from the printing control unit 40 in FIG. 5 for each printing line cycle and transmitted to an image processing unit (not shown). In response to the timing signal SG3, the video signal SG2 is generated from the image processing unit for each of the N−1 line, N line, N + 1 line,... And transmitted to the print control unit 40. In synchronization with this, the clock CHD-CLK and the print data HD-DATA are input from the print control unit 40 to the print head 13.

  In the first embodiment, the print head 13 that can print on an A4 size paper with a resolution of 600 dots per inch is illustrated, and the total number of LEDs 61 is 4992 dots. Therefore, the number of generated pulses of the clock HD-CLK is 4992. When the transmission of the 4992 pulses is completed, a pulse of the latch signal HD-LOAD is generated from the print control unit 40, and the shift in the print head 13 is performed. The print data HD-DATA shift-input to the register 220 is latched by the latch circuit 230.

  Next, an L level strobe signal HD-STB-N is generated from the print control unit 40 for LED driving every N-1 line driving, N line driving, N-1 line driving,. The LED 61 emits light during the LED driving period t when the signal HD-STB-N is at the L level. Thereby, the photosensitive drum 11 shown in FIG. 2 is irradiated with light to form a latent image.

(Operation of reference voltage generation circuit)
9A to 9D are diagrams for explaining the operation of the reference voltage generation circuit 100 in FIG. 1, and FIG. 9A is a circuit diagram around the current subtraction circuit 150 in FIG. FIGS. 4B to 4D are graphs schematically showing temperature / current characteristics of each part of FIG.

  In FIG. 9A, the drain currents of the PMOSs 143 and 121 are I3 and I4, the current flowing into the resistor 163 having the resistance value R163 is I4A, and the current flowing into the drain of the NMOS 162 is I4B.

  FIGS. 9B to 9D show changes in the currents I4, I4B, and I4A depending on the temperature. As described above, the current I4 has a characteristic that its value decreases as the temperature rises. The temperature coefficient is about −0.33 [% / ° C.]. Further, the current I3 and the current I4B have a current mirror relationship, and the current I3 has a characteristic that increases as the temperature rises as described above, and the current I4B also has a characteristic that increases as the temperature rises. ing. Therefore, the temperature coefficient of the current I4B is about +0.33 [% / ° C.].

In FIG. 9A, the relationship between the currents I4, I4A, and I4B is
I4 = I4A + I4B (14)
It is. Than this,
I4A = I4-I4B (15)
It becomes. Therefore, the characteristic graph of the current I4A shown in FIG. 9D is obtained by subtracting the current I4B of FIG. 9C from the current I4 of FIG. 9B, and the temperature is higher than the current I4 of FIG. 9B. It turns out that it becomes a characteristic with big dependence.

  Let us consider the above matters quantitatively. For simplicity of explanation, the current I4 is abbreviated as I, the current I4A is abbreviated as Ia, the current I4B is abbreviated as Ib, the temperature coefficient of the current I is αc, the temperature coefficient of the current Ib is αp, and the temperature coefficient of the current Ia is Let Tc. in this case,

So, from this,

It is. As described above, the current Ia is
Ia = I−Ib (20)
Therefore, from this, the temperature coefficient Tc of the current Ia is expressed by the following equation (21).

  The following formula (22) is obtained by transforming and formulating the formula (2).

As described above, the temperature coefficient αc of the current I4 is about −0.33 [% / ° C.], and the temperature coefficient αp of the current I4B is about +0.33 [% / ° C.]
αp = −αc (23)
If the equation (23) is rearranged, the relationship of the following equation (4) is obtained.

In the equation (24), since the temperature coefficient αp of the current I4B is a known positive value, the temperature coefficient Tc of the current Ia is a negative value, and the value is changed by changing the ratio of the currents Ib and I. be able to. This is achieved by creating a current I4A obtained by subtracting a current I4B having a positive temperature coefficient from a current value I4 having a negative temperature coefficient, as shown in the following equation (25). .
I4A = I4-I4B (25)

  As a result, the current I4A has an increased temperature coefficient compared to the current I4, but the current value itself is smaller than the current I4. However, it is easy to set the reference voltage Vref to a predetermined value by increasing the resistance value R163 of the resistor 163 in accordance with the current decrease. As described above, in the configuration of the reference voltage generation circuit 100 shown in FIG. 1, the temperature coefficient of the reference voltage Vref and the voltage value thereof can be set relatively arbitrarily according to the purpose.

  As described above, in the DBR type LED 61, the light output may be positive temperature dependent. In the print head 13, if the exposure energy amount varies depending on the temperature, the print density varies, which is not preferable. Therefore, in order to compensate for the positive temperature dependency of the LED 61, the drive current value has a negative temperature dependency. It is necessary to give sex. In this case, by using the reference voltage generation circuit 100 shown in FIG. 1, it is possible to reduce the temperature dependence of the light output of the LED 61 to a level that can be ignored by using the LED drive current as a reference.

  As described above, in the reference voltage generating circuit 100 having the configuration shown in FIG. 1, the temperature coefficient of the output reference voltage Vref can be set to a desired value, and the voltage value is also a predetermined value independent of the temperature coefficient. And can be widely applied to various LEDs 61 and their driving devices.

(Effect of Example 1)
According to the reference voltage generating circuit 100, the driving device, the print head 13, and the image forming apparatus 1 of the first embodiment, there are the following effects (a) and (b).

  (A) According to the reference voltage generation circuit 100 of the first embodiment, for example, in the DBR type LED 61, the optical output may be positive temperature dependent. In the print head 13, if the exposure energy amount varies depending on the temperature, the print density varies, which is not preferable. Therefore, in order to compensate for the temperature dependency of the distortion of the LED 61, the drive current value has a negative temperature dependency. Need to give. Therefore, in the first embodiment, the first current circuit 110, the second current circuit 130, and the current subtraction circuit 150 constitute the reference voltage generation circuit 100 in FIG. 1, and therefore, the temperature coefficient of the output reference voltage Vref is a negative value. However, the value can be set relatively freely. As a result, the reference voltage Vref output from the reference voltage generation circuit 100 can be reduced to such an extent that the temperature dependence of the light output of the LED 61 can be ignored using the LED drive current as a reference.

  (B) According to the image forming apparatus 1 of the first embodiment, since the print head 13 having the reference voltage generating circuit 100 is employed, a high-quality image forming apparatus (printer) excellent in space efficiency and light extraction efficiency. Copiers, facsimile machines, multifunction machines, etc.). That is, the use of the print head 13 is effective not only in the above-described full-color image forming apparatus 1 but also in a monochrome or multi-color image forming apparatus, but in particular, a large number of print heads 13 as exposure apparatuses are required. A greater effect can be obtained in a full-color image forming apparatus.

  The configurations of the image forming apparatus 1 and the print head 13 in the second embodiment of the present invention are the same as those in the first embodiment, and the configuration of the reference voltage generation circuit provided in the driving device in the second embodiment is the same as that in the first embodiment. The configuration of the reference voltage generating circuit 100 is different. Therefore, a reference voltage generation circuit according to the second embodiment that is different from the first embodiment will be described below.

(Configuration of Reference Voltage Generating Circuit of Example 2)
FIG. 10 is a circuit diagram showing the configuration of the reference voltage generation circuit according to the second embodiment of the present invention. Elements common to the elements in FIG. 1 showing the reference voltage generation circuit 100 according to the first embodiment are denoted by common reference numerals. It is attached.

  In the reference voltage generating circuit 100A of the second embodiment, instead of the first current circuit 110, the second current circuit 130, and the current subtracting circuit 150, the first current circuit 110A and the second current circuit 130A having different configurations from these are used. And a current subtracting circuit 150A.

  The first current circuit 110A includes a first current mirror circuit 160A having a configuration different from that of the first current mirror circuit 160 of the first embodiment, and an NPN 124 and a resistor 125 similar to those of the first embodiment. The first current mirror circuit 160A includes PMOSs 121, 122, and 123 similar to those of the first embodiment, and newly added NMOSs 153, 126, and 127.

  The NMOS 153 has a drain and a gate connected to the drain side node N153 of the PMOS 121, a source connected to the node N121, and a diode connected between the drain side node N153 and the node N121. The gate-source voltage of the NMOS 153 is Vgs153. The NMOS 126 has a drain and a gate connected to the drain of the PMOS 122, and a source connected to the node N 122 on the collector side of the NPN 124. The gate-source voltage of the NMOS 126 is Vgs126. The NMOS 127 has a drain connected to the drain of the PMOS 123, a source connected to the node N 125 on the resistor 125 side, a gate connected to the gate and drain of the NMOS 126 via the node N 126, and a current mirror circuit together with the NMOS 126. . The gate-source voltage of the NMOS 127 is Vgs127.

  The NMOS 126 and the NMOS 127 are set to have the same gate length and gate width.

  The second current circuit 130A includes a second current mirror circuit 140A having a configuration different from that of the second current mirror circuit 140 of the first embodiment, and resistors 144 and 146 and NPNs 145 and 147 similar to those of the first embodiment. The second current mirror circuit 140A includes PMOSs 141, 142, and 143 similar to those in the first embodiment and newly added NMOSs 148 and 149.

  The NMOS 148 has a drain and a gate connected to the drain of the PMOS 141, and a source connected to the node N 141 on the resistor 144 side. The gate-source voltage of the NMOS 148 is Vgs148. The NMOS 149 has a drain connected to the drain of the PMOS 142, a source connected to the node N142 on the resistor 146 side, a gate connected to the gate and drain of the NMOS 148 via the node N148, and constitutes a current mirror circuit together with the NMOS 148. . The gate-source voltage of the NMOS 149 is Vgs149.

  The NMOS 148 and the NMOS 149 are set to have the same gate length and gate width.

  The NMOS 152 has a drain and a gate connected to the drain-side node N152 of the PMOS 143, a source connected to the drain-side node N143 of the NMOS 161, and a diode connection between the node N152 and the node N143. The gate-source voltage of the NMOS 152 is Vgs 152.

  The NMOS 152 and the NMOS 153 constitute a level shift circuit 151 that transitions (shifts) the level of the power supply voltage VDD.

  In order to simplify the description below, as in the first embodiment, when the gate widths of the PMOSs 141 and 142 are equal to each other, the drain currents I1 and I2 are equal and the output characteristics are approximately provided with constant current characteristics. Become.

  When the current amplification factor of the NPN 145 is large, the base current is negligible compared to the collector current, so that the drain currents I1 and I2 described above are approximately equal to the currents flowing through the resistors 144 and 146, respectively. It is almost equal to the collector current. As described above, since the drain currents I1 and I2 are set to be equal, by setting the resistance values R144 and R146 of the resistors 144 and 146 to be approximately equal, potential drops generated at both ends thereof are equal, and the collectors of the NPNs 145 and 147 are equal. The potentials can also be approximately equal. This is preferable because the operating conditions can be made uniform.

  Further, by setting the gate width of the PMOS 143 to a predetermined ratio with respect to the gate width of the PMOS 142, the current I3 can be set to a value having a predetermined ratio with respect to the current I2. In order to improve the characteristics, it is preferable to set the gate lengths of the PMOSs 141, 142, and 143 to be large.

  Similarly, in the NMOSs 148 and 149, the operation state can be made uniform by equalizing the gate length and the gate width. Therefore, as described above, since the drain currents I1 and I2 are equal, the drain currents of the NMOSs 148 and 149 are also equal, and the gate-source voltages Vgs148 and Vgs149 thereof are also equal. As described above, since the gates of the NMOSs 148 and 149 are connected and have the same potential, even if the potentials of the node N141 and the node N142 are equal and the power supply voltage VDD fluctuates, the potential difference between the node N141 and the node N142 is It remains scarce.

  For example, if the potential of the node N141 decreases, the gate potential (the potential of the node N148) also decreases according to the value of the gate-source voltage Vgs148 of the NMOS 148. At this time, since the gate-source voltage Vgs149 of the NMOS 149 and the gate-source voltage Vgs148 of the NMOS 148 are equal, the potential of the node N142 is also lowered to be equal to the potential of the node N141. Similarly, when the potential of the node N141 increases, the potential of the node N142 increases and becomes substantially equal to the potential of the node N141.

  The node N141 is connected to the base of the NPN 145, and even if the value of the power supply voltage VDD changes, the fluctuation of the base potential is small. As described above, since the potentials of the node N141 and the node N142 are substantially equal and the collector potentials of the NPNs 145 and 147 are substantially equal, the fluctuation of the collector potential of the NPN 147 can be reduced. Therefore, the change in the collector current I2 due to the fluctuation of the power supply voltage VDD can be made small.

(Function of the reference voltage generating circuit 100A)
The functions (A) and (B) of the reference voltage generation circuit 100A of FIG.

(A) Function of Second Current Circuit 130A In order to quantitatively consider the function of the reference voltage generation circuit 100A, first, the drain current I1 in the second current circuit 130A is obtained.

  Since the calculation process is the same as that in the first embodiment, different points will be mainly described.

As described above, even if the current mirror relationship is set and the power supply voltage VDD fluctuates, the PMOSs 141 and 142 can reduce the influence on the current mirror circuit 140A by the action of the NMOSs 148 and 149. And
I1 = I2
Can be. Furthermore, since PMOSs 141, 142, and 143 have a current mirror relationship,
I1 = I2 = I3
Can be.

  The level shift circuit 151 composed of the NMOSs 152 and 153 operates in the same manner as the NMOSs 149 and 149 described above, but functions to lower the potentials given by the gate-source voltages Vgs152 and Vgs153, respectively. .

It can be seen that the drain current I1 described above is proportional to the absolute temperature (T) and has a positive temperature coefficient. The temperature coefficient Tc of the drain currents I1, I2, and I3 in the second current circuit 130A is the same as in the first embodiment.
Tc = (l / T)
It can be seen that the temperature coefficient is Tc = + 0.33 [% / ° C.] around room temperature (25 ° C.).

(B) Function of First Current Circuit 110A Next, consider the function of the first current circuit 110A.

  Similar to the first embodiment, the PMOSs 122 and 123 have a current mirror relationship, and their drain potentials can be made substantially equal by setting the operating conditions appropriately.

  In order to improve the characteristics, it is preferable to set the gate lengths of the PMOSs 122 and 123 large. Similarly, the operation of the NMOSs 126 and 127 can be made uniform by making the gate length and the gate width equal. Therefore, as described above, since the drain currents I5 and I6 are equal, the drain currents of the NMOSs 126 and 127 are also equal, and the gate-source voltages Vgs126 and Vgs127 of both are also equal.

  As described above, since the gates of the NMOSs 126 and 127 are connected and have the same potential, the potentials of the node N122 and the node N125 are equal, and even if the power supply voltage VDD fluctuates, the potential difference between the nodes N122 and N125 is small. Remains. As a result, the potentials of the nodes N122 and N125 are substantially equal.

  Since the potential of the node N122 is equal to the base-emitter voltage Vbe124 of the NPN 124 and the node N125 is connected to one end of the resistor 124 (resistance value R125), the drain current I6 is expressed by the equation (12) of the first embodiment. Given.

As in the first embodiment, when the temperature coefficient of the resistor 125 is ignored for the time being, it can be seen that the temperature coefficient of the drain current I6 is also −0.33 [% / ° C.]. As described above, since the drain currents I4, I5, and I6 are in a proportional relationship, the temperature coefficient of the current I4 is also −0.33 [% / ° C.]. By making the gate width of the PMOS 121 equal to the PMOSs 122 and 123, the drain current I4 can be made equal to the drain current I5. for that reason,
I4 = I5 = I6
It can be. In this case, by setting the gate length and gate width of the NMOS 153 to be equal to those of the NMOSs 126 and 127, the gate-source voltage Vgs153 can be made substantially equal to Vgs126 and Vgs127.

  On the other hand, as in the first embodiment, in the current mirror circuit 160 constituted by the NMOSs 161 and 162, the current I3 flows into the control side node N143. As a result, an inflow current I4B substantially proportional to the current I3 is generated at the subordinate node N121 of the current mirror circuit 160.

  As in the first embodiment, the ratio of the current flowing into the control side node N143 and the dependent side node N121 of the current mirror circuit 160 can be arbitrarily set by changing the size ratio of the NMOSs 161 and 162.

(Operation of Example 2)
In the second embodiment, the operation of the reference voltage generating circuit 100A having a configuration different from that of the first embodiment will be described below.

  11A to 11D are diagrams for explaining the operation of the reference voltage generation circuit 100A in FIG. 10, and FIG. 11A is a circuit diagram around the current subtraction circuit 150A in FIG. FIGS. 4B to 4D are graphs schematically showing temperature / current characteristics of each part of FIG.

  Similarly to FIG. 9A, in FIG. 11A, the drain currents of the PMOSs 143 and 121 are I3 and I4, the current flowing into the resistor 163 having the resistance value R163 is I4A, and the current flowing into the drain of the NMOS 162 is I4B. is there.

  Similarly to FIGS. 9B to 9D, FIGS. 11B to 11D show changes in the currents I4, I4B, and I4A depending on the temperature, and the value of the current I4 increases with increasing temperature. The temperature coefficient is about −0.33 [% / ° C.]. The current I3 has a characteristic proportional to the absolute temperature (T), and its temperature coefficient is about 0.33 [% / ° C.]. Since the current I3 and the current I4B are in a current mirror relationship, the current I4B also has a characteristic that increases as the temperature rises. Therefore, the temperature coefficient of the current I4B is about +0.33 [% / ° C.].

In FIG. 11A, the relationship between the currents I4, I4A, and I4B is
I4 = I4A + I4B (14)
It is. Than this,
I4A = I4-I4B (15)
It becomes. Therefore, the characteristic graph of the current I4A shown in FIG. 11 (d) is obtained by subtracting the current I4B in FIG. 11 (c) from the current I4 in FIG. 11 (b), and the temperature is higher than the current I4 in FIG. 11 (b). It turns out that it becomes a characteristic with big dependence.

  Let us consider the above matters quantitatively. As in the first embodiment, for simplification of description, the current I4 is abbreviated as I, the current I4A is abbreviated as Ia, the current I4B is abbreviated as Ib, the temperature coefficient of the current I is αc, and the temperature coefficient of the current Ib is αp. The temperature coefficient of the current Ia is Tc.

In this case, the relationship between the temperature coefficients αc and αp and the currents I and Ib is expressed by the above equations (16) to (19). The current Ia is
Ia = I−Ib (20)
It is. As a result, the temperature coefficient Tc of the current Ia is expressed by the equations (21) and (22).

Since the temperature coefficient αc of the current I4 is about −0.33 [% / ° C.] and the temperature coefficient αp of the current I4B is about +0.33 [% / ° C.],
αp = −αc (23)
If the equation (23) is rearranged, the relational expression of the temperature coefficient Tc like the equation (24) can be obtained from the currents I and Ib and the temperature coefficient αp. Since αp in Equation (24) is a known positive value, the temperature coefficient Tc of the current Ia is a negative value, and the value can be changed by changing the ratio of the current Ib to the current I. this is,
I4A = I4-I4B (25)
As shown in FIG. 4, the current I4A is obtained by subtracting the current I4B having a positive temperature coefficient from the current I4 having a negative temperature coefficient. As a result, although the temperature coefficient of the current I4A is increased compared to the current I4, the current value itself is smaller than that of the current I4.

  However, it is easy to set the reference voltage Vref to a predetermined value by increasing the resistance value R163 of the resistor 163 in accordance with the current decrease. As described above, in the configuration of FIG. 10, the temperature coefficient of the reference voltage Vref and the voltage value thereof can be set relatively arbitrarily according to the purpose.

  As described above, in the DBR type LED 61, the light output may be positive temperature dependent. In the print head 13, if the exposure energy amount fluctuates depending on the temperature, the print density fluctuates, which is not preferable. Therefore, in order to compensate for the positive temperature dependence of the LED 61, the drive current value has a negative temperature dependence. Need to give. In this case, the reference voltage Vref output from the reference voltage generation circuit 100A shown in FIG. 10 can be used as a reference for the LED drive current, and the temperature dependence of the light output of the LED 61 can be reduced to a negligible level.

  In addition, the reference voltage generation circuit 100A according to the second embodiment has an advantage that the influence on the reference voltage Vref when the power supply voltage VDD is changed can be reduced compared to the reference voltage generation circuit 100 according to the first embodiment. ing.

  As described above, in the reference voltage generating circuit 100A having the configuration of FIG. 10, the temperature coefficient of the output reference voltage Vref can be set to a desired value, and the voltage value is also predetermined independently of the temperature coefficient. And can be widely applied to various LEDs 61 and their driving devices.

(Effect of Example 2)
According to the reference voltage generating circuit 100A, the driving device, the print head 13, and the image forming apparatus 1 of the second embodiment, there are the following effects (i) and (ii).

  (I) According to the reference voltage generation circuit 100A of the second embodiment, as with the effect (a) of the first embodiment, the temperature coefficient of the output reference voltage Vref is a negative value, and the value is relatively free. Can be set to Therefore, the reference voltage Vref output from the reference voltage generation circuit 100A can be used as a reference for the LED drive current, and the temperature dependence of the light output of the LED 61 can be reduced to a negligible level.

  (Ii) In the reference voltage generation circuit 100A according to the second embodiment, the number of parts is increased as compared with the reference voltage generation circuit 100 according to the first embodiment, but the influence of the output reference voltage Vref due to the power supply voltage fluctuation is reduced. it can. Therefore, not only has the effect (b) of the first embodiment, but is effective when applied to the image forming apparatus 1 with higher print quality.

(Modification)
The present invention is not limited to the first and second embodiments, and various usage forms and modifications are possible. For example, the following forms (a) to (d) are used as the usage form and the modified examples.

  (A) In FIG. 1, FIG. 7, and FIG. 10, even if the polarity of the MOS transistor and the bipolar transistor constituting the circuit and the polarity of the power source are changed, substantially the same operational effects as the first and second embodiments can be obtained. . For example, change PMOS to NMOS, change NMOS to PMOS, change NPN to PNP, and change the first power supply to ground GND and the second power supply to VDD power supply in response to these changes. May be.

  (B) In the embodiment, the case where the light source is applied to the LED 61 has been described. However, the present invention is not limited to this, and other driven elements include, for example, a light emitting thyristor, a light emitting transistor, an organic EL element, and a heat generating element. The present invention can also be applied when voltage application control to the resistor is performed.

  (C) For example, it can be used in a printer provided with an organic EL head composed of an array of organic EL elements. Furthermore, the present invention can also be applied to driving display elements (for example, display elements arranged in a row or matrix).

  (D) The present invention is also applicable to driving a 4-terminal thyristor SCS (Silicon Semiconductor Controlled Switch) having first and second gates in addition to a thyristor having a 3-terminal structure. .

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 13 Print head 60, 60-1 to 60-n Light emitting element array 61 LED
100, 100A Reference voltage generation circuit 110, 110A First current circuit 120, 140, 160 First, second, third current mirror circuit 121-123, 141-143 PMOS
124,145,147 NPN
125, 144, 146, 163 Resistance 126, 127, 148, 149, 152, 153 NMOS
130, 130A Second current circuit 150, 150A Current subtraction circuit 151 Level shift circuit 200, 200-1 to 200-n Driver IC
210 Control voltage generation circuit 230 Latch circuit 241 Inverter 242 NAND
250 Drive circuit

Claims (8)

In a reference voltage generation circuit that is driven by a power supply voltage and generates a constant reference voltage,
A first current circuit having a first current mirror circuit having a negative temperature coefficient generated depending on the negative temperature coefficient of the base-emitter voltage of the bipolar transistor;
A second current circuit having a second current mirror circuit having a positive temperature coefficient generated depending on a negative temperature coefficient of the base-emitter voltage of the bipolar transistor;
Subtracting the output current of the second current mirror circuit from the output current of the first current mirror circuit to generate a subtraction current, and outputting the reference voltage proportional to the subtraction current to an output terminal;
A reference voltage generating circuit comprising: The reference current generating circuit according to claim 1, further comprising:
And a level shift circuit connected between the output side of the first current circuit, the output side of the second current circuit, and the input side of the current subtracting circuit, and configured to transition the level of the power supply voltage. The reference voltage generating circuit according to claim 1. The output terminal is
The first power supply is connected to a second power supply having a level different from that of the first power supply through a first resistor,
The first current circuit includes:
The first conductivity type first MOS transistor connected between the first power source and the first node, and the gate connected to the first MOS transistor in common, and connected between the first power source and the second node. A first conductivity type second MOS transistor, and a gate connected to the first MOS transistor in common, and the first conductivity type third MOS transistor connected between the first power supply and the output terminal. The first current mirror circuit,
A second resistor connected between the first node and the second power source;
A first bipolar transistor having a collector and a base connected to the second node and an emitter connected to the second power source;
The second current circuit includes:
A fourth MOS transistor of the first conductivity type connected between the first power supply and the third node, and a gate connected to the fourth MOS transistor in common, and connected between the first power supply and the fourth node. A fifth MOS transistor of the first conductivity type, a fifth MOS transistor of the first conductivity type having a gate connected to the fourth MOS transistor and connected between the first power source and a fifth node; The second current mirror circuit configured by:
A first series circuit having a second bipolar transistor in a forward direction, wherein the second bipolar transistor is connected in series between the third node and the second power supply;
A third resistor in the forward direction and a third bipolar transistor in the forward direction, wherein the third resistor and the third bipolar transistor are connected in series between the fourth node and the second power supply, and a base of the third bipolar transistor is A second series circuit connected to the fourth node and having a collector of the third bipolar transistor connected to a base of the second bipolar transistor;
The subtraction circuit
A seventh conductivity type seventh MOS transistor connected between the fifth node and the second power source, and a gate connected to the seventh MOS transistor in common, and connected between the output terminal and the second power source. 2. The reference voltage generating circuit according to claim 1, further comprising an eighth MOS transistor of the second conductivity type. The output terminal is
The first power supply is connected to a second power supply having a level different from that of the first power supply through a first resistor,
The first current circuit includes:
The first conductivity type first MOS transistor connected between the first power source and the first node, and the gate connected to the first MOS transistor in common, and connected between the first power source and the second node. A first conductivity type second MOS transistor, and a gate connected to the first MOS transistor in common, and the first conductivity type third MOS transistor connected between the first power supply and the output terminal. The first current mirror circuit,
A second resistor connected between the first node and the second power source;
A first bipolar transistor having a collector and a base connected to the second node and an emitter connected to the second power source;
The second current circuit includes:
A fourth MOS transistor of the first conductivity type connected between the first power supply and the third node, and a gate connected to the fourth MOS transistor in common, and connected between the first power supply and the fourth node. A fifth MOS transistor of the first conductivity type, a fifth MOS transistor of the first conductivity type having a gate connected to the fourth MOS transistor and connected between the first power source and a fifth node; The second current mirror circuit configured by:
A first series circuit including a third resistor and a forward second bipolar transistor, wherein the third resistor and the second bipolar transistor are connected in series between the third node and the second power supply;
A fourth resistor and a third bipolar transistor in a forward direction, the fourth resistor and the third bipolar transistor being connected in series between the fourth node and the second power supply, and a base of the third bipolar transistor being A second series circuit connected to the fourth node and having a collector of the third bipolar transistor connected to a base of the second bipolar transistor;
The subtraction circuit
A seventh conductivity type seventh MOS transistor connected between the fifth node and the second power source, and a gate connected to the seventh MOS transistor in common, and connected between the output terminal and the second power source. 2. The reference voltage generating circuit according to claim 1, further comprising an eighth MOS transistor of the second conductivity type. The level shift circuit includes:
A ninth MOS transistor of the second conductivity type diode-connected in a forward direction between the fifth node and the seventh bipolar transistor;
3. The reference voltage generating circuit according to claim 2, further comprising: a second MOS transistor of the second conductivity type that is diode-connected in a forward direction between the third MOS transistor and the output terminal. A reference voltage generating circuit that is driven by a power supply voltage to generate a constant reference voltage, and has a negative temperature coefficient generated depending on the negative temperature coefficient of the base-emitter voltage of the bipolar transistor. A first current circuit having a circuit; a second current circuit having a second current mirror circuit having a positive temperature coefficient generated depending on a negative temperature coefficient of the base-emitter voltage of the bipolar transistor; A current subtracting circuit that subtracts the output current of the second current mirror circuit from the output current of the current mirror circuit to generate a subtracted current and outputs the reference voltage proportional to the subtracted current to an output terminal; A voltage generation circuit;
A control voltage generation circuit for inputting the reference voltage output from the reference voltage generation circuit and generating a control voltage corresponding to the reference voltage;
A power supply terminal to which a power supply voltage output from the first power supply is applied; and a ground terminal to which the control voltage is applied; input a strobe signal and a data signal; and output the data signal by the strobe signal. A logic circuit that controls to output a high level voltage substantially equal to the power supply voltage or a low level voltage substantially equal to the control voltage;
A drive circuit to which the power supply voltage is applied and which supplies a drive current corresponding to the output voltage of the logic circuit to the driven element;
A drive device comprising: A print head comprising a driving device and a light emitting element array,
The driving device includes:
A reference voltage generating circuit that is driven by a power supply voltage to generate a constant reference voltage, and has a negative temperature coefficient generated depending on the negative temperature coefficient of the base-emitter voltage of the bipolar transistor. A first current circuit having a circuit; a second current circuit having a second current mirror circuit having a positive temperature coefficient generated depending on a negative temperature coefficient of the base-emitter voltage of the bipolar transistor; A current subtracting circuit that subtracts the output current of the second current mirror circuit from the output current of the current mirror circuit to generate a subtracted current and outputs the reference voltage proportional to the subtracted current to an output terminal; A voltage generation circuit;
A control voltage generation circuit for inputting the reference voltage output from the reference voltage generation circuit and generating a control voltage corresponding to the reference voltage;
A power supply terminal to which a power supply voltage output from the first power supply is applied; and a ground terminal to which the control voltage is applied; input a strobe signal and a data signal; and output the data signal by the strobe signal. A logic circuit that controls to output a high level voltage substantially equal to the power supply voltage or a low level voltage substantially equal to the control voltage;
A drive circuit to which the power supply voltage is applied and which supplies a drive current corresponding to the output voltage of the logic circuit to the driven element;
The light emitting element array is:
A print head, wherein a plurality of light emitting elements as the driven elements are arranged and emit light by the driving current. An image forming apparatus that includes a print head and that is exposed by the print head to form an image on a recording medium,
The print head includes a driving device and a light emitting element array,
The driving device includes:
A reference voltage generating circuit that is driven by a power supply voltage to generate a constant reference voltage, and has a negative temperature coefficient generated depending on the negative temperature coefficient of the base-emitter voltage of the bipolar transistor. A first current circuit having a circuit; a second current circuit having a second current mirror circuit having a positive temperature coefficient generated depending on a negative temperature coefficient of the base-emitter voltage of the bipolar transistor; A current subtracting circuit that subtracts the output current of the second current mirror circuit from the output current of the current mirror circuit to generate a subtracted current and outputs the reference voltage proportional to the subtracted current to an output terminal; A voltage generation circuit;
A control voltage generation circuit for inputting the reference voltage output from the reference voltage generation circuit and generating a control voltage corresponding to the reference voltage;
A power supply terminal to which a power supply voltage output from the first power supply is applied; and a ground terminal to which the control voltage is applied; input a strobe signal and a data signal; and output the data signal by the strobe signal. A logic circuit that controls to output a high level voltage substantially equal to the power supply voltage or a low level voltage substantially equal to the control voltage;
A drive circuit to which the power supply voltage is applied and which supplies a drive current corresponding to the output voltage of the logic circuit to the driven element;
The light emitting element array is:
An image forming apparatus, wherein a plurality of light emitting elements as the driven elements are arranged and emit light by the driving current.

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