JP2012191101A - Manufacturing method of circuit board - Google Patents

Manufacturing method of circuit board Download PDF

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JP2012191101A
JP2012191101A JP2011055128A JP2011055128A JP2012191101A JP 2012191101 A JP2012191101 A JP 2012191101A JP 2011055128 A JP2011055128 A JP 2011055128A JP 2011055128 A JP2011055128 A JP 2011055128A JP 2012191101 A JP2012191101 A JP 2012191101A
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circuit board
base material
insulating base
interlayer connection
manufacturing
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Jun Ebara
潤 江原
Kazutomo Higa
一智 比嘉
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Panasonic Corp
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Panasonic Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a circuit board having a double side structure or a multilayer structure which has high density and an excellent wiring housing function and achieves stable interlayer electrical connection.SOLUTION: A circuit board for an inner layer electrically connects with an outer layer circuit through conduction holes of an insulation base material for interlayer connection, and a hardening part is selectively formed on the insulation base material for the interlayer connection. The structure minimizes variations caused in the manufacturing processes of the circuit board, dimension changes of the insulation base material or the insulation base material for the interlayer connection, and the like and improves the positioning accuracy of the lamination of the circuit board having the multilayer structure.

Description

本発明は、両面あるいは多層の層間を導通孔を介して電気的に接続する回路基板の製造方法に関するものである。   The present invention relates to a method of manufacturing a circuit board in which both surfaces or multilayer layers are electrically connected through a conduction hole.

近年、電子機器の小型化、高性能化に伴い、産業用にとどまらず広く民生用機器の分野においても、LSI等の半導体チップを高密度に実装できる多層の回路基板が安価に供給されることが強く要望されてきている。このような多層の回路基板では、微細な配線ピッチで形成された複数層の層間を高い接続信頼性で電気的に接続できることが重要である。   In recent years, with the downsizing and higher performance of electronic devices, multilayer circuit boards capable of mounting LSI chips and other semiconductor chips at a high density have been supplied at low cost not only for industrial use but also in the field of consumer equipment. Has been strongly requested. In such a multilayer circuit board, it is important that a plurality of layers formed with a fine wiring pitch can be electrically connected with high connection reliability.

従来、このような市場の要望に対して、従来の多層の回路基板の層間接続の主流となっていたスルーホール内壁の金属めっき導体に代えて、任意の位置において層間接続できる全層IVH構造と呼ばれるインナービアホール接続法は注目されてきた。   Conventionally, in response to such market demand, an all-layer IVH structure capable of interlayer connection at an arbitrary position instead of the metal plating conductor on the inner wall of the through hole, which has been the mainstream of interlayer connection of conventional multilayer circuit boards, The so-called inner via hole connection method has attracted attention.

前記の構造においては、必要な各層間のみを接続することが可能であり、部品実装用のランドの直下にインナービアホールを設けることができるために、基板サイズの小型化や高密度実装を実現することができる。また、インナービアホールにおける電気的接続は導電性ペーストを用いているために、ビアホールにかかる応力を緩和することができ、熱衝撃等による寸法変化に対して安定な電気的接続を実現することができる。   In the above-described structure, it is possible to connect only the necessary layers, and the inner via hole can be provided directly under the component mounting land, so that the substrate size can be reduced and high-density mounting can be realized. be able to. Further, since the electrical connection in the inner via hole uses a conductive paste, the stress applied to the via hole can be relieved and a stable electrical connection can be realized against a dimensional change due to a thermal shock or the like. .

この全層IVH構造の多層の回路基板は、図5に示すような工程で製造される。この従来の回路基板の製造方法について以下に説明する。   This multi-layer circuit board having an all-layer IVH structure is manufactured by a process as shown in FIG. This conventional circuit board manufacturing method will be described below.

まず図5(a)に示すように、絶縁基材21の両側にPETフィルム24をラミネートによって貼り付ける。なお、絶縁基材21には、被圧縮性を有する多孔質等の基材やコアフィルムの両側に接着剤層が形成された3層構造のもの、繊維と樹脂の複合基材等が用いられる。   First, as shown to Fig.5 (a), the PET film 24 is affixed on both sides of the insulating base material 21 by a lamination. As the insulating base material 21, a porous base material having compressibility, a three-layer structure in which an adhesive layer is formed on both sides of the core film, a composite base material of fiber and resin, or the like is used. .

前記のラミネートの際に、絶縁基材21とPETフィルム24は高温状態で接着するため、両者の界面には絶縁基材21とPETフィルム24の熱膨張係数の違いに起因する応力が発生している。   Since the insulating base material 21 and the PET film 24 are bonded at a high temperature during the above-described lamination, stress due to the difference in thermal expansion coefficient between the insulating base material 21 and the PET film 24 is generated at the interface between them. Yes.

次に図5(b)に示すように、レーザー加工等により絶縁基材21とPETフィルム24に貫通孔25を形成する。   Next, as shown in FIG. 5B, through holes 25 are formed in the insulating base material 21 and the PET film 24 by laser processing or the like.

次に図5(c)に示すように、貫通孔25に導電性ペースト26を充填する。このPETフィルム24は絶縁基材21の表面に導電性ペースト26が残存しないようにする役割を果たす。   Next, as shown in FIG. 5 (c), the conductive paste 26 is filled in the through holes 25. The PET film 24 serves to prevent the conductive paste 26 from remaining on the surface of the insulating base material 21.

次に図5(d)に示すように、両側のPETフィルム24を剥離する。この剥離工程において、PETフィルム24を絶縁基材21に形成する際に発生していた両者の間の応力が開放されるため、絶縁基材21に寸法変化が発生する。   Next, as shown in FIG. 5D, the PET films 24 on both sides are peeled off. In this peeling process, since the stress between the two that has been generated when the PET film 24 is formed on the insulating base material 21 is released, a dimensional change occurs in the insulating base material 21.

次に図5(e)に示すように、絶縁基材21の両側から銅箔28を積層配置し、図5(f)に示すように、加熱加圧することにより、銅箔28を絶縁基材21に接着させる。この際、絶縁基材21が厚み方向に収縮するため、導電性ペースト26も厚み方向に圧縮される。これにより、導電性ペースト26内の金属フィラーどうしが高密度に接触し、銅箔28と導電性ペースト26が電気的に接続される。   Next, as shown in FIG. 5 (e), the copper foil 28 is laminated from both sides of the insulating base material 21, and the copper foil 28 is insulated by heating and pressing as shown in FIG. 5 (f). Adhere to 21. At this time, since the insulating substrate 21 contracts in the thickness direction, the conductive paste 26 is also compressed in the thickness direction. As a result, the metal fillers in the conductive paste 26 come into contact with each other at high density, and the copper foil 28 and the conductive paste 26 are electrically connected.

次に図5(g)に示すように、銅箔28に回路29を形成し、両面の回路基板30を得る。   Next, as shown in FIG. 5G, a circuit 29 is formed on the copper foil 28 to obtain a double-sided circuit board 30.

次に図6(a)に示すように、回路基板30の両側に、図5(a)〜(d)と同様の工程で形成した導電性ペースト26が充填された層間接続用の絶縁基材22と銅箔28とを積層する。この層間接続用の絶縁基材22も前述の例と同様に、PETフィルム24の剥離の際に寸法変化が生じている。   Next, as shown in FIG. 6 (a), an insulating substrate for interlayer connection in which conductive paste 26 formed in the same process as in FIGS. 5 (a) to 5 (d) is filled on both sides of the circuit board 30. 22 and copper foil 28 are laminated. The insulating base material 22 for interlayer connection also has a dimensional change when the PET film 24 is peeled off, as in the above example.

次に図6(b)に示すように、加熱加圧することにより、銅箔28と絶縁基材22と回路基板30とを接着する。   Next, as shown in FIG. 6B, the copper foil 28, the insulating base material 22, and the circuit board 30 are bonded by heating and pressing.

この加熱加圧工程で絶縁基材22が厚み方向に収縮するとともに、導電性ペースト26が厚み方向に圧縮され、銅箔28と回路基板30の回路29とが電気的に接続される。   In this heating and pressurizing step, the insulating base material 22 contracts in the thickness direction, the conductive paste 26 is compressed in the thickness direction, and the copper foil 28 and the circuit 29 of the circuit board 30 are electrically connected.

次に、表層の銅箔28を回路形成することにより、図6(c)に示す多層の回路基板40を得る。   Next, a multilayered circuit board 40 shown in FIG. 6C is obtained by forming a circuit on the surface copper foil 28.

なお、この出願の発明に関連する先行技術文献情報としては、例えば、特許文献1が公知である。   For example, Patent Document 1 is known as prior art document information related to the invention of this application.

特開2009−188311号公報JP 2009-188311 A

しかしながら、上記の従来の回路基板の製造方法では、回路形成時や加熱加圧時での寸法変化、および貫通孔の加工位置精度のバラツキに加えて、絶縁基材の表面にラミネートしたPETフィルムを剥離する際に絶縁基材の寸法変化等が生じる。   However, in the conventional circuit board manufacturing method, the PET film laminated on the surface of the insulating substrate is used in addition to the dimensional change at the time of circuit formation or heating and pressurization, and the variation in the processing position accuracy of the through hole. When it peels, the dimensional change etc. of an insulating base material arise.

これにより、回路形成された接続用のランドと絶縁基材に設けられた導通孔との合致が困難となり、著しく悪い場合は、隣接した回路間で絶縁不良に至る可能性もあった。   This makes it difficult to match the connection lands formed in the circuit with the conduction holes provided in the insulating base material, and when it is extremely bad, there is a possibility that insulation failure occurs between adjacent circuits.

これを解決するため、上記工程での加工におけるバラツキや絶縁基材の寸法変化を許容できるように、接続用のランド径を大きくすることも考慮されたが、高密度回路の形成や配線の収容性を向上させるうえでは相反するものであった。特に、導通孔の小径化、回路の細線化または絶縁基材の厚みを薄くした場合、上記の問題が顕著となり、高精細な多層の回路基板を製造する際の課題であった。   In order to solve this, it was considered to increase the land diameter for connection so as to allow variation in processing in the above process and dimensional change of the insulating base material. It was contradictory in improving the property. In particular, when the diameter of the conductive hole is reduced, the circuit is thinned, or the thickness of the insulating base material is reduced, the above problem becomes remarkable, which is a problem in manufacturing a high-definition multilayer circuit board.

本発明は、上記の従来の課題を解決し、高密度で高い配線収容性を備えた両面あるいは多層構造の回路基板を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described conventional problems and to provide a double-sided or multilayer circuit board having a high density and high wiring capacity.

上記目的を達成するために、本発明の回路基板の製造方法は、半硬化状態の絶縁基材を準備する工程と、前記絶縁基材に選択的に硬化部を形成する工程と、前記絶縁基材に導通孔を形成する工程と、前記絶縁基材の表面に金属箔を積層し加熱加圧する工程と、前記金属箔に回路を形成する工程とを備えることを特徴とするものである。   In order to achieve the above object, a method of manufacturing a circuit board according to the present invention includes a step of preparing a semi-cured insulating base, a step of selectively forming a cured portion on the insulating base, and the insulating base. The method includes a step of forming a conduction hole in the material, a step of laminating a metal foil on the surface of the insulating base material, heating and pressing, and a step of forming a circuit on the metal foil.

また、内層用回路基板と半硬化状態の層間接続用絶縁基材を準備する工程と、前記層間接続用絶縁基材に選択的に硬化部を形成する工程と、前記層間接続用絶縁基材に導通孔を形成する工程と、前記内層用回路基板と前記層間接続用絶縁基材と最外層に金属箔を積層する工程と、それを加熱加圧する工程と、前記金属箔に回路を形成する工程とを備えることを特徴とするものである。   A step of preparing an inner layer circuit board and a semi-cured interlayer connection insulating base material; a step of selectively forming a cured portion on the interlayer connection insulating base material; and the interlayer connection insulating base material. A step of forming a conductive hole, a step of laminating a metal foil on the inner layer circuit board, the interlayer connecting insulating base material and the outermost layer, a step of heating and pressing the metal foil, and a step of forming a circuit on the metal foil Are provided.

本発明の回路基板の構造は、絶縁基材あるいは層間接続用絶縁基材には選択的に硬化部が形成されていることから、回路基板の製造過程でのバラツキや、絶縁基材あるいは層間接続用絶縁基材の寸法変化等を最小にし、多層構造の回路基板の位置決め積層精度を向上させることができる。   The structure of the circuit board of the present invention has a cured portion selectively formed in the insulating base material or the insulating base material for interlayer connection. Therefore, it is possible to minimize the dimensional change of the insulating base material for use and improve the positioning and stacking accuracy of the circuit board having a multilayer structure.

これにより、導通孔や配線回路の形成位置を安定させることができ、高精細な全層IVH構造の配線基板を提供することができる。さらに、導電体を微小化し絶縁基材を薄手化した際でも同様の効果を得ることが可能である。   Thereby, the formation position of a conduction hole or a wiring circuit can be stabilized, and a high-definition all-layer IVH structure wiring board can be provided. Furthermore, the same effect can be obtained even when the conductor is miniaturized and the insulating base material is thinned.

本発明の実施の形態における回路基板の製造方法の工程を示す断面図Sectional drawing which shows the process of the manufacturing method of the circuit board in embodiment of this invention 同実施の形態における回路基板の製造方法の一過程を示す概略図Schematic which shows one process of the manufacturing method of the circuit board in the embodiment 同実施の形態における回路基板の製造方法の工程を示す断面図Sectional drawing which shows the process of the manufacturing method of the circuit board in the embodiment 同実施の形態における回路基板の製造方法の一過程を示す概略図Schematic which shows one process of the manufacturing method of the circuit board in the embodiment 従来の回路の製造方法の工程を示す断面図Sectional drawing which shows the process of the manufacturing method of the conventional circuit 従来の回路の製造方法の工程を示す断面図Sectional drawing which shows the process of the manufacturing method of the conventional circuit

以下、本発明の実施の形態について図面を参照しながら説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図1(a)〜(i)は本発明の実施の形態における回路基板の製造方法を示す工程断面図である。   1A to 1I are process cross-sectional views illustrating a circuit board manufacturing method according to an embodiment of the present invention.

まず、図1(a)に示すように半硬化状態(Bステージ状態)の絶縁基材1を準備する。   First, as shown to Fig.1 (a), the semi-hardened state (B stage state) insulating base material 1 is prepared.

本実施の形態では絶縁基材1として60μm厚のガラス繊維の織布とエポキシ樹脂の複合材料を用いる。絶縁基材1としてはガラス繊維の他に、アラミドの織布や不織布の基材に熱硬化樹脂との複合材料等を用いることができる。またポリイミドフィルム、アラミドフィルム、液晶ポリマーフィルムなどを用いてもよい。   In this embodiment, a 60 μm-thick glass fiber woven fabric and an epoxy resin composite material are used as the insulating substrate 1. As the insulating substrate 1, in addition to glass fibers, a composite material with a thermosetting resin or the like can be used for an aramid woven fabric or a nonwoven fabric substrate. Moreover, you may use a polyimide film, an aramid film, a liquid crystal polymer film, etc.

なお絶縁基材1は、後述するように、多層構造の回路基板の製造において層間接続用絶縁基材2として用いることもできる。   As will be described later, the insulating base material 1 can also be used as an insulating base material 2 for interlayer connection in the manufacture of a circuit board having a multilayer structure.

次に図1(b)に示すように、絶縁基材1に選択的に硬化部3を形成する。   Next, as shown in FIG. 1B, the cured portion 3 is selectively formed on the insulating base material 1.

硬化部3は、レーザー加工にて行うことも可能であり、線状または帯状に形成されることが望ましい。この場合のレーザー加工条件は、絶縁基材1中のガラス繊維等の基材を破壊しない程度のレーザーエネルギー条件、あるいは、焦点をずらし帯状に樹脂のみを硬化させる条件で行う。   The hardened portion 3 can be performed by laser processing, and is preferably formed in a linear shape or a strip shape. The laser processing conditions in this case are performed under laser energy conditions that do not destroy the base material such as glass fiber in the insulating base material 1, or under conditions where the focus is shifted and only the resin is cured in a band shape.

これにより、半硬化状態の絶縁基材1の一部が硬化されることにより、寸法を安定させることができ、寸法の歪みを防止することもできるという効果を有する。   Thereby, when a part of the semi-cured insulating base material 1 is cured, the dimensions can be stabilized, and distortion of the dimensions can be prevented.

また、硬化部3は、加熱手段にて絶縁基材1または層間接続用絶縁基材2に加熱加圧して凹状に形成することが可能であり、これにより、寸法の安定化を図るとともに後述する積層、加熱加圧工程において、樹脂の流れを防止し、いわゆる、「ビア倒れ」(樹脂の流れによる導通孔の傾き・変形)のない導通孔を形成することができ、層間接続を安定させることができるという効果を有する。   Moreover, the hardening part 3 can be formed into a concave shape by heating and pressurizing the insulating base material 1 or the interlayer connecting insulating base material 2 with a heating means, thereby stabilizing the dimensions and will be described later. In the laminating and heating / pressing process, the flow of resin can be prevented, and so-called “via collapse” (conduction hole tilt / deformation due to resin flow) can be formed, and the interlayer connection can be stabilized. Has the effect of being able to.

また、半硬化状態の絶縁基材1または層間接続用絶縁基材2に硬化部3が存在することにより、後述する積層工程において、前記基材に張力をかけても歪みや変形が生じにくくなる。すなわち、樹脂が硬化された硬化部3の存在により、前記基材全体の弾性率が低下し、回路基板の製造過程でのバラツキや、絶縁基材1あるいは層間接続用絶縁基材2の寸法変化等を最小にすることができる。   In addition, the presence of the cured portion 3 in the semi-cured insulating base material 1 or the interlayer connection insulating base material 2 makes it difficult for distortion and deformation to occur even when tension is applied to the base material in the laminating process described later. . That is, due to the presence of the cured portion 3 where the resin is cured, the elastic modulus of the entire base material is reduced, variation in the manufacturing process of the circuit board, and dimensional change of the insulating base material 1 or the insulating base material 2 for interlayer connection. Etc. can be minimized.

さらに、本発明の実施の形態における回路基板は製造用ワークでの過程において、図2に示すように、電子部品等が実装される製品となる製品部領域Pと製造工程の終盤工程での外形加工にて除去あるいは、部品実装後に電子機器に組み込まれる前に除去される非製品部領域Rとに区分され、硬化部3は非製品部領域Rに形成することが望ましい。   Further, the circuit board according to the embodiment of the present invention has a product part region P to be a product on which electronic components and the like are mounted and an outer shape in the final stage of the manufacturing process as shown in FIG. It is preferable that the hardened portion 3 is formed in the non-product portion region R by being divided into non-product portion regions R that are removed by processing or removed after being mounted on the electronic device after being mounted.

これにより、硬化部3が形成されることによる回路や導通孔への影響を除くことができる。   Thereby, the influence on the circuit and conduction | electrical_connection hole by the hardening part 3 being formed can be excluded.

特に、硬化部3は製品部領域Pと非製品部領域Rの境界付近に形成することにより、少ない面積で効率的に、かつ製品部領域P内の寸法を安定させるうえでも効果的である。   In particular, by forming the hardened portion 3 near the boundary between the product portion region P and the non-product portion region R, it is effective in stabilizing the dimensions in the product portion region P efficiently with a small area.

なお、境界付近とは、製品部領域Pと非製品部領域Rの境界線Q上を含むものの、製品部領域Pには属さない領域とする。   Note that the vicinity of the boundary includes an area on the boundary line Q between the product part region P and the non-product part region R, but does not belong to the product part region P.

前記の境界が製品部の外形加工線上である場合、その付近に硬化部3を形成することにより、より効果的に製品部領域P内の寸法を安定させることができる。   When the boundary is on the outer shape processing line of the product portion, the dimension in the product portion region P can be more effectively stabilized by forming the hardened portion 3 in the vicinity thereof.

製品部の外形加工線上の付近に硬化部3を形成するうえにおいて、前述のレーザー加工を用いることで容易にかつ正確な位置で精度良く形成することができる。   In forming the hardened portion 3 in the vicinity of the outer shape processing line of the product portion, it can be easily and accurately formed at an accurate position by using the laser processing described above.

次に図1(c)に示すように、硬化部3を有する絶縁基材1の両側にPETフィルム4をラミネートによって貼り付ける。   Next, as shown in FIG.1 (c), the PET film 4 is affixed on both sides of the insulating base material 1 which has the hardening part 3 by lamination.

このラミネートの際に、絶縁基材1とPETフィルム4は高温状態で接着するため、両者の界面には絶縁基材1とPETフィルム4の熱膨張係数の違いに起因する応力が発生する。しかしながら、硬化部3の存在により応力の値は減少する。   During the lamination, the insulating base material 1 and the PET film 4 are bonded at a high temperature, and therefore stress is generated at the interface between the insulating base material 1 and the PET film 4 due to the difference in thermal expansion coefficient between the insulating base material 1 and the PET film 4. However, the stress value decreases due to the presence of the hardened portion 3.

次に図1(d)に示すように、レーザー加工等により絶縁基材1とPETフィルム4に貫通孔5を形成する。   Next, as shown in FIG.1 (d), the through-hole 5 is formed in the insulating base material 1 and the PET film 4 by laser processing etc. FIG.

次に図1(e)に示すように、貫通孔5に導電性ペースト6を充填する。このPETフィルム4は絶縁基材1の表面に導電性ペースト6が残存しないようにする役割を果たす。なお、導電性ペースト6は、銅粉等の金属フィラーと熱硬化性樹脂を主体とするものである。   Next, as shown in FIG. 1E, the through-hole 5 is filled with a conductive paste 6. The PET film 4 serves to prevent the conductive paste 6 from remaining on the surface of the insulating base 1. The conductive paste 6 is mainly composed of a metal filler such as copper powder and a thermosetting resin.

次に図1(f)に示すように、両側のPETフィルム4を剥離し、貫通孔5に導電性ペースト6を充填された硬化前の状態の導通孔7を形成する。   Next, as shown in FIG. 1 (f), the PET films 4 on both sides are peeled, and the through holes 5 are filled with the conductive paste 6 to form the conductive holes 7 in the uncured state.

この剥離工程において、PETフィルム4を絶縁基材1に形成する際に発生したPETフィルム4と絶縁基材1の間の応力が開放されるため、通常は絶縁基材1に寸法変化がおこるものの、硬化部3の存在によりその変化の値は減少する。   In this peeling process, since the stress between the PET film 4 and the insulating base material 1 generated when the PET film 4 is formed on the insulating base material 1 is released, the insulating base material 1 usually undergoes a dimensional change. The value of the change decreases due to the presence of the hardened portion 3.

次に図1(g)に示すように、絶縁基材1の両側に金属箔としての銅箔8を積層配置し、図1(h)に示す加熱加圧することにより、銅箔8を絶縁基材1に接着させる。この際、絶縁基材1が厚み方向に収縮するため、貫通孔5内の導電性ペースト6も厚み方向に圧縮される。これにより、導電性ペースト6中の金属フィラーどうしが高密度に接触し、両側の銅箔8が導通孔7を介して電気的に接続される。   Next, as shown in FIG. 1 (g), copper foils 8 as metal foils are laminated on both sides of the insulating substrate 1, and heated and pressurized as shown in FIG. Adhere to material 1. At this time, since the insulating substrate 1 contracts in the thickness direction, the conductive paste 6 in the through hole 5 is also compressed in the thickness direction. As a result, the metal fillers in the conductive paste 6 come into contact with each other at high density, and the copper foils 8 on both sides are electrically connected through the conduction holes 7.

次に図1(i)に示すように、銅箔8に回路9を形成し、両面の回路基板10を得る。   Next, as shown in FIG. 1I, a circuit 9 is formed on the copper foil 8 to obtain a circuit board 10 on both sides.

なお、導通孔を備えた半硬化状態の絶縁基材1に選択的に形成された硬化部3は、図1(h)の工程の加熱加圧により、絶縁基材1上の硬化部3と非硬化部の区別がつきにくくなるものと思われるが、実際には、レーザー加工にて線状または帯状の硬化部に形成する際に、加熱し変質されることによって残存させることができ、また、加熱手段にて絶縁基材を加熱加圧して凹状に形成することで残存させることも可能である。   Note that the cured portion 3 selectively formed on the semi-cured insulating base material 1 provided with the conduction holes is formed by the heating and pressurization in the step of FIG. It seems that it becomes difficult to distinguish the non-cured part, but in fact, it can be left by heating and alteration when it is formed into a linear or belt-shaped cured part by laser processing. It is also possible to leave the insulating base material by heating and pressing it with a heating means to form a concave shape.

次に多層構造の回路基板の製造方法について図面を参照しながら説明する。   Next, a method of manufacturing a multilayer circuit board will be described with reference to the drawings.

図3(a)〜(c)は本発明の実施の形態における回路基板の製造方法を示す工程断面図である。   3A to 3C are process cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment of the present invention.

まず、図3(a)に示すように、両面に回路を有する内層用回路基板11と半硬化状態の層間接続用絶縁基材2を準備する。   First, as shown in FIG. 3A, an inner layer circuit board 11 having circuits on both sides and a semi-cured interlayer connection insulating base material 2 are prepared.

内層用回路基板11としては、めっき等により両面の導通を図った銅スルーホール配線板でもよいが、図1(a)〜図1(h)の工程で製造した両面の回路基板10を用いることが望ましい。   The inner layer circuit board 11 may be a copper through-hole wiring board that is conductive on both sides by plating or the like, but the double-sided circuit board 10 manufactured in the steps of FIGS. Is desirable.

本実施の形態における内層用回路基板11は、高密度で配線収容性も高く、さらに絶縁基材1に選択的に形成された硬化部3の存在により、寸法も安定したものである。   The inner layer circuit board 11 in the present embodiment has a high density and high wiring capacity, and has a stable dimension due to the presence of the hardened portion 3 selectively formed on the insulating base material 1.

また、層間接続用絶縁基材2は、図1(a)〜図1(f)の過程、すなわち、絶縁基材1に選択的に硬化部3を形成し、絶縁基材1の両側にPETフィルム4をラミネートした後、貫通孔5を形成し、貫通孔5に導電性ペースト6を充填し、PETフィルム4を剥離して得られた導通孔7を有するものを層間接続用絶縁基材2として用いる。   Further, the insulating base material 2 for interlayer connection is formed in the process of FIGS. 1A to 1F, that is, the cured portion 3 is selectively formed on the insulating base material 1, and the PET is formed on both sides of the insulating base material 1. After laminating film 4, through-hole 5 is formed, conductive paste 6 is filled in through-hole 5, and conductive film 7 obtained by peeling PET film 4 is used as insulating base material 2 for interlayer connection. Used as

この層間接続用絶縁基材2も前述の絶縁基材1の事例と同様に、PETフィルム4の剥離の際に寸法変化が生ずるものの、硬化部3の存在により、従来に比較して寸法変化の値は小さくなる。   As in the case of the insulating base material 1, the interlayer connecting insulating base material 2 also undergoes a dimensional change when the PET film 4 is peeled off. The value becomes smaller.

次に図3(a)に示すように、内層用回路基板11としての回路基板の両側に、層間接続用絶縁基材2と金属箔としての銅箔8とを積層する。なお、積層においては、複数の内層用回路基板11と層間接続用絶縁基材2とを準備し、それらを位置合わせしながら交互に積層して、最外層に銅箔8を積層する構成としてもよい。   Next, as shown in FIG. 3A, the interlayer connection insulating base 2 and the copper foil 8 as the metal foil are laminated on both sides of the circuit board as the inner layer circuit board 11. In addition, in the lamination, a plurality of inner layer circuit boards 11 and interlayer connection insulating base materials 2 are prepared, and they are alternately laminated while being aligned, and the copper foil 8 is laminated on the outermost layer. Good.

上記の内層用回路基板11に位置決め固定される層間接続用絶縁基材2の導通孔7は、内層用回路基板11に形成されたランド12の位置を認識し、導通孔7がランド12の中心又は少なくともランド12からはみ出さないよう位置決め固定される。   The conduction hole 7 of the interlayer connection insulating substrate 2 positioned and fixed to the inner layer circuit board 11 recognizes the position of the land 12 formed in the inner layer circuit board 11, and the conduction hole 7 is the center of the land 12. Alternatively, the positioning is fixed so as not to protrude from at least the land 12.

また、上記の積層する工程において、図4に示すように、層間接続用絶縁基材2に形成された硬化部3に張力Tを加えながら行うことも可能である。   Further, in the above-described laminating step, as shown in FIG. 4, it can be performed while applying a tension T to the cured portion 3 formed on the interlayer connection insulating base 2.

すなわち、内層用回路基板11と層間接続用絶縁基材2に形成された認識マークが互いに合致するように、Bステージ状態の層間接続用絶縁基材2に張力Tを加えることにより、寸法を微調整することができる。   That is, by applying tension T to the interlayer connection insulating base material 2 in the B stage state so that the recognition marks formed on the inner layer circuit board 11 and the interlayer connection insulating base material 2 match each other, the dimensions can be reduced. Can be adjusted.

特に、硬化部3が形成されていることから、硬化部3が形成されていない場合に比較して張力Tの影響で層間接続用絶縁基材2が大きく伸びることや変形することを防ぐことができる。   In particular, since the cured portion 3 is formed, it is possible to prevent the interlayer connection insulating base material 2 from being greatly elongated or deformed due to the influence of the tension T as compared with the case where the cured portion 3 is not formed. it can.

次に図3(b)に示すように、加熱加圧することにより、層間接続用絶縁基材2を介して銅箔8と内層用回路基板11とを接着し硬化する。   Next, as shown in FIG. 3B, the copper foil 8 and the inner layer circuit board 11 are bonded and cured through the interlayer connection insulating substrate 2 by heating and pressing.

この加熱加圧工程で層間接続用絶縁基材2が厚み方向に収縮するとともに、導通孔7内の導電性ペースト6が厚み方向に圧縮され、銅箔8と内層用回路基板11の回路9とが導通孔7を介して電気的に接続される。   In this heating and pressurizing step, the interlayer connection insulating base material 2 shrinks in the thickness direction, and the conductive paste 6 in the conduction hole 7 is compressed in the thickness direction, so that the copper foil 8 and the circuit 9 of the inner layer circuit board 11 Are electrically connected through the conduction hole 7.

次に図3(c)に示すように、表層の銅箔8を回路形成し、内層用回路基板11と電気的に接続された外層の回路9とすることにより、多層構造の回路基板20を得ることができる。   Next, as shown in FIG. 3C, a surface layer copper foil 8 is formed into a circuit, and an outer layer circuit 9 electrically connected to the inner layer circuit board 11 is formed. Obtainable.

本実施の形態における回路基板20は、内層用回路基板11及び層間接続用絶縁基材2には選択的に硬化部3が形成されていることから、層間の位置精度と層間の電気的接続を安定させることができる。   In the circuit board 20 in the present embodiment, the inner layer circuit board 11 and the interlayer connection insulating base material 2 are selectively formed with the hardened portion 3, so that the positional accuracy between the layers and the electrical connection between the layers are improved. It can be stabilized.

また、層間接続用絶縁基材2の硬化部3が防止壁としての作用を有することから、積層、加熱加圧工程における基材中の樹脂の流れを抑制し、これによる導通孔7の傾きや変形を防ぐことができ、このことからも本発明は多層構造の回路基板の層間の電気的接続を安定させることができる。   Moreover, since the hardening part 3 of the insulating base material 2 for interlayer connection has a function as a prevention wall, the flow of the resin in the base material in the laminating and heating and pressing processes is suppressed, and the inclination of the conduction hole 7 due to this is suppressed. The deformation can be prevented, and the present invention can also stabilize the electrical connection between the layers of the multilayer circuit board.

なお、本実施の形態においては、内層用回路基板として両面の回路基板10を用いた4層の多層構造の回路基板の事例を示したが、本実施の形態の多層構造の回路基板20を内層用回路基板として用いることで、さらに多層化を図ることも可能である。   In the present embodiment, an example of a circuit board having a multilayer structure of four layers using both-side circuit boards 10 as an inner layer circuit board has been shown, but the circuit board 20 having a multilayer structure of the present embodiment is used as an inner layer. It is possible to further increase the number of layers by using it as a circuit board.

以上のように本発明は、回路基板を構成する絶縁基材あるいは層間接続用絶縁基材に選択的に硬化部が形成されていることを特徴とする。この構成により、回路基板の製造過程でのバラツキや、絶縁基材あるいは層間接続用絶縁基材の寸法変化等を最小にし、多層構造の回路基板の位置決め積層精度を向上させることができる。   As described above, the present invention is characterized in that a cured portion is selectively formed on an insulating base material or an insulating base material for interlayer connection that constitutes a circuit board. With this configuration, variations in the circuit board manufacturing process, changes in dimensions of the insulating base material or the insulating base material for interlayer connection, and the like can be minimized, and the positioning and stacking accuracy of the circuit board having a multilayer structure can be improved.

このことから本発明は、安定した品質の回路基板を提供しうるものであり、産業上の利用可能性は大といえる。   Therefore, the present invention can provide a stable quality circuit board, and can be said to have great industrial applicability.

1 絶縁基材
2 層間接続用絶縁基材
3 硬化部
4 PETフィルム
5 貫通孔
6 導電性ペースト
7 導通孔
8 銅箔
9 回路
10、20 回路基板
11 内層用回路基板
12 ランド
DESCRIPTION OF SYMBOLS 1 Insulation base material 2 Insulation base material for interlayer connection 3 Curing part 4 PET film 5 Through-hole 6 Conductive paste 7 Conductive hole 8 Copper foil 9 Circuit 10, 20 Circuit board 11 Circuit board for inner layer 12 Land

Claims (11)

半硬化状態の絶縁基材を準備する工程と、
前記絶縁基材に選択的に硬化部を形成する工程と、
前記絶縁基材に導通孔を形成する工程と、
前記絶縁基材の表面に金属箔を積層し加熱加圧する工程と、
前記金属箔に回路を形成する工程とを備えることを特徴とする回路基板の製造方法。
Preparing a semi-cured insulating substrate;
Selectively forming a cured portion on the insulating substrate;
Forming a conduction hole in the insulating substrate;
Laminating a metal foil on the surface of the insulating substrate and heating and pressing; and
And a step of forming a circuit on the metal foil.
内層用回路基板と半硬化状態の層間接続用絶縁基材を準備する工程と、
前記層間接続用絶縁基材に選択的に硬化部を形成する工程と、
前記層間接続用絶縁基材に導通孔を形成する工程と、
前記内層用回路基板と前記層間接続用絶縁基材と最外層に金属箔を積層する工程と、
それを加熱加圧する工程と、
前記金属箔に回路を形成する工程とを備えることを特徴とする回路基板の製造方法。
Preparing an inner layer circuit board and a semi-cured interlayer connection insulating base;
Selectively forming a cured portion on the insulating substrate for interlayer connection;
Forming a conduction hole in the insulating substrate for interlayer connection;
Laminating a metal foil on the inner layer circuit board, the interlayer connection insulating base and the outermost layer;
Heating and pressurizing it;
And a step of forming a circuit on the metal foil.
内層用回路基板は、導通孔を備えた絶縁基材と前記導通孔を介して表裏が電気的に接続された内層用回路とを備え、前記絶縁基材には選択的に硬化部が形成されていることを特徴とする請求項2に記載の回路基板の製造方法。 The inner layer circuit board includes an insulating base material having a conduction hole and an inner layer circuit electrically connected to the front and back through the conduction hole, and a cured portion is selectively formed on the insulating base material. The circuit board manufacturing method according to claim 2, wherein 硬化部は線状または帯状に形成されていることを特徴とする請求項1または請求項2に記載の回路基板の製造方法。 The method for manufacturing a circuit board according to claim 1, wherein the hardened portion is formed in a linear shape or a strip shape. 硬化部は加圧により凹状に形成されていることを特徴とする請求項1または請求項2に記載の回路基板の製造方法。 The method for manufacturing a circuit board according to claim 1, wherein the hardened portion is formed in a concave shape by pressurization. 回路基板は製品部領域と非製品部領域を有し、硬化部は非製品部領域に形成されていることを特徴とする請求項1または請求項2に記載の回路基板の製造方法。 The circuit board manufacturing method according to claim 1, wherein the circuit board has a product part region and a non-product part region, and the cured part is formed in the non-product part region. 回路基板は製品部領域と非製品部領域を有し、硬化部は製品部領域と非製品部領域の境界付近に形成されていることを特徴とする請求項1または請求項2に記載の回路基板の製造方法。 3. The circuit according to claim 1, wherein the circuit board has a product part region and a non-product part region, and the hardened part is formed near a boundary between the product part region and the non-product part region. A method for manufacturing a substrate. 製品部領域と非製品部領域の境界は製品部の外形加工線上であることを特徴とする請求項7に記載の回路基板の製造方法。 The circuit board manufacturing method according to claim 7, wherein a boundary between the product part region and the non-product part region is on an outer shape processing line of the product part. 選択的に硬化部を形成する工程は、レーザー加工にて行うことを特徴とする請求項1または請求項2に記載の回路基板の製造方法。 The method for manufacturing a circuit board according to claim 1, wherein the step of selectively forming the hardened portion is performed by laser processing. 選択的に硬化部を形成する工程は、加熱手段を絶縁基材または層間接続用絶縁基材に加熱加圧して行うことを特徴とする請求項1または請求項2に記載の回路基板の製造方法。 The method for manufacturing a circuit board according to claim 1 or 2, wherein the step of selectively forming the hardened portion is performed by heating and pressurizing the heating means to the insulating base material or the insulating base material for interlayer connection. . 前記内層用回路基板と前記層間接続用絶縁基材と最外層に金属箔を積層する工程は、前記層間接続用絶縁基材に形成された硬化部に張力を加えながら行うことを特徴とする請求項2に記載の回路基板の製造方法。 The step of laminating a metal foil on the inner layer circuit board, the interlayer connection insulating base material, and the outermost layer is performed while applying tension to the cured portion formed on the interlayer connection insulating base material. Item 3. A method for manufacturing a circuit board according to Item 2.
JP2011055128A 2011-03-14 2011-03-14 Manufacturing method of circuit board Withdrawn JP2012191101A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114126190A (en) * 2020-08-28 2022-03-01 欣兴电子股份有限公司 Circuit board structure and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114126190A (en) * 2020-08-28 2022-03-01 欣兴电子股份有限公司 Circuit board structure and manufacturing method thereof

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