JP2012179083A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine allowing selection of power amplifiers with serious consideration of the aspect of a sound quality by expanding the selections of the power amplifier.SOLUTION: The game machine includes: a sound synthesizer LSI82; digital analog conversion means 84a and 84b; and power amplifiers 85a and 85b. The sound synthesizer LSI82 synthesizes a digital signal on the basis of sound data for controlling the sound output mode of sound output means 17a to 17c, and outputs the synthesized digital signal by serial communication. The digital analog conversion means 84a and 84b convert to analog the digital signals output from the sound synthesizer LSI82 to generate analog signals and output the generated analog signals as sound signals. The power amplifiers 85a and 85b amplify the sound signals output from the digital analog conversion means 84a and 84b and output the results to the sound output means 17a to 17c.

Description

  The present invention relates to a gaming machine in which sound production by sound output means is executed.

  In general, a gaming machine performs sound effects that generate various sounds in order to increase the player's feelings. Here, a circuit including a voice synthesis LSI and a power amplifier has been proposed in order to execute a voice effect (see, for example, Patent Document 1). The voice synthesis LSI synthesizes a voice signal based on voice data for voice production, and outputs the synthesized voice signal. The power amplifier amplifies the audio signal output from the audio synthesis LSI and outputs the amplified audio signal to a speaker as audio output means. If it does in this way, it will become possible to perform the sound production which generates a sound from a speaker.

Japanese Patent Laying-Open No. 2005-287770 (FIGS. 1, 4, etc.)

  By the way, in the conventional gaming machine, the voice synthesis LSI outputs a digital voice signal by serial communication. Since this digital audio signal is a signal that cannot be heard as it is, it can be converted into an analog audio signal that can be heard as a sound using a power amplifier, and the converted audio signal can be driven to a speaker. Need to be amplified. However, an audio signal cannot be converted or amplified unless a digital amplifier capable of inputting signals by serial communication is used as a power amplifier. However, since there are very few types of commercially available digital amplifiers, there is a problem that the options for power amplifiers are narrow. Moreover, the commercially available digital amplifier has a problem that the sound quality is not so good.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine that enables selection of a power amplifier with an emphasis on sound quality by expanding the choices of the power amplifier.

  In order to solve the above problems, the invention according to claim 1 (means 1) is characterized in that the main control means for controlling the entire gaming machine and the sound output by the sound output means based on the control command from the main control means. A gaming machine including voice control means for performing control to produce an effect, synthesizing a digital signal based on voice data for controlling a voice output mode of the voice output means, and serializing the synthesized digital signal; A voice synthesis LSI that is output by communication; an analog signal is generated by analog conversion of the digital signal output from the voice synthesis LSI; and the analog-to-analog conversion unit that outputs the generated analog signal as a voice signal; Power for amplifying the audio signal output from the digital / analog converting means and outputting the amplified signal to the audio output means The game machine characterized by comprising a pump as its gist.

  Therefore, according to the first aspect of the present invention, the digital-analog conversion means converts the digital signal output from the speech synthesis LSI by serial communication into an analog signal and outputs the analog signal. Even in this case, the audio signal (analog signal) can be amplified by the power amplifier. As a result, the choices of the power amplifier are expanded, so that it is possible to select a power amplifier that emphasizes sound quality.

  The invention according to claim 2 (means 2) is that, in claim 1, the digital-analog conversion means generates the voice signal by analog-converting the digital signal output from the voice synthesis LSI. The gist of the present invention is a preamplifier for amplifying the generated audio signal, wherein an amplification factor of the audio signal amplified by the preamplifier is smaller than an amplification factor of the audio signal amplified by the power amplifier.

  Therefore, according to the second aspect of the present invention, since the digital-analog conversion means is a preamplifier, the digital-analog conversion means has a function different from the function of converting a digital signal into an analog (original function of the preamplifier). Can do. The preamplifier has a function of generating an audio signal by analog-converting a digital signal output from the audio synthesis LSI, and then amplifying the generated audio signal and sending it to a power amplifier. In addition, the preamplifier, for example, functions as a high-frequency filter that corrects frequency characteristics by removing high-frequency signals contained in digital signals, functions that increase or decrease the high and low frequencies of audio, and stereo output A function of adjusting the magnitude of the audio signal output to the left and right audio output means when performing the above. Therefore, if the preamplifier is used as the digital / analog conversion means, the sound quality of the sound output means can be improved.

  Note that the amplification factor of the audio signal amplified by the preamplifier need only be smaller than the amplification factor of the audio signal amplified by the power amplifier, and is generally set to about 2 to 6 times. However, the amplification factor of the audio signal amplified by the preamplifier may be, for example, “1 time (that is, a state where the audio signal is not amplified)”.

  The invention according to claim 3 (means 3) is the substrate according to claim 1 or 2, wherein the voice control means and the overall control means for controlling the plurality of sub-control means including the voice control means are the same. The gist of the invention is that the speech synthesis LSI, the digital-analog conversion means, and the power amplifier are mounted on the substrate.

  Therefore, according to the third aspect of the present invention, since the speech synthesis LSI and the digital / analog conversion means are mounted on the same substrate, they can be brought close to each other. Therefore, even serial communication in which a digital signal cannot be transmitted so far because it is vulnerable to noise can be reliably transmitted from the speech synthesis LSI to the digital-analog conversion means.

  The invention according to claim 4 (means 4) is the branch path branched from the electric path on the electric path connecting the digital-analog converting means and the power amplifier in any one of claims 1 to 3. The gist of the present invention is that an output terminal connected to is provided.

  Therefore, according to the fourth aspect of the present invention, the audio signal converted into the analog signal can be connected to a general audio device via the output terminal and the branch path. For this reason, sound can be output from the audio device.

  As described above in detail, according to the first to fourth aspects of the present invention, it is possible to provide a gaming machine that enables selection of a power amplifier with an emphasis on sound quality by expanding options for the power amplifier. . In particular, according to the third aspect of the present invention, a digital signal can be reliably transmitted from the speech synthesis LSI to the digital-analog conversion means.

The schematic front view which shows the pachinko machine in this invention. The schematic back view which shows the pachinko machine in this invention. The block diagram for demonstrating the connection relation of a main control board and another board | substrate. The block diagram for demonstrating electrical structures, such as a power supply board in this embodiment, a sub control board, and a display control board.

  Hereinafter, an embodiment in which a gaming machine of the present invention is embodied in a pachinko machine 10 will be described with reference to the drawings.

(1) Schematic configuration on the machine surface side of the pachinko machine 10 FIG. 1 schematically shows the machine surface side of the pachinko machine 10. The pachinko machine 10 includes a vertical rectangular outer frame 11 that forms an outline of the machine body. On the front side of the opening of the outer frame 11, a vertical rectangular middle frame 12 constituting the airframe is assembled so as to be openable and detachable. Further, a front frame 14 is assembled on the front side of the middle frame 12 so as to be opened and closed in a laterally open state. The front frame 14 has a structure in which an upper ball tray 15 is integrally assembled below the window 14a while having a window 14a at the center. A glass frame (not shown) for seeing through and protecting the game board 13 disposed inside the machine is assembled on the back side of the front frame 14. Further, an upper frame lamp 16a, a left frame lamp 16b, and a right frame lamp 16c are provided on the front surface of the front frame 14. Each of the frame lamps 16a to 16c includes a light emitter (not shown) (not shown), and is configured by covering the light emitter with a lens member. In these frame lamps 16a to 16c, light emission effects such as lighting (flashing) and light extinction are executed according to various game performance modes (big hit, reach, etc.) of the pachinko machine 10.

  Further, as shown in FIG. 1, a left speaker 17 a is disposed at the upper left portion of the front frame 14, and a right speaker 17 b is disposed at the upper right portion of the front frame 14. The left speaker 17a and the right speaker 17b are for executing sound effects for outputting various sounds. That is, the left speaker 17a and the right speaker 17b have a function as “audio output means”. The left speaker 17a and the right speaker 17b are mounted on the back side of the front frame 14, and a plurality of sound emitting holes are formed at locations corresponding to the left speaker 17a and the right speaker 17b on the front side of the front frame 14.

  Further, a lower ball tray 18 is assembled to be openable and closable below the front frame 14 on the front side of the middle frame 12. On the right side of the lower ball tray 18 is mounted an operation handle 19 that is turned by the player when the game ball is launched. Further, on the left side of the lower ball tray 18, an ashtray 20, a woofer speaker 17c for executing sound effects for outputting various sounds, and the like are disposed. That is, the woofer speaker 17c has a function as “audio output means”. The woofer speaker 17c is attached to the middle frame 12.

  As shown in FIG. 1, a frame-shaped center accessory 60 having a symbol display device 61 is mounted at a substantially central portion of the game board surface 13 a of the game board 13. In addition, although the symbol display device 61 of this embodiment is a liquid crystal type, a dot matrix type, an electroluminescence element type, and a 7 segment type symbol display device may be used. In the symbol display device 61, a game effect (display effect) based on a varying image (or image display) is executed. Then, the symbol display device 61 displays a symbol combination game in which a plurality of types of effect symbols are varied in three columns and a symbol combination is derived in relation to the display effect.

  A start winning device 21 in which a start winning port 21a is formed is disposed below the center combination 60 on the game board surface 13a. The start winning device 21 is integrally configured with an ordinary electric accessory comprising a pair of blade members 21b. The pair of blade members 21b are configured to open and close by the excitation action of the ordinary electric accessory solenoid SOL1 (see FIG. 3). In addition, a start opening switch SE1 (see FIG. 3) for detecting a game ball that has entered the start winning opening 21a is provided behind the start winning apparatus 21. The start port switch SE1 is turned on when a game ball won in the start winning device 21 is detected, and outputs a winning signal. On the other hand, the start port switch SE1 is turned off when no game ball is detected, and no winning signal is output. When a winning signal is output, a symbol variation game is performed by the special symbol display device 51 described later, and a symbol combination game is performed by the symbol display device 61 in relation to the symbol variation game, and a prize ball Is paid out.

  As shown in FIG. 1, a big winning device 23 is arranged below the start winning device 21. A count switch SE2 (see FIG. 3) for detecting a winning game ball is provided in the back of the big winning device 23. Further, the big prize opening door 23a of the big prize winning device 23 can be switched between a closed state in which the game ball is not received and an open state in which the game ball is easily received by the exciting action of the big prize port solenoid SOL2 (see FIG. 3). It has become. In the present embodiment, the “closed state” of the grand prize opening door 23a means a state in which the big prize opening door 23a is completely closed, and the “open state” of the big prize opening door 23a means the grand prize opening door. 23a is in a fully open state. When a game ball is detected by the count switch SE2, a prize ball is paid out.

  Further, a gate 25 having a function of detecting the passage of the game ball is provided on the left side of the center accessory 60. Behind the gate 25 is provided a gate switch SE3 (see FIG. 3) for detecting the passed game ball. Note that, when a game ball is detected by the gate switch SE3, a random number is acquired, and the ordinary electric accessory solenoid SOL1 is driven based on a result of determining whether or not the acquired random number is a predetermined random value. . Since the pair of blade members 21b are opened by such determination (hit determination), it becomes easy for the game ball to win the start winning opening 21a.

  As shown in FIG. 1, a special symbol display device 51 having a visible display unit is disposed on the lower left side of the center accessory 60. The special symbol display device 51 displays a symbol variation game that fluctuates a plurality of types of special symbols in response to the winning of a game ball to the start winning device 21. As a result of the symbol variation game, display results of jackpot and lose Is displayed. For example, when the result of the symbol variation game is a big hit, at the end of the symbol variation game, symbols indicating eight numbers “1” to “8” are displayed as special symbols. Further, when the result of the symbol variation game is lost, at the end of the symbol variation game, a symbol “-” indicating a loss is displayed as a special symbol.

  Furthermore, in this embodiment, the symbol combination game by the symbol display device 61 is performed in accordance with the symbol variation game on the special symbol display device 51. Specifically, the symbol combination game is started almost simultaneously with the start of the symbol variation game, and the result of the symbol combination game is displayed almost simultaneously with the end of the symbol variation game (the display result of jackpot or lose) is displayed. ing. In the present embodiment, the symbol combination game performed on the symbol display device 61 and the symbol variation game performed on the special symbol display device 51 are referred to as “variable game”.

  As shown in FIG. 1, a special symbol hold display device 52 is disposed below the special symbol display device 51. The special symbol hold display device 52 is composed of a plurality of (four) light-emitting units including a first special hold lamp, a second special hold lamp, a third special hold lamp, and a fourth special hold lamp. The special holding lamp is turned on when there is a game ball (special symbol holding ball) stored in response to winning at the start winning device 21, and is turned off when there is no special symbol holding ball. Each special holding lamp is for indicating the number of special symbol holding balls (the number of special symbol holding balls). For example, when there are three special symbol holding balls, three special holding lamps are lit.

  Here, the “number of special symbol reserved balls” is stored in the range of a predetermined maximum value (4 in the present embodiment) the number of game balls won in the start winning device 21 during the change of the special symbol (direction symbol). It is the value. The number of special symbol reserved balls is “+1” by winning a game ball to the start winning device 21 and “−1” by starting a variable game.

  As shown in FIG. 1, a normal symbol display device 53 having a visible display unit is disposed on the lower right side of the center accessory 60. In the normal symbol display device 53, a normal symbol variation game for changing the normal symbol is executed in response to the passing of the game ball to the gate 25 (see FIG. 1). As a result of the normal symbol variation game, random number lottery is performed. A normal symbol indicating the result is stopped and displayed. Note that there are two types of normal symbols in the present embodiment: a winning symbol “◯” or a lost symbol “X”. When the winning symbol is derived (when the normal symbol variation game is won), the normal electric accessory solenoid SOL1 is driven for a predetermined time, and the pair of blade members 21b are opened.

  A normal symbol holding display device 54 is disposed below the normal symbol display device 53. The normal symbol hold display device 54 is composed of a plurality of (four) light-emitting units including a first normal hold lamp, a second normal hold lamp, a third normal hold lamp, and a fourth normal hold lamp. The normal holding lamp is turned on when there is a game ball (ordinary symbol holding ball) stored with the passage of the gate 25 as an opportunity, and is turned off when there is no normal symbol holding ball. Each normal holding lamp is for indicating the number of normal symbol holding balls (the number of normal symbol holding balls). For example, when there are two normal symbol holding balls, two normal holding lamps are lit.

  Here, the “ordinary symbol reserved ball number” is a value stored in a range of a predetermined maximum value (4 in the present embodiment), the number of game balls that have passed through the gate 25. The normal symbol holding ball number is “+1” when the game ball passes to the gate 25 and is “−1” when the normal symbol variation game is started.

(2) Schematic configuration of the back side of the pachinko machine 10 FIG. 2 schematically shows the back side of the pachinko machine 10. On the back side of the middle frame 12, a mechanism set board 3 for assembling back parts is disposed. A ball tank 4 for storing game balls is provided on the entire upper portion of the mechanism set board 3 on the back side. Below the ball tank 4, a tank rail 5 is provided for allowing the game balls flowing out therefrom to flow down in an aligned state. A ball supply path 6 is connected to the lower end (right end) of the tank rail 5 that extends obliquely in the lower right direction, and a ball payout device 7 is connected to the lower end of the ball supply path 6. In addition, a frame external terminal plate 8 for connecting a hall computer (not shown) and the pachinko machine 10 is disposed in the vicinity of the connecting portion between the tank rail 5 and the ball supply path 6. The frame external terminal board 8 is configured to transmit prize ball information, ball rental information, and ball break information to the hall computer.

  As shown in FIGS. 2 to 4, the pachinko machine 10 according to the present embodiment has various substrates (main control board 31, sub integrated control board 32, display control board 33, A payout control board 35, a launch control board 36, a power supply board 37, and the like. The payout control board 35 is electrically connected to the main control board 31 and controls the payout of game balls by the ball payout device 7 based on a payout instruction from the main control board 31. Further, the launch control board 36 is electrically connected to the payout control board 35, and detects the operation state of the operation handle 19 constituting the hitting ball launching device, and controls the launch intensity of the game ball based on it. Plays. Further, the power supply board 37 plays a role of generating a plurality of power supply voltages (34V or 5V DC voltage in the present embodiment) necessary for the operation of each of the boards 31 to 33, 35, and 36. The power supply board 37 is electrically connected to the sub integrated control board 32 and the display control board 33, and supplies the generated power supply voltage to the sub integrated control board 32 and the display control board 33.

  As shown in FIG. 2, the main control board 31, the sub integrated control board 32, the display control board 33, the payout control board 35, and the power supply board 37 are accommodated in a dedicated board case 30. These substrate cases 30 are openable and closable flat boxes made of a transparent or translucent synthetic resin material, and are sealed with screws with the substrates 31 to 33, 35, and 37 arranged in parallel on the bottom thereof. Yes. A large number of through holes (not shown) for releasing heat generated from the substrates 31 to 33, 35, and 37 are formed in the substrate case 30.

  Further, on the left side portion (exposed portion not covered by the substrate case 30) on the sub integrated control board 32, a volume control knob 71 for steplessly changing the volume of the sound output from the speakers 17a to 17c. Is provided. When the volume control knob 71 is turned by a store clerk, the resistance value of the variable resistor 72 (see FIG. 4) provided in the electric path connected to the sub-CPU 32a changes, and the electric path The voltage of the current flowing through changes. For example, when the volume control knob 71 is rotated in the clockwise direction, the resistance value of the variable resistor 72 is reduced and the voltage of the current flowing through the electrical path is increased. In this case, the sub general CPU 32a performs control to increase the volume of the sound output from the speakers 17a to 17c. On the other hand, when the volume control knob 71 is rotated in the counterclockwise direction, the resistance value of the variable resistor 72 is increased and the voltage of the current flowing through the electric path is decreased. In this case, the sub general CPU 32a performs control to reduce the volume of the sound output from the speakers 17a to 17c.

  A power switch (not shown) is provided on the power board 37. When this power switch is operated to the on position by a store clerk at the amusement store, power supply to the pachinko machine 10 is started. When the power switch is operated to the off position, the power supply to the pachinko machine 10 is cut off.

  Further, as shown in FIG. 2, a RAM clear switch 38 is provided at a lower end portion (exposed portion not covered by the substrate case 30) on the power supply substrate 37. The RAM clear switch 38 outputs a RAM clear signal to the main control board 31. The main RAM of the main control board 31 normally has a backup function for storing the gaming state at the time of a power failure and the number of unpaid prize balls remaining. Therefore, when the RAM clear switch 38 is operated when the power switch is operated to the ON position (when power supply to the pachinko machine 10 is started), a RAM clear signal is output and the gaming state stored in the main RAM In addition, all data on the remaining number of unpaid prize balls is erased.

  Further, as shown in FIG. 3, the sub control board 32 is electrically connected to the main control board 31, and the display control board 33 is electrically connected to the sub control board 32.

(2-1) Electrical Configuration of Main Control Board 31 The main control board 31 includes a main CPU 31a that is a “main control means” that controls the entire pachinko machine 10. A start port switch SE1, a count switch SE2, and a gate switch SE3 are connected to the main CPU 31a. Further, a special symbol display device 51, a special symbol hold display device 52, a normal symbol display device 53, and a normal symbol hold display device 54 are connected to the main CPU 31a. Further, the main CPU 31a is connected to a normal electric accessory solenoid SOL1 and a special prize opening solenoid SOL2.

  Further, a main ROM (not shown) and a main RAM (not shown) are electrically connected to the main CPU 31a shown in FIG. The main CPU 31a updates the values of various random numbers such as a jackpot determination random number, a jackpot design random number, a reach determination random number, a variation pattern distribution random number, and the like used for various lotteries relating to the variation game at predetermined intervals. Then, the main CPU 31a rewrites the value before update by setting the updated value in the random number storage area of the main RAM. In the timer storage area of the main RAM, various timers that are appropriately rewritten during the operation of the pachinko machine 10 are stored (set).

  The big hit determination random number is a random number used when determining whether or not the variable game is a big hit (when determining the big hit). The jackpot symbol random number is a random number used when determining a special symbol when the result of the variable game is a jackpot. The reach determination random number is a random number used when determining whether or not to execute the reach effect when the result of the floating game is lost (during reach determination). The variation pattern distribution random number is a random number used when determining the variation pattern for specifying the contents of the effect of the game effect in the variation game.

  The main ROM stores a variation pattern distribution table in which variation patterns for symbol combination games are distributed. Each variation pattern is displayed until the symbols in all the columns stop (the symbol combination game ends) after the symbols (effect symbols) displayed on the symbol display device 61 start varying (the symbol combination game starts). This is for specifying the time and contents of the game effects (display effects, light-emitting effects, and sound effects). Each variation pattern is assigned a variation pattern distribution random number value. In addition, the variation pattern distribution table is allocated with a variation pattern for a big hit effect, a variation pattern for a loss reach effect, and a variation pattern for a loss effect. The variation pattern for the jackpot effect shows the pattern that becomes the base of the jackpot effect that displays the symbol combination (the jackpot symbol combination) in which the middle symbol stops at the same symbol as the left symbol and the right symbol after reaching the reach effect. Yes. The variation pattern for the lost reach production is the pattern that becomes the base of the lost reach production that displays the symbol combination (the combination of the lost symbols) that the middle symbol stops at a different symbol from the left symbol and the right symbol after reaching the reach effect. Show. The variation pattern for losing effect indicates a pattern serving as a base of losing effect for deriving a symbol combination of losing symbols (a symbol combination from which a symbol combination that is a big hit or reach is not derived). Note that the effect time (variation time) of the big hit effect, the lose reach effect, and the lose effect differs for each variation pattern.

  Next, various processes related to the symbol variation game executed by the main CPU 31a shown in FIG. 3 (such as jackpot determination, reach determination, jackpot symbol, lost symbol, variation pattern determination, etc.) will be described.

  The main CPU 31a acquires, from the main RAM, the value of the big hit determination random number and the value of the big hit symbol random number that are updated every predetermined period when the start winning condition is satisfied (the detection of the game ball by the start winning device 21). These values are stored (stored) in a random number storage area of the main RAM. The main CPU 31a determines whether or not the result of the symbol variation game is a big hit. Specifically, the main CPU 31a compares the jackpot determination random number stored in the random number storage area of the main RAM with the jackpot determination value stored in the main ROM immediately before the start of the symbol variation game, A big hit determination (big hit lottery) is performed to determine whether or not the symbol variation game is successful. In the present embodiment, the numbers that can be taken by the jackpot determination random numbers are 0 to 946 (total of 947 different integers). Then, the main CPU 31a uses the three jackpot determination values determined in advance from the values that can be taken by the jackpot determination random number, and determines the jackpot lottery probability as 3/947 (= 315.7) as a jackpot determination. I do.

  When the determination result of the big hit determination is negative (the value of the big hit determination random number and the big hit determination value do not match), the main CPU 31a shown in FIG. 3 determines the symbol “-” which is a lost symbol as a special symbol. Further, the main CPU 31a stores data corresponding to the determined special symbol in the main RAM until processing for the next symbol variation game is performed.

  Then, the main CPU 31a compares the reach determination random number value read from the main RAM with the reach determination value stored in the main ROM, and determines whether or not to execute the lose reach. In the present embodiment, the numerical values that can be taken by the random numbers for reach determination are 0 to 180 (a total of 181 types of integers). The reach determination value is a value determined in advance from numerical values that can be taken by the reach determination random number.

  If the determination result of reach determination is affirmative (the value of the reach determination random number and the reach determination value match), the main CPU 31a shown in FIG. 3 determines the loss reach. If the determination result of reach determination is negative (the reach determination random number value and the reach determination value do not match), the main CPU 31a determines a loss (a loss without a reach).

  On the other hand, if the determination result of the big hit determination is affirmative (the value of the big hit determination random number matches the big hit determination value), the main CPU 31a determines the big hit. When the jackpot determination is made, the main CPU 31a sets a symbol indicating any one of “1” to “8” as a special symbol based on the value of the jackpot symbol random number stored in the random number storage area of the main RAM. Determine as. Then, the main CPU 31a stores data corresponding to the determined special symbol in the main RAM until a process related to the next symbol variation game is performed.

  Then, the main CPU 31a shown in FIG. 3 determines the variation pattern based on the determination results of the jackpot determination and reach determination. Specifically, when the big hit is determined in the big hit determination, the main CPU 31a reads the value of the fluctuation pattern distribution random number from the main RAM, and based on the value, the fluctuation pattern for the big hit effect from the fluctuation pattern distribution table. To decide. Further, when losing reach is determined in the reach determination, the main CPU 31a reads the variation pattern distribution random number value from the main RAM, and determines the variation pattern for losing reach production from the variation pattern distribution table based on the value. To do. Further, when the loss is determined in the reach determination, the main CPU 31a reads the variation pattern distribution random number value from the main RAM, and determines the variation pattern for the loss effect from the variation pattern distribution table based on the value.

  When the main CPU 31a shown in FIG. 3 determines the special symbol and the variation pattern, the main CPU 31a sets (stores) the variation time associated with each variation pattern as the variation timer in the timer storage area of the main RAM, and displays the special symbol display. The device 51 is caused to start changing special symbols.

  Further, when the main CPU 31a instructs the sub-central CPU 32a of the sub-general control board 32 to perform control, a control command or the like is used as a control signal (8-bit signal), and the signal is output to an output port (not shown) and output buffer ( (Not shown) at a predetermined timing. Specifically, the main CPU 31a first generates a variation pattern designation command for designating a variation pattern and instructing the start of symbol variation, and sets it as a control command (stored in the main RAM). The control command set here is output in the next command output process. Next, the main CPU 31a sets (stores in the main RAM) a special symbol designation command for designating a special symbol as a control command. The control command set here is output in the next command output process. Further, the main CPU 31a subtracts the variation timer set at the beginning of the variation every interrupt (4 ms). When the variation time associated with the variation pattern elapses (when the variation timer reaches 0 ms), the main CPU 31a sets (outputs) a symbol stop command that instructs the stop of the special symbol and the effect symbol as a control command. .

  The main CPU 31a shown in FIG. 3 reads a read signal (INT signal or strobe signal) for instructing the sub-central CPU 32a to read a control command constituting the control signal in accordance with the output timing of the control signal. Are output via an output port and an output buffer.

(2-2) Electrical Configuration of Sub-Overall Control Board 32 The sub-overall control board 32 shown in FIGS. 3 and 4 is a sub-control that is “voice control means”, “sub-control means”, and “overall control means”. A CPU 32a is provided. The sub general CPU 32a operates based on a power supply voltage (a DC voltage of 5 V in the present embodiment) supplied from the power supply board 37. An input buffer (not shown) for inputting a control signal and a read signal output from the main CPU 31a is electrically connected to the sub general CPU 32a. Further, an input port (not shown) is electrically connected to the input buffer, and a control signal and a read signal are input to the sub general CPU 32a via the input port.

  In addition, a sub general ROM 32b and a sub general RAM 32c are connected to the sub general CPU 32a. The sub general CPU 32a updates the values of various random numbers used for determining the game effect at predetermined intervals. Then, the sub general CPU 32a sets the updated value in the setting area of the sub general RAM 32c and rewrites the value before the update. For example, the random number storage area of the sub control RAM 32c stores a random number for lost left symbol, a random number for lost symbol, a random number for lost right symbol, and the like.

  Further, the sub-supervision ROM 32b shown in FIG. 3 stores a plurality of types of light effect data and a plurality of types of sound effect data used when the symbol combination game is performed. The light emission effect data is information for the sub-general CPU 32a to control the light emission output mode of the frame lamps 16a to 16c. The sound effect data is information for the sub-integrating CPU 32a to control the sound output mode (sound effect type, language sound type, sound output time, etc.) of the speakers 17a to 17c.

  By the way, when a variation pattern designation command is input from the main CPU 31a, the sub general CPU 32a shown in FIGS. 3 and 4 stores the variation pattern designated by the variation pattern designation command in the sub general RAM 32c. Yes. Further, when a special symbol designation command is input, the sub overall CPU 32a stores the special symbol designated by the special symbol designation command in the sub overall RAM 32c.

  Further, the sub general CPU 32a generates an effect symbol that is stopped and displayed on the symbol display device 61 at the end of the symbol combination game, based on the special symbol stored in the sub general RAM 32c. For example, when the special symbol stored in the sub general RAM 32c is any one of “1” to “8”, the variation pattern stored in the sub general RAM 32c is a variation pattern for the big hit effect. In this case, the sub general CPU 32a generates the effect symbols (effect symbol left, middle, and right) that are finally stopped by the symbol display device 61 so that all the columns have the same type of symbols. More specifically, the sub general CPU 32a generates the effect symbol left, the effect symbol in the effect symbol, and the effect symbol right (each effect symbol is the same type) based on the special symbol. The generated effect symbols (effect symbol left, middle, and right) are derived to the symbol display device 61 as a final symbol combination. Then, the sub general CPU 32a stores data corresponding to the generated effect symbol left, effect symbol, and effect symbol right in the sub effect RAM 32c.

  When the special symbol stored in the sub-general RAM 32c is “−” and the variation pattern stored in the sub-general RAM 32c is a variation pattern for the lost reach effect, the sub-general shown in FIGS. The CPU 32a determines the lose reach. In this case, the sub-control CPU 32a determines the left, middle and right effect symbols so that the left column and the right column are the same type of symbols, and the middle column is a different type of symbols from the left and right two columns. Specifically, the effect symbol left and the effect symbol right (both effect symbols are of the same type) are generated on the basis of the random number value for the lost symbol. Then, an effect symbol is generated based on the value of the random symbol for the lose symbol. If the value of the random symbol for losing and the value of random number for the left symbol (or the value of random number for the right of losing symbol) match, the sub-control CPU 32 a ) Are generated so that they do not match. Then, the sub general CPU 32a stores data corresponding to the generated effect symbol left, effect symbol, and effect symbol right in the sub effect RAM 32c. In the present embodiment, the numbers that can be taken by random numbers for the left symbol for lost, the random number for right for lost, and the random number for middle for lost are 10 integers from 0 to 9, and one numerical value corresponds to each type of symbol. It is attached.

  When the special symbol stored in the sub-general RAM 32c is “−” and the variation pattern stored in the sub-general RAM 32c is a variation pattern for a loss effect, the sub-general CPU 32a shown in FIGS. Decides to lose. In this case, the sub general CPU 32a generates the effect symbols left, middle, and right so that all the columns do not become the same type of symbols. Specifically, the production symbol left is generated based on the value of the random symbol for the loss left symbol, the production symbol is generated based on the value of the random number for the middle symbol of the loss, and the production is produced based on the value of the random number for the loss right symbol. Generate the symbol right. In the case where the value of the lost symbol random number and the value of the lost right symbol random match, the sub-control CPU 32a generates the effect symbol right so that the effect symbol left and the effect symbol right do not match. Then, the sub general CPU 32a stores data corresponding to the generated effect symbol left, effect symbol, and effect symbol right in the sub effect RAM 32c.

  Further, when the change pattern designation command is input, the sub general CPU 32a sets (generates) any one of a plurality of types of light effect data stored in the sub general ROM 32b, and sets the set light effect data. The data is stored in the storage area of the sub general RAM 32c. As a result, the sub general CPU 32a performs light emission control (light emission effect) based on the light emission effect data corresponding to the variation pattern designation command. More specifically, the sub general CPU 32 a converts the light emission effect data stored in the sub general RAM 32 c into a light emission control signal and outputs the light emission control signal to the lamp driving circuit 42. As a result, the lamp driving circuit 42 can cause the frame lamps 16a to 16c to perform a predetermined light emission operation (lighting, blinking, etc.) based on the light emission control signal.

  When a change pattern designation command is input, the sub-control CPU 32a shown in FIGS. 3 and 4 sets (generates) any one of a plurality of types of sound effect data stored in the sub-control ROM 32b. Thus, the set sound effect data is stored in the storage area of the sub-control RAM 32c. As a result, the sub general CPU 32a performs voice control (voice production) based on the voice production data corresponding to the variation pattern designation command. More specifically, the sub general CPU 32 a converts the sound effect data stored in the sub general RAM 32 c into a sound effect signal and outputs the sound effect signal to the sound generation circuit 81. As a result, the sound generation circuit 81 can cause the speakers 17a to 17c to perform a predetermined output operation (sound output) based on the sound effect signal.

  The sub control CPU 32a outputs a change pattern specifying command for specifying a change pattern stored in the sub control RAM 32c to the display control CPU 33a of the display control board 33 as a control command. Thereby, the specific contents of the game effect executed by the display control CPU 33a are controlled by the sub general CPU 32a based on the control command from the main CPU 31a. Further, the sub general CPU 32a outputs an effect symbol left designation command for designating the effect symbol left of the effect symbol to the display control CPU 33a as a control command. Similarly, the sub-general CPU 32a outputs, to the display control CPU 33a, control commands that specify an effect symbol right specifying command for specifying the effect symbol right of the effect symbol and an effect symbol specifying instruction for specifying the effect symbol of the effect symbol. . Thereafter, when a symbol stop command is input from the main CPU 31a, the sub-control CPU 32a instructs the lamp driving circuit 42 to stop the light emission of the frame lamps 16a to 16c, and the sound generation circuit 81 outputs sound from the speakers 17a to 17c. Stop is instructed. Then, the sub control CPU 32a outputs the input symbol stop command to the display control CPU 33a as a control command.

  3 and 4 uses the above control commands and the like as control signals (8-bit signals), and the signals are output via an output port (not shown) and an output buffer (not shown). Output at the timing. In addition, the sub general CPU 32a outputs a read signal (INT signal or strobe signal) for instructing the display control CPU 33a to read the control command constituting the control signal in accordance with the output timing of the control signal. The output is made via an output buffer.

  Further, the sub integrated control board 32 includes a power generation circuit 41, a lamp driving circuit 42, and a sound generation circuit 81. In other words, the power generation circuit 41, the lamp drive circuit 42, and the sound generation circuit 81 are installed on the same sub integrated control board 32 as the sub integrated CPU 32a. The power generation circuit 41 generates a 12V drive voltage necessary for the operation of the lamp drive circuit 42 based on the power supply voltage (34V DC voltage in the present embodiment) supplied from the power supply substrate 37, and generates a sound. A drive voltage of 15V required for the operation of the generation circuit 81 is generated. The lamp driving circuit 42 dynamically drives the frame lamps 16 a to 16 c based on the driving voltage supplied from the power generation circuit 41.

  The sound generation circuit 81 shown in FIGS. 3 and 4 is provided on an electrical path that connects the sub general CPU 32a and the speakers 17a to 17c. The sound generation circuit 81 drives the speakers 17 a to 17 c based on the drive voltage supplied from the power generation circuit 41. More specifically, the sound generation circuit 81 includes a speech synthesis LSI 82 mounted on the sub general control board 32. The voice synthesis LSI 82 has a function of controlling the contents of voice effects performed by the speakers 17a to 17c. In addition, a voice data ROM 83 is electrically connected to the voice synthesis LSI 82. The voice synthesis LSI 82 synthesizes a digital signal based on voice data for controlling the voice output mode of the voice output means (the left speaker 17a, the right speaker 17b, and the woofer speaker 17c), and the synthesized digital signal is serially communicated. Output. Note that the digital signal of this embodiment is a signal that cannot be heard as voice.

  Note that the sound data ROM 83 shown in FIG. 4 stores a plurality of sound data for executing sound effects by the speakers 17a to 17c. The audio data includes data for reproducing music for reproducing music having a predetermined melody and data for reproducing sound effects for reproducing sound effects. The music playback time is stored in the audio data ROM 83 in association with the music playback data. The sound effect is, for example, an imitation sound composed of a single sound, and specifically, a bell sound, a copper sword sound, a chime sound, or the like. Note that the sound effect playback time is shorter than the music playback time, and is set in the range of 0.2 to 0.5 seconds in the present embodiment.

  The sound generation circuit 81 includes preamplifiers 84a and 84b and power amplifiers 85a and 85b mounted on the sub general control board 32. The preamplifier 84a and the power amplifier 85a are provided on an electrical path that connects the speech synthesis LSI 82 and the speakers 17a and 17b. The preamplifier 84b and the power amplifier 85b are provided on an electrical path that connects the speech synthesis LSI 82 and the woofer speaker 17c.

  As shown in FIG. 4, the input terminals of the preamplifiers 84 a and 84 b are electrically connected to the output port of the speech synthesis LSI 82. The electrical path connecting the preamplifier 84a and the speech synthesis LSI 82 and the electrical path connecting the preamplifier 84b and the speech synthesis LSI 82 are each constituted by four wires. That is, in the present embodiment, the digital signal synthesized by the voice synthesis LSI 82 is output by 4-wire serial communication. The preamplifiers 84a and 84b generate analog signals by converting the digital signals output from the speech synthesis LSI 82 into analog signals. That is, the preamplifiers 84a and 84b have a function as “digital / analog converting means”. Further, the preamplifiers 84a and 84b amplify the generated analog signal after generating the analog signal, and output the amplified analog signal as an audio signal. Note that the amplification factor (about 2 to 4 times in the present embodiment) of the audio signal (analog signal) amplified by the preamplifiers 84a and 84b is the amplification factor (this embodiment) of the audio signal amplified by the power amplifiers 85a and 85b. Is smaller than about 6 to 80 times. The audio signals amplified by the preamplifiers 84a and 84b are signals that can be heard as audio, but are not amplified to such an extent that the speakers 17a to 17c can be driven.

  As shown in FIG. 4, the input terminal of the power amplifier 85a is electrically connected to the output terminal of the preamplifier 84a, and the input terminal of the power amplifier 85b is electrically connected to the output terminal of the preamplifier 84b. Then, the power amplifier 85a amplifies the audio signal output from the preamplifier 84a, outputs it to the left speaker 17a via the rectifier circuit 86a, and outputs it to the right speaker 17b via the rectifier circuit 86b. The power amplifier 85 b amplifies the audio signal output from the preamplifier 84 b and outputs the amplified audio signal to the woofer speaker 17 c via the rectifier circuit 87. Note that the power amplifiers 85a and 85b of the present embodiment are power amplifiers with specifications that do not support serial communication, and are 2-channel amplifiers that can drive two speakers.

  Also, the sub-central CPU 32a shown in FIGS. 3 and 4 performs control for causing the speakers 17a to 17c to execute sound effects. More specifically, the sub general CPU 32a gives an audio production designation signal for instructing the type of audio production (music, sound effect) and instructing the start of the audio production based on the winning signal output from the main CPU 31a. Generate. Then, the sub general CPU 32a outputs the generated voice effect designation signal to the voice synthesis LSI 82. The voice synthesis LSI 82 selects one voice data from a plurality of voice data stored in the voice data ROM 83 on the basis of the voice effect designation signal output from the sub general CPU 32a, and performs voice control using the selected voice data. Generate information. Next, the voice synthesis LSI 82 generates volume control information based on the voice effect designation signal output from the sub general CPU 32a. Furthermore, the speech synthesis LSI 82 generates signal transmission information that indicates to which speakers 17a to 17c the current signal is to be transmitted, based on the audio effect designation signal output from the sub-general CPU 32a. Then, the voice synthesis LSI 82 synthesizes a digital signal based on the generated voice control information, volume control information, and signal transmission information, and outputs this signal to the preamplifiers 84a and 84b and the power amplifiers 85a and 85b. At this time, information included in the digital signal is output in the order of audio control information → volume control information → signal transmission information. As a result, the speakers 17a to 17c are converted (analog converted) from digital signals by the preamplifiers 84a and 84b, and based on the audio signals amplified by the preamplifiers 84a and 84b and the power amplifiers 85a and 85b, Output).

(2-3) Electrical Configuration of Display Control Board 33 As shown in FIGS. 3 and 4, the display control board 33 includes a display control CPU 33 a that is a “sub-control means” and an inverter board 43. . The display control CPU 33a generates a drive voltage (12V DC voltage in this embodiment) necessary for the operation of the inverter board 43 based on the power supply voltage (34V DC voltage in this embodiment) supplied from the power supply board 37. It is supposed to be. The inverter board 43 supplies the drive voltage supplied from the display control CPU 33 a to the backlight of the symbol display device 61. Further, a display ROM (not shown) and a display RAM (not shown) are connected to the display control CPU 33a. The display RAM temporarily stores (sets) various information that can be appropriately rewritten during the operation of the pachinko machine 10.

  The display ROM stores a plurality of types of display effect data used when the symbol combination game is performed. The display effect data is information for the display control CPU 33a to control the display content (symbol fluctuation or the like) of the symbol display device 61, that is, information for instructing the symbol display device 61 to execute the display effect.

  When a variation pattern designation command is input from the sub-central CPU 32a shown in FIGS. 3 and 4, the display control CPU 33a stores the variation pattern designated by the variation pattern designation command in the display RAM. Yes.

  Further, when an effect symbol left designation command is input from the sub-general CPU 32a, the display control CPU 33a stores the effect symbol left designated by the command in the display RAM. Similarly, when an effect symbol right designation command is input from the sub-control CPU 32a, the display control CPU 33a stores the effect symbol right specified by the command in the display RAM, and when the effect symbol designation command is input, The effect design specified by the command is stored in the display RAM.

  After that, when a symbol stop command is input from the sub-central CPU 32a shown in FIGS. 3 and 4, the display control CPU 33a is based on the effect symbols left, right, and center that are input at the start of variation and stored in the display RAM. The symbol display device 61 is instructed to stop the effect symbol. Thereby, the designated effect symbol is stopped and displayed on the symbol display device 61.

  When a variation pattern designation command is input, the display control CPU 33a sets (generates) any one of a plurality of types of display effect data stored in the display ROM, and displays the set display effect data. The data is stored in a RAM storage area. Thereby, the display control CPU 33a performs display control based on the variation pattern designation command and the display effect data. More specifically, the display control CPU 33a converts display effect data stored in the display RAM into a symbol signal and outputs the symbol signal to the symbol display device 61. As a result, the symbol display device 61 can perform a predetermined display (such as a symbol combination game) based on the symbol signal.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the pachinko machine 10 of the present embodiment, the preamplifiers 84a and 84b convert the digital signal output from the voice synthesis LSI 82 by serial communication into a voice signal (analog signal) and output the voice signal. For this reason, even if the power amplifiers 85a and 85b are not compatible with serial communication, the audio signals can be amplified by the power amplifiers 85a and 85b. As a result, the choices of the power amplifiers 85a and 85b are widened, so that it is possible to select the power amplifiers 85a and 85b that emphasize sound quality.

  (2) Since the “analog-digital conversion means” of the present embodiment is the preamplifiers 84a, 84b, the analog-digital conversion means has a function (an original function of the preamplifiers 84a, 84b) different from the function of converting a digital signal into analog. To have. Specifically, the preamplifiers 84a and 84b have a function as a high-frequency filter that corrects frequency characteristics by removing high-frequency signals contained in digital signals. Therefore, since it is possible to prevent the high frequency components included in the digital signal from being output to the speakers 17a to 17c, the sound quality of the speakers 17a to 17c can be improved.

  (3) In this embodiment, since the amplification of the audio signal is shared by the preamplifiers 84a and 84b, the burden on the power amplifiers 85a and 85b is reduced, and excessive heat generation of the power amplifiers 85a and 85b can be prevented. it can. Therefore, since the malfunction of the power amplifiers 85a and 85b due to heat generation can be prevented, the reliability of the pachinko machine 10 is improved.

  (4) In the present embodiment, the speech synthesis LSI 82 and the sub integrated CPU 32a are different. For this reason, the voice synthesizing LSI 82 can be specialized in the function for voice production, it becomes easy to improve the quality of the voice production, and the variation of the voice production can be increased. In addition, since the processing related to the voice production can be shared by the voice synthesis LSI 82, the burden on the sub-integrated CPU 32a can be reduced. Furthermore, when changing the contents of the sound production (music, sound effects), it is only necessary to replace the sound data ROM 83.

  In addition, you may change the said embodiment as follows.

  In the above embodiment, on the electrical path connecting the preamplifier 84a and the power amplifier 85a (see point A in FIG. 4) or on the electrical path connecting the preamplifier 84b and the power amplifier 85b, a branch path branched from the electrical path An output terminal (not shown) connected to (not shown) may be provided. In this way, the audio signal converted into the analog signal by the preamplifier 84a (or the preamplifier 84b) can be connected to a general audio device via the output terminal and the branch path. For this reason, sound can be output from the audio device. That is, the audio signal can be used, for example, when shooting a new model of promotional video or when debugging.

  The output terminal may be provided on an electrical path that connects the power amplifiers 85a and 85b and the rectifier circuits 86a, 86b, and 87. However, in this case, since the audio signal extracted from the output terminal is a signal amplified by the preamplifiers 84a and 84b and the power amplifiers 85a and 85b, the volume is too high. Therefore, the output terminal is preferably provided on an electrical path connecting the preamplifiers 84a and 84b and the power amplifiers 85a and 85b.

  In the above embodiment, the amplification factor of the audio signal amplified by the preamplifiers 84a and 84b is set to about 2 to 4 times. However, the amplification factor of the audio signal amplified by the preamplifiers 84a and 84b may be changed as appropriate. For example, the amplification factor of the audio signal amplified by the preamplifiers 84a and 84b may be increased or decreased. Further, the amplification factor of the audio signal amplified by the preamplifiers 84a and 84b may be changed to “1 time (that is, a state where the audio signal is not amplified)”. Therefore, the “digital / analog conversion means” is not necessarily limited to the preamplifiers 84a and 84b, and does not amplify an audio signal such as a conventionally known D / A converter (Digital-to-Analog Converter). It may be a thing.

  In the above embodiment, the sound generation circuit 81 is provided with two power amplifiers 85a and 85b (2ch), and the three speakers 17a to 17c are driven by the power amplifiers 85a and 85b. However, the number of power amplifiers (and the number of channels) and the number of speakers may be changed as appropriate. For example, by omitting the power amplifier 85b (and the preamplifier 84b) and omitting the woofer speaker 17c, the number of power amplifiers and speakers may be changed to one each. In addition to driving the woofer speaker 17c, the power amplifier 85b may drive another speaker to change the number of speakers to four. Furthermore, the number of power amplifiers (and preamplifiers) may be changed to one by changing the power amplifier to a multi-channel type such as 4ch or 6ch. If the number of power amplifiers (and the number of channels) and the number of speakers are increased, the sound quality of the speakers can be easily pursued. On the other hand, if the number of power amplifiers (and the number of channels) and the number of speakers are reduced, the configuration of the sound generation circuit 81 and thus the structure of the pachinko machine 10 can be simplified.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) In the means 3, the voice synthesis LSI includes voice control information generated using the voice data, and volume control information generated based on a voice effect designation signal output from the overall control means. The digital signal is synthesized based on signal transmission information generated based on the audio effect designation signal and indicating the transmission destination of the current signal, and the information included in the digital signal includes the audio control information, A game machine characterized in that the volume control information and the signal transmission information are output in this order.

  (2) In the means 3, the board generates a sound that causes the sound output means to execute the sound effect based on a sound effect designation signal that indicates the type of the sound effect and instructs the start of the sound effect. The sound generation circuit comprises: audio data storage means for storing the audio data; audio synthesis LSI for synthesizing the digital signal based on the audio data stored in the audio data storage means; and the digital A gaming machine comprising analog conversion means and the power amplifier.

DESCRIPTION OF SYMBOLS 10 ... Pachinko machine 17a as a game machine ... Left speaker 17b as voice output means ... Right speaker 17c as voice output means ... Woofer speaker 31a as voice output means ... Main CPU as main control means
32 ... Sub-control board 32a as a board ... Sub-control CPU as voice control means, overall control means, and sub-control means
33a ... Display control CPU as sub-control means
82: Speech synthesis LSI
84a, 84b... Preamplifiers 85a, 85b as digital / analog converting means.

Claims (4)

Main control means for controlling the entire gaming machine;
A gaming machine comprising: voice control means for performing control to execute voice production by voice output means based on a control command from the main control means,
A voice synthesis LSI that synthesizes a digital signal based on voice data for controlling the voice output mode of the voice output means, and outputs the synthesized digital signal by serial communication;
A digital-analog conversion means for generating an analog signal by converting the digital signal output from the voice synthesis LSI into an analog signal, and outputting the generated analog signal as a voice signal;
A gaming machine comprising: a power amplifier that amplifies the audio signal output from the digital-analog conversion means and outputs the amplified audio signal to the audio output means. The digital-analog conversion means is a preamplifier that amplifies the generated audio signal after generating the audio signal by analog-converting the digital signal output from the speech synthesis LSI,
The gaming machine according to claim 1, wherein an amplification factor of the audio signal amplified by the preamplifier is smaller than an amplification factor of the audio signal amplified by the power amplifier. The voice control means and the overall control means for controlling the plurality of sub-control means including the voice control means are installed on the same substrate,
The gaming machine according to claim 1, wherein the voice synthesis LSI, the digital-analog conversion unit, and the power amplifier are mounted on the substrate.   The output terminal connected to the branch path branched from the said electrical path is provided on the electrical path which connects the said digital analog conversion means and the said power amplifier. The gaming machine according to the item.

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