JP2012160701A - Semiconductor-mounting member and method of manufacturing semiconductor-mounting member - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor-mounting member in which the yield does not deteriorate while providing support for multi-wiring and enhancement of power supply.SOLUTION: A semiconductor-mounting member 100 is composed of two printed wiring boards of a second substrate 110 and a first substrate 10. For this reason, the yield does not deteriorate compared to the case where the number of layers in one built-up substrate is increased and the size of the one built-up substrate is enlarged for the purpose of support for multi-wiring and enhancement of power supply. The combination of the built-up substrate with long manufacturing time and a stacked substrate with short manufacturing time can shorten the total manufacturing time.

Description

The present invention relates to a semiconductor mounting member for mounting a semiconductor by mounting a second printed wiring board on a first printed wiring board.

As a mounting board for a CPU of a computer, a build-up board formed by laminating an interlayer insulating layer and a conductor circuit on a core board as described in Patent Document 1 is used.

JP 2001-223315 A

A printed wiring board having a large number of layers and a large size is used as a mounting board for a CPU of a server computer having a higher performance than a personal computer, from the viewpoint of adapting to multilayer wiring and enhancing power supply. When the number of layers is large and the size is large as compared with a printed wiring board for mounting a CPU in a personal computer, there arises a problem that the yield decreases.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor mounting member that does not decrease the yield while supporting the multilayer wiring and strengthening the power supply, and a method for manufacturing the same. There is.

According to the first aspect of the present invention, a plurality of first insulating layers having through holes, a first conductor formed on the first insulating layer, and the first conductors provided in the through holes A first substrate having via conductors, a core substrate having through holes, second conductors formed on both surfaces of the core substrate, and the second conductors formed inside the through holes. A second substrate having a through-hole conductor connecting the first and second core layers, and a build-up layer formed on the core substrate and the second conductor, the second insulating layer and the third conductor being alternately stacked, and A first bump provided on the outermost layer of the first conductor and connecting the first substrate and the second substrate; and a third bump located on the outermost layer of the third conductor. A semiconductor mounting comprising a second bump provided on the conductor and connecting the semiconductor element. A timber, the thickness of the second substrate, and technical features is thicker than the first substrate.

According to a first aspect of the present invention, the semiconductor mounting member includes a first substrate and a second substrate provided on the first substrate via bumps. That is, in the semiconductor mounting member according to claim 1, a conventional wiring board having a multilayer wiring and a large size is divided into at least two members, the number of layers of each member is reduced, and the members are connected by bumps. ing. As a result, the yield can be improved as compared with a conventional wiring board having a multilayer wiring and a large size.
The thickness of the second substrate is thicker than that of the first substrate. In this case, the stress generated when the semiconductor element is mounted on the second substrate is relaxed inside the relatively thick second substrate until the stress propagates to the bumps interposed between the first substrate and the second substrate. Presumed to be. As a result, connection reliability between the first substrate and the second substrate is easily ensured.

It is sectional drawing of the semiconductor device based on embodiment of this invention. It is sectional drawing of the 1st board | substrate which concerns on embodiment. It is a top view of the 1st substrate concerning an embodiment. It is a manufacturing process figure of the 1st substrate concerning an embodiment. It is a manufacturing process figure of the 1st substrate concerning an embodiment. It is a manufacturing process figure of the 1st substrate concerning an embodiment. It is a manufacturing-process figure of the 1st board | substrate which concerns on 1st Embodiment. It is sectional drawing of the 2nd board | substrate which concerns on embodiment. It is a top view of the 2nd substrate concerning an embodiment. It is a manufacturing process figure of the 2nd substrate concerning an embodiment. It is a manufacturing process figure of the 2nd substrate concerning an embodiment. It is a manufacturing process figure of the 2nd substrate concerning an embodiment. It is a manufacturing process figure of the 2nd substrate concerning an embodiment. It is a manufacturing process figure of the semiconductor mounting member concerning an embodiment. It is sectional drawing of the semiconductor mounting member which concerns on embodiment.

The semiconductor mounting member according to the present embodiment will be described with reference to FIGS.
First, FIG. 1 shows a state (semiconductor device) in which a semiconductor element 200 is mounted on a semiconductor mounting member 100. FIG. 15 shows the semiconductor mounting member 100 in a state before the semiconductor element 200 is mounted.
The semiconductor mounting member 100 includes a first substrate 110 and a second substrate 10 provided on the first substrate 110 via bumps 186.
A resin filler 188 is filled between the first substrate 110 and the second substrate 1. The semiconductor element 200 is mounted on the second substrate 10 via the solder bumps 86. A resin filler 288 is filled between the second substrate 10 and the semiconductor element 200.

The first substrate 110 is configured to have a thickness t1 (about 0.8 mm). The second substrate 10 has a thickness t2 (about 1.0 mm). In the present embodiment, the first substrate 110 and the second substrate 10 are configured so that 1 <t2 / t1 <2.
When the thickness t1 of the first substrate 110 and the thickness t2 of the second substrate 10 satisfy the above relationship, the stress generated in the bump 186 when mounting the semiconductor element 200 while suppressing an increase in the thickness of the entire mounting member 10 It is speculated that it will be possible to effectively mitigate.

[First board]
FIG. 2 shows a cross-sectional view of the first substrate 110.
The first substrate 110 includes a first insulating layer 130 having a first surface F and a second surface S substantially at the center in the thickness direction. On the first surface F of the insulating layer 130, a first insulating layer 140A having a first conductor 147 is formed. A first insulating layer 150A having a first conductor 157 and a first insulating layer 160A having a first conductor 167 are sequentially formed on the first insulating layer 140A. On the other hand, a first insulating layer 140B having a first conductor 148 is formed on the second surface S of the insulating layer 130. A first insulating layer 150B having a first conductor 158 and a first insulating layer 160B having a first conductor 168 are sequentially formed on the first insulating layer 140B.
A through hole is provided in each first insulating layer. Via conductors 136, 146A, 146B, 156A, 156B, 166A, 166B made of plating are formed inside each through hole. By the via conductors 136, 146A, 146B, 156A, 156B, 166A, 166B, the first conductors located in different layers are electrically connected to each other.

A solder resist layer 180 provided with an opening 181 is formed on the outermost insulating layers 160A and 160B. Solder bumps 186 for connecting the above-described second substrate 10 are formed in the openings 181 of the solder resist layer 180 on the insulating layer 160A. A pad including the first conductor 168 exposed through the opening is provided in the opening 181 of the solder resist layer 180 on the insulating layer 160B.
The via conductors 136, 146A, 146B, 156A, 156B, 166A, and 166B are stacked in a column shape. The “columnar” means a state in which a pair of via conductors adjacent in the thickness direction are in contact with each other. Thereby, the distance of the conductor in the thickness direction is shortened, and the wiring resistance is reduced. As a result, power supply voltage and signal loss are suppressed.

FIG. 3 is a plan view of the first substrate 110. As shown in the figure, the solder bumps 186 provided on the first substrate 110 have a peripheral arrangement. Of the four sides constituting the arrangement region of the bumps 186, the arrangement region X on one arbitrary side is wider than the arrangement region Y on the other three sides.
In addition, in the arrangement region of the bumps 186, the bumps forming at least one corner C are arranged in a diagonal line. The corners C where the bumps are arranged in a diagonal line can serve as a mark when the first and second substrates 10 and 110 are aligned with each other.

Next, a method for manufacturing the second substrate 110 described above with reference to FIG. 2 will be described with reference to FIGS.
(1) A copper-clad laminate 130A in which a copper foil 132 of about 10 μm is laminated on both sides of an insulating layer 130 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of about 60 μm is used as a starting material (FIG. 4 (A)).

(2) After forming the via opening 133 reaching the copper foil 132 on the back side by laser (FIG. 4B), the entire surface is subjected to electroless plating to provide the electroless plating film 131 (FIG. 4 ( C)).

(3) Electrolytic plating is performed to provide an electrolytic plating film 135 on the electroless plating film 131 and in the via opening 133 (FIG. 5A).

(4) An etching resist 137 is formed in a portion where the first conductor is to be formed (FIG. 5B).

(5) After the electrolytic plating film 135, the electroless plating film 131, and the copper foil 132 in the portion where the resist 137 is not formed are dissolved by etching, the resist 137 is removed, and the via conductor 136 and the first conductors 137, 138 are formed. (FIG. 5C). Thereafter, the first conductor is roughened (not shown).

(6) A prepreg having a copper foil 142A only on one side is laminated, and an insulating layer 140A is formed on the first surface F of the insulating layer 130. Similarly, a prepreg having a copper foil 142B only on one surface is laminated on the second surface S, and an insulating layer 140B is formed on the second surface S of the insulating layer 130 (FIG. 5D).

(7) Via holes 143A for via conductors are formed in the insulating layer 140A and via holes 143B for via conductors are formed in the insulating layer 140B by a laser (FIG. 6A). An electrolytic plating film 141 is provided (FIG. 6B).

(8) Electrolytic plating treatment is performed to provide an electrolytic plating film 145 on the electroless plating film 141 and in the through holes 143A and 143B (FIG. 6C).

(9) An etching resist 147 is formed in a portion where the first conductor is to be formed (FIG. 6D).

(10) After the electrolytic plating film 145, the electroless plating film 141, and the copper foils 142A and 142B in the non-formed portion of the resist 147 are dissolved by etching, the resist 147 is removed, and the via conductors 146A and 146B and the first conductor 147, 148 is formed (FIG. 7A). Thereafter, the first conductors 147 and 148 are roughened (not shown).

(11) The above-described steps (6) to (10) are repeated (FIG. 7B).

(12) A solder resist layer 180 having an opening 181 and a thickness of about 20 μm is formed (FIG. 7C).

(13) A nickel plating layer 182 was formed in the opening 181 of the solder resist layer 180. A gold plating layer 184 is formed (FIG. 7D). In addition to the nickel-gold layer, a nickel-palladium-gold layer may be formed.

(14) A solder ball is mounted in the opening 181 and reflowed at a predetermined temperature to form a solder bump 186 (FIG. 2).

[Second board]
FIG. 8 shows a cross-sectional view of the second substrate 10.
The second substrate 10 includes a core substrate 30 having a first surface F and a second surface S at a substantially central portion in the thickness direction. A second conductor 34 is formed on the first surface F and the second surface S of the core substrate 30. Through holes 33 a and 33 b are formed in the core substrate 30. These through holes have different diameters. In the present embodiment, the first through hole 33b having a diameter of 180 μm and the second through hole 33a having a diameter of 250 μm are provided. Inside these through holes, through hole conductors for connecting the second conductors 34 are provided. Of these through-hole conductors, the first through-hole conductor 36a is provided in the large-diameter first through hole, and the second through-hole conductor 36b is provided in the small-diameter second through-hole.

The first through-hole conductor 36a is a signal conductor, and the second through-hole conductor 36b is a power source or ground conductor. The electrical functions of the through-hole conductors 36a and 36b are not limited to this.
On the first surface F and the second surface S of the core substrate 30, build-up layers 55 are provided in which interlayer resin insulation layers 50 and third conductors 58 are alternately stacked. The second conductor 34 and the third conductor 58 are connected via a via conductor 59, and the third conductors 58 located in different layers are electrically connected via a via conductor 69.
On the outermost interlayer resin insulating layer 70, a solder resist layer 80 having an opening is formed. Solder bumps 86 for mounting semiconductor elements are formed in the openings of the solder resist layer 80 on the first surface side.

FIG. 9A shows a plan view of a first surface (surface on which a semiconductor element is mounted) of the second substrate 10.
The second substrate 10 has a substantially rectangular shape and has a semiconductor element mounting region R1 in which the second bumps 86 are formed. The center C1 of the semiconductor element mounting region R1 is shifted from the center C2 of the first surface of the second substrate 10. That is, a wider region R2 than the others exists on the outer periphery of the semiconductor element mounting region R1. The region R2 is a region located in a direction opposite to the direction from the center C2 of the second substrate 10 toward the center C1 of the semiconductor element mounting region R1. At this time, in the outer periphery of the semiconductor element mounting region R1, when the region of three sides other than the region R2 is R3, the width of the region R2 is r2, and the width of the region R3 is r3, r2> r3 is satisfied.

After the resin filler is once applied to the wide region R2, the resin filler is poured between and around the plurality of bumps 86 forming the semiconductor element mounting region R1.
Thereby, it becomes possible to effectively suppress the generation of a cavity in the resin filler existing between the semiconductor element mounting region R1 and the semiconductor element mounted thereon.
Further, in the other three sides R3 of the outer periphery of the semiconductor element mounting region R1, the width becomes relatively narrow, so that the resin filler hardly flows along these three sides, and the semiconductor element mounting region R1 The resin filler can easily flow between the plurality of bumps to be formed.

  As shown in FIG. 9B, the back surface (second surface) of the second substrate 10 has a pad array composed of pads 88 corresponding to the bump array of the first substrate 110. Among these, a triangular display mark M is provided at a location corresponding to the corner C of the first substrate 110. The display mark M has a purpose of aligning both the first substrate 110 and the second substrate 10 when they are connected.

Next, a method for manufacturing the second substrate 10 will be described with reference to FIGS.
(1) A copper-clad laminate 30A in which copper foils 32 are laminated on both surfaces of an insulating substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.2 to 0.8 mm is used as a starting material. (FIG. 10A).

(2) First, the through-hole 33 for a through hole is formed in a copper clad laminated board using a drill or a laser (FIG. 10 (B)). Thereafter, an electroless plating treatment 31 is performed to provide an electroless plating film 31 (FIG. 10C). At this time, two types of through holes (for example, 180 μm) 33b and through holes (for example, 250 μm) 33a having different diameters are formed.

(3) Electrolytic plating treatment is performed, and an electrolytic plating film 35 is provided on the plating film 31 and in the through hole 33 for the through hole (FIG. 10D). Next, a hole filling resin is filled in the space formed by the electrolytic plating film 35. The filling of the hole filling resin may be omitted, and the electrolytic plating film may be filled in the through hole 33 for the through hole.

(4) An etching resist 37 is formed on the portion where the second conductor is to be formed (FIG. 10E).

(5) After the electrolytic plating film 35, the electroless plating film 31, and the copper foil 32 where the resist 37 is not formed are dissolved by etching, the resist 37 is removed, and the through-hole conductors 36a and 36b and the second conductor 34 Is formed (FIG. 11A). Thereafter, the second conductor 34 is roughened (not shown).

(6) While raising the temperature of the resin film for interlayer resin insulation layers (Ajinomoto Co., Inc .; trade name: ABF-45SH) having a thickness of about 25 μm on both surfaces of the core substrate 30 that has undergone the above-described steps. Vacuum-bonding is performed to provide an interlayer resin insulation layer 50 (FIG. 11B).

(7) Next, a via hole opening 51 having a diameter of about 60 μm is provided in the interlayer resin insulation layer 50 with a CO 2 gas laser (FIG. 11C). A roughened surface of the interlayer resin insulation layer 50 is provided by immersing in an oxidizing agent such as chromic acid or permanganate (not shown).

(8) A catalyst such as palladium is applied in advance to the surface layer of the interlayer resin insulation layer 50 and immersed in an electroless plating solution for 5 to 60 minutes, thereby providing an electroless plating film 52 in a range of 0.1 to 5 μm. (FIG. 11D).

(9) A commercially available photosensitive dry film is affixed to the substrate 30 that has been subjected to the above processing, a photomask film is placed and exposed, and then developed with sodium carbonate to provide a plating resist 54 having a thickness of 15 μm. (FIG. 12 (A)).

(10) Next, electrolytic plating is performed to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 12B).

(11) After the plating resist 54 is peeled and removed with an amine solution, the electroless plating film 52 under the plating resist is dissolved and removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide. A second conductor 58 and a via conductor 59 having a thickness of about 15 μm made of the electrolytic plating film 56 are formed (FIG. 12C). The surfaces of the third conductor 58 and the via conductor 59 are roughened by an etching solution containing a cupric complex and an organic acid (not shown).

(12) In the same manner as (6)-(11) above, the interlayer resin insulation layer 60 in which the via conductor 69 and the second conductor 68 are formed, and the interlayer resin insulation in which the via conductor 79 and the third conductor 58 are formed. A layer 70 is formed (FIG. 12D).

(13) A commercially available solder resist composition is applied to both sides of the substrate in a thickness of 20 μm, and after drying, a photomask having a thickness of 5 mm on which the pattern of the solder resist opening is drawn is applied to the solder resist layer. Is exposed to ultraviolet light and developed with a DMTG solution to form a small-diameter opening 81 on the upper surface side and a large-diameter opening 81 on the lower surface side. Further, heat treatment is performed to cure the solder resist layer, and a solder resist pattern layer 80 having openings 81 and a thickness of about 20 μm is formed (FIG. 13A).

(14) Next, the substrate on which the solder resist layer 80 was formed was immersed in an electroless nickel plating solution to form a nickel plating layer 82 having a thickness of 5 μm in the opening 81. Further, the substrate is immersed in an electroless gold plating solution to form a gold plating layer 84 having a thickness of 0.03 μm on the nickel plating layer 82 (FIG. 13B). In addition to the nickel-gold layer, a nickel-palladium-gold layer may be formed.

(15) A mask having an opening is placed in alignment with the opening 81 of the substrate, and the solder ball 86α is mounted in the opening 81 (FIG. 13C).

(16) Reflow is performed at about 200 ° C., and the solder ball 86α is used as the solder bump 86 to complete the second substrate 10 (FIG. 8).

[Method of manufacturing semiconductor mounting member]
The connection between the second substrate 10 and the first substrate 110 will be described with reference to FIG.
As shown in FIG. 14A, the second substrate 10 is inverted so that the solder bumps 76 are located on the lower side. Then, the first substrate 110 is sucked by a suction member (not shown), and the solder bumps 186 of the first substrate 110 are positioned so as to correspond to the pads 88 of the second substrate 10. Then, reflow is performed at about 200 ° C. with the solder bump 186 in contact with the pad 88, and the second substrate 10 and the first substrate 110 are connected as shown in FIG.

Then, a resin filler 188 is filled between the first substrate 110 and the second substrate 10 to complete the semiconductor mounting member 100 (FIG. 15).

Next, the semiconductor element 200 is mounted via the solder bumps 86, and a resin filler 288 is filled between the semiconductor element 200 and the second substrate 10 (FIG. 1).
Here, the same resin filler 288 is filled between the first substrate 110 and the second substrate 10 and between the semiconductor element 200 and the second substrate 10. Thereby, the reliability required when mounting the semiconductor element can be easily secured, and the occurrence of cracks in the bump 186 can be suppressed.

In the present embodiment, since the semiconductor mounting member 100 is composed of two printed wiring boards, the first substrate 110 and the second substrate 10, a single build-up substrate is formed for the purpose of dealing with multilayer wiring and strengthening the power supply. Compared with increasing the number of layers and increasing the size, the yield does not decrease.

Further, in the present embodiment, bumps that contribute to the connection of both substrates are provided on the first substrate 10 side without forming bumps on both surfaces of the second substrate 110. Usually, the second substrate 10 has a longer manufacturing time than the first substrate 110, and its production efficiency is low. For this reason, when bumps are formed on both surfaces of the second substrate 10, the production efficiency further decreases. Therefore, by providing bumps contributing to the connection of both substrates on the first substrate 110 side, the production efficiency of the second substrate 10 can be improved, and as a result, the production efficiency of the mounting member can be improved.
Further, in the present embodiment, the first substrate 110 is mounted on the second substrate 10 disposed on the lower side. If the second substrate 10 is mounted on the first substrate 110 disposed on the lower side using an adsorption member, the first surface (the surface on which the bumps 86 are provided) of the second substrate 10 becomes the adsorption surface. At this time, the bump 86 may be damaged during mounting due to interference with the suction member. On the other hand, in this embodiment, bumps are not formed on the surface of the first substrate 110 on the side where the suction member contacts. For this reason, there is no possibility that the bumps are damaged when both substrates are connected.

The second substrate 10 is thicker than the first substrate 110. In this case, the stress generated when the semiconductor element is mounted is relaxed inside the relatively thick second substrate 10 until it propagates to the bumps interposed between the first substrate 110 and the second substrate 10. It is guessed. As a result, connection reliability between the first substrate 110 and the second substrate 10 is easily ensured.

DESCRIPTION OF SYMBOLS 10 2nd board | substrate 30 Core board | substrate 34 2nd conductor 36 Through-hole conductor 50 Interlayer resin insulation layer 58 3rd conductor 59 Via conductor 80 Solder resist layer 86 2nd solder bump 100 Semiconductor mounting member 110 1st board | substrate 130 Insulation layer 136 Via conductor 137 First conductor 186 First solder bump 200 Semiconductor element

Claims (13)

A plurality of first insulating layers having through holes; a first conductor formed on the first insulating layer; and a via conductor provided in the through hole and connecting the first conductors to each other. A first substrate;
A core substrate having a through hole; second conductors formed on both surfaces of the core substrate; a through-hole conductor formed inside the through hole to connect the second conductors; A second substrate having a buildup layer formed on the second conductor and formed by alternately laminating the second insulating layer and the third conductor;
A first bump provided on a first conductor located in an outermost layer of the first conductors, and connecting the first substrate and the second substrate;
A second bump that is provided on the third conductor located in the outermost layer of the third conductors and connects the semiconductor elements;
A semiconductor mounting member comprising:
The second substrate is thicker than the first substrate. 2. The semiconductor mounting member according to claim 1, wherein 1 <t2 / t1 <2 is established, where t1 is a thickness of the first substrate and t2 is a thickness of the second substrate. 2. The semiconductor mounting member according to claim 1, wherein a resin filler of the same material is filled between the first substrate and the second substrate and between the second substrate and the semiconductor element. The semiconductor mounting member according to claim 1, wherein the first bump has a peripheral arrangement. The array area of any one side among the four sides constituting the array area of the first bump is wider than the array area of one side facing the array area of any one side. Semiconductor mounting member. The semiconductor mounting member according to claim 1, wherein the via conductor of the first substrate is formed by filling the through hole with plating. The semiconductor mounting member according to claim 1, wherein the via conductor of the first substrate is formed by being stacked in a column shape. The semiconductor mounting member according to claim 1, wherein the second substrate includes a first through-hole conductor and a second through-hole conductor having a diameter smaller than that of the first through-hole conductor. 9. The semiconductor mounting member according to claim 8, wherein the first through-hole conductor is a power source or ground conductor, and the second through-hole conductor is a signal conductor. It is a manufacturing method of the semiconductor mounting member according to claim 1,
Forming a first bump on the first substrate;
Forming a second bump on the first surface of the second substrate on which the semiconductor element is mounted;
Connecting the first substrate and the second substrate via the first bump;
Filling a resin filler between the first substrate and the second substrate. A method for manufacturing a semiconductor mounting member, comprising: Mounting a semiconductor element on the second substrate via the second bump;
The method for manufacturing a semiconductor mounting member according to claim 10, further comprising filling a resin filler between the second substrate and the semiconductor element. The method for manufacturing a semiconductor mounting member according to claim 11, wherein the same resin filler is filled between the first substrate and the second substrate and between the second substrate and the semiconductor element. The second substrate is disposed such that a second surface opposite to the first surface is positioned above, and the first substrate is connected to the second substrate via the first bump. The manufacturing method of 10 semiconductor mounting members.

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