JP2012156370A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of accurately detecting a current flowing in a main cell, and hard to be affected by a high voltage even when the high voltage is used.SOLUTION: The main cell is insulated and isolated from a sense cell by a trench isolation structure 1d. Thereby, even if a high voltage of 100 V or higher is applied to a collector of the main cell, noise resulting from that can be controlled so as not to be induced to an output terminal for current detection. Even if the emitter potential of the sense cell rises due to a current flowing in a sense resistance Rs, since the emitter of the sense cell is electrically completely isolated from the emitter of the main cell, no parasitic transistor starts action. As a matter of course, it can be suppressed that noise generated from a resistance layer 14 is induced to the output terminal for current detection. Accordingly, the current flowing in the main cell can be accurately detected, and even when a high voltage is used, the semiconductor device hard to be affected by the high voltage can be obtained.

Description

  The present invention relates to a semiconductor device in which a power element including a semiconductor switching element is divided into a main cell and a sense cell, and a current flowing through the main cell is detected by the sense cell.

  Conventionally, Patent Document 1 discloses a semiconductor integrated circuit provided with a current detection unit (sense cell) for detecting a current flowing in an emitter of a lateral IGBT in addition to a main cell in which a lateral IGBT is formed. This semiconductor integrated circuit has the same structure as that of the lateral IGBT formed in the main cell, but has a structure in which a lateral IGBT for current detection with different emitter lengths is formed in the current detection unit and these are connected in a current mirror. . In such a structure, a current obtained by reducing the current flowing through the emitter of the lateral IGBT of the main cell to a predetermined ratio flows through the emitter of the current detection unit, and therefore flows through the emitter of the main cell based on the current flowing through the current detection unit. Current can be detected. Specifically, in this semiconductor integrated circuit, a main cell is formed by arranging a plurality of cells constituting a lateral IGBT in parallel in a semiconductor chip, and a current is applied to an end of the semiconductor chip away from the main cell. The detection unit is arranged.

Japanese Patent Publication No. 08-34709

However, for example, when the configuration of the semiconductor integrated circuit disclosed in the above-mentioned conventional publication is applied to the circuit configuration having the main cell 100 and the sense cell 101 shown in FIG. 14, the output for detecting the current value flowing through the current detection unit If the resistance value of the sense resistor Rs is increased to increase the voltage across the sense resistor Rs for voltage formation, the emitter potential of the sense cell 101 increases. For this reason, the potential of the p-type body layer electrically connected to the emitter electrode rises, and the PN junction formed between the p-type body layer and the n ⁻ -type drift layer is forward-biased. The output becomes unstable. For this reason, it is necessary to suppress the voltage across the sense resistor Rs, that is, the maximum voltage of the output voltage to about 0.3V. When a high voltage (for example, 200 to 600 V) is applied to the collector, the output voltage is affected by the coupling with the high voltage, and a correct voltage cannot be output.

  Here, the lateral IGBT has been described as an example of the semiconductor element. However, in the case where the main cell and the sense cell are configured with respect to another element, for example, a diode, and the current detection function is provided, the same as described above. Problems can arise.

  In view of the above-described points, an object of the present invention is to provide a semiconductor device that can accurately detect a current flowing through a main cell and is not easily affected even when a high voltage is used.

  In order to achieve the above object, according to the first aspect of the present invention, between the first electrode (12, 29) and the second electrode (13, 28) formed on the surface of the semiconductor substrate (1, 21). By having a current flow, a horizontal semiconductor element that flows a current in a horizontal direction that is the horizontal direction of the semiconductor substrate (1, 21) is provided. The horizontal semiconductor element is divided into a main cell and a sense cell, and a current flowing in the sense cell is detected. Thus, in the semiconductor device for detecting the current flowing in the main cell, the main cell and the sense cell are insulated and separated by the element isolation structure (1d, 21d, 56) formed on the semiconductor substrate (1, 21). Yes.

  Thus, the main cell and the sense cell are insulated and separated by the element isolation structure (1d, 21d, 56). For this reason, even when a high voltage of 100 V or higher is applied to the collector on the high voltage side portion of the main cell, for example, when the lateral semiconductor element is a lateral IGBT, noise caused by the voltage is applied to the output terminal for current detection. It can be prevented from being induced. Further, even if the potential of the portion on the low voltage side of the sense cell, for example, when the lateral semiconductor element is a lateral IGBT, the emitter potential rises due to the current flowing through the sense resistors (Rs, Rs1, Rs2), the low voltage side of the main cell Therefore, the parasitic transistor does not operate.

  Therefore, it is possible to accurately detect the current flowing through the main cell, and to make the semiconductor device less susceptible to the influence even when a high voltage is used. Even when the resistance layers (14, 30) constituting the field plate for suppressing the bias of the potential gradient of the semiconductor element are formed, the noise generated from the resistance layer (14, 30) is applied to the output terminal for current detection. Induction can also be suppressed. For this reason, when forming a resistance layer (14, 30), the said effect can be acquired more effectively.

  According to the second aspect of the present invention, the sense resistor (Rs, Rs1, Rs2) is connected to the sense cell, and the voltage between the sense cell and the sense resistor (Rs, Rs1, Rs2) is output as the output voltage (V1, V2). The current flowing in the sense cell is detected based on the output voltage (V1, V2), and the maximum voltage of the output voltage (V1, V2) is set to 0.7 V or more.

  Thus, by setting the maximum voltage of the output voltage (V1, V2) to 0.7V or higher, that is, larger than 0.7V which is the forward voltage of the PN junction of silicon, a larger output voltage can be obtained. Based on (V1, V2), current detection can be performed.

  For example, as described in claim 3, the present invention can be applied to a semiconductor device having a lateral semiconductor switching element and a lateral diode as the lateral semiconductor element. Also in this case, the lateral semiconductor switching element is divided into a main cell and a sense cell, and the main cell and the sense cell of the lateral semiconductor switching element are insulated and separated by the element isolation structure (1d). In addition, the main cell and the sense cell of the lateral diode are insulated and separated by the element isolation structure (21d). The first electrode (12) of the main cell and sense cell of the lateral semiconductor switching element is electrically connected to the main electrode of the lateral diode and second electrode (28) of the sense cell, and the second electrode of the main cell of the lateral semiconductor switching element. The electrode (13) and the first electrode (29) of the main cell of the lateral diode are connected to the second electrode (13) of the sense cell of the lateral semiconductor switching element via the sense resistor (Rs1) for the lateral semiconductor switching element. In addition, by connecting the first electrode (29) of the sense cell of the lateral diode via the sense resistor (Rs2) for the lateral diode, the current path by the parallel connection of the lateral semiconductor switching element and the lateral diode can be reduced. Constitute. With such a circuit configuration, the output voltage (V1) between the sense cell of the lateral semiconductor switching element and the sense resistor (Rs1) for the lateral semiconductor switching element, the sense cell of the lateral diode and the sense resistor (Rs2) for the lateral diode. It is possible to determine whether the current flowing in the current path is positive or negative and whether the current is increasing or decreasing.

  In this case, as described in claim 4, the sense cell (53a to 53f) of the lateral semiconductor switching element, the sense resistor (Rs1) for the lateral semiconductor switching element, and the sense cell (55a to 55f) of the lateral diode and the lateral diode The sense resistors (Rs2) are preferably arranged in a line. With such a layout, the chip area of the semiconductor device can be minimized while making it possible to connect these parts at the shortest distance. In particular, the sense resistor (Rs1) for the lateral semiconductor switching element and the lateral diode are provided between the sense cells (53a to 53f) of the lateral semiconductor switching element and the sense cells (55a to 55f) of the lateral diode as described in claim 5. Preferably, a sense resistor (Rs2) is arranged.

  In the sixth aspect of the invention, the main cells (52a to 52f) of the horizontal semiconductor switching element and the main cells (54a to 54f) of the horizontal diode are arranged with a space therebetween, and the main cells of the horizontal semiconductor switching element are arranged. Between the cells (52a to 52f) and the main cells (54a to 54f) of the lateral diode, the sense cells (53a to 53f) of the lateral semiconductor switching element, the sense resistor (Rs1) for the lateral semiconductor switching element, and the sense cell of the lateral diode (55a to 55f) and a sense resistor (Rs2) for a lateral diode are arranged.

  With such a layout, the main cells (52a to 52f) of the horizontal semiconductor switching element and the main cells (54a to 54f) of the horizontal diode, the sense cells (53a to 53f) of the horizontal semiconductor switching element, and the sense cell (55a) of the horizontal diode. ˜55f) and the like can be arranged in a layout that can be connected at the shortest distance.

  In the invention according to claim 7, the main cells (52a to 52f) of the horizontal semiconductor switching element and the main cells (54a to 54f) of the horizontal diode are arranged with a space therebetween, and the main cells of the horizontal semiconductor switching element are arranged. A buffer circuit (56a-56f) for amplifying output voltages (V1, V2) is also provided between the cells (52a-52f) and the main cells (54a-54f) of the lateral diode.

  Thus, it can also be set as the structure provided with the buffer circuit (56a-56f). In this case, if the buffer circuit (56a to 56f) is provided between the main cell (52a to 52f) of the horizontal semiconductor switching element and the main cell (54a to 54f) of the horizontal diode, Similar effects can be obtained.

  The invention according to claim 8 has a control circuit part (51) for driving on / off of the semiconductor switching element, the control circuit part (51) includes a comparator, and the comparator is constituted only by CMOS. It is characterized by being composed.

  Thus, in the case where the control circuit unit (51) is provided with a comparator, the structure described in claims 3 to 6 is particularly effective when the comparator is composed of only CMOS. That is, the comparator using the CMOS has a larger offset voltage than the comparator using the bipolar transistor. For this reason, applying a circuit configuration in which the output voltage largely changes near the current 0 point is suitable for accurately detecting the positive / negative switching of the current.

  According to the ninth aspect of the invention, in addition to the sense cell provided in the region separated from the main cell of the lateral semiconductor element by the element isolation structure (1d, 21d), the element isolation structure (1d, 21d) provides isolation. In the region where the main cell of the lateral semiconductor element is provided, a sense cell is further provided between the main cells.

  In this way, in the region where the main cell of the lateral semiconductor element separated by the element isolation structure (1d, 21d) is provided, it is different from the main cell if a sense cell is further provided between the main cells. Current detection can be performed by both the sense cell arranged in the region and the sense cell arranged in the same region as the main cell. Such a configuration is suitable when it is desired to accurately detect both the positive / negative switching of the current flowing through the main cell and the absolute value of the current. That is, the detection of the current 0 point is detected based on the output voltage of the sense cell arranged in a different area from the main cell, and the absolute value of the current may be detected by the sense cell arranged in the same area as the main cell.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

It is the figure which showed the cross-sectional structure of the semiconductor device which has horizontal type IGBT concerning 1st Embodiment of this invention. FIG. 2 is a top surface layout diagram of the semiconductor device having the lateral IGBT shown in FIG. 1. It is the figure which showed the cross-sectional structure of the semiconductor device which has horizontal type | mold FWD concerning 2nd Embodiment of this invention. FIG. 4 is a top layout view of the semiconductor device having the lateral FWD shown in FIG. 3. It is the circuit diagram which showed an example of the circuit structure with which the horizontal type IGBT and horizontal type FWD concerning 3rd Embodiment of this invention are provided. FIG. 6 is a schematic diagram illustrating a detection image of a current value and a direction when on / off control of a current path is performed using the circuit configuration illustrated in FIG. 5. FIG. 7 is a waveform diagram illustrating the total current I, the output voltages V1 and V2, and the total value V of the output voltages V1 and V2 when the operation illustrated in FIG. 6 is performed. It is the figure which showed the collector voltage-collector current characteristic of horizontal type IGBT. FIG. 7 is a diagram showing a relationship between a current Isense flowing in a sense cell 41 and an output voltage V1 with respect to a collector current Ic of the main cell 40. It is a top surface layout diagram of the semiconductor device which constituted the inverter circuit concerning a 4th embodiment of the present invention. It is the enlarged view which showed an example of the wiring layout. It is a top surface layout view of a semiconductor device provided with a lateral IGBT according to a fifth embodiment of the present invention. It is sectional drawing on the C-C 'line of FIG. It is a circuit diagram when a sense resistor for current detection is connected to a semiconductor integrated circuit having a main cell and a sense cell.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. In the present embodiment, a case will be described in which one embodiment of the present invention is applied to a semiconductor device provided with a lateral IGBT as a power element composed of a semiconductor switching element.

  FIG. 1 is a diagram showing a cross-sectional configuration of a semiconductor device having a lateral IGBT according to the present embodiment. FIG. 2 is a top surface layout diagram of the semiconductor device having the lateral IGBT shown in FIG. FIG. 1 corresponds to a cross section on the line A-A ′ in FIG. 2. Although FIG. 2 is not a cross-sectional view, hatching is partially shown for easy understanding of the drawing. Hereinafter, the structure of the lateral IGBT according to the present embodiment will be described with reference to these drawings.

  As shown in FIG. 1, in the present embodiment, a lateral IGBT is formed using an SOI substrate 1, and in addition to the main cell of the lateral IGBT for turning on / off current supply to a load (not shown). A sense cell including a lateral IGBT having the same structure as the main cell as a current detection element is also formed.

The SOI substrate 1 is formed by forming an active layer 1c made of silicon on a support substrate 1a made of silicon or the like via a buried oxide film (box) 1b. In this embodiment, the active layer 1c the n ^- is functioning as a type drift layer 2, the the n ^- surface portion of the type drift layer 2, the components constituting the lateral IGBT is formed in the main cell and sensing cell.

The thickness of the buried oxide film 1b in the SOI substrate 1, the thickness of the active layer 1c (n ⁻ type drift layer 2), and the impurity concentration are arbitrary, but are designed to obtain a desired breakdown voltage. For example, the thickness of the buried oxide film 1b is preferably 4 μm or more in order to obtain a high breakdown voltage, and in particular, the thickness is 5 μm or more in order to ensure a stable breakdown voltage of 600 V or more. Is preferable. For the active layer 1c, the n-type impurity concentration is 1 × 10 ^{14 to} 1.2 × 10 ¹⁵ cm ⁻³ when the thickness is 15 μm or less in order to ensure a stable withstand voltage of 600 V or more. When the thickness is 20 μm, the n-type impurity concentration is preferably 1 × 10 ¹⁴ to 8 × 10 ¹⁴ cm ⁻³ .

  The active layer 1c is element-isolated by a trench isolation structure 1d extending from the substrate surface to the buried oxide film 1b, and is divided into a plurality of trench islands that are electrically isolated from each other. The main cell and the sense cell are each surrounded by a trench isolation structure 1d and are arranged in different trench islands. For example, in the trench isolation structure 1d, after forming a trench reaching the buried oxide film 1b with respect to the active layer 1c, an oxide film is formed by thermally oxidizing the inner wall surface of the trench, and further, the trench is formed with Poly-Si or the like. It is formed by embedding the inside.

A LOCOS oxide film 3 is formed on the surface of the n ⁻ -type drift layer 2, and each part constituting the lateral IGBT is separated by the LOCOS oxide film 3. A p ⁺ -type collector region 4 having one direction as a longitudinal direction is formed in a portion of the surface layer portion of the n ⁻ -type drift layer 2 where the LOCOS oxide film 3 is not formed. The periphery of the p ⁺ -type collector region 4 is surrounded by an n-type buffer layer 5 having a higher impurity concentration than the n ⁻ -type drift layer 2.

Further, in the surface layer portion of the n ⁻ type drift layer 2 where the LOCOS oxide film 3 is not formed, the channel p well layer 6, the n ⁺ type emitter region 7, p ^{+ with the} p ⁺ type collector region 4 as the center. A type contact layer 8 and a p-type body layer 9 are formed.

The channel p well layer 6 is a part for forming a channel region on the surface, and has a thickness of 2 μm or less and a width of 6 μm or less, for example. As shown in FIG. 2, the channel p-well layer 6 has a linear portion having the same direction as the p ⁺ -type collector region 4 (and a collector electrode 12 described later) as the longitudinal direction, and the p ⁺ -type collector region The p ⁺ -type collector region 4 is concentrically formed around the p ⁺ -type collector region 4.

Further, the n ⁺ -type emitter region 7 is formed in the surface layer portion of the channel p-well layer 6 so as to terminate inside the termination position of the channel p-well layer 6, and the longitudinal direction of the p ⁺ -type collector region 4 And the same direction as the longitudinal direction. In the present embodiment, as shown in FIG. 2, n ⁺ type emitter regions 7 are arranged on both sides of the p type contact layer 8 and the p type body layer 9, and the p ⁺ type collector region 4 They are not formed at the corners, that is, at both ends of the p ⁺ -type collector region 4 having one direction as the longitudinal direction, but are in a linear layout arranged in parallel with the p ⁺ -type collector region 4.

The p ⁺ -type contact layer 8 is for fixing the channel p-well layer 6 to the emitter potential, and has a higher impurity concentration than the channel p-well layer 6. As shown in FIG. 2, this p ⁺ type contact layer 8 also has a linear portion whose longitudinal direction is the same direction as p ⁺ type collector region 4 (and collector electrode 12 described later), and p ⁺ type collector region Centering on 4, the p ⁺ -type collector region 4 is arranged concentrically so as to surround one circumference.

The p-type body layer 9 serves to reduce a voltage drop caused by a hole current flowing from the collector to the emitter via the surface. The p-type body layer 9 also, p ⁺ -type collector region 4 (and later the collector electrode 12) and the same direction has a linear portion whose longitudinal direction, around the p ⁺ -type collector region 4, p ⁺ The mold collector region 4 is arranged concentrically so as to surround the periphery of the mold collector region 4. This p-type body layer 9 makes it difficult for the parasitic npn transistor constituted by the n ⁺ -type emitter region 7, the channel p-well layer 6 and the n ⁻ -type drift layer 2 to operate, and further improves the turn-off time. It becomes possible.

The channel p-well layer 6, n ⁺ -type emitter region 7, p ⁺ -type contact layer 8 and p-type body layer 9 thus configured are arranged on both sides of the p ⁺ -type collector region 4 for each cell. Has been. Therefore, in the place where the cells are arranged adjacent to each other, between the adjacent cells, as shown in FIG. 2, the channel p-well layer 6, the n ⁺ -type emitter region 7, the p ⁺ -type contact layer 8 and A layout in which two sets of p-type body layers 9 are arranged.

  A gate electrode 11 made of doped Poly-Si or the like is disposed on the surface of the channel p well layer 6 with a gate insulating film 10 interposed therebetween. By applying a gate voltage to the gate electrode 11, a channel region is formed on the surface portion of the channel p-well layer 6.

Further, a collector electrode 12 electrically connected to the p ⁺ type collector region 4 is formed on the surface of the p ⁺ type collector region 4, and the n ⁺ type emitter region 7 and the p ⁺ type contact layer are formed. An emitter electrode 13 electrically connected to the n ⁺ -type emitter region 7 and the p ⁺ -type contact layer 8 is formed on the surface of 8.

Furthermore, in the present embodiment, the resistance layer 14 constituting the field plate in which doped Poly-Si is extended is formed on the surface of the LOCOS oxide film 3 formed between the collector and gate, In this way, the bias of the potential gradient is eliminated. Specifically, as shown in FIG. 2, the resistance layer 14 has a structure wound in a spiral around the collector electrode 12, and one end thereof is electrically connected to the collector electrode 12 as shown in FIG. And the other end is connected to the gate electrode 11. For this reason, the portion of the resistance layer 14 connected to the collector electrode 12 is set to the collector potential, and proceeds from the resistance layer 14 to the emitter side while gradually decreasing the voltage due to the internal resistance. Therefore, the potential of the resistance layer 14 becomes a potential gradient corresponding to the distance from the collector electrode 12, and the potential gradient in the n ⁻ type drift layer 2 located below the resistance layer 14 via the LOCOS oxide film 3 is also constant. Can be kept in. As a result, electric field concentration that can occur when there is a bias in the potential gradient can be suppressed, the withstand voltage can be improved, impact ionization can be suppressed, and an increase in switching time during switching (turn-off) can be suppressed. Is possible.

With such a structure, a lateral IGBT laid out in an oval shape is configured, and the main cell and the sense cell are configured by the lateral IGBT laid out in an oval shape. Specifically, a main cell is formed by a plurality of horizontal IGBTs having an elliptical layout structure, and a plurality of them are arranged side by side in a direction perpendicular to the longitudinal direction of the p ⁺ -type collector region 4. A sense cell is constituted by a lateral IGBT of one cell arranged on the outside. Then, the main cell and the sense cell are separated by the trench isolation structure 1d, and these are arranged on different trench islands so that the sense cell is electrically isolated from the main cell.

The horizontal IGBT according to the present embodiment is configured by the above structure. In the lateral IGBT configured as described above, when a desired gate voltage is applied to the gate electrode 11, the lateral IGBT is positioned below the gate electrode 11 sandwiched between the n ⁺ -type emitter region 7 and the n ⁻ -type drift layer 2. A channel region is formed in the surface layer portion of the channel p-well layer 6 to be operated, and electrons flow into the n ⁻ -type drift layer 2 from the emitter electrode 13 and the n ⁺ -type emitter region 7 through the channel region. Along with this, n through the collector electrode 12 and the p ⁺ -type collector region 4 ^- hole flows into the type drift layer 2, n ^- conductivity modulation occurs in the type drift layer 2. Thereby, an IGBT operation of flowing a large current between the emitter and the collector is performed.

  Further, in the present embodiment, the main cell having the same structure as the sense cell is provided, and the emitter of the main cell corresponds to the current mirror ratio corresponding to the area ratio (more specifically, the ratio of the emitter length in each cell). A current obtained by reducing the flowing current is caused to flow to the emitter of the sense cell. The current flowing through the emitter is detected by converting this current into an output voltage corresponding to the voltage across the sense resistor Rs disposed between the emitters of the main cell and the sense cell.

In performing such current detection, when a lateral IGBT is used as a high voltage element to which a high voltage of 100 V or more is applied to the collector, for example, the collector potential changes between 0 V and 100 V during switching. As a result of this coupling with the high voltage, noise is induced at the output terminal for current detection. For this reason, noise is added to the output voltage, and it is difficult to accurately detect the current. Further, when the output voltage at the sense resistor Rs is increased, the PN junction formed between the p-type body layer 9 and the n ⁻ -type drift layer 2 is forward-biased, and the parasitic transistor operates, so that the output is not good. It becomes stable. Furthermore, in the high breakdown voltage device, when the resistance layer 14 constituting the field plate is arranged to ensure the breakdown voltage as in the present embodiment, the potential of the resistance layer 14 also changes during switching, so that it can be a noise generation source. It is difficult to detect current.

  However, in the lateral IGBT of this embodiment, the main cell and the sense cell are insulated and separated by the trench isolation structure 1d. For this reason, even if a high voltage of 100 V or higher is applied to the collector of the main cell, noise caused by the high voltage can be prevented from being induced in the output terminal for current detection. Even if the emitter potential of the sense cell is increased by the current flowing through the sense resistor Rs, the parasitic transistor does not operate because it is electrically completely separated from the emitter of the main cell. Of course, it is also possible to suppress the noise generated from the resistance layer 14 from being induced in the current detection output terminal. Therefore, it is possible to accurately detect the current flowing through the main cell, and to make the semiconductor device less susceptible to the influence even when a high voltage is used.

  In order to further improve noise immunity, it is preferable to increase the current flowing through the sense cell. For this reason, when the area ratio of the main cell and the sense cell is set to 1/100 to 1/5, it is possible to increase the current that can be passed through the sense cell, and to make the semiconductor device further excellent in noise resistance.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, a case will be described in which a lateral free wheel diode (hereinafter referred to as FWD) is provided with a current detection function, instead of a semiconductor device including a lateral IGBT as in the first embodiment.

  FIG. 3 is a diagram showing a cross-sectional configuration of a semiconductor device having a lateral FWD according to the present embodiment. FIG. 4 is a top surface layout diagram of the semiconductor device having the lateral FWD shown in FIG. FIG. 3 corresponds to a cross section taken along line B-B ′ in FIG. 4. Although FIG. 4 is not a cross-sectional view, hatching is partially shown for easy understanding of the drawing. Hereinafter, the structure of the horizontal FWD according to the present embodiment will be described with reference to these drawings.

As shown in FIG. 3, the horizontal FWD is also formed using the SOI substrate 21 in this embodiment. The SOI substrate 21 includes a support substrate 21a, a buried oxide film 21b, and an active layer 21c, and has a configuration similar to that of the SOI substrate 1 described in the first embodiment. Then, an active layer 21c n ^- as type cathode layer 22, the n ^- each part constituting a lateral FWD to type cathode layer 22 is formed. The active layer 21c of the SOI substrate 21 is isolated by a trench isolation structure 21d extending from the substrate surface to the buried oxide film 21b, and is divided into a plurality of trench islands that are electrically isolated from each other. The trench isolation structure 21d of the present embodiment is configured similarly to the trench isolation structure 1d described in the first embodiment, and the main cell and the sense cell are surrounded by the trench isolation structure 21d, and are arranged in different trench islands. Structure.

Further, as shown in FIG. 3, a LOCOS oxide film 23 is formed on the surface of the n ⁻ -type cathode layer 22, and each part constituting the lateral FWD is separated by the LOCOS oxide film 23. An n ⁺ -type contact layer 24 and an n-type buffer layer 25 having one direction as a longitudinal direction are formed in a portion of the surface layer portion of the n ⁻ -type cathode layer 22 where the LOCOS oxide film 23 is not formed. A p-type anode layer 26 and a p ⁺ -type contact layer 27 are formed so as to surround the n ⁺ -type contact layer 24 and the n-type buffer layer 25.

Further, a cathode electrode 28 electrically connected to the n ⁺ type contact layer 24 and an anode electrode 29 electrically connected to the p ⁺ type contact layer 27 and the p type anode layer 26 are provided on the substrate surface. Yes. Further, a resistance layer 30 formed by extending doped Poly-Si is formed on the surface of the LOCOS oxide film 23 formed between the anode and the cathode, and the potential gradient between the anode and the cathode is uneven. It is supposed to disappear. The resistance layer 30 is also wound in a spiral shape with the cathode electrode 28 as the center. As shown in FIG. 3, one end of the resistance layer 30 is connected to the cathode electrode 28 and the other end is connected to the anode electrode 29. It is connected. Therefore, the potential of the resistance layer 30 becomes a potential gradient corresponding to the distance from the cathode electrode 28, and the potential gradient in the active layer 21c located below the resistance layer 30 via the LOCOS oxide film 23 is also kept constant. Can be drunk.

  As described above, in the present embodiment, in the lateral FWD, the main cell and the sense cell are separated by the trench isolation structure 21d and arranged in different trench islands so that they are completely separated electrically. I have to. Also in the lateral FWD having such a structure, as in the lateral IGBT described in the first embodiment, for example, a sense resistor Rs is connected to the anode of the sense cell, and the cathode of the main cell and the cathode of the sense cell are connected to each other. The present invention can be applied to a circuit configuration in which the sense resistor Rs is connected to the anode of the main cell. That is, the current flowing through the main cell can be detected by converting the current flowing through the sense cell into the output voltage of the sense resistor Rs and outputting it.

  In such a circuit configuration, by adopting a lateral FWD having the structure as in the present embodiment, even when a high voltage of 100 V or higher is applied to the cathode of the main cell, noise caused by the applied voltage is output for current detection. It can be prevented from being induced at the terminal. Further, even if the anode potential of the sense cell rises due to the current flowing through the sense resistor, the parasitic transistor does not operate because it is electrically separated from the anode of the main cell. Of course, the noise generated from the resistance layer 30 can also be suppressed from being induced in the output terminal for current detection. Therefore, it is possible to accurately detect the current flowing through the main cell, and to make the semiconductor device less susceptible to the influence even when a high voltage is used.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, a circuit configuration including both the lateral IGBT described in the first embodiment and the lateral FWD described in the second embodiment will be described. Since the structures of the lateral IGBT and the lateral FWD are the same as those in the first and second embodiments, a circuit configuration provided with the lateral IGBT and the lateral FWD will be described here.

  FIG. 5 is a circuit diagram showing an example of a circuit configuration provided with a lateral IGBT and a lateral FWD. As shown in this figure, a horizontal IGBT main cell 40 and a sense cell 41 are provided, and a horizontal FWD main cell 42 and a sense cell 43 are provided, and sense resistors Rs1 and Rs2 are provided for the sense cells 41 and 43, respectively. Are connected to each other. Specifically, the cathode-anode of the main cell 42 of the lateral FWD is electrically connected to the collector-emitter of the main cell 40 of the lateral IGBT, and the sense resistor Rs1 is connected to the emitter of the sense cell 41 of the lateral IGBT. The sense resistor Rs2 is connected to the anode of the sense cell 43 of the horizontal FWD. In this way, a current path is configured by a circuit configuration in which the lateral IGBT and the lateral FWD are connected in parallel, and on / off of current supply to a load connected to this circuit can be controlled. Such a circuit configuration is applied to each arm of the upper and lower arms provided in each phase of an inverter circuit for driving a three-phase motor, for example.

  In this circuit, the current flowing in the current path through the lateral IGBT or the lateral FWD is detected, the current value and the direction of the current are detected, and whether or not the current is in an overcurrent state is detected. For example, by transmitting the output voltages V1 and V2 of the sense resistors Rs1 and Rs2 to a microcomputer (not shown), the current value and the direction of the current can be detected, and it can be detected that the current is in an overcurrent state. And by controlling the gate voltage of the lateral IGBT based on the detection result, it is possible to protect the inverter circuit and the three-phase motor from malfunctioning, for example, by stopping the driving of the lateral IGBT when overcurrent is detected. Become.

  Hereinafter, specific current detection when performing on / off control of the current path using this circuit, that is, a method for detecting the value and direction of the current flowing in the lateral IGBT or the lateral FWD is shown in FIG. A schematic diagram showing a detection image is shown and described with reference to this figure.

  First, prior to a specific method of current detection, the operation of each arm constituting the inverter circuit will be described assuming that the circuit configuration shown in FIG. 5 is applied to the inverter circuit.

  In each arm constituting the inverter circuit, when the lateral IGBT is turned on, a current flows between the collector and the emitter of the lateral IGBT. Therefore, a current flows from the collector to the emitter side on the lateral IGBT side, and no current flows on the lateral FWD side. A state is reached (the state shown in FIG. 6A). Next, when the lateral IGBT is switched from on to off, a reflux current flows through the lateral FWD (state shown in FIG. 6B). For this reason, current does not flow on the lateral IGBT side, and current flows from the anode to the cathode side in the lateral FWD. Then, after the period in which the reflux current flows, the current does not flow in both the lateral IGBT and the lateral FWD (state in FIG. 6C). Current detection is performed on the premise of such an operation.

  Specifically, as shown in FIG. 6A, when the lateral IGBT of the main cell 40 is turned on in the lower arm, the lateral IGBT of the sense cell 41 is also turned on accordingly, and a current also flows through the sense resistor Rs1. . At this time, the output voltage V1 indicated by the potential between the lateral IGBT of the sense cell 41 and the sense resistor Rs1 is a value obtained by subtracting the ON voltage of the lateral IGBT of the sense cell 41 with reference to the high voltage applied from the power supply. The potential becomes positive. On the other hand, since no current flows in the lateral FWD, the output voltage V2 indicated by the potential between the lateral FWD of the sense cell 43 and the sense resistor Rs2 becomes zero. Therefore, the absolute value of the current value of the current flowing in the current path can be detected based on the output voltage V1, and the current is forward (high voltage side) when the output voltage V1 is positive and the output voltage V2 is zero. To the low voltage side) can be detected.

  Further, as shown in FIG. 6B, when the lateral IGBT of the main cell 40 is turned off in the lower arm, the lateral IGBT of the sense cell 41 is also turned off simultaneously, so that no current flows and the output voltage V1 becomes zero. . On the other hand, at the moment when the lateral IGBTs of the main cell 40 and the sense cell 41 are turned off, a reflux current flows through the lateral FWD of the main cell 42 and the sense cell 43. Therefore, the output voltage V2 becomes a value obtained by subtracting the voltage drop at the sense resistor Rs2 with respect to GND, and becomes a negative potential. Accordingly, the absolute value of the current value of the current flowing in the current path can be detected based on the output voltage V2, and when the output voltage V1 is zero and the output voltage V2 is negative, the current is in the reverse direction (low voltage side). To the high voltage side) can be detected.

  Then, as shown in FIG. 6C, when a period in which the reflux current flows after the lateral IGBTs of the main cell 40 and the sense cell 41 are turned off, the lateral IGBTs of the main cell 40 and the sense cell 41, the sense cell 42, and the sense cell 43. No current flows through the horizontal FWD. For this reason, both the output voltage V1 and the output voltage V2 become zero, and it can be detected that no current flows.

  FIG. 7 is a waveform diagram showing the total current I, the output voltages V1 and V2, and the total value V of the output voltages V1 and V2 when the above operation is performed. As shown in this figure, the sign of the output voltages V1, V2 or their total value V changes abruptly in the vicinity of the current 0 point where the total current I becomes zero. Further, the output voltages V1, V2 or their total value V increase as the current increases, and the output voltage pressures V1, V2 or their total value V decrease as the current decreases. Therefore, it is possible to accurately determine whether the entire current is positive or negative and to determine whether the current is increasing or decreasing, and the magnitude and direction of the current can be detected.

  When the resistance values of the sense resistors Rs1 and Rs2 are set large so that high voltages close to the on-voltage of the lateral IGBT of the main cell 40 or the Vf of the lateral FWD of the main cell 42 are generated as the output voltages V1 and V2. preferable. For example, when a lateral IGBT having a collector voltage-collector current characteristic as shown in FIG. 8 is used and the mirror ratio of the main cell 40 and the sense cell 41 is 1/70 and the sense resistor Rs1 is 1000Ω, the main IGBT is used. The relationship between the current Isense flowing through the sense cell 41 and the output voltage V1 with respect to the collector current Ic of the cell 40 is expressed as shown in FIG. As is clear from this figure, in the low current region, the output voltage V1 has a large slope with respect to the current. In the large current region, the slope gradually decreases, but a positive slope can be secured at least until the output voltage V1 becomes 1 V or higher. Similarly, in the horizontal FWD, by setting the mirror ratio of the main cell 42 and the sense cell 43 and the sense resistor Rs2 as appropriate, a positive slope is obtained until the output voltage V2 becomes at least 1 V or more with respect to the current flowing in the horizontal FWD. Can be secured. Therefore, by setting the sense resistors Rs1 and Rs2, the output voltages V1 and 2 are set to a maximum output of 0.7 V or more, which is the forward voltage of the silicon PN junction (that is, the on-voltage of the lateral IGBT or the Vf of the lateral FWD). can do. Therefore, current detection can be performed based on the larger output voltages V1 and V2.

  As described above, with the circuit configuration including both the lateral IGBT and the second lateral FWD described in the first embodiment, for example, each arm of the inverter is configured, and the magnitude and direction of the current flowing through this circuit configuration are detected. It becomes possible.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In the present embodiment, a case where the circuit configuration including the lateral IGBT and the lateral FWD described in the third embodiment is applied to a semiconductor device configuring an inverter circuit will be described. The structures of the lateral IGBT and the lateral FWD are the same as those in the first and second embodiments.

  FIG. 10 is a top surface layout diagram of the semiconductor device constituting the inverter circuit according to the present embodiment. The inverter circuit shown in this figure drives a three-phase motor based on a high voltage (for example, 288 V) applied from a main power source such as a battery. A semiconductor device has a basic configuration of an inverter circuit as an integrated circuit. A chip inverter driver IC is configured. Specifically, the driving of a three-phase motor is controlled by a control microcomputer (not shown) provided outside the semiconductor device, and the control microcomputer supplies alternating current to each phase of the three-phase motor in turn when the motor is driven. Thus, the three-phase motor is driven by controlling the inverter circuit.

  The semiconductor device is formed on an SOI substrate, and an inverter output circuit 50 in which upper and lower arms 50a to 50f connected in series are connected in parallel for three phases, and upper and lower arms 50a to 50f for three phases, that is, six arms 50a to 50f. The control circuit unit 51 including various circuits such as a circuit for controlling the control is provided.

  As shown in FIG. 10, the upper arms 50a, 50c, 50e for three phases and the lower arms 50b, 50d, 50f for three phases are alternately laid out in the left-right direction on the paper. In this embodiment, the lower arm 50b, the upper arm 50a, the upper arm 50c, the lower arm 50d, the lower arm 50f, and the upper arm 50e are alternately arranged in this order from the left in FIG. Further, the control circuit unit 51 is configured by providing various circuits corresponding to the upper and lower arms 50a to 50f. Then, the lateral IGBTs of the main cells 52a to 52f and the sense cells 53a to 53f and the lateral FWDs of the main cells 54a to 54f and the sense cells 55a to 55f and the control circuit unit 51 provided in the arms 50a to 50f are insulated by the trench isolation structure 56, respectively. The structure is separated. The trench isolation structure 56 has the same structure as the trench isolation structures 1d and 21d described in the first and second embodiments.

  In such a structure, a plurality of horizontal IGBTs of main cells 52a to 52f having an oval top surface layout are arranged side by side in one direction (up and down direction in the drawing), and the main cell 54a is spaced apart from the main cell 54a. A plurality of horizontal FWDs of ~ 54f are arranged side by side in the same direction. In each of the arms 50a to 50f, between the lateral IGBT of the main cells 52a to 52f and the lateral FWD of the main cells 54a to 54f, the lateral IGBT of the sense cells 53a to 53f and the lateral FWD of the sense cells 55a to 55f and the sense resistor Rs1. , Rs2 are formed. Further, in order to amplify the output voltages V1 and V2, the arms 50a to 50f are provided with buffer circuits 56a to 56f, and the buffer circuits 56a to 56f are also the lateral IGBTs of the main cells 52a to 52f and the main cells 54a to 54f. Are formed between the horizontal FWDs. The lateral IGBTs of the sense cells 53a to 53f and the lateral FWDs of the sense cells 55a to 55f, the sense resistors Rs1 and Rs2, and the buffer circuits 56a to 56f provided in each arm 50f include the sense resistors Rs1 and Rs2 as the sense cells 53a to 53f and the sense cells. In a state sandwiched between 55a to 55f, they are arranged in a line.

  As described above, the lateral IGBT and the lateral FWD shown in the first and second embodiments can be applied to the semiconductor device constituting the inverter circuit. As described above, in each arm 50a-50f, the lateral IGBTs of the main cells 52a-52f and the lateral FWDs of the main cells 54a-54f are arranged in one direction, and the lateral IGBTs of the sense cells 53a-53f are arranged between them. A lateral FWD and sense resistors Rs1 and Rs2 of the sense cells 55a to 55f are arranged. As a result, the chip area of the semiconductor device can be minimized and an increase in the chip area can be suppressed. Also, when the buffer circuits 56a to 56f are provided, they are arranged between the horizontal IGBTs of the main cells 52a to 52f and the horizontal FWDs of the main cells 54a to 54f. For this reason, even if the buffer circuits 56a to 56f are provided, the chip area of the semiconductor device can be minimized.

  Further, the lateral IGBTs of the sense cells 53a to 53f, the lateral FWD of the sense cells 55a to 55f, the sense resistors Rs1 and Rs2, and the buffer circuits 56a to 56f are arranged in a line. For this reason, the chip area of the semiconductor device can be minimized while the connection between them can be performed at the shortest distance. In particular, the sense resistors Rs1 and Rs2 are preferably arranged between the sense cells 53a to 53f and the sense cells 55a to 55f.

  Further, the lateral IGBTs of the sense cells 53a to 53f, the lateral FWD of the sense cells 55a to 55f, the sense resistors Rs1 and Rs2, and the buffer circuits 56a to 56f are arranged between the lateral IGBT of the main cells 52a to 52f and the lateral FWD of the main cells 54a to 54f. It is arranged. For this reason, it is possible to provide a layout that can connect the main cells 52a to 52f and the main cells 54a to 54f, the sense cells 53a to 53f, the sense cells 55a to 55f, and the like with the shortest distance.

  FIG. 11 is an enlarged view showing an example of this wiring layout. Note that FIG. 11 corresponds to an enlarged view of the vicinity of the sense cell in FIG. 10 and is not a cross-sectional view, but hatching of the wiring layout is shown for easy understanding of the drawing.

  As shown in this figure, the emitter wiring 57 and collector wiring 58 of the lateral IGBT of each main cell 52a to 52f and the anode wiring 59 and cathode wiring 60 of the lateral FWD of each main cell 54a to 54f are the main cells 52a to 52f and the main cell 52a to 52f. The cells 54a to 54f are drawn in a direction perpendicular to the arrangement direction of the cells 54a to 54f. Further, on both sides of the main cells 52a to 52f and the main cells 54a to 54f, the negative common wiring 61, the collector wiring 58, and the cathode wiring 60 to which the emitter wiring 57 and the anode wiring 59 are connected are parallel to the arrangement direction. The positive-side common wiring 62 to be connected is extended.

  In the region surrounded by the emitter wiring 57, the anode wiring 59 and the negative electrode common wiring 61, the collector wiring 58, the cathode wiring 60 and the positive electrode common wiring 62 laid out in this way, the lateral IGBTs of the sense cells 53a to 53f, Wiring 64 is arranged to connect desired portions of the lateral FWD of sense cells 55a to 55f, sense resistors Rs1 and Rs2, and buffer circuits 56a to 56f. The sense resistor Rs1 is connected to the negative common wiring 61 by connecting the wiring 65 to the emitter wiring 57, and the negative resistance common wiring 61 is connected to the sense resistance Rs2 by connecting the wiring 66 to the anode wiring 59. Connected with.

  Thus, since the wiring connected to each part which comprises each arm 50a-50f can be connected by the shortest distance, it becomes possible to suppress the malfunction by noise more. Specifically, the sense resistors Rs1 and Rs2 can be electrically connected to the lateral IGBT emitter wiring 57 of the main cells 52a to 52f and the lateral FWD anode wiring 59 of the main cells 54a to 54f at the shortest distance. Thereby, it is possible to suppress malfunction due to noise when the wiring length between them becomes long. Further, since the main cells 52a to 52f and 54a to 54f are arranged on both sides of the sense cells 53a to 53f, 55a to 55f, etc., the emitter wiring 57 and the collector wiring of the lateral IGBT of each main cell 52a to 52f. 58 and the horizontal FWD anode wiring 59 and cathode wiring 60 of each of the main cells 54a to 54f can be connected through the common wirings 61 and 62 at the shortest distance. Thereby, it is also possible to suppress malfunction due to noise when the wiring length between them becomes long.

  Such a structure is particularly effective when the comparator is provided in the control circuit unit 51 and the comparator is constituted only by CMOS. That is, the comparator using the CMOS has a larger offset voltage than the comparator using the bipolar transistor. For this reason, applying a circuit configuration in which the output voltage largely changes near the current 0 point is suitable for accurately detecting the positive / negative switching of the current.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. In the present embodiment, a sense cell is configured using a part of the main cell of the lateral IGBT described in the first embodiment. Since the basic structure of the lateral IGBT is the same as that of the first embodiment, only the parts different from the first embodiment will be described.

  FIG. 12 is a top surface layout diagram of the semiconductor device including the lateral IGBT according to the present embodiment. 13 is a cross-sectional view taken along line C-C ′ of FIG. Note that the cross section taken along the line D-D 'of FIG. 12 is the same as FIG.

As shown in FIGS. 12 and 13, in the present embodiment, the trench island where the sense cell is arranged is separated from the trench island where the main cell is arranged by the trench isolation structure 1d, as in the first embodiment. The sense cell is also formed in the trench island where the main cell is disposed. Specifically, in the direction perpendicular to the longitudinal direction of the p ⁺ -type collector region 4, a plurality of horizontal IGBT main cells are arranged side by side, and the outermost straight line of the emitter in the arrangement direction among the cells located on the outermost side of them. The sense cell is configured by using the unit.

That is, as shown in FIGS. 12 and 13, the channel p-well layer 6, the n ⁺ -type emitter region 7 and the p ⁺ -type contact layer 8 are divided into two at the central position in the linear portion of the emitter constituting the sense cell. As a result, the region is divided into three regions, and the p-type body layer 9 is also divided in the same manner, although not shown. The divided central portion is used as a sense cell, and main cells are arranged on both sides of the sense cell. That is, the emitter of the sense cell is sandwiched between the emitters of the main cell. The p-type body layer 9 is also divided between the sense cell and the main cell, and the p-type body layer 9 of each of the sense cell and the main cell is junction-separated. Thereby, leakage through the p-type body layer 9 can be prevented.

Further, between the n ⁺ -type emitter region 7 shed, toward the end of the p ⁺ -type contact layer 8 on the end portion of the n ⁺ -type emitter region 7, the longitudinal direction and the vertical direction of the p ⁺ -type contact layer 8 The p ⁺ type separation layer 8a is provided. By providing this p ⁺ type isolation layer 8a, a parasitic transistor constituted by the n ⁺ type emitter region 7, the p type body layer 9, and the n − type drift layer 2 operates on the main cell side and the sense cell side, respectively. It is possible to prevent.

  The horizontal IGBT according to the present embodiment is configured by the above structure. In the lateral IGBT configured as described above, current detection can be performed by both the sense cell arranged in a trench island different from the main cell and the sense cell arranged in the same trench island as the main cell. Such a lateral IGBT is suitable when it is desired to accurately detect both the positive / negative switching of the current flowing through the main cell and the absolute value of the current.

  Specifically, the current 0 point is detected based on the output voltage of the sense cell arranged in a trench island different from the main cell, and the absolute value of the current is detected by the sense cell arranged in the same trench island as the main cell. .

  The sense cell placed on a trench island different from the main cell may not accurately correspond to the absolute value of the current flowing through the main cell, but switching between positive and negative current flowing through the main cell by increasing the output voltage Can be detected. That is, in a sense cell arranged on a trench island different from the main cell, the current density flowing through the emitter of the sense cell and the current density flowing through the emitter of the sense cell are greatly different, and the output voltage corresponds exactly to the absolute value of the current. It may not be. For this reason, it is difficult to detect an accurate absolute value of the current, but it is easy to detect the positive / negative switching of the current flowing through the main cell by increasing the output voltage.

  On the other hand, a sense cell arranged on the same trench island as the main cell can generate an output voltage which is small relative to the absolute value of the current. In other words, by arranging the sense cell so that it is sandwiched between the main cells on the same trench island as the main cell, the current density flowing to the emitter of the sense cell can be made closer to the current density flowing to the emitter of the sense cell, and the mirror ratio is the main cell. And the length ratio in the longitudinal direction of the emitter of each sense cell. Therefore, it is possible to generate an output voltage that accurately corresponds to the absolute value of the current flowing through the main cell, and it is possible to accurately detect the absolute value of the current flowing through the main cell based on the output voltage.

  Therefore, the lateral IGBT according to the present embodiment can accurately detect both the positive / negative switching of the current flowing through the main cell and the absolute value of the current. In the sense cell arranged on the same trench island as the main cell, since the effective area can be made smaller than that of the main cell, the mirror ratio can be reduced, the current flowing through the sense cell can be reduced, and the loss can be reduced. Further, in the sense cell arranged on a trench island different from the main cell, the effective area cannot be made much smaller than that of the main cell, but the current flowing through the sense cell is limited by increasing the resistance value of the sense resistor Rs1 connected to the sense cell. Loss can be reduced.

(Other embodiments)
In each of the above embodiments, an example of the configuration of a semiconductor device including a lateral IGBT has been described, but the design can be changed as appropriate.

  For example, in each of the above embodiments, the case where the lateral IGBT and the lateral FWD are formed on the SOI substrates 1 and 21 has been described. However, the lateral IGBT and the lateral FWD may be formed on a semiconductor substrate such as a simple silicon substrate that does not have an SOI structure. Further, the structure of the lateral IGBT or the lateral FWD may be changed. For example, in each of the above embodiments, the resistance layers 14 and 30 are formed to make the potential gradient more uniform. However, the resistance layers 14 and 30 may not be formed. Further, although the other end of the resistance layer 14 is connected to the gate electrode 11, a structure in which it is connected to the emitter electrode 13 may be used. Moreover, although the trench isolation structures 1d and 21d have been described as an example of the element isolation structure, other element isolation structures may be used.

Further, in the first embodiment and the like, an n-channel type lateral IGBT in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the conductivity type of each component is reversed. The present invention can also be applied to a p-channel type lateral IGBT. That is, the drift layer is composed of the n ⁻ type drift layer 2, the channel layer is composed of the channel p well layer 6, the first impurity region is the p ⁺ type collector region 4, and the second impurity region is the n ⁺ type emitter region 7. Although the n-channel type lateral IGBT configured as described above is given as an example, a p-channel type lateral IGBT can be obtained by inverting these conductivity types.

  Further, in each of the above-described embodiments, the lateral IGBT that is the lateral semiconductor switching element and the lateral FWD that is the lateral diode are described as examples of the lateral semiconductor element that flows current in the lateral direction that is the horizontal direction of the semiconductor substrate. However, the present invention may be applied to another lateral semiconductor element, for example, a semiconductor device having a lateral power MOSFET that is a lateral semiconductor switching element.

That is, in the first embodiment, the first impurity region is constituted by the p ⁺ type collector region 4, the second impurity region is constituted by the n ⁺ type emitter region 7, the first electrode is the collector electrode 12, and the second electrode is the emitter electrode 13. As an example, a horizontal IGBT is used. In the second embodiment, a horizontal FWD in which the first electrode is the anode electrode 29 and the second electrode is the cathode electrode 28 is taken as an example. In contrast, the first impurity region n ⁺ -type drain region instead of p ⁺ -type collector region 4, the second impurity region n ⁺ -type source region instead of the n ⁺ -type emitter region 7, the drain electrode first The present invention can also be applied to a lateral power MOSFET in which the electrode and the source electrode are the second electrodes.

1, 21 SOI substrate 1d, 21d Trench isolation structure 2 n ⁻ type drift layer 4 p ⁺ type collector region 6 channel p well layer 7 n ⁺ type emitter region 8 p ⁺ type contact layer 9 p type body layer 10 gate insulating film 11 Gate electrode 12 Collector electrode 13 Emitter electrode 14, 30 Resistance layer 22 n ⁻ type cathode layer 24 n ⁺ type contact layer 26 p type anode layer 27 p ⁺ type contact layer 28 Cathode electrode 29 Anode electrode 40 Horizontal IGBT main cell 41 Horizontal type IGBT sense cell 42 Horizontal FWD main cell 43 Horizontal FWD sense cell 50 Inverter circuit 51 Control circuit section Rs Sense resistor

Claims (9)

By passing a current between the first electrode (12, 29) and the second electrode (13, 28) formed on the surface of the semiconductor substrate (1, 21), the horizontal direction of the semiconductor substrate (1, 21) is increased. In a semiconductor device having a lateral semiconductor element that conducts current in a lateral direction that is a direction, dividing the lateral semiconductor element into a main cell and a sense cell, and detecting a current flowing in the sense cell by detecting a current flowing in the sense cell ,
A semiconductor device, wherein the main cell and the sense cell are insulated and separated by an element isolation structure (1d, 21d, 56) formed on the semiconductor substrate (1, 21).   A sense resistor (Rs, Rs1, Rs2) is connected to the sense cell, and a voltage between the sense cell and the sense resistor (Rs, Rs1, Rs2) is output as an output voltage (V1, V2), and the output voltage ( The current flowing through the sense cell is detected based on V1, V2), and the maximum voltage of the output voltage (V1, V2) is set to 0.7 V or more. Semiconductor device. The lateral semiconductor element has a lateral semiconductor switching element and a lateral diode,
The lateral semiconductor switching element is divided into a main cell and a sense cell, and the main cell and the sense cell of the lateral semiconductor switching element are insulated and separated by the element isolation structure (1d).
The lateral diode is also divided into a main cell and a sense cell, and the main cell and the sense cell of the lateral diode are insulated and separated by the element isolation structure (21d),
The first electrode (12) of the main cell and sense cell of the lateral semiconductor switching element is electrically connected to the main cell of the lateral diode and the second electrode (28) of the sense cell;
The second electrode (13) of the main cell of the lateral semiconductor switching element and the first electrode (29) of the main cell of the lateral diode are connected to the second electrode (13) of the sense cell of the lateral semiconductor switching element. Connected via the sense resistor (Rs1) for the lateral semiconductor switching element, and also connected to the first electrode (29) of the sense cell of the lateral diode via the sense resistor (Rs2) for the lateral diode,
A current path is configured by parallel connection of the lateral semiconductor switching element and the lateral diode,
The output voltage (V1) between the sense cell of the lateral semiconductor switching element and the sense resistor (Rs1) for the lateral semiconductor switching element, and the sense cell for the lateral diode and the sense resistor (Rs2) for the lateral diode The semiconductor device according to claim 1, wherein positive / negative of current flowing through the current path and increase / decrease in current are determined based on an output voltage (V 2) between them.   The sense cell (53a to 53f) of the lateral semiconductor switching element, the sense resistor (Rs1) for the lateral semiconductor switching element, the sense cell (55a to 55f) of the lateral diode, and the sense resistor (Rs2) for the lateral diode. The semiconductor device according to claim 3, wherein the semiconductor devices are arranged in a line.   Between the sense cell (53a to 53f) of the lateral semiconductor switching element and the sense cell (55a to 55f) of the lateral diode, the sense resistor (Rs1) for the lateral semiconductor switching element and the sense resistor (for the lateral diode) 5. The semiconductor device according to claim 4, wherein Rs2) is arranged.   The main cells (52a to 52f) of the horizontal semiconductor switching element and the main cells (54a to 54f) of the horizontal diode are arranged at intervals, and the main cells (52a to 52f) of the horizontal semiconductor switching element are arranged. Between the main cell (54a to 54f) of the lateral diode and the sense cell (53a to 53f) of the lateral semiconductor switching element, the sense resistor (Rs1) for the lateral semiconductor switching element, and the sense cell ( The semiconductor device according to claim 4, wherein 55a to 55f) and the sense resistor (Rs2) for the lateral diode are arranged.   The main cells (52a to 52f) of the horizontal semiconductor switching element and the main cells (54a to 54f) of the horizontal diode are arranged at intervals, and the main cells (52a to 52f) of the horizontal semiconductor switching element are arranged. A buffer circuit (56a-56f) for amplifying the output voltage (V1, V2) is also provided between the main cell (54a-54f) of the lateral diode and the horizontal diode. The semiconductor device according to any one of the above.   It has a control circuit part (51) for driving on / off of the semiconductor switching element, the control circuit part (51) includes a comparator, and the comparator is constituted only by CMOS. The semiconductor device according to claim 3. In addition to the sense cell provided in a region separated from the main cell of the lateral semiconductor element by the element isolation structure (1d, 21d),
The sense cell is further provided between the main cells in a region where the main cell of the lateral semiconductor element separated by the element isolation structure (1d, 21d) is provided. 9. The semiconductor device according to any one of items 8 to 8.

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